3 * (C) COPYRIGHT ARM Limited. All rights reserved.
5 * This program is free software and is provided to you under the terms of the
6 * GNU General Public License version 2 as published by the Free Software
7 * Foundation, and any use by you of this program is subject to the terms
10 * A copy of the licence is included with the program, and can also be obtained
11 * from Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
12 * Boston, MA 02110-1301, USA.
18 #ifndef _KBASE_GATOR_HWCNT_NAMES_H_
19 #define _KBASE_GATOR_HWCNT_NAMES_H_
22 * "Short names" for hardware counters used by Streamline. Counters names are
23 * stored in accordance with their memory layout in the binary counter block
24 * emitted by the Mali GPU. Each "master" in the GPU emits a fixed-size block
25 * of 64 counters, and each GPU implements the same set of "masters" although
26 * the counters each master exposes within its block of 64 may vary.
28 * Counters which are an empty string are simply "holes" in the counter memory
29 * where no counter exists.
32 static const char * const hardware_counter_names_mali_t60x[] = {
39 "T60x_MESSAGES_RECEIVED",
47 "T60x_JS0_WAIT_ISSUE",
48 "T60x_JS0_WAIT_DEPEND",
49 "T60x_JS0_WAIT_FINISH",
55 "T60x_JS1_WAIT_ISSUE",
56 "T60x_JS1_WAIT_DEPEND",
57 "T60x_JS1_WAIT_FINISH",
63 "T60x_JS2_WAIT_ISSUE",
64 "T60x_JS2_WAIT_DEPEND",
65 "T60x_JS2_WAIT_FINISH",
103 "T60x_TI_JOBS_PROCESSED",
109 "T60x_TI_VCACHE_HIT",
110 "T60x_TI_VCACHE_MISS",
111 "T60x_TI_FRONT_FACING",
112 "T60x_TI_BACK_FACING",
113 "T60x_TI_PRIM_VISIBLE",
114 "T60x_TI_PRIM_CULLED",
115 "T60x_TI_PRIM_CLIPPED",
128 "T60x_TI_COMMAND_4_7",
129 "T60x_TI_COMMAND_8_15",
130 "T60x_TI_COMMAND_16_63",
131 "T60x_TI_COMMAND_64",
132 "T60x_TI_COMPRESS_IN",
133 "T60x_TI_COMPRESS_OUT",
134 "T60x_TI_COMPRESS_FLUSH",
135 "T60x_TI_TIMESTAMPS",
136 "T60x_TI_PCACHE_HIT",
137 "T60x_TI_PCACHE_MISS",
138 "T60x_TI_PCACHE_LINE",
139 "T60x_TI_PCACHE_STALL",
141 "T60x_TI_WRBUF_MISS",
142 "T60x_TI_WRBUF_LINE",
143 "T60x_TI_WRBUF_PARTIAL",
144 "T60x_TI_WRBUF_STALL",
146 "T60x_TI_LOADING_DESC",
147 "T60x_TI_INDEX_WAIT",
148 "T60x_TI_INDEX_RANGE_WAIT",
149 "T60x_TI_VERTEX_WAIT",
150 "T60x_TI_PCACHE_WAIT",
151 "T60x_TI_WRBUF_WAIT",
159 "T60x_TI_UTLB_STALL",
160 "T60x_TI_UTLB_REPLAY_MISS",
161 "T60x_TI_UTLB_REPLAY_FULL",
162 "T60x_TI_UTLB_NEW_MISS",
171 "T60x_FRAG_PRIMITIVES",
172 "T60x_FRAG_PRIMITIVES_DROPPED",
173 "T60x_FRAG_CYCLES_DESC",
174 "T60x_FRAG_CYCLES_PLR",
175 "T60x_FRAG_CYCLES_VERT",
176 "T60x_FRAG_CYCLES_TRISETUP",
177 "T60x_FRAG_CYCLES_RAST",
179 "T60x_FRAG_DUMMY_THREADS",
180 "T60x_FRAG_QUADS_RAST",
181 "T60x_FRAG_QUADS_EZS_TEST",
182 "T60x_FRAG_QUADS_EZS_KILLED",
183 "T60x_FRAG_THREADS_LZS_TEST",
184 "T60x_FRAG_THREADS_LZS_KILLED",
185 "T60x_FRAG_CYCLES_NO_TILE",
186 "T60x_FRAG_NUM_TILES",
187 "T60x_FRAG_TRANS_ELIM",
188 "T60x_COMPUTE_ACTIVE",
189 "T60x_COMPUTE_TASKS",
190 "T60x_COMPUTE_THREADS",
191 "T60x_COMPUTE_CYCLES_DESC",
192 "T60x_TRIPIPE_ACTIVE",
194 "T60x_ARITH_CYCLES_REG",
195 "T60x_ARITH_CYCLES_L0",
196 "T60x_ARITH_FRAG_DEPEND",
200 "T60x_LS_REISSUES_MISS",
201 "T60x_LS_REISSUES_VD",
202 "T60x_LS_REISSUE_ATTRIB_MISS",
207 "T60x_TEX_WORDS_DESC",
209 "T60x_TEX_RECIRC_FMISS",
210 "T60x_TEX_RECIRC_DESC",
211 "T60x_TEX_RECIRC_MULTI",
212 "T60x_TEX_RECIRC_PMISS",
213 "T60x_TEX_RECIRC_CONF",
214 "T60x_LSC_READ_HITS",
215 "T60x_LSC_READ_MISSES",
216 "T60x_LSC_WRITE_HITS",
217 "T60x_LSC_WRITE_MISSES",
218 "T60x_LSC_ATOMIC_HITS",
219 "T60x_LSC_ATOMIC_MISSES",
220 "T60x_LSC_LINE_FETCHES",
221 "T60x_LSC_DIRTY_LINE",
223 "T60x_AXI_TLB_STALL",
224 "T60x_AXI_TLB_MIESS",
225 "T60x_AXI_TLB_TRANSACTION",
228 "T60x_AXI_BEATS_READ",
229 "T60x_AXI_BEATS_WRITTEN",
238 "T60x_MMU_REPLAY_FULL",
239 "T60x_MMU_REPLAY_MISS",
240 "T60x_MMU_TABLE_WALK",
249 "T60x_UTLB_NEW_MISS",
250 "T60x_UTLB_REPLAY_FULL",
251 "T60x_UTLB_REPLAY_MISS",
262 "T60x_L2_EXT_WRITE_BEATS",
263 "T60x_L2_EXT_READ_BEATS",
264 "T60x_L2_ANY_LOOKUP",
265 "T60x_L2_READ_LOOKUP",
266 "T60x_L2_SREAD_LOOKUP",
267 "T60x_L2_READ_REPLAY",
268 "T60x_L2_READ_SNOOP",
270 "T60x_L2_CLEAN_MISS",
271 "T60x_L2_WRITE_LOOKUP",
272 "T60x_L2_SWRITE_LOOKUP",
273 "T60x_L2_WRITE_REPLAY",
274 "T60x_L2_WRITE_SNOOP",
276 "T60x_L2_EXT_READ_FULL",
277 "T60x_L2_EXT_READ_HALF",
278 "T60x_L2_EXT_WRITE_FULL",
279 "T60x_L2_EXT_WRITE_HALF",
281 "T60x_L2_EXT_READ_LINE",
283 "T60x_L2_EXT_WRITE_LINE",
284 "T60x_L2_EXT_WRITE_SMALL",
285 "T60x_L2_EXT_BARRIER",
286 "T60x_L2_EXT_AR_STALL",
287 "T60x_L2_EXT_R_BUF_FULL",
288 "T60x_L2_EXT_RD_BUF_FULL",
290 "T60x_L2_EXT_W_STALL",
291 "T60x_L2_EXT_W_BUF_FULL",
292 "T60x_L2_EXT_R_W_HAZARD",
293 "T60x_L2_TAG_HAZARD",
294 "T60x_L2_SNOOP_FULL",
295 "T60x_L2_REPLAY_FULL"
297 static const char * const hardware_counter_names_mali_t62x[] = {
303 "T62x_MESSAGES_SENT",
304 "T62x_MESSAGES_RECEIVED",
311 "T62x_JS0_WAIT_READ",
312 "T62x_JS0_WAIT_ISSUE",
313 "T62x_JS0_WAIT_DEPEND",
314 "T62x_JS0_WAIT_FINISH",
319 "T62x_JS1_WAIT_READ",
320 "T62x_JS1_WAIT_ISSUE",
321 "T62x_JS1_WAIT_DEPEND",
322 "T62x_JS1_WAIT_FINISH",
327 "T62x_JS2_WAIT_READ",
328 "T62x_JS2_WAIT_ISSUE",
329 "T62x_JS2_WAIT_DEPEND",
330 "T62x_JS2_WAIT_FINISH",
368 "T62x_TI_JOBS_PROCESSED",
374 "T62x_TI_VCACHE_HIT",
375 "T62x_TI_VCACHE_MISS",
376 "T62x_TI_FRONT_FACING",
377 "T62x_TI_BACK_FACING",
378 "T62x_TI_PRIM_VISIBLE",
379 "T62x_TI_PRIM_CULLED",
380 "T62x_TI_PRIM_CLIPPED",
393 "T62x_TI_COMMAND_5_7",
394 "T62x_TI_COMMAND_8_15",
395 "T62x_TI_COMMAND_16_63",
396 "T62x_TI_COMMAND_64",
397 "T62x_TI_COMPRESS_IN",
398 "T62x_TI_COMPRESS_OUT",
399 "T62x_TI_COMPRESS_FLUSH",
400 "T62x_TI_TIMESTAMPS",
401 "T62x_TI_PCACHE_HIT",
402 "T62x_TI_PCACHE_MISS",
403 "T62x_TI_PCACHE_LINE",
404 "T62x_TI_PCACHE_STALL",
406 "T62x_TI_WRBUF_MISS",
407 "T62x_TI_WRBUF_LINE",
408 "T62x_TI_WRBUF_PARTIAL",
409 "T62x_TI_WRBUF_STALL",
411 "T62x_TI_LOADING_DESC",
412 "T62x_TI_INDEX_WAIT",
413 "T62x_TI_INDEX_RANGE_WAIT",
414 "T62x_TI_VERTEX_WAIT",
415 "T62x_TI_PCACHE_WAIT",
416 "T62x_TI_WRBUF_WAIT",
424 "T62x_TI_UTLB_STALL",
425 "T62x_TI_UTLB_REPLAY_MISS",
426 "T62x_TI_UTLB_REPLAY_FULL",
427 "T62x_TI_UTLB_NEW_MISS",
434 "T62x_SHADER_CORE_ACTIVE",
436 "T62x_FRAG_PRIMITIVES",
437 "T62x_FRAG_PRIMITIVES_DROPPED",
438 "T62x_FRAG_CYCLES_DESC",
439 "T62x_FRAG_CYCLES_FPKQ_ACTIVE",
440 "T62x_FRAG_CYCLES_VERT",
441 "T62x_FRAG_CYCLES_TRISETUP",
442 "T62x_FRAG_CYCLES_EZS_ACTIVE",
444 "T62x_FRAG_DUMMY_THREADS",
445 "T62x_FRAG_QUADS_RAST",
446 "T62x_FRAG_QUADS_EZS_TEST",
447 "T62x_FRAG_QUADS_EZS_KILLED",
448 "T62x_FRAG_THREADS_LZS_TEST",
449 "T62x_FRAG_THREADS_LZS_KILLED",
450 "T62x_FRAG_CYCLES_NO_TILE",
451 "T62x_FRAG_NUM_TILES",
452 "T62x_FRAG_TRANS_ELIM",
453 "T62x_COMPUTE_ACTIVE",
454 "T62x_COMPUTE_TASKS",
455 "T62x_COMPUTE_THREADS",
456 "T62x_COMPUTE_CYCLES_DESC",
457 "T62x_TRIPIPE_ACTIVE",
459 "T62x_ARITH_CYCLES_REG",
460 "T62x_ARITH_CYCLES_L0",
461 "T62x_ARITH_FRAG_DEPEND",
465 "T62x_LS_REISSUES_MISS",
466 "T62x_LS_REISSUES_VD",
467 "T62x_LS_REISSUE_ATTRIB_MISS",
472 "T62x_TEX_WORDS_DESC",
474 "T62x_TEX_RECIRC_FMISS",
475 "T62x_TEX_RECIRC_DESC",
476 "T62x_TEX_RECIRC_MULTI",
477 "T62x_TEX_RECIRC_PMISS",
478 "T62x_TEX_RECIRC_CONF",
479 "T62x_LSC_READ_HITS",
480 "T62x_LSC_READ_MISSES",
481 "T62x_LSC_WRITE_HITS",
482 "T62x_LSC_WRITE_MISSES",
483 "T62x_LSC_ATOMIC_HITS",
484 "T62x_LSC_ATOMIC_MISSES",
485 "T62x_LSC_LINE_FETCHES",
486 "T62x_LSC_DIRTY_LINE",
488 "T62x_AXI_TLB_STALL",
489 "T62x_AXI_TLB_MIESS",
490 "T62x_AXI_TLB_TRANSACTION",
493 "T62x_AXI_BEATS_READ",
494 "T62x_AXI_BEATS_WRITTEN",
503 "T62x_MMU_REPLAY_FULL",
504 "T62x_MMU_REPLAY_MISS",
505 "T62x_MMU_TABLE_WALK",
514 "T62x_UTLB_NEW_MISS",
515 "T62x_UTLB_REPLAY_FULL",
516 "T62x_UTLB_REPLAY_MISS",
527 "T62x_L2_EXT_WRITE_BEATS",
528 "T62x_L2_EXT_READ_BEATS",
529 "T62x_L2_ANY_LOOKUP",
530 "T62x_L2_READ_LOOKUP",
531 "T62x_L2_SREAD_LOOKUP",
532 "T62x_L2_READ_REPLAY",
533 "T62x_L2_READ_SNOOP",
535 "T62x_L2_CLEAN_MISS",
536 "T62x_L2_WRITE_LOOKUP",
537 "T62x_L2_SWRITE_LOOKUP",
538 "T62x_L2_WRITE_REPLAY",
539 "T62x_L2_WRITE_SNOOP",
541 "T62x_L2_EXT_READ_FULL",
542 "T62x_L2_EXT_READ_HALF",
543 "T62x_L2_EXT_WRITE_FULL",
544 "T62x_L2_EXT_WRITE_HALF",
546 "T62x_L2_EXT_READ_LINE",
548 "T62x_L2_EXT_WRITE_LINE",
549 "T62x_L2_EXT_WRITE_SMALL",
550 "T62x_L2_EXT_BARRIER",
551 "T62x_L2_EXT_AR_STALL",
552 "T62x_L2_EXT_R_BUF_FULL",
553 "T62x_L2_EXT_RD_BUF_FULL",
555 "T62x_L2_EXT_W_STALL",
556 "T62x_L2_EXT_W_BUF_FULL",
557 "T62x_L2_EXT_R_W_HAZARD",
558 "T62x_L2_TAG_HAZARD",
559 "T62x_L2_SNOOP_FULL",
560 "T62x_L2_REPLAY_FULL"
563 static const char * const hardware_counter_names_mali_t72x[] = {
634 "T72x_TI_JOBS_PROCESSED",
640 "T72x_TI_FRONT_FACING",
641 "T72x_TI_BACK_FACING",
642 "T72x_TI_PRIM_VISIBLE",
643 "T72x_TI_PRIM_CULLED",
644 "T72x_TI_PRIM_CLIPPED",
702 "T72x_FRAG_PRIMITIVES",
703 "T72x_FRAG_PRIMITIVES_DROPPED",
705 "T72x_FRAG_DUMMY_THREADS",
706 "T72x_FRAG_QUADS_RAST",
707 "T72x_FRAG_QUADS_EZS_TEST",
708 "T72x_FRAG_QUADS_EZS_KILLED",
709 "T72x_FRAG_THREADS_LZS_TEST",
710 "T72x_FRAG_THREADS_LZS_KILLED",
711 "T72x_FRAG_CYCLES_NO_TILE",
712 "T72x_FRAG_NUM_TILES",
713 "T72x_FRAG_TRANS_ELIM",
714 "T72x_COMPUTE_ACTIVE",
715 "T72x_COMPUTE_TASKS",
716 "T72x_COMPUTE_THREADS",
717 "T72x_TRIPIPE_ACTIVE",
719 "T72x_ARITH_CYCLES_REG",
723 "T72x_LS_REISSUES_MISS",
727 "T72x_LSC_READ_HITS",
728 "T72x_LSC_READ_MISSES",
729 "T72x_LSC_WRITE_HITS",
730 "T72x_LSC_WRITE_MISSES",
731 "T72x_LSC_ATOMIC_HITS",
732 "T72x_LSC_ATOMIC_MISSES",
733 "T72x_LSC_LINE_FETCHES",
734 "T72x_LSC_DIRTY_LINE",
767 "T72x_L2_EXT_WRITE_BEAT",
768 "T72x_L2_EXT_READ_BEAT",
769 "T72x_L2_READ_SNOOP",
771 "T72x_L2_WRITE_SNOOP",
773 "T72x_L2_EXT_WRITE_SMALL",
774 "T72x_L2_EXT_BARRIER",
775 "T72x_L2_EXT_AR_STALL",
776 "T72x_L2_EXT_W_STALL",
777 "T72x_L2_SNOOP_FULL",
829 static const char * const hardware_counter_names_mali_t76x[] = {
835 "T76x_MESSAGES_SENT",
836 "T76x_MESSAGES_RECEIVED",
843 "T76x_JS0_WAIT_READ",
844 "T76x_JS0_WAIT_ISSUE",
845 "T76x_JS0_WAIT_DEPEND",
846 "T76x_JS0_WAIT_FINISH",
851 "T76x_JS1_WAIT_READ",
852 "T76x_JS1_WAIT_ISSUE",
853 "T76x_JS1_WAIT_DEPEND",
854 "T76x_JS1_WAIT_FINISH",
859 "T76x_JS2_WAIT_READ",
860 "T76x_JS2_WAIT_ISSUE",
861 "T76x_JS2_WAIT_DEPEND",
862 "T76x_JS2_WAIT_FINISH",
900 "T76x_TI_JOBS_PROCESSED",
906 "T76x_TI_VCACHE_HIT",
907 "T76x_TI_VCACHE_MISS",
908 "T76x_TI_FRONT_FACING",
909 "T76x_TI_BACK_FACING",
910 "T76x_TI_PRIM_VISIBLE",
911 "T76x_TI_PRIM_CULLED",
912 "T76x_TI_PRIM_CLIPPED",
925 "T76x_TI_COMMAND_5_7",
926 "T76x_TI_COMMAND_8_15",
927 "T76x_TI_COMMAND_16_63",
928 "T76x_TI_COMMAND_64",
929 "T76x_TI_COMPRESS_IN",
930 "T76x_TI_COMPRESS_OUT",
931 "T76x_TI_COMPRESS_FLUSH",
932 "T76x_TI_TIMESTAMPS",
933 "T76x_TI_PCACHE_HIT",
934 "T76x_TI_PCACHE_MISS",
935 "T76x_TI_PCACHE_LINE",
936 "T76x_TI_PCACHE_STALL",
938 "T76x_TI_WRBUF_MISS",
939 "T76x_TI_WRBUF_LINE",
940 "T76x_TI_WRBUF_PARTIAL",
941 "T76x_TI_WRBUF_STALL",
943 "T76x_TI_LOADING_DESC",
944 "T76x_TI_INDEX_WAIT",
945 "T76x_TI_INDEX_RANGE_WAIT",
946 "T76x_TI_VERTEX_WAIT",
947 "T76x_TI_PCACHE_WAIT",
948 "T76x_TI_WRBUF_WAIT",
957 "T76x_TI_UTLB_NEW_MISS",
958 "T76x_TI_UTLB_REPLAY_FULL",
959 "T76x_TI_UTLB_REPLAY_MISS",
960 "T76x_TI_UTLB_STALL",
968 "T76x_FRAG_PRIMITIVES",
969 "T76x_FRAG_PRIMITIVES_DROPPED",
970 "T76x_FRAG_CYCLES_DESC",
971 "T76x_FRAG_CYCLES_FPKQ_ACTIVE",
972 "T76x_FRAG_CYCLES_VERT",
973 "T76x_FRAG_CYCLES_TRISETUP",
974 "T76x_FRAG_CYCLES_EZS_ACTIVE",
976 "T76x_FRAG_DUMMY_THREADS",
977 "T76x_FRAG_QUADS_RAST",
978 "T76x_FRAG_QUADS_EZS_TEST",
979 "T76x_FRAG_QUADS_EZS_KILLED",
980 "T76x_FRAG_THREADS_LZS_TEST",
981 "T76x_FRAG_THREADS_LZS_KILLED",
982 "T76x_FRAG_CYCLES_NO_TILE",
983 "T76x_FRAG_NUM_TILES",
984 "T76x_FRAG_TRANS_ELIM",
985 "T76x_COMPUTE_ACTIVE",
986 "T76x_COMPUTE_TASKS",
987 "T76x_COMPUTE_THREADS",
988 "T76x_COMPUTE_CYCLES_DESC",
989 "T76x_TRIPIPE_ACTIVE",
991 "T76x_ARITH_CYCLES_REG",
992 "T76x_ARITH_CYCLES_L0",
993 "T76x_ARITH_FRAG_DEPEND",
996 "T76x_LS_REISSUE_ATTR",
997 "T76x_LS_REISSUES_VARY",
998 "T76x_LS_VARY_RV_MISS",
999 "T76x_LS_VARY_RV_HIT",
1000 "T76x_LS_NO_UNPARK",
1003 "T76x_TEX_WORDS_L0",
1004 "T76x_TEX_WORDS_DESC",
1006 "T76x_TEX_RECIRC_FMISS",
1007 "T76x_TEX_RECIRC_DESC",
1008 "T76x_TEX_RECIRC_MULTI",
1009 "T76x_TEX_RECIRC_PMISS",
1010 "T76x_TEX_RECIRC_CONF",
1011 "T76x_LSC_READ_HITS",
1013 "T76x_LSC_WRITE_HITS",
1014 "T76x_LSC_WRITE_OP",
1015 "T76x_LSC_ATOMIC_HITS",
1016 "T76x_LSC_ATOMIC_OP",
1017 "T76x_LSC_LINE_FETCHES",
1018 "T76x_LSC_DIRTY_LINE",
1020 "T76x_AXI_TLB_STALL",
1021 "T76x_AXI_TLB_MIESS",
1022 "T76x_AXI_TLB_TRANSACTION",
1025 "T76x_AXI_BEATS_READ",
1026 "T76x_AXI_BEATS_WRITTEN",
1034 "T76x_MMU_NEW_MISS",
1035 "T76x_MMU_REPLAY_FULL",
1036 "T76x_MMU_REPLAY_MISS",
1037 "T76x_MMU_TABLE_WALK",
1038 "T76x_MMU_REQUESTS",
1042 "T76x_UTLB_NEW_MISS",
1043 "T76x_UTLB_REPLAY_FULL",
1044 "T76x_UTLB_REPLAY_MISS",
1059 "T76x_L2_EXT_WRITE_BEATS",
1060 "T76x_L2_EXT_READ_BEATS",
1061 "T76x_L2_ANY_LOOKUP",
1062 "T76x_L2_READ_LOOKUP",
1063 "T76x_L2_SREAD_LOOKUP",
1064 "T76x_L2_READ_REPLAY",
1065 "T76x_L2_READ_SNOOP",
1067 "T76x_L2_CLEAN_MISS",
1068 "T76x_L2_WRITE_LOOKUP",
1069 "T76x_L2_SWRITE_LOOKUP",
1070 "T76x_L2_WRITE_REPLAY",
1071 "T76x_L2_WRITE_SNOOP",
1072 "T76x_L2_WRITE_HIT",
1073 "T76x_L2_EXT_READ_FULL",
1075 "T76x_L2_EXT_WRITE_FULL",
1076 "T76x_L2_EXT_R_W_HAZARD",
1078 "T76x_L2_EXT_READ_LINE",
1079 "T76x_L2_EXT_WRITE",
1080 "T76x_L2_EXT_WRITE_LINE",
1081 "T76x_L2_EXT_WRITE_SMALL",
1082 "T76x_L2_EXT_BARRIER",
1083 "T76x_L2_EXT_AR_STALL",
1084 "T76x_L2_EXT_R_BUF_FULL",
1085 "T76x_L2_EXT_RD_BUF_FULL",
1086 "T76x_L2_EXT_R_RAW",
1087 "T76x_L2_EXT_W_STALL",
1088 "T76x_L2_EXT_W_BUF_FULL",
1089 "T76x_L2_EXT_R_BUF_FULL",
1090 "T76x_L2_TAG_HAZARD",
1091 "T76x_L2_SNOOP_FULL",
1092 "T76x_L2_REPLAY_FULL"