2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/fence.h>
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_gds.h"
56 #include "gpu_scheduler.h"
61 extern int amdgpu_modeset;
62 extern int amdgpu_vram_limit;
63 extern int amdgpu_gart_size;
64 extern int amdgpu_benchmarking;
65 extern int amdgpu_testing;
66 extern int amdgpu_audio;
67 extern int amdgpu_disp_priority;
68 extern int amdgpu_hw_i2c;
69 extern int amdgpu_pcie_gen2;
70 extern int amdgpu_msi;
71 extern int amdgpu_lockup_timeout;
72 extern int amdgpu_dpm;
73 extern int amdgpu_smc_load_fw;
74 extern int amdgpu_aspm;
75 extern int amdgpu_runtime_pm;
76 extern int amdgpu_hard_reset;
77 extern unsigned amdgpu_ip_block_mask;
78 extern int amdgpu_bapm;
79 extern int amdgpu_deep_color;
80 extern int amdgpu_vm_size;
81 extern int amdgpu_vm_block_size;
82 extern int amdgpu_enable_scheduler;
83 extern int amdgpu_sched_jobs;
85 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
86 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
87 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
88 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
89 #define AMDGPU_IB_POOL_SIZE 16
90 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
91 #define AMDGPUFB_CONN_LIMIT 4
92 #define AMDGPU_BIOS_NUM_SCRATCH 8
94 /* max number of rings */
95 #define AMDGPU_MAX_RINGS 16
96 #define AMDGPU_MAX_GFX_RINGS 1
97 #define AMDGPU_MAX_COMPUTE_RINGS 8
98 #define AMDGPU_MAX_VCE_RINGS 2
100 /* number of hw syncs before falling back on blocking */
101 #define AMDGPU_NUM_SYNCS 4
103 /* hardcode that limit for now */
104 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
106 /* hard reset data */
107 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
110 #define AMDGPU_RESET_GFX (1 << 0)
111 #define AMDGPU_RESET_COMPUTE (1 << 1)
112 #define AMDGPU_RESET_DMA (1 << 2)
113 #define AMDGPU_RESET_CP (1 << 3)
114 #define AMDGPU_RESET_GRBM (1 << 4)
115 #define AMDGPU_RESET_DMA1 (1 << 5)
116 #define AMDGPU_RESET_RLC (1 << 6)
117 #define AMDGPU_RESET_SEM (1 << 7)
118 #define AMDGPU_RESET_IH (1 << 8)
119 #define AMDGPU_RESET_VMC (1 << 9)
120 #define AMDGPU_RESET_MC (1 << 10)
121 #define AMDGPU_RESET_DISPLAY (1 << 11)
122 #define AMDGPU_RESET_UVD (1 << 12)
123 #define AMDGPU_RESET_VCE (1 << 13)
124 #define AMDGPU_RESET_VCE1 (1 << 14)
127 #define AMDGPU_CG_BLOCK_GFX (1 << 0)
128 #define AMDGPU_CG_BLOCK_MC (1 << 1)
129 #define AMDGPU_CG_BLOCK_SDMA (1 << 2)
130 #define AMDGPU_CG_BLOCK_UVD (1 << 3)
131 #define AMDGPU_CG_BLOCK_VCE (1 << 4)
132 #define AMDGPU_CG_BLOCK_HDP (1 << 5)
133 #define AMDGPU_CG_BLOCK_BIF (1 << 6)
136 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0)
137 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1)
138 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2)
139 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3)
140 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4)
141 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
142 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6)
143 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7)
144 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8)
145 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9)
146 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10)
147 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11)
148 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12)
149 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13)
150 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14)
151 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15)
152 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16)
155 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0)
156 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1)
157 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2)
158 #define AMDGPU_PG_SUPPORT_UVD (1 << 3)
159 #define AMDGPU_PG_SUPPORT_VCE (1 << 4)
160 #define AMDGPU_PG_SUPPORT_CP (1 << 5)
161 #define AMDGPU_PG_SUPPORT_GDS (1 << 6)
162 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7)
163 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8)
164 #define AMDGPU_PG_SUPPORT_ACP (1 << 9)
165 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10)
167 /* GFX current status */
168 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
169 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
170 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
171 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
172 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
174 /* max cursor sizes (in pixels) */
175 #define CIK_CURSOR_WIDTH 128
176 #define CIK_CURSOR_HEIGHT 128
178 struct amdgpu_device;
183 struct amdgpu_semaphore;
184 struct amdgpu_cs_parser;
185 struct amdgpu_irq_src;
189 AMDGPU_CP_IRQ_GFX_EOP = 0,
190 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
191 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
192 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
193 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
194 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
195 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
196 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
197 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
202 enum amdgpu_sdma_irq {
203 AMDGPU_SDMA_IRQ_TRAP0 = 0,
204 AMDGPU_SDMA_IRQ_TRAP1,
209 enum amdgpu_thermal_irq {
210 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
211 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
213 AMDGPU_THERMAL_IRQ_LAST
216 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
217 enum amd_ip_block_type block_type,
218 enum amd_clockgating_state state);
219 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
220 enum amd_ip_block_type block_type,
221 enum amd_powergating_state state);
223 struct amdgpu_ip_block_version {
224 enum amd_ip_block_type type;
228 const struct amd_ip_funcs *funcs;
231 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
232 enum amd_ip_block_type type,
233 u32 major, u32 minor);
235 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
236 struct amdgpu_device *adev,
237 enum amd_ip_block_type type);
239 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
240 struct amdgpu_buffer_funcs {
241 /* maximum bytes in a single operation */
242 uint32_t copy_max_bytes;
244 /* number of dw to reserve per operation */
245 unsigned copy_num_dw;
247 /* used for buffer migration */
248 void (*emit_copy_buffer)(struct amdgpu_ring *ring,
249 /* src addr in bytes */
251 /* dst addr in bytes */
253 /* number of byte to transfer */
254 uint32_t byte_count);
256 /* maximum bytes in a single operation */
257 uint32_t fill_max_bytes;
259 /* number of dw to reserve per operation */
260 unsigned fill_num_dw;
262 /* used for buffer clearing */
263 void (*emit_fill_buffer)(struct amdgpu_ring *ring,
264 /* value to write to memory */
266 /* dst addr in bytes */
268 /* number of byte to fill */
269 uint32_t byte_count);
272 /* provided by hw blocks that can write ptes, e.g., sdma */
273 struct amdgpu_vm_pte_funcs {
274 /* copy pte entries from GART */
275 void (*copy_pte)(struct amdgpu_ib *ib,
276 uint64_t pe, uint64_t src,
278 /* write pte one entry at a time with addr mapping */
279 void (*write_pte)(struct amdgpu_ib *ib,
281 uint64_t addr, unsigned count,
282 uint32_t incr, uint32_t flags);
283 /* for linear pte/pde updates without addr mapping */
284 void (*set_pte_pde)(struct amdgpu_ib *ib,
286 uint64_t addr, unsigned count,
287 uint32_t incr, uint32_t flags);
288 /* pad the indirect buffer to the necessary number of dw */
289 void (*pad_ib)(struct amdgpu_ib *ib);
292 /* provided by the gmc block */
293 struct amdgpu_gart_funcs {
294 /* flush the vm tlb via mmio */
295 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
297 /* write pte/pde updates using the cpu */
298 int (*set_pte_pde)(struct amdgpu_device *adev,
299 void *cpu_pt_addr, /* cpu addr of page table */
300 uint32_t gpu_page_idx, /* pte/pde to update */
301 uint64_t addr, /* addr to write into pte/pde */
302 uint32_t flags); /* access flags */
305 /* provided by the ih block */
306 struct amdgpu_ih_funcs {
307 /* ring read/write ptr handling, called from interrupt context */
308 u32 (*get_wptr)(struct amdgpu_device *adev);
309 void (*decode_iv)(struct amdgpu_device *adev,
310 struct amdgpu_iv_entry *entry);
311 void (*set_rptr)(struct amdgpu_device *adev);
314 /* provided by hw blocks that expose a ring buffer for commands */
315 struct amdgpu_ring_funcs {
316 /* ring read/write ptr handling */
317 u32 (*get_rptr)(struct amdgpu_ring *ring);
318 u32 (*get_wptr)(struct amdgpu_ring *ring);
319 void (*set_wptr)(struct amdgpu_ring *ring);
320 /* validating and patching of IBs */
321 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
322 /* command emit functions */
323 void (*emit_ib)(struct amdgpu_ring *ring,
324 struct amdgpu_ib *ib);
325 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
326 uint64_t seq, unsigned flags);
327 bool (*emit_semaphore)(struct amdgpu_ring *ring,
328 struct amdgpu_semaphore *semaphore,
330 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
332 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
333 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
334 uint32_t gds_base, uint32_t gds_size,
335 uint32_t gws_base, uint32_t gws_size,
336 uint32_t oa_base, uint32_t oa_size);
337 /* testing functions */
338 int (*test_ring)(struct amdgpu_ring *ring);
339 int (*test_ib)(struct amdgpu_ring *ring);
340 bool (*is_lockup)(struct amdgpu_ring *ring);
346 bool amdgpu_get_bios(struct amdgpu_device *adev);
347 bool amdgpu_read_bios(struct amdgpu_device *adev);
352 struct amdgpu_dummy_page {
356 int amdgpu_dummy_page_init(struct amdgpu_device *adev);
357 void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
364 #define AMDGPU_MAX_PPLL 3
366 struct amdgpu_clock {
367 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
368 struct amdgpu_pll spll;
369 struct amdgpu_pll mpll;
371 uint32_t default_mclk;
372 uint32_t default_sclk;
373 uint32_t default_dispclk;
374 uint32_t current_dispclk;
376 uint32_t max_pixel_clock;
382 struct amdgpu_fence_driver {
383 struct amdgpu_ring *ring;
385 volatile uint32_t *cpu_addr;
386 /* sync_seq is protected by ring emission lock */
387 uint64_t sync_seq[AMDGPU_MAX_RINGS];
390 struct amdgpu_irq_src *irq_src;
392 struct delayed_work lockup_work;
395 /* some special values for the owner field */
396 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
397 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul)
398 #define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul)
400 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0)
401 #define AMDGPU_FENCE_FLAG_INT (1 << 1)
403 struct amdgpu_fence {
407 struct amdgpu_ring *ring;
410 /* filp or special value for fence creator */
413 wait_queue_t fence_wake;
416 struct amdgpu_user_fence {
418 struct amdgpu_bo *bo;
419 /* write-back address offset to bo start */
424 int amdgpu_fence_driver_init(struct amdgpu_device *adev);
425 void amdgpu_fence_driver_fini(struct amdgpu_device *adev);
426 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);
428 void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
429 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
430 struct amdgpu_irq_src *irq_src,
432 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
433 void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
434 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
435 struct amdgpu_fence **fence);
436 void amdgpu_fence_process(struct amdgpu_ring *ring);
437 int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
438 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
439 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
441 bool amdgpu_fence_signaled(struct amdgpu_fence *fence);
442 int amdgpu_fence_wait(struct amdgpu_fence *fence, bool interruptible);
443 int amdgpu_fence_wait_any(struct amdgpu_device *adev,
444 struct amdgpu_fence **fences,
446 struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence);
447 void amdgpu_fence_unref(struct amdgpu_fence **fence);
449 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
450 struct amdgpu_ring *ring);
451 void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
452 struct amdgpu_ring *ring);
454 static inline struct amdgpu_fence *amdgpu_fence_later(struct amdgpu_fence *a,
455 struct amdgpu_fence *b)
465 BUG_ON(a->ring != b->ring);
467 if (a->seq > b->seq) {
474 static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence *a,
475 struct amdgpu_fence *b)
485 BUG_ON(a->ring != b->ring);
487 return a->seq < b->seq;
490 int amdgpu_user_fence_emit(struct amdgpu_ring *ring, struct amdgpu_user_fence *user,
491 void *owner, struct amdgpu_fence **fence);
497 struct ttm_bo_global_ref bo_global_ref;
498 struct drm_global_reference mem_global_ref;
499 struct ttm_bo_device bdev;
500 bool mem_global_referenced;
503 #if defined(CONFIG_DEBUG_FS)
508 /* buffer handling */
509 const struct amdgpu_buffer_funcs *buffer_funcs;
510 struct amdgpu_ring *buffer_funcs_ring;
513 int amdgpu_copy_buffer(struct amdgpu_ring *ring,
517 struct reservation_object *resv,
518 struct amdgpu_fence **fence);
519 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
521 struct amdgpu_bo_list_entry {
522 struct amdgpu_bo *robj;
523 struct ttm_validate_buffer tv;
524 struct amdgpu_bo_va *bo_va;
525 unsigned prefered_domains;
526 unsigned allowed_domains;
530 struct amdgpu_bo_va_mapping {
531 struct list_head list;
532 struct interval_tree_node it;
537 /* bo virtual addresses in a specific vm */
538 struct amdgpu_bo_va {
539 /* protected by bo being reserved */
540 struct list_head bo_list;
542 struct amdgpu_fence *last_pt_update;
545 /* protected by vm mutex */
546 struct list_head mappings;
547 struct list_head vm_status;
549 /* constant after initialization */
550 struct amdgpu_vm *vm;
551 struct amdgpu_bo *bo;
554 #define AMDGPU_GEM_DOMAIN_MAX 0x3
557 /* Protected by gem.mutex */
558 struct list_head list;
559 /* Protected by tbo.reserved */
561 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
562 struct ttm_placement placement;
563 struct ttm_buffer_object tbo;
564 struct ttm_bo_kmap_obj kmap;
572 /* list of all virtual address to which this bo
576 /* Constant after initialization */
577 struct amdgpu_device *adev;
578 struct drm_gem_object gem_base;
580 struct ttm_bo_kmap_obj dma_buf_vmap;
582 struct amdgpu_mn *mn;
583 struct list_head mn_list;
585 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
587 void amdgpu_gem_object_free(struct drm_gem_object *obj);
588 int amdgpu_gem_object_open(struct drm_gem_object *obj,
589 struct drm_file *file_priv);
590 void amdgpu_gem_object_close(struct drm_gem_object *obj,
591 struct drm_file *file_priv);
592 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
593 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
594 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
595 struct dma_buf_attachment *attach,
596 struct sg_table *sg);
597 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
598 struct drm_gem_object *gobj,
600 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
601 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
602 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
603 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
604 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
605 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
607 /* sub-allocation manager, it has to be protected by another lock.
608 * By conception this is an helper for other part of the driver
609 * like the indirect buffer or semaphore, which both have their
612 * Principe is simple, we keep a list of sub allocation in offset
613 * order (first entry has offset == 0, last entry has the highest
616 * When allocating new object we first check if there is room at
617 * the end total_size - (last_object_offset + last_object_size) >=
618 * alloc_size. If so we allocate new object there.
620 * When there is not enough room at the end, we start waiting for
621 * each sub object until we reach object_offset+object_size >=
622 * alloc_size, this object then become the sub object we return.
624 * Alignment can't be bigger than page size.
626 * Hole are not considered for allocation to keep things simple.
627 * Assumption is that there won't be hole (all object on same
630 struct amdgpu_sa_manager {
631 wait_queue_head_t wq;
632 struct amdgpu_bo *bo;
633 struct list_head *hole;
634 struct list_head flist[AMDGPU_MAX_RINGS];
635 struct list_head olist;
645 /* sub-allocation buffer */
646 struct amdgpu_sa_bo {
647 struct list_head olist;
648 struct list_head flist;
649 struct amdgpu_sa_manager *manager;
652 struct amdgpu_fence *fence;
660 struct list_head objects;
663 int amdgpu_gem_init(struct amdgpu_device *adev);
664 void amdgpu_gem_fini(struct amdgpu_device *adev);
665 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
666 int alignment, u32 initial_domain,
667 u64 flags, bool kernel,
668 struct drm_gem_object **obj);
670 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
671 struct drm_device *dev,
672 struct drm_mode_create_dumb *args);
673 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
674 struct drm_device *dev,
675 uint32_t handle, uint64_t *offset_p);
680 struct amdgpu_semaphore {
681 struct amdgpu_sa_bo *sa_bo;
686 int amdgpu_semaphore_create(struct amdgpu_device *adev,
687 struct amdgpu_semaphore **semaphore);
688 bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring,
689 struct amdgpu_semaphore *semaphore);
690 bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring,
691 struct amdgpu_semaphore *semaphore);
692 void amdgpu_semaphore_free(struct amdgpu_device *adev,
693 struct amdgpu_semaphore **semaphore,
694 struct amdgpu_fence *fence);
700 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
701 struct amdgpu_fence *sync_to[AMDGPU_MAX_RINGS];
702 struct amdgpu_fence *last_vm_update;
705 void amdgpu_sync_create(struct amdgpu_sync *sync);
706 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
708 int amdgpu_sync_resv(struct amdgpu_device *adev,
709 struct amdgpu_sync *sync,
710 struct reservation_object *resv,
712 int amdgpu_sync_rings(struct amdgpu_sync *sync,
713 struct amdgpu_ring *ring);
714 void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync,
715 struct amdgpu_fence *fence);
718 * GART structures, functions & helpers
722 #define AMDGPU_GPU_PAGE_SIZE 4096
723 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
724 #define AMDGPU_GPU_PAGE_SHIFT 12
725 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
728 dma_addr_t table_addr;
729 struct amdgpu_bo *robj;
731 unsigned num_gpu_pages;
732 unsigned num_cpu_pages;
735 dma_addr_t *pages_addr;
737 const struct amdgpu_gart_funcs *gart_funcs;
740 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
741 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
742 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
743 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
744 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
745 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
746 int amdgpu_gart_init(struct amdgpu_device *adev);
747 void amdgpu_gart_fini(struct amdgpu_device *adev);
748 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset,
750 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset,
751 int pages, struct page **pagelist,
752 dma_addr_t *dma_addr, uint32_t flags);
755 * GPU MC structures, functions & helpers
758 resource_size_t aper_size;
759 resource_size_t aper_base;
760 resource_size_t agp_base;
761 /* for some chips with <= 32MB we need to lie
762 * about vram size near mc fb location */
764 u64 visible_vram_size;
775 const struct firmware *fw; /* MC firmware */
777 struct amdgpu_irq_src vm_fault;
782 * GPU doorbell structures, functions & helpers
784 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
786 AMDGPU_DOORBELL_KIQ = 0x000,
787 AMDGPU_DOORBELL_HIQ = 0x001,
788 AMDGPU_DOORBELL_DIQ = 0x002,
789 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
790 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
791 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
792 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
793 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
794 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
795 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
796 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
797 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
798 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
799 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
800 AMDGPU_DOORBELL_IH = 0x1E8,
801 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
802 AMDGPU_DOORBELL_INVALID = 0xFFFF
803 } AMDGPU_DOORBELL_ASSIGNMENT;
805 struct amdgpu_doorbell {
807 resource_size_t base;
808 resource_size_t size;
810 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
813 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
814 phys_addr_t *aperture_base,
815 size_t *aperture_size,
816 size_t *start_offset);
822 struct amdgpu_flip_work {
823 struct work_struct flip_work;
824 struct work_struct unpin_work;
825 struct amdgpu_device *adev;
828 struct drm_pending_vblank_event *event;
829 struct amdgpu_bo *old_rbo;
839 struct amdgpu_sa_bo *sa_bo;
843 struct amdgpu_ring *ring;
844 struct amdgpu_fence *fence;
845 struct amdgpu_user_fence *user;
846 struct amdgpu_vm *vm;
847 struct amdgpu_ctx *ctx;
848 struct amdgpu_sync sync;
849 uint32_t gds_base, gds_size;
850 uint32_t gws_base, gws_size;
851 uint32_t oa_base, oa_size;
853 /* resulting sequence number */
857 enum amdgpu_ring_type {
858 AMDGPU_RING_TYPE_GFX,
859 AMDGPU_RING_TYPE_COMPUTE,
860 AMDGPU_RING_TYPE_SDMA,
861 AMDGPU_RING_TYPE_UVD,
865 extern struct amd_sched_backend_ops amdgpu_sched_ops;
868 struct amdgpu_device *adev;
869 const struct amdgpu_ring_funcs *funcs;
870 struct amdgpu_fence_driver fence_drv;
871 struct amd_gpu_scheduler *scheduler;
873 spinlock_t fence_lock;
874 struct mutex *ring_lock;
875 struct amdgpu_bo *ring_obj;
876 volatile uint32_t *ring;
878 u64 next_rptr_gpu_addr;
879 volatile u32 *next_rptr_cpu_addr;
883 unsigned ring_free_dw;
886 atomic64_t last_activity;
893 u64 last_semaphore_signal_addr;
894 u64 last_semaphore_wait_addr;
898 struct amdgpu_bo *mqd_obj;
902 unsigned next_rptr_offs;
904 struct amdgpu_ctx *current_ctx;
905 enum amdgpu_ring_type type;
914 /* maximum number of VMIDs */
915 #define AMDGPU_NUM_VM 16
917 /* number of entries in page table */
918 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size)
920 /* PTBs (Page Table Blocks) need to be aligned to 32K */
921 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768
922 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1)
923 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK)
925 #define AMDGPU_PTE_VALID (1 << 0)
926 #define AMDGPU_PTE_SYSTEM (1 << 1)
927 #define AMDGPU_PTE_SNOOPED (1 << 2)
930 #define AMDGPU_PTE_EXECUTABLE (1 << 4)
932 #define AMDGPU_PTE_READABLE (1 << 5)
933 #define AMDGPU_PTE_WRITEABLE (1 << 6)
935 /* PTE (Page Table Entry) fragment field for different page sizes */
936 #define AMDGPU_PTE_FRAG_4KB (0 << 7)
937 #define AMDGPU_PTE_FRAG_64KB (4 << 7)
938 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
940 struct amdgpu_vm_pt {
941 struct amdgpu_bo *bo;
945 struct amdgpu_vm_id {
947 uint64_t pd_gpu_addr;
948 /* last flushed PD/PT update */
949 struct amdgpu_fence *flushed_updates;
950 /* last use of vmid */
951 struct amdgpu_fence *last_id_use;
959 /* protecting invalidated and freed */
960 spinlock_t status_lock;
962 /* BOs moved, but not yet updated in the PT */
963 struct list_head invalidated;
965 /* BOs freed, but not yet updated in the PT */
966 struct list_head freed;
968 /* contains the page directory */
969 struct amdgpu_bo *page_directory;
970 unsigned max_pde_used;
972 /* array of page tables, one for each page directory entry */
973 struct amdgpu_vm_pt *page_tables;
975 /* for id and flush management per ring */
976 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS];
979 struct amdgpu_vm_manager {
980 struct amdgpu_fence *active[AMDGPU_NUM_VM];
982 /* number of VMIDs */
984 /* vram base address for page table entry */
985 u64 vram_base_offset;
988 /* for hw to save the PD addr on suspend/resume */
989 uint32_t saved_table_addr[AMDGPU_NUM_VM];
990 /* vm pte handling */
991 const struct amdgpu_vm_pte_funcs *vm_pte_funcs;
992 struct amdgpu_ring *vm_pte_funcs_ring;
996 * context related structures
999 #define AMDGPU_CTX_MAX_CS_PENDING 16
1001 struct amdgpu_ctx_ring {
1003 struct fence *fences[AMDGPU_CTX_MAX_CS_PENDING];
1004 struct amd_context_entity c_entity;
1008 struct kref refcount;
1009 struct amdgpu_device *adev;
1010 unsigned reset_counter;
1011 spinlock_t ring_lock;
1012 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
1015 struct amdgpu_ctx_mgr {
1016 struct amdgpu_device *adev;
1018 /* protected by lock */
1019 struct idr ctx_handles;
1022 int amdgpu_ctx_alloc(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
1024 int amdgpu_ctx_free(struct amdgpu_device *adev, struct amdgpu_fpriv *fpriv,
1027 void amdgpu_ctx_fini(struct amdgpu_fpriv *fpriv);
1029 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
1030 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
1032 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
1033 struct fence *fence);
1034 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
1035 struct amdgpu_ring *ring, uint64_t seq);
1037 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
1038 struct drm_file *filp);
1042 * file private structure
1045 struct amdgpu_fpriv {
1046 struct amdgpu_vm vm;
1047 struct mutex bo_list_lock;
1048 struct idr bo_list_handles;
1049 struct amdgpu_ctx_mgr ctx_mgr;
1056 struct amdgpu_bo_list {
1058 struct amdgpu_bo *gds_obj;
1059 struct amdgpu_bo *gws_obj;
1060 struct amdgpu_bo *oa_obj;
1062 unsigned num_entries;
1063 struct amdgpu_bo_list_entry *array;
1066 struct amdgpu_bo_list *
1067 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
1068 void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
1069 void amdgpu_bo_list_copy(struct amdgpu_device *adev,
1070 struct amdgpu_bo_list *dst,
1071 struct amdgpu_bo_list *src);
1072 void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
1077 #include "clearstate_defs.h"
1080 /* for power gating */
1081 struct amdgpu_bo *save_restore_obj;
1082 uint64_t save_restore_gpu_addr;
1083 volatile uint32_t *sr_ptr;
1084 const u32 *reg_list;
1086 /* for clear state */
1087 struct amdgpu_bo *clear_state_obj;
1088 uint64_t clear_state_gpu_addr;
1089 volatile uint32_t *cs_ptr;
1090 const struct cs_section_def *cs_data;
1091 u32 clear_state_size;
1093 struct amdgpu_bo *cp_table_obj;
1094 uint64_t cp_table_gpu_addr;
1095 volatile uint32_t *cp_table_ptr;
1100 struct amdgpu_bo *hpd_eop_obj;
1101 u64 hpd_eop_gpu_addr;
1108 * GPU scratch registers structures, functions & helpers
1110 struct amdgpu_scratch {
1118 * GFX configurations
1120 struct amdgpu_gca_config {
1121 unsigned max_shader_engines;
1122 unsigned max_tile_pipes;
1123 unsigned max_cu_per_sh;
1124 unsigned max_sh_per_se;
1125 unsigned max_backends_per_se;
1126 unsigned max_texture_channel_caches;
1128 unsigned max_gs_threads;
1129 unsigned max_hw_contexts;
1130 unsigned sc_prim_fifo_size_frontend;
1131 unsigned sc_prim_fifo_size_backend;
1132 unsigned sc_hiz_tile_fifo_size;
1133 unsigned sc_earlyz_tile_fifo_size;
1135 unsigned num_tile_pipes;
1136 unsigned backend_enable_mask;
1137 unsigned mem_max_burst_length_bytes;
1138 unsigned mem_row_size_in_kb;
1139 unsigned shader_engine_tile_size;
1141 unsigned multi_gpu_tile_size;
1142 unsigned mc_arb_ramcfg;
1143 unsigned gb_addr_config;
1145 uint32_t tile_mode_array[32];
1146 uint32_t macrotile_mode_array[16];
1150 struct mutex gpu_clock_mutex;
1151 struct amdgpu_gca_config config;
1152 struct amdgpu_rlc rlc;
1153 struct amdgpu_mec mec;
1154 struct amdgpu_scratch scratch;
1155 const struct firmware *me_fw; /* ME firmware */
1156 uint32_t me_fw_version;
1157 const struct firmware *pfp_fw; /* PFP firmware */
1158 uint32_t pfp_fw_version;
1159 const struct firmware *ce_fw; /* CE firmware */
1160 uint32_t ce_fw_version;
1161 const struct firmware *rlc_fw; /* RLC firmware */
1162 uint32_t rlc_fw_version;
1163 const struct firmware *mec_fw; /* MEC firmware */
1164 uint32_t mec_fw_version;
1165 const struct firmware *mec2_fw; /* MEC2 firmware */
1166 uint32_t mec2_fw_version;
1167 uint32_t me_feature_version;
1168 uint32_t ce_feature_version;
1169 uint32_t pfp_feature_version;
1170 uint32_t rlc_feature_version;
1171 uint32_t mec_feature_version;
1172 uint32_t mec2_feature_version;
1173 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1174 unsigned num_gfx_rings;
1175 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1176 unsigned num_compute_rings;
1177 struct amdgpu_irq_src eop_irq;
1178 struct amdgpu_irq_src priv_reg_irq;
1179 struct amdgpu_irq_src priv_inst_irq;
1181 uint32_t gfx_current_status;
1182 /* sync signal for const engine */
1183 unsigned ce_sync_offs;
1185 unsigned ce_ram_size;
1188 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
1189 unsigned size, struct amdgpu_ib *ib);
1190 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib);
1191 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
1192 struct amdgpu_ib *ib, void *owner);
1193 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1194 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1195 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1196 /* Ring access between begin & end cannot sleep */
1197 void amdgpu_ring_free_size(struct amdgpu_ring *ring);
1198 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
1199 int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw);
1200 void amdgpu_ring_commit(struct amdgpu_ring *ring);
1201 void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
1202 void amdgpu_ring_undo(struct amdgpu_ring *ring);
1203 void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
1204 void amdgpu_ring_lockup_update(struct amdgpu_ring *ring);
1205 bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring);
1206 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
1208 int amdgpu_ring_restore(struct amdgpu_ring *ring,
1209 unsigned size, uint32_t *data);
1210 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
1211 unsigned ring_size, u32 nop, u32 align_mask,
1212 struct amdgpu_irq_src *irq_src, unsigned irq_type,
1213 enum amdgpu_ring_type ring_type);
1214 void amdgpu_ring_fini(struct amdgpu_ring *ring);
1219 struct amdgpu_cs_chunk {
1223 void __user *user_ptr;
1226 union amdgpu_sched_job_param {
1228 struct amdgpu_vm *vm;
1231 struct amdgpu_fence **fence;
1235 struct amdgpu_bo *bo;
1239 struct amdgpu_cs_parser {
1240 struct amdgpu_device *adev;
1241 struct drm_file *filp;
1242 struct amdgpu_ctx *ctx;
1243 struct amdgpu_bo_list *bo_list;
1246 struct amdgpu_cs_chunk *chunks;
1248 struct amdgpu_bo_list_entry *vm_bos;
1249 struct list_head validated;
1251 struct amdgpu_ib *ibs;
1254 struct ww_acquire_ctx ticket;
1257 struct amdgpu_user_fence uf;
1259 struct amdgpu_ring *ring;
1260 struct mutex job_lock;
1261 struct work_struct job_work;
1262 int (*prepare_job)(struct amdgpu_cs_parser *sched_job);
1263 union amdgpu_sched_job_param job_param;
1264 int (*run_job)(struct amdgpu_cs_parser *sched_job);
1265 int (*free_job)(struct amdgpu_cs_parser *sched_job);
1268 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
1270 return p->ibs[ib_idx].ptr[idx];
1276 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1279 struct amdgpu_bo *wb_obj;
1280 volatile uint32_t *wb;
1282 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1283 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1286 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1287 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1290 * struct amdgpu_pm - power management datas
1291 * It keeps track of various data needed to take powermanagement decision.
1294 enum amdgpu_pm_state_type {
1295 /* not used for dpm */
1296 POWER_STATE_TYPE_DEFAULT,
1297 POWER_STATE_TYPE_POWERSAVE,
1298 /* user selectable states */
1299 POWER_STATE_TYPE_BATTERY,
1300 POWER_STATE_TYPE_BALANCED,
1301 POWER_STATE_TYPE_PERFORMANCE,
1302 /* internal states */
1303 POWER_STATE_TYPE_INTERNAL_UVD,
1304 POWER_STATE_TYPE_INTERNAL_UVD_SD,
1305 POWER_STATE_TYPE_INTERNAL_UVD_HD,
1306 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
1307 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
1308 POWER_STATE_TYPE_INTERNAL_BOOT,
1309 POWER_STATE_TYPE_INTERNAL_THERMAL,
1310 POWER_STATE_TYPE_INTERNAL_ACPI,
1311 POWER_STATE_TYPE_INTERNAL_ULV,
1312 POWER_STATE_TYPE_INTERNAL_3DPERF,
1315 enum amdgpu_int_thermal_type {
1317 THERMAL_TYPE_EXTERNAL,
1318 THERMAL_TYPE_EXTERNAL_GPIO,
1321 THERMAL_TYPE_ADT7473_WITH_INTERNAL,
1322 THERMAL_TYPE_EVERGREEN,
1326 THERMAL_TYPE_EMC2103_WITH_INTERNAL,
1331 enum amdgpu_dpm_auto_throttle_src {
1332 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
1333 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
1336 enum amdgpu_dpm_event_src {
1337 AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
1338 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
1339 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
1340 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
1341 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
1344 #define AMDGPU_MAX_VCE_LEVELS 6
1346 enum amdgpu_vce_level {
1347 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
1348 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
1349 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
1350 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
1351 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
1352 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
1356 u32 caps; /* vbios flags */
1357 u32 class; /* vbios flags */
1358 u32 class2; /* vbios flags */
1366 enum amdgpu_vce_level vce_level;
1371 struct amdgpu_dpm_thermal {
1372 /* thermal interrupt work */
1373 struct work_struct work;
1374 /* low temperature threshold */
1376 /* high temperature threshold */
1378 /* was last interrupt low to high or high to low */
1380 /* interrupt source */
1381 struct amdgpu_irq_src irq;
1384 enum amdgpu_clk_action
1390 struct amdgpu_blacklist_clocks
1394 enum amdgpu_clk_action action;
1397 struct amdgpu_clock_and_voltage_limits {
1404 struct amdgpu_clock_array {
1409 struct amdgpu_clock_voltage_dependency_entry {
1414 struct amdgpu_clock_voltage_dependency_table {
1416 struct amdgpu_clock_voltage_dependency_entry *entries;
1419 union amdgpu_cac_leakage_entry {
1431 struct amdgpu_cac_leakage_table {
1433 union amdgpu_cac_leakage_entry *entries;
1436 struct amdgpu_phase_shedding_limits_entry {
1442 struct amdgpu_phase_shedding_limits_table {
1444 struct amdgpu_phase_shedding_limits_entry *entries;
1447 struct amdgpu_uvd_clock_voltage_dependency_entry {
1453 struct amdgpu_uvd_clock_voltage_dependency_table {
1455 struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
1458 struct amdgpu_vce_clock_voltage_dependency_entry {
1464 struct amdgpu_vce_clock_voltage_dependency_table {
1466 struct amdgpu_vce_clock_voltage_dependency_entry *entries;
1469 struct amdgpu_ppm_table {
1471 u16 cpu_core_number;
1473 u32 small_ac_platform_tdp;
1475 u32 small_ac_platform_tdc;
1482 struct amdgpu_cac_tdp_table {
1484 u16 configurable_tdp;
1486 u16 battery_power_limit;
1487 u16 small_power_limit;
1488 u16 low_cac_leakage;
1489 u16 high_cac_leakage;
1490 u16 maximum_power_delivery_limit;
1493 struct amdgpu_dpm_dynamic_state {
1494 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
1495 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
1496 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
1497 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
1498 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
1499 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
1500 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
1501 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
1502 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
1503 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
1504 struct amdgpu_clock_array valid_sclk_values;
1505 struct amdgpu_clock_array valid_mclk_values;
1506 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
1507 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
1508 u32 mclk_sclk_ratio;
1509 u32 sclk_mclk_delta;
1510 u16 vddc_vddci_delta;
1511 u16 min_vddc_for_pcie_gen2;
1512 struct amdgpu_cac_leakage_table cac_leakage_table;
1513 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
1514 struct amdgpu_ppm_table *ppm_table;
1515 struct amdgpu_cac_tdp_table *cac_tdp_table;
1518 struct amdgpu_dpm_fan {
1529 u16 default_max_fan_pwm;
1530 u16 default_fan_output_sensitivity;
1531 u16 fan_output_sensitivity;
1532 bool ucode_fan_control;
1535 enum amdgpu_pcie_gen {
1536 AMDGPU_PCIE_GEN1 = 0,
1537 AMDGPU_PCIE_GEN2 = 1,
1538 AMDGPU_PCIE_GEN3 = 2,
1539 AMDGPU_PCIE_GEN_INVALID = 0xffff
1542 enum amdgpu_dpm_forced_level {
1543 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
1544 AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
1545 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
1548 struct amdgpu_vce_state {
1559 struct amdgpu_dpm_funcs {
1560 int (*get_temperature)(struct amdgpu_device *adev);
1561 int (*pre_set_power_state)(struct amdgpu_device *adev);
1562 int (*set_power_state)(struct amdgpu_device *adev);
1563 void (*post_set_power_state)(struct amdgpu_device *adev);
1564 void (*display_configuration_changed)(struct amdgpu_device *adev);
1565 u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
1566 u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
1567 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
1568 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
1569 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
1570 bool (*vblank_too_short)(struct amdgpu_device *adev);
1571 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
1572 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
1573 void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
1574 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
1575 u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
1576 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
1577 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
1581 struct amdgpu_ps *ps;
1582 /* number of valid power states */
1584 /* current power state that is active */
1585 struct amdgpu_ps *current_ps;
1586 /* requested power state */
1587 struct amdgpu_ps *requested_ps;
1588 /* boot up power state */
1589 struct amdgpu_ps *boot_ps;
1590 /* default uvd power state */
1591 struct amdgpu_ps *uvd_ps;
1592 /* vce requirements */
1593 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS];
1594 enum amdgpu_vce_level vce_level;
1595 enum amdgpu_pm_state_type state;
1596 enum amdgpu_pm_state_type user_state;
1598 u32 voltage_response_time;
1599 u32 backbias_response_time;
1601 u32 new_active_crtcs;
1602 int new_active_crtc_count;
1603 u32 current_active_crtcs;
1604 int current_active_crtc_count;
1605 struct amdgpu_dpm_dynamic_state dyn_state;
1606 struct amdgpu_dpm_fan fan;
1609 u32 near_tdp_limit_adjusted;
1610 u32 sq_ramping_threshold;
1614 u16 load_line_slope;
1617 /* special states active */
1618 bool thermal_active;
1621 /* thermal handling */
1622 struct amdgpu_dpm_thermal thermal;
1624 enum amdgpu_dpm_forced_level forced_level;
1633 struct amdgpu_i2c_chan *i2c_bus;
1634 /* internal thermal controller on rv6xx+ */
1635 enum amdgpu_int_thermal_type int_thermal_type;
1636 struct device *int_hwmon_dev;
1637 /* fan control parameters */
1639 u8 fan_pulses_per_revolution;
1644 struct amdgpu_dpm dpm;
1645 const struct firmware *fw; /* SMC firmware */
1646 uint32_t fw_version;
1647 const struct amdgpu_dpm_funcs *funcs;
1653 #define AMDGPU_MAX_UVD_HANDLES 10
1654 #define AMDGPU_UVD_STACK_SIZE (1024*1024)
1655 #define AMDGPU_UVD_HEAP_SIZE (1024*1024)
1656 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1659 struct amdgpu_bo *vcpu_bo;
1663 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1664 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1665 struct delayed_work idle_work;
1666 const struct firmware *fw; /* UVD firmware */
1667 struct amdgpu_ring ring;
1668 struct amdgpu_irq_src irq;
1669 bool address_64_bit;
1675 #define AMDGPU_MAX_VCE_HANDLES 16
1676 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1678 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1679 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1682 struct amdgpu_bo *vcpu_bo;
1684 unsigned fw_version;
1685 unsigned fb_version;
1686 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1687 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
1688 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
1689 struct delayed_work idle_work;
1690 const struct firmware *fw; /* VCE firmware */
1691 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1692 struct amdgpu_irq_src irq;
1693 unsigned harvest_config;
1699 struct amdgpu_sdma {
1701 const struct firmware *fw;
1702 uint32_t fw_version;
1703 uint32_t feature_version;
1705 struct amdgpu_ring ring;
1711 struct amdgpu_firmware {
1712 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1714 struct amdgpu_bo *fw_buf;
1715 unsigned int fw_size;
1721 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1727 void amdgpu_test_moves(struct amdgpu_device *adev);
1728 void amdgpu_test_ring_sync(struct amdgpu_device *adev,
1729 struct amdgpu_ring *cpA,
1730 struct amdgpu_ring *cpB);
1731 void amdgpu_test_syncing(struct amdgpu_device *adev);
1736 #if defined(CONFIG_MMU_NOTIFIER)
1737 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1738 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1740 static int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1744 static void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1750 struct amdgpu_debugfs {
1751 struct drm_info_list *files;
1755 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1756 struct drm_info_list *files,
1758 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1760 #if defined(CONFIG_DEBUG_FS)
1761 int amdgpu_debugfs_init(struct drm_minor *minor);
1762 void amdgpu_debugfs_cleanup(struct drm_minor *minor);
1766 * amdgpu smumgr functions
1768 struct amdgpu_smumgr_funcs {
1769 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1770 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1771 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1777 struct amdgpu_smumgr {
1778 struct amdgpu_bo *toc_buf;
1779 struct amdgpu_bo *smu_buf;
1780 /* asic priv smu data */
1782 spinlock_t smu_lock;
1783 /* smumgr functions */
1784 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1785 /* ucode loading complete flag */
1790 * ASIC specific register table accessible by UMD
1792 struct amdgpu_allowed_register_entry {
1793 uint32_t reg_offset;
1798 struct amdgpu_cu_info {
1799 uint32_t number; /* total active CU number */
1800 uint32_t ao_cu_mask;
1801 uint32_t bitmap[4][4];
1806 * ASIC specific functions.
1808 struct amdgpu_asic_funcs {
1809 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1810 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1811 u32 sh_num, u32 reg_offset, u32 *value);
1812 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1813 int (*reset)(struct amdgpu_device *adev);
1814 /* wait for mc_idle */
1815 int (*wait_for_mc_idle)(struct amdgpu_device *adev);
1816 /* get the reference clock */
1817 u32 (*get_xclk)(struct amdgpu_device *adev);
1818 /* get the gpu clock counter */
1819 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
1820 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info);
1821 /* MM block clocks */
1822 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1823 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1829 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1830 struct drm_file *filp);
1831 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1832 struct drm_file *filp);
1834 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1835 struct drm_file *filp);
1836 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1837 struct drm_file *filp);
1838 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1839 struct drm_file *filp);
1840 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1841 struct drm_file *filp);
1842 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1843 struct drm_file *filp);
1844 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1845 struct drm_file *filp);
1846 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1847 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1849 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1850 struct drm_file *filp);
1852 /* VRAM scratch page for HDP bug, default vram page */
1853 struct amdgpu_vram_scratch {
1854 struct amdgpu_bo *robj;
1855 volatile uint32_t *ptr;
1862 struct amdgpu_atif_notification_cfg {
1867 struct amdgpu_atif_notifications {
1868 bool display_switch;
1869 bool expansion_mode_change;
1871 bool forced_power_state;
1872 bool system_power_state;
1873 bool display_conf_change;
1875 bool brightness_change;
1876 bool dgpu_display_event;
1879 struct amdgpu_atif_functions {
1881 bool sbios_requests;
1882 bool select_active_disp;
1884 bool get_tv_standard;
1885 bool set_tv_standard;
1886 bool get_panel_expansion_mode;
1887 bool set_panel_expansion_mode;
1888 bool temperature_change;
1889 bool graphics_device_types;
1892 struct amdgpu_atif {
1893 struct amdgpu_atif_notifications notifications;
1894 struct amdgpu_atif_functions functions;
1895 struct amdgpu_atif_notification_cfg notification_cfg;
1896 struct amdgpu_encoder *encoder_for_bl;
1899 struct amdgpu_atcs_functions {
1903 bool pcie_bus_width;
1906 struct amdgpu_atcs {
1907 struct amdgpu_atcs_functions functions;
1913 void *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1914 void amdgpu_cgs_destroy_device(void *cgs_device);
1918 * Core structure, functions and helpers.
1920 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1921 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1923 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1924 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1926 struct amdgpu_ip_block_status {
1932 struct amdgpu_device {
1934 struct drm_device *ddev;
1935 struct pci_dev *pdev;
1936 struct rw_semaphore exclusive_lock;
1939 enum amd_asic_type asic_type;
1942 uint32_t external_rev_id;
1943 unsigned long flags;
1945 const struct amdgpu_asic_funcs *asic_funcs;
1951 struct work_struct reset_work;
1952 struct notifier_block acpi_nb;
1953 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1954 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1955 unsigned debugfs_count;
1956 #if defined(CONFIG_DEBUG_FS)
1957 struct dentry *debugfs_regs;
1959 struct amdgpu_atif atif;
1960 struct amdgpu_atcs atcs;
1961 struct mutex srbm_mutex;
1962 /* GRBM index mutex. Protects concurrent access to GRBM index */
1963 struct mutex grbm_idx_mutex;
1964 struct dev_pm_domain vga_pm_domain;
1965 bool have_disp_power_ref;
1970 uint16_t bios_header_start;
1971 struct amdgpu_bo *stollen_vga_memory;
1972 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1974 /* Register/doorbell mmio */
1975 resource_size_t rmmio_base;
1976 resource_size_t rmmio_size;
1977 void __iomem *rmmio;
1978 /* protects concurrent MM_INDEX/DATA based register access */
1979 spinlock_t mmio_idx_lock;
1980 /* protects concurrent SMC based register access */
1981 spinlock_t smc_idx_lock;
1982 amdgpu_rreg_t smc_rreg;
1983 amdgpu_wreg_t smc_wreg;
1984 /* protects concurrent PCIE register access */
1985 spinlock_t pcie_idx_lock;
1986 amdgpu_rreg_t pcie_rreg;
1987 amdgpu_wreg_t pcie_wreg;
1988 /* protects concurrent UVD register access */
1989 spinlock_t uvd_ctx_idx_lock;
1990 amdgpu_rreg_t uvd_ctx_rreg;
1991 amdgpu_wreg_t uvd_ctx_wreg;
1992 /* protects concurrent DIDT register access */
1993 spinlock_t didt_idx_lock;
1994 amdgpu_rreg_t didt_rreg;
1995 amdgpu_wreg_t didt_wreg;
1996 /* protects concurrent ENDPOINT (audio) register access */
1997 spinlock_t audio_endpt_idx_lock;
1998 amdgpu_block_rreg_t audio_endpt_rreg;
1999 amdgpu_block_wreg_t audio_endpt_wreg;
2000 void __iomem *rio_mem;
2001 resource_size_t rio_mem_size;
2002 struct amdgpu_doorbell doorbell;
2004 /* clock/pll info */
2005 struct amdgpu_clock clock;
2008 struct amdgpu_mc mc;
2009 struct amdgpu_gart gart;
2010 struct amdgpu_dummy_page dummy_page;
2011 struct amdgpu_vm_manager vm_manager;
2013 /* memory management */
2014 struct amdgpu_mman mman;
2015 struct amdgpu_gem gem;
2016 struct amdgpu_vram_scratch vram_scratch;
2017 struct amdgpu_wb wb;
2018 atomic64_t vram_usage;
2019 atomic64_t vram_vis_usage;
2020 atomic64_t gtt_usage;
2021 atomic64_t num_bytes_moved;
2022 atomic_t gpu_reset_counter;
2025 struct amdgpu_mode_info mode_info;
2026 struct work_struct hotplug_work;
2027 struct amdgpu_irq_src crtc_irq;
2028 struct amdgpu_irq_src pageflip_irq;
2029 struct amdgpu_irq_src hpd_irq;
2032 wait_queue_head_t fence_queue;
2033 unsigned fence_context;
2034 struct mutex ring_lock;
2036 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
2038 struct amdgpu_sa_manager ring_tmp_bo;
2041 struct amdgpu_irq irq;
2044 struct amdgpu_pm pm;
2049 struct amdgpu_smumgr smu;
2052 struct amdgpu_gfx gfx;
2055 struct amdgpu_sdma sdma[2];
2056 struct amdgpu_irq_src sdma_trap_irq;
2057 struct amdgpu_irq_src sdma_illegal_inst_irq;
2061 struct amdgpu_uvd uvd;
2064 struct amdgpu_vce vce;
2067 struct amdgpu_firmware firmware;
2070 struct amdgpu_gds gds;
2072 const struct amdgpu_ip_block_version *ip_blocks;
2074 struct amdgpu_ip_block_status *ip_block_status;
2075 struct mutex mn_lock;
2076 DECLARE_HASHTABLE(mn_hash, 7);
2078 /* tracking pinned memory */
2082 /* amdkfd interface */
2083 struct kfd_dev *kfd;
2085 /* kernel conext for IB submission */
2086 struct amdgpu_ctx *kernel_ctx;
2089 bool amdgpu_device_is_px(struct drm_device *dev);
2090 int amdgpu_device_init(struct amdgpu_device *adev,
2091 struct drm_device *ddev,
2092 struct pci_dev *pdev,
2094 void amdgpu_device_fini(struct amdgpu_device *adev);
2095 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
2097 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
2098 bool always_indirect);
2099 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
2100 bool always_indirect);
2101 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
2102 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
2104 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
2105 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
2110 extern const struct fence_ops amdgpu_fence_ops;
2111 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f)
2113 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
2115 if (__f->base.ops == &amdgpu_fence_ops)
2122 * Registers read & write functions.
2124 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false)
2125 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true)
2126 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false))
2127 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false)
2128 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true)
2129 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2130 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
2131 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
2132 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
2133 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
2134 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
2135 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
2136 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
2137 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
2138 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
2139 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
2140 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
2141 #define WREG32_P(reg, val, mask) \
2143 uint32_t tmp_ = RREG32(reg); \
2145 tmp_ |= ((val) & ~(mask)); \
2146 WREG32(reg, tmp_); \
2148 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2149 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
2150 #define WREG32_PLL_P(reg, val, mask) \
2152 uint32_t tmp_ = RREG32_PLL(reg); \
2154 tmp_ |= ((val) & ~(mask)); \
2155 WREG32_PLL(reg, tmp_); \
2157 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
2158 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
2159 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
2161 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
2162 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
2164 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
2165 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
2167 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
2168 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
2169 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
2171 #define REG_GET_FIELD(value, reg, field) \
2172 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
2177 #define RBIOS8(i) (adev->bios[i])
2178 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
2179 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
2184 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
2186 if (ring->count_dw <= 0)
2187 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
2188 ring->ring[ring->wptr++] = v;
2189 ring->wptr &= ring->ptr_mask;
2191 ring->ring_free_dw--;
2197 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
2198 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
2199 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev))
2200 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
2201 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
2202 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
2203 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
2204 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
2205 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
2206 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info))
2207 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
2208 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
2209 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
2210 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags)))
2211 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
2212 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib)))
2213 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
2214 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
2215 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
2216 #define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r))
2217 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
2218 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
2219 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
2220 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib))
2221 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
2222 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
2223 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait))
2224 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
2225 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
2226 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
2227 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
2228 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
2229 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
2230 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
2231 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
2232 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev))
2233 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
2234 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
2235 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
2236 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
2237 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
2238 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
2239 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base))
2240 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
2241 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
2242 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
2243 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
2244 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
2245 #define amdgpu_emit_copy_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((r), (s), (d), (b))
2246 #define amdgpu_emit_fill_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((r), (s), (d), (b))
2247 #define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev))
2248 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
2249 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
2250 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
2251 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
2252 #define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l))
2253 #define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l))
2254 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
2255 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m))
2256 #define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l))
2257 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
2258 #define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g))
2259 #define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g))
2260 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
2261 #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m))
2262 #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev))
2263 #define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s))
2264 #define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s))
2266 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
2268 /* Common functions */
2269 int amdgpu_gpu_reset(struct amdgpu_device *adev);
2270 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
2271 bool amdgpu_card_posted(struct amdgpu_device *adev);
2272 void amdgpu_update_display_priority(struct amdgpu_device *adev);
2273 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev);
2274 struct amdgpu_cs_parser *amdgpu_cs_parser_create(struct amdgpu_device *adev,
2275 struct drm_file *filp,
2276 struct amdgpu_ctx *ctx,
2277 struct amdgpu_ib *ibs,
2280 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
2281 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
2282 u32 ip_instance, u32 ring,
2283 struct amdgpu_ring **out_ring);
2284 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
2285 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
2286 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
2288 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
2289 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
2290 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
2291 struct ttm_mem_reg *mem);
2292 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
2293 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
2294 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
2295 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
2296 const u32 *registers,
2297 const u32 array_size);
2299 bool amdgpu_device_is_px(struct drm_device *dev);
2301 #if defined(CONFIG_VGA_SWITCHEROO)
2302 void amdgpu_register_atpx_handler(void);
2303 void amdgpu_unregister_atpx_handler(void);
2305 static inline void amdgpu_register_atpx_handler(void) {}
2306 static inline void amdgpu_unregister_atpx_handler(void) {}
2312 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
2313 extern int amdgpu_max_kms_ioctl;
2315 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
2316 int amdgpu_driver_unload_kms(struct drm_device *dev);
2317 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
2318 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
2319 void amdgpu_driver_postclose_kms(struct drm_device *dev,
2320 struct drm_file *file_priv);
2321 void amdgpu_driver_preclose_kms(struct drm_device *dev,
2322 struct drm_file *file_priv);
2323 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
2324 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
2325 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc);
2326 int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc);
2327 void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc);
2328 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
2330 struct timeval *vblank_time,
2332 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
2338 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2339 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
2340 struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
2341 struct amdgpu_vm *vm,
2342 struct list_head *head);
2343 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
2344 struct amdgpu_sync *sync);
2345 void amdgpu_vm_flush(struct amdgpu_ring *ring,
2346 struct amdgpu_vm *vm,
2347 struct amdgpu_fence *updates);
2348 void amdgpu_vm_fence(struct amdgpu_device *adev,
2349 struct amdgpu_vm *vm,
2350 struct amdgpu_fence *fence);
2351 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr);
2352 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
2353 struct amdgpu_vm *vm);
2354 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2355 struct amdgpu_vm *vm);
2356 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
2357 struct amdgpu_vm *vm, struct amdgpu_sync *sync);
2358 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
2359 struct amdgpu_bo_va *bo_va,
2360 struct ttm_mem_reg *mem);
2361 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2362 struct amdgpu_bo *bo);
2363 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
2364 struct amdgpu_bo *bo);
2365 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2366 struct amdgpu_vm *vm,
2367 struct amdgpu_bo *bo);
2368 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2369 struct amdgpu_bo_va *bo_va,
2370 uint64_t addr, uint64_t offset,
2371 uint64_t size, uint32_t flags);
2372 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2373 struct amdgpu_bo_va *bo_va,
2375 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2376 struct amdgpu_bo_va *bo_va);
2379 * functions used by amdgpu_encoder.c
2381 struct amdgpu_afmt_acr {
2395 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
2398 #if defined(CONFIG_ACPI)
2399 int amdgpu_acpi_init(struct amdgpu_device *adev);
2400 void amdgpu_acpi_fini(struct amdgpu_device *adev);
2401 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
2402 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
2403 u8 perf_req, bool advertise);
2404 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
2406 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
2407 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
2410 struct amdgpu_bo_va_mapping *
2411 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
2412 uint64_t addr, struct amdgpu_bo **bo);
2414 #include "amdgpu_object.h"