drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <glisse@freedesktop.org>
  26  */
  27 #include <linux/list_sort.h>
  28 #include <drm/drmP.h>
  29 #include <drm/amdgpu_drm.h>
  30 #include "amdgpu.h"
  31 #include "amdgpu_trace.h"
  32
  33 #define AMDGPU_CS_MAX_PRIORITY          32u
  34 #define AMDGPU_CS_NUM_BUCKETS           (AMDGPU_CS_MAX_PRIORITY + 1)
  35
  36 /* This is based on the bucket sort with O(n) time complexity.
  37  * An item with priority "i" is added to bucket[i]. The lists are then
  38  * concatenated in descending order.
  39  */
  40 struct amdgpu_cs_buckets {
  41         struct list_head bucket[AMDGPU_CS_NUM_BUCKETS];
  42 };
  43
  44 static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b)
  45 {
  46         unsigned i;
  47
  48         for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++)
  49                 INIT_LIST_HEAD(&b->bucket[i]);
  50 }
  51
  52 static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b,
  53                                   struct list_head *item, unsigned priority)
  54 {
  55         /* Since buffers which appear sooner in the relocation list are
  56          * likely to be used more often than buffers which appear later
  57          * in the list, the sort mustn't change the ordering of buffers
  58          * with the same priority, i.e. it must be stable.
  59          */
  60         list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]);
  61 }
  62
  63 static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b,
  64                                        struct list_head *out_list)
  65 {
  66         unsigned i;
  67
  68         /* Connect the sorted buckets in the output list. */
  69         for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) {
  70                 list_splice(&b->bucket[i], out_list);
  71         }
  72 }
  73
  74 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
  75                        u32 ip_instance, u32 ring,
  76                        struct amdgpu_ring **out_ring)
  77 {
  78         /* Right now all IPs have only one instance - multiple rings. */
  79         if (ip_instance != 0) {
  80                 DRM_ERROR("invalid ip instance: %d\n", ip_instance);
  81                 return -EINVAL;
  82         }
  83
  84         switch (ip_type) {
  85         default:
  86                 DRM_ERROR("unknown ip type: %d\n", ip_type);
  87                 return -EINVAL;
  88         case AMDGPU_HW_IP_GFX:
  89                 if (ring < adev->gfx.num_gfx_rings) {
  90                         *out_ring = &adev->gfx.gfx_ring[ring];
  91                 } else {
  92                         DRM_ERROR("only %d gfx rings are supported now\n",
  93                                   adev->gfx.num_gfx_rings);
  94                         return -EINVAL;
  95                 }
  96                 break;
  97         case AMDGPU_HW_IP_COMPUTE:
  98                 if (ring < adev->gfx.num_compute_rings) {
  99                         *out_ring = &adev->gfx.compute_ring[ring];
 100                 } else {
 101                         DRM_ERROR("only %d compute rings are supported now\n",
 102                                   adev->gfx.num_compute_rings);
 103                         return -EINVAL;
 104                 }
 105                 break;
 106         case AMDGPU_HW_IP_DMA:
 107                 if (ring < 2) {
 108                         *out_ring = &adev->sdma[ring].ring;
 109                 } else {
 110                         DRM_ERROR("only two SDMA rings are supported\n");
 111                         return -EINVAL;
 112                 }
 113                 break;
 114         case AMDGPU_HW_IP_UVD:
 115                 *out_ring = &adev->uvd.ring;
 116                 break;
 117         case AMDGPU_HW_IP_VCE:
 118                 if (ring < 2){
 119                         *out_ring = &adev->vce.ring[ring];
 120                 } else {
 121                         DRM_ERROR("only two VCE rings are supported\n");
 122                         return -EINVAL;
 123                 }
 124                 break;
 125         }
 126         return 0;
 127 }
 128
 129 static void amdgpu_job_work_func(struct work_struct *work)
 130 {
 131         struct amdgpu_cs_parser *sched_job =
 132                 container_of(work, struct amdgpu_cs_parser,
 133                              job_work);
 134         mutex_lock(&sched_job->job_lock);
 135         if (sched_job->free_job)
 136                 sched_job->free_job(sched_job);
 137         mutex_unlock(&sched_job->job_lock);
 138         /* after processing job, free memory */
 139         fence_put(&sched_job->s_fence->base);
 140         kfree(sched_job);
 141 }
 142 struct amdgpu_cs_parser *amdgpu_cs_parser_create(struct amdgpu_device *adev,
 143                                                struct drm_file *filp,
 144                                                struct amdgpu_ctx *ctx,
 145                                                struct amdgpu_ib *ibs,
 146                                                uint32_t num_ibs)
 147 {
 148         struct amdgpu_cs_parser *parser;
 149         int i;
 150
 151         parser = kzalloc(sizeof(struct amdgpu_cs_parser), GFP_KERNEL);
 152         if (!parser)
 153                 return NULL;
 154
 155         parser->adev = adev;
 156         parser->filp = filp;
 157         parser->ctx = ctx;
 158         parser->ibs = ibs;
 159         parser->num_ibs = num_ibs;
 160         if (amdgpu_enable_scheduler) {
 161                 mutex_init(&parser->job_lock);
 162                 INIT_WORK(&parser->job_work, amdgpu_job_work_func);
 163         }
 164         for (i = 0; i < num_ibs; i++)
 165                 ibs[i].ctx = ctx;
 166
 167         return parser;
 168 }
 169
 170 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
 171 {
 172         union drm_amdgpu_cs *cs = data;
 173         uint64_t *chunk_array_user;
 174         uint64_t *chunk_array = NULL;
 175         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 176         struct amdgpu_bo_list *bo_list = NULL;
 177         unsigned size, i;
 178         int r = 0;
 179
 180         if (!cs->in.num_chunks)
 181                 goto out;
 182
 183         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 184         if (!p->ctx) {
 185                 r = -EINVAL;
 186                 goto out;
 187         }
 188         bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
 189         if (!amdgpu_enable_scheduler)
 190                 p->bo_list = bo_list;
 191         else {
 192                 if (bo_list && !bo_list->has_userptr) {
 193                         p->bo_list = amdgpu_bo_list_clone(bo_list);
 194                         amdgpu_bo_list_put(bo_list);
 195                         if (!p->bo_list)
 196                                 return -ENOMEM;
 197                 } else if (bo_list && bo_list->has_userptr)
 198                         p->bo_list = bo_list;
 199                 else
 200                         p->bo_list = NULL;
 201         }
 202
 203         /* get chunks */
 204         INIT_LIST_HEAD(&p->validated);
 205         chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 206         if (chunk_array == NULL) {
 207                 r = -ENOMEM;
 208                 goto out;
 209         }
 210
 211         chunk_array_user = (uint64_t __user *)(cs->in.chunks);
 212         if (copy_from_user(chunk_array, chunk_array_user,
 213                            sizeof(uint64_t)*cs->in.num_chunks)) {
 214                 r = -EFAULT;
 215                 goto out;
 216         }
 217
 218         p->nchunks = cs->in.num_chunks;
 219         p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 220                             GFP_KERNEL);
 221         if (p->chunks == NULL) {
 222                 r = -ENOMEM;
 223                 goto out;
 224         }
 225
 226         for (i = 0; i < p->nchunks; i++) {
 227                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 228                 struct drm_amdgpu_cs_chunk user_chunk;
 229                 uint32_t __user *cdata;
 230
 231                 chunk_ptr = (void __user *)chunk_array[i];
 232                 if (copy_from_user(&user_chunk, chunk_ptr,
 233                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 234                         r = -EFAULT;
 235                         goto out;
 236                 }
 237                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 238                 p->chunks[i].length_dw = user_chunk.length_dw;
 239
 240                 size = p->chunks[i].length_dw;
 241                 cdata = (void __user *)user_chunk.chunk_data;
 242                 p->chunks[i].user_ptr = cdata;
 243
 244                 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
 245                 if (p->chunks[i].kdata == NULL) {
 246                         r = -ENOMEM;
 247                         goto out;
 248                 }
 249                 size *= sizeof(uint32_t);
 250                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 251                         r = -EFAULT;
 252                         goto out;
 253                 }
 254
 255                 switch (p->chunks[i].chunk_id) {
 256                 case AMDGPU_CHUNK_ID_IB:
 257                         p->num_ibs++;
 258                         break;
 259
 260                 case AMDGPU_CHUNK_ID_FENCE:
 261                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 262                         if (p->chunks[i].length_dw * sizeof(uint32_t) >= size) {
 263                                 uint32_t handle;
 264                                 struct drm_gem_object *gobj;
 265                                 struct drm_amdgpu_cs_chunk_fence *fence_data;
 266
 267                                 fence_data = (void *)p->chunks[i].kdata;
 268                                 handle = fence_data->handle;
 269                                 gobj = drm_gem_object_lookup(p->adev->ddev,
 270                                                              p->filp, handle);
 271                                 if (gobj == NULL) {
 272                                         r = -EINVAL;
 273                                         goto out;
 274                                 }
 275
 276                                 p->uf.bo = gem_to_amdgpu_bo(gobj);
 277                                 p->uf.offset = fence_data->offset;
 278                         } else {
 279                                 r = -EINVAL;
 280                                 goto out;
 281                         }
 282                         break;
 283
 284                 case AMDGPU_CHUNK_ID_DEPENDENCIES:
 285                         break;
 286
 287                 default:
 288                         r = -EINVAL;
 289                         goto out;
 290                 }
 291         }
 292
 293
 294         p->ibs = kmalloc_array(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL);
 295         if (!p->ibs)
 296                 r = -ENOMEM;
 297
 298 out:
 299         kfree(chunk_array);
 300         return r;
 301 }
 302
 303 /* Returns how many bytes TTM can move per IB.
 304  */
 305 static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
 306 {
 307         u64 real_vram_size = adev->mc.real_vram_size;
 308         u64 vram_usage = atomic64_read(&adev->vram_usage);
 309
 310         /* This function is based on the current VRAM usage.
 311          *
 312          * - If all of VRAM is free, allow relocating the number of bytes that
 313          *   is equal to 1/4 of the size of VRAM for this IB.
 314
 315          * - If more than one half of VRAM is occupied, only allow relocating
 316          *   1 MB of data for this IB.
 317          *
 318          * - From 0 to one half of used VRAM, the threshold decreases
 319          *   linearly.
 320          *         __________________
 321          * 1/4 of -|\               |
 322          * VRAM    | \              |
 323          *         |  \             |
 324          *         |   \            |
 325          *         |    \           |
 326          *         |     \          |
 327          *         |      \         |
 328          *         |       \________|1 MB
 329          *         |----------------|
 330          *    VRAM 0 %             100 %
 331          *         used            used
 332          *
 333          * Note: It's a threshold, not a limit. The threshold must be crossed
 334          * for buffer relocations to stop, so any buffer of an arbitrary size
 335          * can be moved as long as the threshold isn't crossed before
 336          * the relocation takes place. We don't want to disable buffer
 337          * relocations completely.
 338          *
 339          * The idea is that buffers should be placed in VRAM at creation time
 340          * and TTM should only do a minimum number of relocations during
 341          * command submission. In practice, you need to submit at least
 342          * a dozen IBs to move all buffers to VRAM if they are in GTT.
 343          *
 344          * Also, things can get pretty crazy under memory pressure and actual
 345          * VRAM usage can change a lot, so playing safe even at 50% does
 346          * consistently increase performance.
 347          */
 348
 349         u64 half_vram = real_vram_size >> 1;
 350         u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
 351         u64 bytes_moved_threshold = half_free_vram >> 1;
 352         return max(bytes_moved_threshold, 1024*1024ull);
 353 }
 354
 355 int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p)
 356 {
 357         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 358         struct amdgpu_vm *vm = &fpriv->vm;
 359         struct amdgpu_device *adev = p->adev;
 360         struct amdgpu_bo_list_entry *lobj;
 361         struct list_head duplicates;
 362         struct amdgpu_bo *bo;
 363         u64 bytes_moved = 0, initial_bytes_moved;
 364         u64 bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(adev);
 365         int r;
 366
 367         INIT_LIST_HEAD(&duplicates);
 368         r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates);
 369         if (unlikely(r != 0)) {
 370                 return r;
 371         }
 372
 373         list_for_each_entry(lobj, &p->validated, tv.head) {
 374                 bo = lobj->robj;
 375                 if (!bo->pin_count) {
 376                         u32 domain = lobj->prefered_domains;
 377                         u32 current_domain =
 378                                 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 379
 380                         /* Check if this buffer will be moved and don't move it
 381                          * if we have moved too many buffers for this IB already.
 382                          *
 383                          * Note that this allows moving at least one buffer of
 384                          * any size, because it doesn't take the current "bo"
 385                          * into account. We don't want to disallow buffer moves
 386                          * completely.
 387                          */
 388                         if (current_domain != AMDGPU_GEM_DOMAIN_CPU &&
 389                             (domain & current_domain) == 0 && /* will be moved */
 390                             bytes_moved > bytes_moved_threshold) {
 391                                 /* don't move it */
 392                                 domain = current_domain;
 393                         }
 394
 395                 retry:
 396                         amdgpu_ttm_placement_from_domain(bo, domain);
 397                         initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 398                         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 399                         bytes_moved += atomic64_read(&adev->num_bytes_moved) -
 400                                        initial_bytes_moved;
 401
 402                         if (unlikely(r)) {
 403                                 if (r != -ERESTARTSYS && domain != lobj->allowed_domains) {
 404                                         domain = lobj->allowed_domains;
 405                                         goto retry;
 406                                 }
 407                                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 408                                 return r;
 409                         }
 410                 }
 411                 lobj->bo_va = amdgpu_vm_bo_find(vm, bo);
 412         }
 413         return 0;
 414 }
 415
 416 static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
 417 {
 418         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 419         struct amdgpu_cs_buckets buckets;
 420         bool need_mmap_lock = false;
 421         int i, r;
 422
 423         if (p->bo_list) {
 424                 need_mmap_lock = p->bo_list->has_userptr;
 425                 amdgpu_cs_buckets_init(&buckets);
 426                 for (i = 0; i < p->bo_list->num_entries; i++)
 427                         amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head,
 428                                                                   p->bo_list->array[i].priority);
 429
 430                 amdgpu_cs_buckets_get_list(&buckets, &p->validated);
 431         }
 432
 433         p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm,
 434                                       &p->validated);
 435
 436         if (need_mmap_lock)
 437                 down_read(&current->mm->mmap_sem);
 438
 439         r = amdgpu_cs_list_validate(p);
 440
 441         if (need_mmap_lock)
 442                 up_read(&current->mm->mmap_sem);
 443
 444         return r;
 445 }
 446
 447 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 448 {
 449         struct amdgpu_bo_list_entry *e;
 450         int r;
 451
 452         list_for_each_entry(e, &p->validated, tv.head) {
 453                 struct reservation_object *resv = e->robj->tbo.resv;
 454                 r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp);
 455
 456                 if (r)
 457                         return r;
 458         }
 459         return 0;
 460 }
 461
 462 static int cmp_size_smaller_first(void *priv, struct list_head *a,
 463                                   struct list_head *b)
 464 {
 465         struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head);
 466         struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head);
 467
 468         /* Sort A before B if A is smaller. */
 469         return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
 470 }
 471
 472 static void amdgpu_cs_parser_fini_early(struct amdgpu_cs_parser *parser, int error, bool backoff)
 473 {
 474         if (!error) {
 475                 /* Sort the buffer list from the smallest to largest buffer,
 476                  * which affects the order of buffers in the LRU list.
 477                  * This assures that the smallest buffers are added first
 478                  * to the LRU list, so they are likely to be later evicted
 479                  * first, instead of large buffers whose eviction is more
 480                  * expensive.
 481                  *
 482                  * This slightly lowers the number of bytes moved by TTM
 483                  * per frame under memory pressure.
 484                  */
 485                 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
 486
 487                 ttm_eu_fence_buffer_objects(&parser->ticket,
 488                                 &parser->validated,
 489                                 &parser->ibs[parser->num_ibs-1].fence->base);
 490         } else if (backoff) {
 491                 ttm_eu_backoff_reservation(&parser->ticket,
 492                                            &parser->validated);
 493         }
 494 }
 495
 496 static void amdgpu_cs_parser_fini_late(struct amdgpu_cs_parser *parser)
 497 {
 498         unsigned i;
 499         if (parser->ctx)
 500                 amdgpu_ctx_put(parser->ctx);
 501         if (parser->bo_list) {
 502                 if (amdgpu_enable_scheduler && !parser->bo_list->has_userptr)
 503                         amdgpu_bo_list_free(parser->bo_list);
 504                 else
 505                         amdgpu_bo_list_put(parser->bo_list);
 506         }
 507         drm_free_large(parser->vm_bos);
 508         for (i = 0; i < parser->nchunks; i++)
 509                 drm_free_large(parser->chunks[i].kdata);
 510         kfree(parser->chunks);
 511         if (parser->ibs)
 512                 for (i = 0; i < parser->num_ibs; i++)
 513                         amdgpu_ib_free(parser->adev, &parser->ibs[i]);
 514         kfree(parser->ibs);
 515         if (parser->uf.bo)
 516                 drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base);
 517
 518         if (!amdgpu_enable_scheduler)
 519                 kfree(parser);
 520 }
 521
 522 /**
 523  * cs_parser_fini() - clean parser states
 524  * @parser:     parser structure holding parsing context.
 525  * @error:      error number
 526  *
 527  * If error is set than unvalidate buffer, otherwise just free memory
 528  * used by parsing context.
 529  **/
 530 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
 531 {
 532        amdgpu_cs_parser_fini_early(parser, error, backoff);
 533        amdgpu_cs_parser_fini_late(parser);
 534 }
 535
 536 static int amdgpu_cs_parser_free_job(struct amdgpu_cs_parser *sched_job)
 537 {
 538        amdgpu_cs_parser_fini_late(sched_job);
 539        return 0;
 540 }
 541
 542 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
 543                                    struct amdgpu_vm *vm)
 544 {
 545         struct amdgpu_device *adev = p->adev;
 546         struct amdgpu_bo_va *bo_va;
 547         struct amdgpu_bo *bo;
 548         int i, r;
 549
 550         r = amdgpu_vm_update_page_directory(adev, vm);
 551         if (r)
 552                 return r;
 553
 554         r = amdgpu_sync_fence(adev, &p->ibs[0].sync, vm->page_directory_fence);
 555         if (r)
 556                 return r;
 557
 558         r = amdgpu_vm_clear_freed(adev, vm);
 559         if (r)
 560                 return r;
 561
 562         if (p->bo_list) {
 563                 for (i = 0; i < p->bo_list->num_entries; i++) {
 564                         struct fence *f;
 565
 566                         /* ignore duplicates */
 567                         bo = p->bo_list->array[i].robj;
 568                         if (!bo)
 569                                 continue;
 570
 571                         bo_va = p->bo_list->array[i].bo_va;
 572                         if (bo_va == NULL)
 573                                 continue;
 574
 575                         r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem);
 576                         if (r)
 577                                 return r;
 578
 579                         f = bo_va->last_pt_update;
 580                         r = amdgpu_sync_fence(adev, &p->ibs[0].sync, f);
 581                         if (r)
 582                                 return r;
 583                 }
 584         }
 585
 586         return amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync);
 587 }
 588
 589 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 590                                  struct amdgpu_cs_parser *parser)
 591 {
 592         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 593         struct amdgpu_vm *vm = &fpriv->vm;
 594         struct amdgpu_ring *ring;
 595         int i, r;
 596
 597         if (parser->num_ibs == 0)
 598                 return 0;
 599
 600         /* Only for UVD/VCE VM emulation */
 601         for (i = 0; i < parser->num_ibs; i++) {
 602                 ring = parser->ibs[i].ring;
 603                 if (ring->funcs->parse_cs) {
 604                         r = amdgpu_ring_parse_cs(ring, parser, i);
 605                         if (r)
 606                                 return r;
 607                 }
 608         }
 609
 610         mutex_lock(&vm->mutex);
 611         r = amdgpu_bo_vm_update_pte(parser, vm);
 612         if (r) {
 613                 goto out;
 614         }
 615         amdgpu_cs_sync_rings(parser);
 616         if (!amdgpu_enable_scheduler)
 617                 r = amdgpu_ib_schedule(adev, parser->num_ibs, parser->ibs,
 618                                        parser->filp);
 619
 620 out:
 621         mutex_unlock(&vm->mutex);
 622         return r;
 623 }
 624
 625 static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
 626 {
 627         if (r == -EDEADLK) {
 628                 r = amdgpu_gpu_reset(adev);
 629                 if (!r)
 630                         r = -EAGAIN;
 631         }
 632         return r;
 633 }
 634
 635 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 636                              struct amdgpu_cs_parser *parser)
 637 {
 638         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 639         struct amdgpu_vm *vm = &fpriv->vm;
 640         int i, j;
 641         int r;
 642
 643         for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) {
 644                 struct amdgpu_cs_chunk *chunk;
 645                 struct amdgpu_ib *ib;
 646                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 647                 struct amdgpu_ring *ring;
 648
 649                 chunk = &parser->chunks[i];
 650                 ib = &parser->ibs[j];
 651                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 652
 653                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 654                         continue;
 655
 656                 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
 657                                        chunk_ib->ip_instance, chunk_ib->ring,
 658                                        &ring);
 659                 if (r)
 660                         return r;
 661
 662                 if (ring->funcs->parse_cs) {
 663                         struct amdgpu_bo_va_mapping *m;
 664                         struct amdgpu_bo *aobj = NULL;
 665                         uint64_t offset;
 666                         uint8_t *kptr;
 667
 668                         m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
 669                                                    &aobj);
 670                         if (!aobj) {
 671                                 DRM_ERROR("IB va_start is invalid\n");
 672                                 return -EINVAL;
 673                         }
 674
 675                         if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
 676                             (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 677                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 678                                 return -EINVAL;
 679                         }
 680
 681                         /* the IB should be reserved at this point */
 682                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 683                         if (r) {
 684                                 return r;
 685                         }
 686
 687                         offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
 688                         kptr += chunk_ib->va_start - offset;
 689
 690                         r =  amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib);
 691                         if (r) {
 692                                 DRM_ERROR("Failed to get ib !\n");
 693                                 return r;
 694                         }
 695
 696                         memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 697                         amdgpu_bo_kunmap(aobj);
 698                 } else {
 699                         r =  amdgpu_ib_get(ring, vm, 0, ib);
 700                         if (r) {
 701                                 DRM_ERROR("Failed to get ib !\n");
 702                                 return r;
 703                         }
 704
 705                         ib->gpu_addr = chunk_ib->va_start;
 706                 }
 707
 708                 ib->length_dw = chunk_ib->ib_bytes / 4;
 709                 ib->flags = chunk_ib->flags;
 710                 ib->ctx = parser->ctx;
 711                 j++;
 712         }
 713
 714         if (!parser->num_ibs)
 715                 return 0;
 716
 717         /* add GDS resources to first IB */
 718         if (parser->bo_list) {
 719                 struct amdgpu_bo *gds = parser->bo_list->gds_obj;
 720                 struct amdgpu_bo *gws = parser->bo_list->gws_obj;
 721                 struct amdgpu_bo *oa = parser->bo_list->oa_obj;
 722                 struct amdgpu_ib *ib = &parser->ibs[0];
 723
 724                 if (gds) {
 725                         ib->gds_base = amdgpu_bo_gpu_offset(gds);
 726                         ib->gds_size = amdgpu_bo_size(gds);
 727                 }
 728                 if (gws) {
 729                         ib->gws_base = amdgpu_bo_gpu_offset(gws);
 730                         ib->gws_size = amdgpu_bo_size(gws);
 731                 }
 732                 if (oa) {
 733                         ib->oa_base = amdgpu_bo_gpu_offset(oa);
 734                         ib->oa_size = amdgpu_bo_size(oa);
 735                 }
 736         }
 737         /* wrap the last IB with user fence */
 738         if (parser->uf.bo) {
 739                 struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1];
 740
 741                 /* UVD & VCE fw doesn't support user fences */
 742                 if (ib->ring->type == AMDGPU_RING_TYPE_UVD ||
 743                     ib->ring->type == AMDGPU_RING_TYPE_VCE)
 744                         return -EINVAL;
 745
 746                 ib->user = &parser->uf;
 747         }
 748
 749         return 0;
 750 }
 751
 752 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
 753                                   struct amdgpu_cs_parser *p)
 754 {
 755         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 756         struct amdgpu_ib *ib;
 757         int i, j, r;
 758
 759         if (!p->num_ibs)
 760                 return 0;
 761
 762         /* Add dependencies to first IB */
 763         ib = &p->ibs[0];
 764         for (i = 0; i < p->nchunks; ++i) {
 765                 struct drm_amdgpu_cs_chunk_dep *deps;
 766                 struct amdgpu_cs_chunk *chunk;
 767                 unsigned num_deps;
 768
 769                 chunk = &p->chunks[i];
 770
 771                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_DEPENDENCIES)
 772                         continue;
 773
 774                 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
 775                 num_deps = chunk->length_dw * 4 /
 776                         sizeof(struct drm_amdgpu_cs_chunk_dep);
 777
 778                 for (j = 0; j < num_deps; ++j) {
 779                         struct amdgpu_ring *ring;
 780                         struct amdgpu_ctx *ctx;
 781                         struct fence *fence;
 782
 783                         r = amdgpu_cs_get_ring(adev, deps[j].ip_type,
 784                                                deps[j].ip_instance,
 785                                                deps[j].ring, &ring);
 786                         if (r)
 787                                 return r;
 788
 789                         ctx = amdgpu_ctx_get(fpriv, deps[j].ctx_id);
 790                         if (ctx == NULL)
 791                                 return -EINVAL;
 792
 793                         fence = amdgpu_ctx_get_fence(ctx, ring,
 794                                                      deps[j].handle);
 795                         if (IS_ERR(fence)) {
 796                                 r = PTR_ERR(fence);
 797                                 amdgpu_ctx_put(ctx);
 798                                 return r;
 799
 800                         } else if (fence) {
 801                                 r = amdgpu_sync_fence(adev, &ib->sync, fence);
 802                                 fence_put(fence);
 803                                 amdgpu_ctx_put(ctx);
 804                                 if (r)
 805                                         return r;
 806                         }
 807                 }
 808         }
 809
 810         return 0;
 811 }
 812
 813 static int amdgpu_cs_parser_prepare_job(struct amdgpu_cs_parser *sched_job)
 814 {
 815         int r, i;
 816         struct amdgpu_cs_parser *parser = sched_job;
 817         struct amdgpu_device *adev = sched_job->adev;
 818         bool reserved_buffers = false;
 819
 820         r = amdgpu_cs_parser_relocs(parser);
 821         if (r) {
 822                 if (r != -ERESTARTSYS) {
 823                         if (r == -ENOMEM)
 824                                 DRM_ERROR("Not enough memory for command submission!\n");
 825                         else
 826                                 DRM_ERROR("Failed to process the buffer list %d!\n", r);
 827                 }
 828         }
 829
 830         if (!r) {
 831                 reserved_buffers = true;
 832                 r = amdgpu_cs_ib_fill(adev, parser);
 833         }
 834         if (!r) {
 835                 r = amdgpu_cs_dependencies(adev, parser);
 836                 if (r)
 837                         DRM_ERROR("Failed in the dependencies handling %d!\n", r);
 838         }
 839         if (r) {
 840                 amdgpu_cs_parser_fini(parser, r, reserved_buffers);
 841                 return r;
 842         }
 843
 844         for (i = 0; i < parser->num_ibs; i++)
 845                 trace_amdgpu_cs(parser, i);
 846
 847         r = amdgpu_cs_ib_vm_chunk(adev, parser);
 848         return r;
 849 }
 850
 851 static struct amdgpu_ring *amdgpu_cs_parser_get_ring(
 852         struct amdgpu_device *adev,
 853         struct amdgpu_cs_parser *parser)
 854 {
 855         int i, r;
 856
 857         struct amdgpu_cs_chunk *chunk;
 858         struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 859         struct amdgpu_ring *ring;
 860         for (i = 0; i < parser->nchunks; i++) {
 861                 chunk = &parser->chunks[i];
 862                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 863
 864                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 865                         continue;
 866
 867                 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
 868                                        chunk_ib->ip_instance, chunk_ib->ring,
 869                                        &ring);
 870                 if (r)
 871                         return NULL;
 872                 break;
 873         }
 874         return ring;
 875 }
 876
 877 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 878 {
 879         struct amdgpu_device *adev = dev->dev_private;
 880         union drm_amdgpu_cs *cs = data;
 881         struct amdgpu_cs_parser *parser;
 882         int r;
 883
 884         down_read(&adev->exclusive_lock);
 885         if (!adev->accel_working) {
 886                 up_read(&adev->exclusive_lock);
 887                 return -EBUSY;
 888         }
 889
 890         parser = amdgpu_cs_parser_create(adev, filp, NULL, NULL, 0);
 891         if (!parser)
 892                 return -ENOMEM;
 893         r = amdgpu_cs_parser_init(parser, data);
 894         if (r) {
 895                 DRM_ERROR("Failed to initialize parser !\n");
 896                 amdgpu_cs_parser_fini(parser, r, false);
 897                 up_read(&adev->exclusive_lock);
 898                 r = amdgpu_cs_handle_lockup(adev, r);
 899                 return r;
 900         }
 901
 902         if (amdgpu_enable_scheduler && parser->num_ibs) {
 903                 struct amdgpu_ring * ring =
 904                         amdgpu_cs_parser_get_ring(adev, parser);
 905                 r = amdgpu_cs_parser_prepare_job(parser);
 906                 if (r)
 907                         goto out;
 908                 parser->ring = ring;
 909                 parser->free_job = amdgpu_cs_parser_free_job;
 910                 mutex_lock(&parser->job_lock);
 911                 r = amd_sched_push_job(ring->scheduler,
 912                                        &parser->ctx->rings[ring->idx].entity,
 913                                        parser,
 914                                        &parser->s_fence);
 915                 if (r) {
 916                         mutex_unlock(&parser->job_lock);
 917                         goto out;
 918                 }
 919                 parser->ibs[parser->num_ibs - 1].sequence =
 920                         amdgpu_ctx_add_fence(parser->ctx, ring,
 921                                              &parser->s_fence->base,
 922                                              parser->s_fence->v_seq);
 923                 cs->out.handle = parser->s_fence->v_seq;
 924                 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
 925                 ttm_eu_fence_buffer_objects(&parser->ticket,
 926                                 &parser->validated,
 927                                 &parser->s_fence->base);
 928
 929                 mutex_unlock(&parser->job_lock);
 930                 up_read(&adev->exclusive_lock);
 931                 return 0;
 932         }
 933         r = amdgpu_cs_parser_prepare_job(parser);
 934         if (r)
 935                 goto out;
 936
 937         cs->out.handle = parser->ibs[parser->num_ibs - 1].sequence;
 938 out:
 939         amdgpu_cs_parser_fini(parser, r, true);
 940         up_read(&adev->exclusive_lock);
 941         r = amdgpu_cs_handle_lockup(adev, r);
 942         return r;
 943 }
 944
 945 /**
 946  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
 947  *
 948  * @dev: drm device
 949  * @data: data from userspace
 950  * @filp: file private
 951  *
 952  * Wait for the command submission identified by handle to finish.
 953  */
 954 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
 955                          struct drm_file *filp)
 956 {
 957         union drm_amdgpu_wait_cs *wait = data;
 958         struct amdgpu_device *adev = dev->dev_private;
 959         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
 960         struct amdgpu_ring *ring = NULL;
 961         struct amdgpu_ctx *ctx;
 962         struct fence *fence;
 963         long r;
 964
 965         r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
 966                                wait->in.ring, &ring);
 967         if (r)
 968                 return r;
 969
 970         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
 971         if (ctx == NULL)
 972                 return -EINVAL;
 973
 974         fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
 975         if (IS_ERR(fence))
 976                 r = PTR_ERR(fence);
 977         else if (fence) {
 978                 r = fence_wait_timeout(fence, true, timeout);
 979                 fence_put(fence);
 980         } else
 981                 r = 1;
 982
 983         amdgpu_ctx_put(ctx);
 984         if (r < 0)
 985                 return r;
 986
 987         memset(wait, 0, sizeof(*wait));
 988         wait->out.status = (r == 0);
 989
 990         return 0;
 991 }
 992
 993 /**
 994  * amdgpu_cs_find_bo_va - find bo_va for VM address
 995  *
 996  * @parser: command submission parser context
 997  * @addr: VM address
 998  * @bo: resulting BO of the mapping found
 999  *
1000  * Search the buffer objects in the command submission context for a certain
1001  * virtual memory address. Returns allocation structure when found, NULL
1002  * otherwise.
1003  */
1004 struct amdgpu_bo_va_mapping *
1005 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1006                        uint64_t addr, struct amdgpu_bo **bo)
1007 {
1008         struct amdgpu_bo_list_entry *reloc;
1009         struct amdgpu_bo_va_mapping *mapping;
1010
1011         addr /= AMDGPU_GPU_PAGE_SIZE;
1012
1013         list_for_each_entry(reloc, &parser->validated, tv.head) {
1014                 if (!reloc->bo_va)
1015                         continue;
1016
1017                 list_for_each_entry(mapping, &reloc->bo_va->valids, list) {
1018                         if (mapping->it.start > addr ||
1019                             addr > mapping->it.last)
1020                                 continue;
1021
1022                         *bo = reloc->bo_va->bo;
1023                         return mapping;
1024                 }
1025
1026                 list_for_each_entry(mapping, &reloc->bo_va->invalids, list) {
1027                         if (mapping->it.start > addr ||
1028                             addr > mapping->it.last)
1029                                 continue;
1030
1031                         *bo = reloc->bo_va->bo;
1032                         return mapping;
1033                 }
1034         }
1035
1036         return NULL;
1037 }