drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <glisse@freedesktop.org>
  26  */
  27 #include <linux/list_sort.h>
  28 #include <drm/drmP.h>
  29 #include <drm/amdgpu_drm.h>
  30 #include "amdgpu.h"
  31 #include "amdgpu_trace.h"
  32
  33 #define AMDGPU_CS_MAX_PRIORITY          32u
  34 #define AMDGPU_CS_NUM_BUCKETS           (AMDGPU_CS_MAX_PRIORITY + 1)
  35
  36 /* This is based on the bucket sort with O(n) time complexity.
  37  * An item with priority "i" is added to bucket[i]. The lists are then
  38  * concatenated in descending order.
  39  */
  40 struct amdgpu_cs_buckets {
  41         struct list_head bucket[AMDGPU_CS_NUM_BUCKETS];
  42 };
  43
  44 static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b)
  45 {
  46         unsigned i;
  47
  48         for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++)
  49                 INIT_LIST_HEAD(&b->bucket[i]);
  50 }
  51
  52 static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b,
  53                                   struct list_head *item, unsigned priority)
  54 {
  55         /* Since buffers which appear sooner in the relocation list are
  56          * likely to be used more often than buffers which appear later
  57          * in the list, the sort mustn't change the ordering of buffers
  58          * with the same priority, i.e. it must be stable.
  59          */
  60         list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]);
  61 }
  62
  63 static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b,
  64                                        struct list_head *out_list)
  65 {
  66         unsigned i;
  67
  68         /* Connect the sorted buckets in the output list. */
  69         for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) {
  70                 list_splice(&b->bucket[i], out_list);
  71         }
  72 }
  73
  74 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
  75                        u32 ip_instance, u32 ring,
  76                        struct amdgpu_ring **out_ring)
  77 {
  78         /* Right now all IPs have only one instance - multiple rings. */
  79         if (ip_instance != 0) {
  80                 DRM_ERROR("invalid ip instance: %d\n", ip_instance);
  81                 return -EINVAL;
  82         }
  83
  84         switch (ip_type) {
  85         default:
  86                 DRM_ERROR("unknown ip type: %d\n", ip_type);
  87                 return -EINVAL;
  88         case AMDGPU_HW_IP_GFX:
  89                 if (ring < adev->gfx.num_gfx_rings) {
  90                         *out_ring = &adev->gfx.gfx_ring[ring];
  91                 } else {
  92                         DRM_ERROR("only %d gfx rings are supported now\n",
  93                                   adev->gfx.num_gfx_rings);
  94                         return -EINVAL;
  95                 }
  96                 break;
  97         case AMDGPU_HW_IP_COMPUTE:
  98                 if (ring < adev->gfx.num_compute_rings) {
  99                         *out_ring = &adev->gfx.compute_ring[ring];
 100                 } else {
 101                         DRM_ERROR("only %d compute rings are supported now\n",
 102                                   adev->gfx.num_compute_rings);
 103                         return -EINVAL;
 104                 }
 105                 break;
 106         case AMDGPU_HW_IP_DMA:
 107                 if (ring < 2) {
 108                         *out_ring = &adev->sdma[ring].ring;
 109                 } else {
 110                         DRM_ERROR("only two SDMA rings are supported\n");
 111                         return -EINVAL;
 112                 }
 113                 break;
 114         case AMDGPU_HW_IP_UVD:
 115                 *out_ring = &adev->uvd.ring;
 116                 break;
 117         case AMDGPU_HW_IP_VCE:
 118                 if (ring < 2){
 119                         *out_ring = &adev->vce.ring[ring];
 120                 } else {
 121                         DRM_ERROR("only two VCE rings are supported\n");
 122                         return -EINVAL;
 123                 }
 124                 break;
 125         }
 126         return 0;
 127 }
 128
 129 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
 130 {
 131         union drm_amdgpu_cs *cs = data;
 132         uint64_t *chunk_array_user;
 133         uint64_t *chunk_array = NULL;
 134         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 135         unsigned size, i;
 136         int r = 0;
 137
 138         if (!cs->in.num_chunks)
 139                 goto out;
 140
 141         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 142         if (!p->ctx) {
 143                 r = -EINVAL;
 144                 goto out;
 145         }
 146         p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
 147
 148         /* get chunks */
 149         INIT_LIST_HEAD(&p->validated);
 150         chunk_array = kcalloc(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 151         if (chunk_array == NULL) {
 152                 r = -ENOMEM;
 153                 goto out;
 154         }
 155
 156         chunk_array_user = (uint64_t *)(unsigned long)(cs->in.chunks);
 157         if (copy_from_user(chunk_array, chunk_array_user,
 158                            sizeof(uint64_t)*cs->in.num_chunks)) {
 159                 r = -EFAULT;
 160                 goto out;
 161         }
 162
 163         p->nchunks = cs->in.num_chunks;
 164         p->chunks = kcalloc(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 165                             GFP_KERNEL);
 166         if (p->chunks == NULL) {
 167                 r = -ENOMEM;
 168                 goto out;
 169         }
 170
 171         for (i = 0; i < p->nchunks; i++) {
 172                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 173                 struct drm_amdgpu_cs_chunk user_chunk;
 174                 uint32_t __user *cdata;
 175
 176                 chunk_ptr = (void __user *)(unsigned long)chunk_array[i];
 177                 if (copy_from_user(&user_chunk, chunk_ptr,
 178                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 179                         r = -EFAULT;
 180                         goto out;
 181                 }
 182                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 183                 p->chunks[i].length_dw = user_chunk.length_dw;
 184                 if (p->chunks[i].chunk_id == AMDGPU_CHUNK_ID_IB)
 185                         p->num_ibs++;
 186
 187                 size = p->chunks[i].length_dw;
 188                 cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
 189                 p->chunks[i].user_ptr = cdata;
 190
 191                 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
 192                 if (p->chunks[i].kdata == NULL) {
 193                         r = -ENOMEM;
 194                         goto out;
 195                 }
 196                 size *= sizeof(uint32_t);
 197                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 198                         r = -EFAULT;
 199                         goto out;
 200                 }
 201
 202                 if (p->chunks[i].chunk_id == AMDGPU_CHUNK_ID_FENCE) {
 203                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 204                         if (p->chunks[i].length_dw * sizeof(uint32_t) >= size) {
 205                                 uint32_t handle;
 206                                 struct drm_gem_object *gobj;
 207                                 struct drm_amdgpu_cs_chunk_fence *fence_data;
 208
 209                                 fence_data = (void *)p->chunks[i].kdata;
 210                                 handle = fence_data->handle;
 211                                 gobj = drm_gem_object_lookup(p->adev->ddev,
 212                                                              p->filp, handle);
 213                                 if (gobj == NULL) {
 214                                         r = -EINVAL;
 215                                         goto out;
 216                                 }
 217
 218                                 p->uf.bo = gem_to_amdgpu_bo(gobj);
 219                                 p->uf.offset = fence_data->offset;
 220                         } else {
 221                                 r = -EINVAL;
 222                                 goto out;
 223                         }
 224                 }
 225         }
 226
 227         p->ibs = kcalloc(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL);
 228         if (!p->ibs) {
 229                 r = -ENOMEM;
 230                 goto out;
 231         }
 232
 233         p->ib_bos = kcalloc(p->num_ibs, sizeof(struct amdgpu_bo_list_entry),
 234                             GFP_KERNEL);
 235         if (!p->ib_bos)
 236                 r = -ENOMEM;
 237
 238 out:
 239         kfree(chunk_array);
 240         return r;
 241 }
 242
 243 /* Returns how many bytes TTM can move per IB.
 244  */
 245 static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
 246 {
 247         u64 real_vram_size = adev->mc.real_vram_size;
 248         u64 vram_usage = atomic64_read(&adev->vram_usage);
 249
 250         /* This function is based on the current VRAM usage.
 251          *
 252          * - If all of VRAM is free, allow relocating the number of bytes that
 253          *   is equal to 1/4 of the size of VRAM for this IB.
 254
 255          * - If more than one half of VRAM is occupied, only allow relocating
 256          *   1 MB of data for this IB.
 257          *
 258          * - From 0 to one half of used VRAM, the threshold decreases
 259          *   linearly.
 260          *         __________________
 261          * 1/4 of -|\               |
 262          * VRAM    | \              |
 263          *         |  \             |
 264          *         |   \            |
 265          *         |    \           |
 266          *         |     \          |
 267          *         |      \         |
 268          *         |       \________|1 MB
 269          *         |----------------|
 270          *    VRAM 0 %             100 %
 271          *         used            used
 272          *
 273          * Note: It's a threshold, not a limit. The threshold must be crossed
 274          * for buffer relocations to stop, so any buffer of an arbitrary size
 275          * can be moved as long as the threshold isn't crossed before
 276          * the relocation takes place. We don't want to disable buffer
 277          * relocations completely.
 278          *
 279          * The idea is that buffers should be placed in VRAM at creation time
 280          * and TTM should only do a minimum number of relocations during
 281          * command submission. In practice, you need to submit at least
 282          * a dozen IBs to move all buffers to VRAM if they are in GTT.
 283          *
 284          * Also, things can get pretty crazy under memory pressure and actual
 285          * VRAM usage can change a lot, so playing safe even at 50% does
 286          * consistently increase performance.
 287          */
 288
 289         u64 half_vram = real_vram_size >> 1;
 290         u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
 291         u64 bytes_moved_threshold = half_free_vram >> 1;
 292         return max(bytes_moved_threshold, 1024*1024ull);
 293 }
 294
 295 int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p)
 296 {
 297         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 298         struct amdgpu_vm *vm = &fpriv->vm;
 299         struct amdgpu_device *adev = p->adev;
 300         struct amdgpu_bo_list_entry *lobj;
 301         struct list_head duplicates;
 302         struct amdgpu_bo *bo;
 303         u64 bytes_moved = 0, initial_bytes_moved;
 304         u64 bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(adev);
 305         int r;
 306
 307         INIT_LIST_HEAD(&duplicates);
 308         r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates);
 309         if (unlikely(r != 0)) {
 310                 return r;
 311         }
 312
 313         list_for_each_entry(lobj, &p->validated, tv.head) {
 314                 bo = lobj->robj;
 315                 if (!bo->pin_count) {
 316                         u32 domain = lobj->prefered_domains;
 317                         u32 current_domain =
 318                                 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 319
 320                         /* Check if this buffer will be moved and don't move it
 321                          * if we have moved too many buffers for this IB already.
 322                          *
 323                          * Note that this allows moving at least one buffer of
 324                          * any size, because it doesn't take the current "bo"
 325                          * into account. We don't want to disallow buffer moves
 326                          * completely.
 327                          */
 328                         if (current_domain != AMDGPU_GEM_DOMAIN_CPU &&
 329                             (domain & current_domain) == 0 && /* will be moved */
 330                             bytes_moved > bytes_moved_threshold) {
 331                                 /* don't move it */
 332                                 domain = current_domain;
 333                         }
 334
 335                 retry:
 336                         amdgpu_ttm_placement_from_domain(bo, domain);
 337                         initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 338                         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 339                         bytes_moved += atomic64_read(&adev->num_bytes_moved) -
 340                                        initial_bytes_moved;
 341
 342                         if (unlikely(r)) {
 343                                 if (r != -ERESTARTSYS && domain != lobj->allowed_domains) {
 344                                         domain = lobj->allowed_domains;
 345                                         goto retry;
 346                                 }
 347                                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 348                                 return r;
 349                         }
 350                 }
 351                 lobj->bo_va = amdgpu_vm_bo_find(vm, bo);
 352         }
 353         return 0;
 354 }
 355
 356 static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
 357 {
 358         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 359         struct amdgpu_cs_buckets buckets;
 360         bool need_mmap_lock = false;
 361         int i, r;
 362
 363         if (p->bo_list) {
 364                 need_mmap_lock = p->bo_list->has_userptr;
 365                 amdgpu_cs_buckets_init(&buckets);
 366                 for (i = 0; i < p->bo_list->num_entries; i++)
 367                         amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head,
 368                                                                   p->bo_list->array[i].priority);
 369
 370                 amdgpu_cs_buckets_get_list(&buckets, &p->validated);
 371         }
 372
 373         p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm,
 374                                       &p->validated);
 375
 376         for (i = 0; i < p->num_ibs; i++) {
 377                 if (!p->ib_bos[i].robj)
 378                         continue;
 379
 380                 list_add(&p->ib_bos[i].tv.head, &p->validated);
 381         }
 382
 383         if (need_mmap_lock)
 384                 down_read(&current->mm->mmap_sem);
 385
 386         r = amdgpu_cs_list_validate(p);
 387
 388         if (need_mmap_lock)
 389                 up_read(&current->mm->mmap_sem);
 390
 391         return r;
 392 }
 393
 394 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 395 {
 396         struct amdgpu_bo_list_entry *e;
 397         int r;
 398
 399         list_for_each_entry(e, &p->validated, tv.head) {
 400                 struct reservation_object *resv = e->robj->tbo.resv;
 401                 r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp);
 402
 403                 if (r)
 404                         return r;
 405         }
 406         return 0;
 407 }
 408
 409 static int cmp_size_smaller_first(void *priv, struct list_head *a,
 410                                   struct list_head *b)
 411 {
 412         struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head);
 413         struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head);
 414
 415         /* Sort A before B if A is smaller. */
 416         return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
 417 }
 418
 419 /**
 420  * cs_parser_fini() - clean parser states
 421  * @parser:     parser structure holding parsing context.
 422  * @error:      error number
 423  *
 424  * If error is set than unvalidate buffer, otherwise just free memory
 425  * used by parsing context.
 426  **/
 427 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
 428 {
 429         unsigned i;
 430
 431         if (!error) {
 432                 /* Sort the buffer list from the smallest to largest buffer,
 433                  * which affects the order of buffers in the LRU list.
 434                  * This assures that the smallest buffers are added first
 435                  * to the LRU list, so they are likely to be later evicted
 436                  * first, instead of large buffers whose eviction is more
 437                  * expensive.
 438                  *
 439                  * This slightly lowers the number of bytes moved by TTM
 440                  * per frame under memory pressure.
 441                  */
 442                 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
 443
 444                 ttm_eu_fence_buffer_objects(&parser->ticket,
 445                                 &parser->validated,
 446                                 &parser->ibs[parser->num_ibs-1].fence->base);
 447         } else if (backoff) {
 448                 ttm_eu_backoff_reservation(&parser->ticket,
 449                                            &parser->validated);
 450         }
 451
 452         if (parser->ctx)
 453                 amdgpu_ctx_put(parser->ctx);
 454         if (parser->bo_list)
 455                 amdgpu_bo_list_put(parser->bo_list);
 456         drm_free_large(parser->vm_bos);
 457         for (i = 0; i < parser->nchunks; i++)
 458                 drm_free_large(parser->chunks[i].kdata);
 459         kfree(parser->chunks);
 460         for (i = 0; i < parser->num_ibs; i++) {
 461                 struct amdgpu_bo *bo = parser->ib_bos[i].robj;
 462                 amdgpu_ib_free(parser->adev, &parser->ibs[i]);
 463
 464                 if (bo)
 465                         drm_gem_object_unreference_unlocked(&bo->gem_base);
 466         }
 467         kfree(parser->ibs);
 468         kfree(parser->ib_bos);
 469         if (parser->uf.bo)
 470                 drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base);
 471 }
 472
 473 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
 474                                    struct amdgpu_vm *vm)
 475 {
 476         struct amdgpu_device *adev = p->adev;
 477         struct amdgpu_bo_va *bo_va;
 478         struct amdgpu_bo *bo;
 479         int i, r;
 480
 481         r = amdgpu_vm_update_page_directory(adev, vm);
 482         if (r)
 483                 return r;
 484
 485         r = amdgpu_vm_clear_freed(adev, vm);
 486         if (r)
 487                 return r;
 488
 489         if (p->bo_list) {
 490                 for (i = 0; i < p->bo_list->num_entries; i++) {
 491                         /* ignore duplicates */
 492                         bo = p->bo_list->array[i].robj;
 493                         if (!bo)
 494                                 continue;
 495
 496                         bo_va = p->bo_list->array[i].bo_va;
 497                         if (bo_va == NULL)
 498                                 continue;
 499
 500                         r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem);
 501                         if (r)
 502                                 return r;
 503
 504                         amdgpu_sync_fence(&p->ibs[0].sync, bo_va->last_pt_update);
 505                 }
 506         }
 507
 508         for (i = 0; i < p->num_ibs; i++) {
 509                 bo = p->ib_bos[i].robj;
 510                 if (!bo)
 511                         continue;
 512
 513                 bo_va = p->ib_bos[i].bo_va;
 514                 if (!bo_va)
 515                         continue;
 516
 517                 r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem);
 518                 if (r)
 519                         return r;
 520
 521                 amdgpu_sync_fence(&p->ibs[0].sync, bo_va->last_pt_update);
 522         }
 523         return amdgpu_vm_clear_invalids(adev, vm);
 524 }
 525
 526 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 527                                  struct amdgpu_cs_parser *parser)
 528 {
 529         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 530         struct amdgpu_vm *vm = &fpriv->vm;
 531         struct amdgpu_ring *ring;
 532         int i, r;
 533
 534         if (parser->num_ibs == 0)
 535                 return 0;
 536
 537         /* Only for UVD/VCE VM emulation */
 538         for (i = 0; i < parser->num_ibs; i++) {
 539                 ring = parser->ibs[i].ring;
 540                 if (ring->funcs->parse_cs) {
 541                         r = amdgpu_ring_parse_cs(ring, parser, i);
 542                         if (r)
 543                                 return r;
 544                 }
 545         }
 546
 547         mutex_lock(&vm->mutex);
 548         r = amdgpu_bo_vm_update_pte(parser, vm);
 549         if (r) {
 550                 goto out;
 551         }
 552         amdgpu_cs_sync_rings(parser);
 553
 554         r = amdgpu_ib_schedule(adev, parser->num_ibs, parser->ibs,
 555                                parser->filp);
 556
 557 out:
 558         mutex_unlock(&vm->mutex);
 559         return r;
 560 }
 561
 562 static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
 563 {
 564         if (r == -EDEADLK) {
 565                 r = amdgpu_gpu_reset(adev);
 566                 if (!r)
 567                         r = -EAGAIN;
 568         }
 569         return r;
 570 }
 571
 572 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 573                              struct amdgpu_cs_parser *parser)
 574 {
 575         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 576         struct amdgpu_vm *vm = &fpriv->vm;
 577         int i, j;
 578         int r;
 579
 580         for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) {
 581                 struct amdgpu_cs_chunk *chunk;
 582                 struct amdgpu_ib *ib;
 583                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 584                 struct amdgpu_bo_list_entry *ib_bo;
 585                 struct amdgpu_ring *ring;
 586                 struct drm_gem_object *gobj;
 587                 struct amdgpu_bo *aobj;
 588                 void *kptr;
 589
 590                 chunk = &parser->chunks[i];
 591                 ib = &parser->ibs[j];
 592                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 593
 594                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 595                         continue;
 596
 597                 gobj = drm_gem_object_lookup(adev->ddev, parser->filp, chunk_ib->handle);
 598                 if (gobj == NULL)
 599                         return -ENOENT;
 600                 aobj = gem_to_amdgpu_bo(gobj);
 601
 602                 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
 603                                        chunk_ib->ip_instance, chunk_ib->ring,
 604                                        &ring);
 605                 if (r) {
 606                         drm_gem_object_unreference_unlocked(gobj);
 607                         return r;
 608                 }
 609
 610                 if (ring->funcs->parse_cs) {
 611                         r = amdgpu_bo_reserve(aobj, false);
 612                         if (r) {
 613                                 drm_gem_object_unreference_unlocked(gobj);
 614                                 return r;
 615                         }
 616
 617                         r = amdgpu_bo_kmap(aobj, &kptr);
 618                         if (r) {
 619                                 amdgpu_bo_unreserve(aobj);
 620                                 drm_gem_object_unreference_unlocked(gobj);
 621                                 return r;
 622                         }
 623
 624                         r =  amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib);
 625                         if (r) {
 626                                 DRM_ERROR("Failed to get ib !\n");
 627                                 amdgpu_bo_unreserve(aobj);
 628                                 drm_gem_object_unreference_unlocked(gobj);
 629                                 return r;
 630                         }
 631
 632                         memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 633                         amdgpu_bo_kunmap(aobj);
 634                         amdgpu_bo_unreserve(aobj);
 635                 } else {
 636                         r =  amdgpu_ib_get(ring, vm, 0, ib);
 637                         if (r) {
 638                                 DRM_ERROR("Failed to get ib !\n");
 639                                 drm_gem_object_unreference_unlocked(gobj);
 640                                 return r;
 641                         }
 642
 643                         ib->gpu_addr = chunk_ib->va_start;
 644                 }
 645                 ib->length_dw = chunk_ib->ib_bytes / 4;
 646
 647                 ib->flags = chunk_ib->flags;
 648                 ib->ctx = parser->ctx;
 649
 650                 ib_bo = &parser->ib_bos[j];
 651                 ib_bo->robj = aobj;
 652                 ib_bo->prefered_domains = aobj->initial_domain;
 653                 ib_bo->allowed_domains = aobj->initial_domain;
 654                 ib_bo->priority = 0;
 655                 ib_bo->tv.bo = &aobj->tbo;
 656                 ib_bo->tv.shared = true;
 657                 j++;
 658         }
 659
 660         if (!parser->num_ibs)
 661                 return 0;
 662
 663         /* add GDS resources to first IB */
 664         if (parser->bo_list) {
 665                 struct amdgpu_bo *gds = parser->bo_list->gds_obj;
 666                 struct amdgpu_bo *gws = parser->bo_list->gws_obj;
 667                 struct amdgpu_bo *oa = parser->bo_list->oa_obj;
 668                 struct amdgpu_ib *ib = &parser->ibs[0];
 669
 670                 if (gds) {
 671                         ib->gds_base = amdgpu_bo_gpu_offset(gds);
 672                         ib->gds_size = amdgpu_bo_size(gds);
 673                 }
 674                 if (gws) {
 675                         ib->gws_base = amdgpu_bo_gpu_offset(gws);
 676                         ib->gws_size = amdgpu_bo_size(gws);
 677                 }
 678                 if (oa) {
 679                         ib->oa_base = amdgpu_bo_gpu_offset(oa);
 680                         ib->oa_size = amdgpu_bo_size(oa);
 681                 }
 682         }
 683
 684         /* wrap the last IB with user fence */
 685         if (parser->uf.bo) {
 686                 struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1];
 687
 688                 /* UVD & VCE fw doesn't support user fences */
 689                 if (ib->ring->type == AMDGPU_RING_TYPE_UVD ||
 690                     ib->ring->type == AMDGPU_RING_TYPE_VCE)
 691                         return -EINVAL;
 692
 693                 ib->user = &parser->uf;
 694         }
 695
 696         return 0;
 697 }
 698
 699 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 700 {
 701         struct amdgpu_device *adev = dev->dev_private;
 702         union drm_amdgpu_cs *cs = data;
 703         struct amdgpu_cs_parser parser;
 704         int r, i;
 705
 706         down_read(&adev->exclusive_lock);
 707         if (!adev->accel_working) {
 708                 up_read(&adev->exclusive_lock);
 709                 return -EBUSY;
 710         }
 711         /* initialize parser */
 712         memset(&parser, 0, sizeof(struct amdgpu_cs_parser));
 713         parser.filp = filp;
 714         parser.adev = adev;
 715         r = amdgpu_cs_parser_init(&parser, data);
 716         if (r) {
 717                 DRM_ERROR("Failed to initialize parser !\n");
 718                 amdgpu_cs_parser_fini(&parser, r, false);
 719                 up_read(&adev->exclusive_lock);
 720                 r = amdgpu_cs_handle_lockup(adev, r);
 721                 return r;
 722         }
 723
 724         r = amdgpu_cs_ib_fill(adev, &parser);
 725         if (!r) {
 726                 r = amdgpu_cs_parser_relocs(&parser);
 727                 if (r && r != -ERESTARTSYS)
 728                         DRM_ERROR("Failed to parse relocation %d!\n", r);
 729         }
 730
 731         if (r) {
 732                 amdgpu_cs_parser_fini(&parser, r, false);
 733                 up_read(&adev->exclusive_lock);
 734                 r = amdgpu_cs_handle_lockup(adev, r);
 735                 return r;
 736         }
 737
 738         for (i = 0; i < parser.num_ibs; i++)
 739                 trace_amdgpu_cs(&parser, i);
 740
 741         r = amdgpu_cs_ib_vm_chunk(adev, &parser);
 742         if (r) {
 743                 goto out;
 744         }
 745
 746         cs->out.handle = parser.ibs[parser.num_ibs - 1].fence->seq;
 747 out:
 748         amdgpu_cs_parser_fini(&parser, r, true);
 749         up_read(&adev->exclusive_lock);
 750         r = amdgpu_cs_handle_lockup(adev, r);
 751         return r;
 752 }
 753
 754 /**
 755  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
 756  *
 757  * @dev: drm device
 758  * @data: data from userspace
 759  * @filp: file private
 760  *
 761  * Wait for the command submission identified by handle to finish.
 762  */
 763 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
 764                          struct drm_file *filp)
 765 {
 766         union drm_amdgpu_wait_cs *wait = data;
 767         struct amdgpu_device *adev = dev->dev_private;
 768         uint64_t seq[AMDGPU_MAX_RINGS] = {0};
 769         struct amdgpu_ring *ring = NULL;
 770         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
 771         struct amdgpu_ctx *ctx;
 772         long r;
 773
 774         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
 775         if (ctx == NULL)
 776                 return -EINVAL;
 777
 778         r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
 779                                wait->in.ring, &ring);
 780         if (r)
 781                 return r;
 782
 783         seq[ring->idx] = wait->in.handle;
 784
 785         r = amdgpu_fence_wait_seq_timeout(adev, seq, true, timeout);
 786         amdgpu_ctx_put(ctx);
 787         if (r < 0)
 788                 return r;
 789
 790         memset(wait, 0, sizeof(*wait));
 791         wait->out.status = (r == 0);
 792
 793         return 0;
 794 }
 795
 796 /**
 797  * amdgpu_cs_find_bo_va - find bo_va for VM address
 798  *
 799  * @parser: command submission parser context
 800  * @addr: VM address
 801  * @bo: resulting BO of the mapping found
 802  *
 803  * Search the buffer objects in the command submission context for a certain
 804  * virtual memory address. Returns allocation structure when found, NULL
 805  * otherwise.
 806  */
 807 struct amdgpu_bo_va_mapping *
 808 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
 809                        uint64_t addr, struct amdgpu_bo **bo)
 810 {
 811         struct amdgpu_bo_list_entry *reloc;
 812         struct amdgpu_bo_va_mapping *mapping;
 813
 814         addr /= AMDGPU_GPU_PAGE_SIZE;
 815
 816         list_for_each_entry(reloc, &parser->validated, tv.head) {
 817                 if (!reloc->bo_va)
 818                         continue;
 819
 820                 list_for_each_entry(mapping, &reloc->bo_va->mappings, list) {
 821                         if (mapping->it.start > addr ||
 822                             addr > mapping->it.last)
 823                                 continue;
 824
 825                         *bo = reloc->bo_va->bo;
 826                         return mapping;
 827                 }
 828         }
 829
 830         return NULL;
 831 }