drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/console.h>
  29 #include <linux/slab.h>
  30 #include <linux/debugfs.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/amdgpu_drm.h>
  34 #include <linux/vgaarb.h>
  35 #include <linux/vga_switcheroo.h>
  36 #include <linux/efi.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_i2c.h"
  39 #include "atom.h"
  40 #include "amdgpu_atombios.h"
  41 #ifdef CONFIG_DRM_AMDGPU_CIK
  42 #include "cik.h"
  43 #endif
  44 #include "vi.h"
  45 #include "bif/bif_4_1_d.h"
  46
  47 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
  48 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
  49
  50 static const char *amdgpu_asic_name[] = {
  51         "BONAIRE",
  52         "KAVERI",
  53         "KABINI",
  54         "HAWAII",
  55         "MULLINS",
  56         "TOPAZ",
  57         "TONGA",
  58         "FIJI",
  59         "CARRIZO",
  60         "LAST",
  61 };
  62
  63 bool amdgpu_device_is_px(struct drm_device *dev)
  64 {
  65         struct amdgpu_device *adev = dev->dev_private;
  66
  67         if (adev->flags & AMD_IS_PX)
  68                 return true;
  69         return false;
  70 }
  71
  72 /*
  73  * MMIO register access helper functions.
  74  */
  75 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
  76                         bool always_indirect)
  77 {
  78         if ((reg * 4) < adev->rmmio_size && !always_indirect)
  79                 return readl(((void __iomem *)adev->rmmio) + (reg * 4));
  80         else {
  81                 unsigned long flags;
  82                 uint32_t ret;
  83
  84                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
  85                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
  86                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
  87                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
  88
  89                 return ret;
  90         }
  91 }
  92
  93 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
  94                     bool always_indirect)
  95 {
  96         if ((reg * 4) < adev->rmmio_size && !always_indirect)
  97                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
  98         else {
  99                 unsigned long flags;
 100
 101                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
 102                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
 103                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
 104                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
 105         }
 106 }
 107
 108 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
 109 {
 110         if ((reg * 4) < adev->rio_mem_size)
 111                 return ioread32(adev->rio_mem + (reg * 4));
 112         else {
 113                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 114                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
 115         }
 116 }
 117
 118 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 119 {
 120
 121         if ((reg * 4) < adev->rio_mem_size)
 122                 iowrite32(v, adev->rio_mem + (reg * 4));
 123         else {
 124                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
 125                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
 126         }
 127 }
 128
 129 /**
 130  * amdgpu_mm_rdoorbell - read a doorbell dword
 131  *
 132  * @adev: amdgpu_device pointer
 133  * @index: doorbell index
 134  *
 135  * Returns the value in the doorbell aperture at the
 136  * requested doorbell index (CIK).
 137  */
 138 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
 139 {
 140         if (index < adev->doorbell.num_doorbells) {
 141                 return readl(adev->doorbell.ptr + index);
 142         } else {
 143                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
 144                 return 0;
 145         }
 146 }
 147
 148 /**
 149  * amdgpu_mm_wdoorbell - write a doorbell dword
 150  *
 151  * @adev: amdgpu_device pointer
 152  * @index: doorbell index
 153  * @v: value to write
 154  *
 155  * Writes @v to the doorbell aperture at the
 156  * requested doorbell index (CIK).
 157  */
 158 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
 159 {
 160         if (index < adev->doorbell.num_doorbells) {
 161                 writel(v, adev->doorbell.ptr + index);
 162         } else {
 163                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
 164         }
 165 }
 166
 167 /**
 168  * amdgpu_invalid_rreg - dummy reg read function
 169  *
 170  * @adev: amdgpu device pointer
 171  * @reg: offset of register
 172  *
 173  * Dummy register read function.  Used for register blocks
 174  * that certain asics don't have (all asics).
 175  * Returns the value in the register.
 176  */
 177 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
 178 {
 179         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
 180         BUG();
 181         return 0;
 182 }
 183
 184 /**
 185  * amdgpu_invalid_wreg - dummy reg write function
 186  *
 187  * @adev: amdgpu device pointer
 188  * @reg: offset of register
 189  * @v: value to write to the register
 190  *
 191  * Dummy register read function.  Used for register blocks
 192  * that certain asics don't have (all asics).
 193  */
 194 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
 195 {
 196         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
 197                   reg, v);
 198         BUG();
 199 }
 200
 201 /**
 202  * amdgpu_block_invalid_rreg - dummy reg read function
 203  *
 204  * @adev: amdgpu device pointer
 205  * @block: offset of instance
 206  * @reg: offset of register
 207  *
 208  * Dummy register read function.  Used for register blocks
 209  * that certain asics don't have (all asics).
 210  * Returns the value in the register.
 211  */
 212 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
 213                                           uint32_t block, uint32_t reg)
 214 {
 215         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
 216                   reg, block);
 217         BUG();
 218         return 0;
 219 }
 220
 221 /**
 222  * amdgpu_block_invalid_wreg - dummy reg write function
 223  *
 224  * @adev: amdgpu device pointer
 225  * @block: offset of instance
 226  * @reg: offset of register
 227  * @v: value to write to the register
 228  *
 229  * Dummy register read function.  Used for register blocks
 230  * that certain asics don't have (all asics).
 231  */
 232 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
 233                                       uint32_t block,
 234                                       uint32_t reg, uint32_t v)
 235 {
 236         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
 237                   reg, block, v);
 238         BUG();
 239 }
 240
 241 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
 242 {
 243         int r;
 244
 245         if (adev->vram_scratch.robj == NULL) {
 246                 r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
 247                                      PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, 0,
 248                                      NULL, &adev->vram_scratch.robj);
 249                 if (r) {
 250                         return r;
 251                 }
 252         }
 253
 254         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 255         if (unlikely(r != 0))
 256                 return r;
 257         r = amdgpu_bo_pin(adev->vram_scratch.robj,
 258                           AMDGPU_GEM_DOMAIN_VRAM, &adev->vram_scratch.gpu_addr);
 259         if (r) {
 260                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 261                 return r;
 262         }
 263         r = amdgpu_bo_kmap(adev->vram_scratch.robj,
 264                                 (void **)&adev->vram_scratch.ptr);
 265         if (r)
 266                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 267         amdgpu_bo_unreserve(adev->vram_scratch.robj);
 268
 269         return r;
 270 }
 271
 272 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
 273 {
 274         int r;
 275
 276         if (adev->vram_scratch.robj == NULL) {
 277                 return;
 278         }
 279         r = amdgpu_bo_reserve(adev->vram_scratch.robj, false);
 280         if (likely(r == 0)) {
 281                 amdgpu_bo_kunmap(adev->vram_scratch.robj);
 282                 amdgpu_bo_unpin(adev->vram_scratch.robj);
 283                 amdgpu_bo_unreserve(adev->vram_scratch.robj);
 284         }
 285         amdgpu_bo_unref(&adev->vram_scratch.robj);
 286 }
 287
 288 /**
 289  * amdgpu_program_register_sequence - program an array of registers.
 290  *
 291  * @adev: amdgpu_device pointer
 292  * @registers: pointer to the register array
 293  * @array_size: size of the register array
 294  *
 295  * Programs an array or registers with and and or masks.
 296  * This is a helper for setting golden registers.
 297  */
 298 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
 299                                       const u32 *registers,
 300                                       const u32 array_size)
 301 {
 302         u32 tmp, reg, and_mask, or_mask;
 303         int i;
 304
 305         if (array_size % 3)
 306                 return;
 307
 308         for (i = 0; i < array_size; i +=3) {
 309                 reg = registers[i + 0];
 310                 and_mask = registers[i + 1];
 311                 or_mask = registers[i + 2];
 312
 313                 if (and_mask == 0xffffffff) {
 314                         tmp = or_mask;
 315                 } else {
 316                         tmp = RREG32(reg);
 317                         tmp &= ~and_mask;
 318                         tmp |= or_mask;
 319                 }
 320                 WREG32(reg, tmp);
 321         }
 322 }
 323
 324 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
 325 {
 326         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
 327 }
 328
 329 /*
 330  * GPU doorbell aperture helpers function.
 331  */
 332 /**
 333  * amdgpu_doorbell_init - Init doorbell driver information.
 334  *
 335  * @adev: amdgpu_device pointer
 336  *
 337  * Init doorbell driver information (CIK)
 338  * Returns 0 on success, error on failure.
 339  */
 340 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
 341 {
 342         /* doorbell bar mapping */
 343         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
 344         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
 345
 346         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
 347                                              AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
 348         if (adev->doorbell.num_doorbells == 0)
 349                 return -EINVAL;
 350
 351         adev->doorbell.ptr = ioremap(adev->doorbell.base, adev->doorbell.num_doorbells * sizeof(u32));
 352         if (adev->doorbell.ptr == NULL) {
 353                 return -ENOMEM;
 354         }
 355         DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)adev->doorbell.base);
 356         DRM_INFO("doorbell mmio size: %u\n", (unsigned)adev->doorbell.size);
 357
 358         return 0;
 359 }
 360
 361 /**
 362  * amdgpu_doorbell_fini - Tear down doorbell driver information.
 363  *
 364  * @adev: amdgpu_device pointer
 365  *
 366  * Tear down doorbell driver information (CIK)
 367  */
 368 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
 369 {
 370         iounmap(adev->doorbell.ptr);
 371         adev->doorbell.ptr = NULL;
 372 }
 373
 374 /**
 375  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
 376  *                                setup amdkfd
 377  *
 378  * @adev: amdgpu_device pointer
 379  * @aperture_base: output returning doorbell aperture base physical address
 380  * @aperture_size: output returning doorbell aperture size in bytes
 381  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
 382  *
 383  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
 384  * takes doorbells required for its own rings and reports the setup to amdkfd.
 385  * amdgpu reserved doorbells are at the start of the doorbell aperture.
 386  */
 387 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
 388                                 phys_addr_t *aperture_base,
 389                                 size_t *aperture_size,
 390                                 size_t *start_offset)
 391 {
 392         /*
 393          * The first num_doorbells are used by amdgpu.
 394          * amdkfd takes whatever's left in the aperture.
 395          */
 396         if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
 397                 *aperture_base = adev->doorbell.base;
 398                 *aperture_size = adev->doorbell.size;
 399                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
 400         } else {
 401                 *aperture_base = 0;
 402                 *aperture_size = 0;
 403                 *start_offset = 0;
 404         }
 405 }
 406
 407 /*
 408  * amdgpu_wb_*()
 409  * Writeback is the the method by which the the GPU updates special pages
 410  * in memory with the status of certain GPU events (fences, ring pointers,
 411  * etc.).
 412  */
 413
 414 /**
 415  * amdgpu_wb_fini - Disable Writeback and free memory
 416  *
 417  * @adev: amdgpu_device pointer
 418  *
 419  * Disables Writeback and frees the Writeback memory (all asics).
 420  * Used at driver shutdown.
 421  */
 422 static void amdgpu_wb_fini(struct amdgpu_device *adev)
 423 {
 424         if (adev->wb.wb_obj) {
 425                 if (!amdgpu_bo_reserve(adev->wb.wb_obj, false)) {
 426                         amdgpu_bo_kunmap(adev->wb.wb_obj);
 427                         amdgpu_bo_unpin(adev->wb.wb_obj);
 428                         amdgpu_bo_unreserve(adev->wb.wb_obj);
 429                 }
 430                 amdgpu_bo_unref(&adev->wb.wb_obj);
 431                 adev->wb.wb = NULL;
 432                 adev->wb.wb_obj = NULL;
 433         }
 434 }
 435
 436 /**
 437  * amdgpu_wb_init- Init Writeback driver info and allocate memory
 438  *
 439  * @adev: amdgpu_device pointer
 440  *
 441  * Disables Writeback and frees the Writeback memory (all asics).
 442  * Used at driver startup.
 443  * Returns 0 on success or an -error on failure.
 444  */
 445 static int amdgpu_wb_init(struct amdgpu_device *adev)
 446 {
 447         int r;
 448
 449         if (adev->wb.wb_obj == NULL) {
 450                 r = amdgpu_bo_create(adev, AMDGPU_MAX_WB * 4, PAGE_SIZE, true,
 451                                      AMDGPU_GEM_DOMAIN_GTT, 0,  NULL, &adev->wb.wb_obj);
 452                 if (r) {
 453                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
 454                         return r;
 455                 }
 456                 r = amdgpu_bo_reserve(adev->wb.wb_obj, false);
 457                 if (unlikely(r != 0)) {
 458                         amdgpu_wb_fini(adev);
 459                         return r;
 460                 }
 461                 r = amdgpu_bo_pin(adev->wb.wb_obj, AMDGPU_GEM_DOMAIN_GTT,
 462                                 &adev->wb.gpu_addr);
 463                 if (r) {
 464                         amdgpu_bo_unreserve(adev->wb.wb_obj);
 465                         dev_warn(adev->dev, "(%d) pin WB bo failed\n", r);
 466                         amdgpu_wb_fini(adev);
 467                         return r;
 468                 }
 469                 r = amdgpu_bo_kmap(adev->wb.wb_obj, (void **)&adev->wb.wb);
 470                 amdgpu_bo_unreserve(adev->wb.wb_obj);
 471                 if (r) {
 472                         dev_warn(adev->dev, "(%d) map WB bo failed\n", r);
 473                         amdgpu_wb_fini(adev);
 474                         return r;
 475                 }
 476
 477                 adev->wb.num_wb = AMDGPU_MAX_WB;
 478                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
 479
 480                 /* clear wb memory */
 481                 memset((char *)adev->wb.wb, 0, AMDGPU_GPU_PAGE_SIZE);
 482         }
 483
 484         return 0;
 485 }
 486
 487 /**
 488  * amdgpu_wb_get - Allocate a wb entry
 489  *
 490  * @adev: amdgpu_device pointer
 491  * @wb: wb index
 492  *
 493  * Allocate a wb slot for use by the driver (all asics).
 494  * Returns 0 on success or -EINVAL on failure.
 495  */
 496 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
 497 {
 498         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
 499         if (offset < adev->wb.num_wb) {
 500                 __set_bit(offset, adev->wb.used);
 501                 *wb = offset;
 502                 return 0;
 503         } else {
 504                 return -EINVAL;
 505         }
 506 }
 507
 508 /**
 509  * amdgpu_wb_free - Free a wb entry
 510  *
 511  * @adev: amdgpu_device pointer
 512  * @wb: wb index
 513  *
 514  * Free a wb slot allocated for use by the driver (all asics)
 515  */
 516 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
 517 {
 518         if (wb < adev->wb.num_wb)
 519                 __clear_bit(wb, adev->wb.used);
 520 }
 521
 522 /**
 523  * amdgpu_vram_location - try to find VRAM location
 524  * @adev: amdgpu device structure holding all necessary informations
 525  * @mc: memory controller structure holding memory informations
 526  * @base: base address at which to put VRAM
 527  *
 528  * Function will place try to place VRAM at base address provided
 529  * as parameter (which is so far either PCI aperture address or
 530  * for IGP TOM base address).
 531  *
 532  * If there is not enough space to fit the unvisible VRAM in the 32bits
 533  * address space then we limit the VRAM size to the aperture.
 534  *
 535  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
 536  * this shouldn't be a problem as we are using the PCI aperture as a reference.
 537  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
 538  * not IGP.
 539  *
 540  * Note: we use mc_vram_size as on some board we need to program the mc to
 541  * cover the whole aperture even if VRAM size is inferior to aperture size
 542  * Novell bug 204882 + along with lots of ubuntu ones
 543  *
 544  * Note: when limiting vram it's safe to overwritte real_vram_size because
 545  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
 546  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
 547  * ones)
 548  *
 549  * Note: IGP TOM addr should be the same as the aperture addr, we don't
 550  * explicitly check for that thought.
 551  *
 552  * FIXME: when reducing VRAM size align new size on power of 2.
 553  */
 554 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
 555 {
 556         uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
 557
 558         mc->vram_start = base;
 559         if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
 560                 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
 561                 mc->real_vram_size = mc->aper_size;
 562                 mc->mc_vram_size = mc->aper_size;
 563         }
 564         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 565         if (limit && limit < mc->real_vram_size)
 566                 mc->real_vram_size = limit;
 567         dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
 568                         mc->mc_vram_size >> 20, mc->vram_start,
 569                         mc->vram_end, mc->real_vram_size >> 20);
 570 }
 571
 572 /**
 573  * amdgpu_gtt_location - try to find GTT location
 574  * @adev: amdgpu device structure holding all necessary informations
 575  * @mc: memory controller structure holding memory informations
 576  *
 577  * Function will place try to place GTT before or after VRAM.
 578  *
 579  * If GTT size is bigger than space left then we ajust GTT size.
 580  * Thus function will never fails.
 581  *
 582  * FIXME: when reducing GTT size align new size on power of 2.
 583  */
 584 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
 585 {
 586         u64 size_af, size_bf;
 587
 588         size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
 589         size_bf = mc->vram_start & ~mc->gtt_base_align;
 590         if (size_bf > size_af) {
 591                 if (mc->gtt_size > size_bf) {
 592                         dev_warn(adev->dev, "limiting GTT\n");
 593                         mc->gtt_size = size_bf;
 594                 }
 595                 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
 596         } else {
 597                 if (mc->gtt_size > size_af) {
 598                         dev_warn(adev->dev, "limiting GTT\n");
 599                         mc->gtt_size = size_af;
 600                 }
 601                 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
 602         }
 603         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
 604         dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
 605                         mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
 606 }
 607
 608 /*
 609  * GPU helpers function.
 610  */
 611 /**
 612  * amdgpu_card_posted - check if the hw has already been initialized
 613  *
 614  * @adev: amdgpu_device pointer
 615  *
 616  * Check if the asic has been initialized (all asics).
 617  * Used at driver startup.
 618  * Returns true if initialized or false if not.
 619  */
 620 bool amdgpu_card_posted(struct amdgpu_device *adev)
 621 {
 622         uint32_t reg;
 623
 624         /* then check MEM_SIZE, in case the crtcs are off */
 625         reg = RREG32(mmCONFIG_MEMSIZE);
 626
 627         if (reg)
 628                 return true;
 629
 630         return false;
 631
 632 }
 633
 634 /**
 635  * amdgpu_boot_test_post_card - check and possibly initialize the hw
 636  *
 637  * @adev: amdgpu_device pointer
 638  *
 639  * Check if the asic is initialized and if not, attempt to initialize
 640  * it (all asics).
 641  * Returns true if initialized or false if not.
 642  */
 643 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev)
 644 {
 645         if (amdgpu_card_posted(adev))
 646                 return true;
 647
 648         if (adev->bios) {
 649                 DRM_INFO("GPU not posted. posting now...\n");
 650                 if (adev->is_atom_bios)
 651                         amdgpu_atom_asic_init(adev->mode_info.atom_context);
 652                 return true;
 653         } else {
 654                 dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
 655                 return false;
 656         }
 657 }
 658
 659 /**
 660  * amdgpu_dummy_page_init - init dummy page used by the driver
 661  *
 662  * @adev: amdgpu_device pointer
 663  *
 664  * Allocate the dummy page used by the driver (all asics).
 665  * This dummy page is used by the driver as a filler for gart entries
 666  * when pages are taken out of the GART
 667  * Returns 0 on sucess, -ENOMEM on failure.
 668  */
 669 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
 670 {
 671         if (adev->dummy_page.page)
 672                 return 0;
 673         adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
 674         if (adev->dummy_page.page == NULL)
 675                 return -ENOMEM;
 676         adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
 677                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 678         if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
 679                 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
 680                 __free_page(adev->dummy_page.page);
 681                 adev->dummy_page.page = NULL;
 682                 return -ENOMEM;
 683         }
 684         return 0;
 685 }
 686
 687 /**
 688  * amdgpu_dummy_page_fini - free dummy page used by the driver
 689  *
 690  * @adev: amdgpu_device pointer
 691  *
 692  * Frees the dummy page used by the driver (all asics).
 693  */
 694 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
 695 {
 696         if (adev->dummy_page.page == NULL)
 697                 return;
 698         pci_unmap_page(adev->pdev, adev->dummy_page.addr,
 699                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 700         __free_page(adev->dummy_page.page);
 701         adev->dummy_page.page = NULL;
 702 }
 703
 704
 705 /* ATOM accessor methods */
 706 /*
 707  * ATOM is an interpreted byte code stored in tables in the vbios.  The
 708  * driver registers callbacks to access registers and the interpreter
 709  * in the driver parses the tables and executes then to program specific
 710  * actions (set display modes, asic init, etc.).  See amdgpu_atombios.c,
 711  * atombios.h, and atom.c
 712  */
 713
 714 /**
 715  * cail_pll_read - read PLL register
 716  *
 717  * @info: atom card_info pointer
 718  * @reg: PLL register offset
 719  *
 720  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 721  * Returns the value of the PLL register.
 722  */
 723 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
 724 {
 725         return 0;
 726 }
 727
 728 /**
 729  * cail_pll_write - write PLL register
 730  *
 731  * @info: atom card_info pointer
 732  * @reg: PLL register offset
 733  * @val: value to write to the pll register
 734  *
 735  * Provides a PLL register accessor for the atom interpreter (r4xx+).
 736  */
 737 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
 738 {
 739
 740 }
 741
 742 /**
 743  * cail_mc_read - read MC (Memory Controller) register
 744  *
 745  * @info: atom card_info pointer
 746  * @reg: MC register offset
 747  *
 748  * Provides an MC register accessor for the atom interpreter (r4xx+).
 749  * Returns the value of the MC register.
 750  */
 751 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 752 {
 753         return 0;
 754 }
 755
 756 /**
 757  * cail_mc_write - write MC (Memory Controller) register
 758  *
 759  * @info: atom card_info pointer
 760  * @reg: MC register offset
 761  * @val: value to write to the pll register
 762  *
 763  * Provides a MC register accessor for the atom interpreter (r4xx+).
 764  */
 765 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 766 {
 767
 768 }
 769
 770 /**
 771  * cail_reg_write - write MMIO register
 772  *
 773  * @info: atom card_info pointer
 774  * @reg: MMIO register offset
 775  * @val: value to write to the pll register
 776  *
 777  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
 778  */
 779 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 780 {
 781         struct amdgpu_device *adev = info->dev->dev_private;
 782
 783         WREG32(reg, val);
 784 }
 785
 786 /**
 787  * cail_reg_read - read MMIO register
 788  *
 789  * @info: atom card_info pointer
 790  * @reg: MMIO register offset
 791  *
 792  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
 793  * Returns the value of the MMIO register.
 794  */
 795 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 796 {
 797         struct amdgpu_device *adev = info->dev->dev_private;
 798         uint32_t r;
 799
 800         r = RREG32(reg);
 801         return r;
 802 }
 803
 804 /**
 805  * cail_ioreg_write - write IO register
 806  *
 807  * @info: atom card_info pointer
 808  * @reg: IO register offset
 809  * @val: value to write to the pll register
 810  *
 811  * Provides a IO register accessor for the atom interpreter (r4xx+).
 812  */
 813 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
 814 {
 815         struct amdgpu_device *adev = info->dev->dev_private;
 816
 817         WREG32_IO(reg, val);
 818 }
 819
 820 /**
 821  * cail_ioreg_read - read IO register
 822  *
 823  * @info: atom card_info pointer
 824  * @reg: IO register offset
 825  *
 826  * Provides an IO register accessor for the atom interpreter (r4xx+).
 827  * Returns the value of the IO register.
 828  */
 829 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
 830 {
 831         struct amdgpu_device *adev = info->dev->dev_private;
 832         uint32_t r;
 833
 834         r = RREG32_IO(reg);
 835         return r;
 836 }
 837
 838 /**
 839  * amdgpu_atombios_fini - free the driver info and callbacks for atombios
 840  *
 841  * @adev: amdgpu_device pointer
 842  *
 843  * Frees the driver info and register access callbacks for the ATOM
 844  * interpreter (r4xx+).
 845  * Called at driver shutdown.
 846  */
 847 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
 848 {
 849         if (adev->mode_info.atom_context)
 850                 kfree(adev->mode_info.atom_context->scratch);
 851         kfree(adev->mode_info.atom_context);
 852         adev->mode_info.atom_context = NULL;
 853         kfree(adev->mode_info.atom_card_info);
 854         adev->mode_info.atom_card_info = NULL;
 855 }
 856
 857 /**
 858  * amdgpu_atombios_init - init the driver info and callbacks for atombios
 859  *
 860  * @adev: amdgpu_device pointer
 861  *
 862  * Initializes the driver info and register access callbacks for the
 863  * ATOM interpreter (r4xx+).
 864  * Returns 0 on sucess, -ENOMEM on failure.
 865  * Called at driver startup.
 866  */
 867 static int amdgpu_atombios_init(struct amdgpu_device *adev)
 868 {
 869         struct card_info *atom_card_info =
 870             kzalloc(sizeof(struct card_info), GFP_KERNEL);
 871
 872         if (!atom_card_info)
 873                 return -ENOMEM;
 874
 875         adev->mode_info.atom_card_info = atom_card_info;
 876         atom_card_info->dev = adev->ddev;
 877         atom_card_info->reg_read = cail_reg_read;
 878         atom_card_info->reg_write = cail_reg_write;
 879         /* needed for iio ops */
 880         if (adev->rio_mem) {
 881                 atom_card_info->ioreg_read = cail_ioreg_read;
 882                 atom_card_info->ioreg_write = cail_ioreg_write;
 883         } else {
 884                 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
 885                 atom_card_info->ioreg_read = cail_reg_read;
 886                 atom_card_info->ioreg_write = cail_reg_write;
 887         }
 888         atom_card_info->mc_read = cail_mc_read;
 889         atom_card_info->mc_write = cail_mc_write;
 890         atom_card_info->pll_read = cail_pll_read;
 891         atom_card_info->pll_write = cail_pll_write;
 892
 893         adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
 894         if (!adev->mode_info.atom_context) {
 895                 amdgpu_atombios_fini(adev);
 896                 return -ENOMEM;
 897         }
 898
 899         mutex_init(&adev->mode_info.atom_context->mutex);
 900         amdgpu_atombios_scratch_regs_init(adev);
 901         amdgpu_atom_allocate_fb_scratch(adev->mode_info.atom_context);
 902         return 0;
 903 }
 904
 905 /* if we get transitioned to only one device, take VGA back */
 906 /**
 907  * amdgpu_vga_set_decode - enable/disable vga decode
 908  *
 909  * @cookie: amdgpu_device pointer
 910  * @state: enable/disable vga decode
 911  *
 912  * Enable/disable vga decode (all asics).
 913  * Returns VGA resource flags.
 914  */
 915 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
 916 {
 917         struct amdgpu_device *adev = cookie;
 918         amdgpu_asic_set_vga_state(adev, state);
 919         if (state)
 920                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 921                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 922         else
 923                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 924 }
 925
 926 /**
 927  * amdgpu_check_pot_argument - check that argument is a power of two
 928  *
 929  * @arg: value to check
 930  *
 931  * Validates that a certain argument is a power of two (all asics).
 932  * Returns true if argument is valid.
 933  */
 934 static bool amdgpu_check_pot_argument(int arg)
 935 {
 936         return (arg & (arg - 1)) == 0;
 937 }
 938
 939 /**
 940  * amdgpu_check_arguments - validate module params
 941  *
 942  * @adev: amdgpu_device pointer
 943  *
 944  * Validates certain module parameters and updates
 945  * the associated values used by the driver (all asics).
 946  */
 947 static void amdgpu_check_arguments(struct amdgpu_device *adev)
 948 {
 949         /* vramlimit must be a power of two */
 950         if (!amdgpu_check_pot_argument(amdgpu_vram_limit)) {
 951                 dev_warn(adev->dev, "vram limit (%d) must be a power of 2\n",
 952                                 amdgpu_vram_limit);
 953                 amdgpu_vram_limit = 0;
 954         }
 955
 956         if (amdgpu_gart_size != -1) {
 957                 /* gtt size must be power of two and greater or equal to 32M */
 958                 if (amdgpu_gart_size < 32) {
 959                         dev_warn(adev->dev, "gart size (%d) too small\n",
 960                                  amdgpu_gart_size);
 961                         amdgpu_gart_size = -1;
 962                 } else if (!amdgpu_check_pot_argument(amdgpu_gart_size)) {
 963                         dev_warn(adev->dev, "gart size (%d) must be a power of 2\n",
 964                                  amdgpu_gart_size);
 965                         amdgpu_gart_size = -1;
 966                 }
 967         }
 968
 969         if (!amdgpu_check_pot_argument(amdgpu_vm_size)) {
 970                 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
 971                          amdgpu_vm_size);
 972                 amdgpu_vm_size = 8;
 973         }
 974
 975         if (amdgpu_vm_size < 1) {
 976                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
 977                          amdgpu_vm_size);
 978                 amdgpu_vm_size = 8;
 979         }
 980
 981         /*
 982          * Max GPUVM size for Cayman, SI and CI are 40 bits.
 983          */
 984         if (amdgpu_vm_size > 1024) {
 985                 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
 986                          amdgpu_vm_size);
 987                 amdgpu_vm_size = 8;
 988         }
 989
 990         /* defines number of bits in page table versus page directory,
 991          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
 992          * page table and the remaining bits are in the page directory */
 993         if (amdgpu_vm_block_size == -1) {
 994
 995                 /* Total bits covered by PD + PTs */
 996                 unsigned bits = ilog2(amdgpu_vm_size) + 18;
 997
 998                 /* Make sure the PD is 4K in size up to 8GB address space.
 999                    Above that split equal between PD and PTs */
1000                 if (amdgpu_vm_size <= 8)
1001                         amdgpu_vm_block_size = bits - 9;
1002                 else
1003                         amdgpu_vm_block_size = (bits + 3) / 2;
1004
1005         } else if (amdgpu_vm_block_size < 9) {
1006                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1007                          amdgpu_vm_block_size);
1008                 amdgpu_vm_block_size = 9;
1009         }
1010
1011         if (amdgpu_vm_block_size > 24 ||
1012             (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1013                 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1014                          amdgpu_vm_block_size);
1015                 amdgpu_vm_block_size = 9;
1016         }
1017 }
1018
1019 /**
1020  * amdgpu_switcheroo_set_state - set switcheroo state
1021  *
1022  * @pdev: pci dev pointer
1023  * @state: vga switcheroo state
1024  *
1025  * Callback for the switcheroo driver.  Suspends or resumes the
1026  * the asics before or after it is powered up using ACPI methods.
1027  */
1028 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1029 {
1030         struct drm_device *dev = pci_get_drvdata(pdev);
1031
1032         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1033                 return;
1034
1035         if (state == VGA_SWITCHEROO_ON) {
1036                 unsigned d3_delay = dev->pdev->d3_delay;
1037
1038                 printk(KERN_INFO "amdgpu: switched on\n");
1039                 /* don't suspend or resume card normally */
1040                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1041
1042                 amdgpu_resume_kms(dev, true, true);
1043
1044                 dev->pdev->d3_delay = d3_delay;
1045
1046                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1047                 drm_kms_helper_poll_enable(dev);
1048         } else {
1049                 printk(KERN_INFO "amdgpu: switched off\n");
1050                 drm_kms_helper_poll_disable(dev);
1051                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1052                 amdgpu_suspend_kms(dev, true, true);
1053                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1054         }
1055 }
1056
1057 /**
1058  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1059  *
1060  * @pdev: pci dev pointer
1061  *
1062  * Callback for the switcheroo driver.  Check of the switcheroo
1063  * state can be changed.
1064  * Returns true if the state can be changed, false if not.
1065  */
1066 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1067 {
1068         struct drm_device *dev = pci_get_drvdata(pdev);
1069
1070         /*
1071         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1072         * locking inversion with the driver load path. And the access here is
1073         * completely racy anyway. So don't bother with locking for now.
1074         */
1075         return dev->open_count == 0;
1076 }
1077
1078 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1079         .set_gpu_state = amdgpu_switcheroo_set_state,
1080         .reprobe = NULL,
1081         .can_switch = amdgpu_switcheroo_can_switch,
1082 };
1083
1084 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1085                                   enum amd_ip_block_type block_type,
1086                                   enum amd_clockgating_state state)
1087 {
1088         int i, r = 0;
1089
1090         for (i = 0; i < adev->num_ip_blocks; i++) {
1091                 if (adev->ip_blocks[i].type == block_type) {
1092                         r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1093                                                                             state);
1094                         if (r)
1095                                 return r;
1096                 }
1097         }
1098         return r;
1099 }
1100
1101 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1102                                   enum amd_ip_block_type block_type,
1103                                   enum amd_powergating_state state)
1104 {
1105         int i, r = 0;
1106
1107         for (i = 0; i < adev->num_ip_blocks; i++) {
1108                 if (adev->ip_blocks[i].type == block_type) {
1109                         r = adev->ip_blocks[i].funcs->set_powergating_state((void *)adev,
1110                                                                             state);
1111                         if (r)
1112                                 return r;
1113                 }
1114         }
1115         return r;
1116 }
1117
1118 const struct amdgpu_ip_block_version * amdgpu_get_ip_block(
1119                                         struct amdgpu_device *adev,
1120                                         enum amd_ip_block_type type)
1121 {
1122         int i;
1123
1124         for (i = 0; i < adev->num_ip_blocks; i++)
1125                 if (adev->ip_blocks[i].type == type)
1126                         return &adev->ip_blocks[i];
1127
1128         return NULL;
1129 }
1130
1131 /**
1132  * amdgpu_ip_block_version_cmp
1133  *
1134  * @adev: amdgpu_device pointer
1135  * @type: enum amd_ip_block_type
1136  * @major: major version
1137  * @minor: minor version
1138  *
1139  * return 0 if equal or greater
1140  * return 1 if smaller or the ip_block doesn't exist
1141  */
1142 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1143                                 enum amd_ip_block_type type,
1144                                 u32 major, u32 minor)
1145 {
1146         const struct amdgpu_ip_block_version *ip_block;
1147         ip_block = amdgpu_get_ip_block(adev, type);
1148
1149         if (ip_block && ((ip_block->major > major) ||
1150                         ((ip_block->major == major) &&
1151                         (ip_block->minor >= minor))))
1152                 return 0;
1153
1154         return 1;
1155 }
1156
1157 static int amdgpu_early_init(struct amdgpu_device *adev)
1158 {
1159         int i, r;
1160
1161         switch (adev->asic_type) {
1162         case CHIP_TOPAZ:
1163         case CHIP_TONGA:
1164         case CHIP_FIJI:
1165         case CHIP_CARRIZO:
1166                 if (adev->asic_type == CHIP_CARRIZO)
1167                         adev->family = AMDGPU_FAMILY_CZ;
1168                 else
1169                         adev->family = AMDGPU_FAMILY_VI;
1170
1171                 r = vi_set_ip_blocks(adev);
1172                 if (r)
1173                         return r;
1174                 break;
1175 #ifdef CONFIG_DRM_AMDGPU_CIK
1176         case CHIP_BONAIRE:
1177         case CHIP_HAWAII:
1178         case CHIP_KAVERI:
1179         case CHIP_KABINI:
1180         case CHIP_MULLINS:
1181                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1182                         adev->family = AMDGPU_FAMILY_CI;
1183                 else
1184                         adev->family = AMDGPU_FAMILY_KV;
1185
1186                 r = cik_set_ip_blocks(adev);
1187                 if (r)
1188                         return r;
1189                 break;
1190 #endif
1191         default:
1192                 /* FIXME: not supported yet */
1193                 return -EINVAL;
1194         }
1195
1196         adev->ip_block_status = kcalloc(adev->num_ip_blocks,
1197                                         sizeof(struct amdgpu_ip_block_status), GFP_KERNEL);
1198         if (adev->ip_block_status == NULL)
1199                 return -ENOMEM;
1200
1201         if (adev->ip_blocks == NULL) {
1202                 DRM_ERROR("No IP blocks found!\n");
1203                 return r;
1204         }
1205
1206         for (i = 0; i < adev->num_ip_blocks; i++) {
1207                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1208                         DRM_ERROR("disabled ip block: %d\n", i);
1209                         adev->ip_block_status[i].valid = false;
1210                 } else {
1211                         if (adev->ip_blocks[i].funcs->early_init) {
1212                                 r = adev->ip_blocks[i].funcs->early_init((void *)adev);
1213                                 if (r == -ENOENT)
1214                                         adev->ip_block_status[i].valid = false;
1215                                 else if (r)
1216                                         return r;
1217                                 else
1218                                         adev->ip_block_status[i].valid = true;
1219                         } else {
1220                                 adev->ip_block_status[i].valid = true;
1221                         }
1222                 }
1223         }
1224
1225         return 0;
1226 }
1227
1228 static int amdgpu_init(struct amdgpu_device *adev)
1229 {
1230         int i, r;
1231
1232         for (i = 0; i < adev->num_ip_blocks; i++) {
1233                 if (!adev->ip_block_status[i].valid)
1234                         continue;
1235                 r = adev->ip_blocks[i].funcs->sw_init((void *)adev);
1236                 if (r)
1237                         return r;
1238                 adev->ip_block_status[i].sw = true;
1239                 /* need to do gmc hw init early so we can allocate gpu mem */
1240                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1241                         r = amdgpu_vram_scratch_init(adev);
1242                         if (r)
1243                                 return r;
1244                         r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1245                         if (r)
1246                                 return r;
1247                         r = amdgpu_wb_init(adev);
1248                         if (r)
1249                                 return r;
1250                         adev->ip_block_status[i].hw = true;
1251                 }
1252         }
1253
1254         for (i = 0; i < adev->num_ip_blocks; i++) {
1255                 if (!adev->ip_block_status[i].sw)
1256                         continue;
1257                 /* gmc hw init is done early */
1258                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC)
1259                         continue;
1260                 r = adev->ip_blocks[i].funcs->hw_init((void *)adev);
1261                 if (r)
1262                         return r;
1263                 adev->ip_block_status[i].hw = true;
1264         }
1265
1266         return 0;
1267 }
1268
1269 static int amdgpu_late_init(struct amdgpu_device *adev)
1270 {
1271         int i = 0, r;
1272
1273         for (i = 0; i < adev->num_ip_blocks; i++) {
1274                 if (!adev->ip_block_status[i].valid)
1275                         continue;
1276                 /* enable clockgating to save power */
1277                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1278                                                                     AMD_CG_STATE_GATE);
1279                 if (r)
1280                         return r;
1281                 if (adev->ip_blocks[i].funcs->late_init) {
1282                         r = adev->ip_blocks[i].funcs->late_init((void *)adev);
1283                         if (r)
1284                                 return r;
1285                 }
1286         }
1287
1288         return 0;
1289 }
1290
1291 static int amdgpu_fini(struct amdgpu_device *adev)
1292 {
1293         int i, r;
1294
1295         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1296                 if (!adev->ip_block_status[i].hw)
1297                         continue;
1298                 if (adev->ip_blocks[i].type == AMD_IP_BLOCK_TYPE_GMC) {
1299                         amdgpu_wb_fini(adev);
1300                         amdgpu_vram_scratch_fini(adev);
1301                 }
1302                 /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1303                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1304                                                                     AMD_CG_STATE_UNGATE);
1305                 if (r)
1306                         return r;
1307                 r = adev->ip_blocks[i].funcs->hw_fini((void *)adev);
1308                 /* XXX handle errors */
1309                 adev->ip_block_status[i].hw = false;
1310         }
1311
1312         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1313                 if (!adev->ip_block_status[i].sw)
1314                         continue;
1315                 r = adev->ip_blocks[i].funcs->sw_fini((void *)adev);
1316                 /* XXX handle errors */
1317                 adev->ip_block_status[i].sw = false;
1318                 adev->ip_block_status[i].valid = false;
1319         }
1320
1321         return 0;
1322 }
1323
1324 static int amdgpu_suspend(struct amdgpu_device *adev)
1325 {
1326         int i, r;
1327
1328         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1329                 if (!adev->ip_block_status[i].valid)
1330                         continue;
1331                 /* ungate blocks so that suspend can properly shut them down */
1332                 r = adev->ip_blocks[i].funcs->set_clockgating_state((void *)adev,
1333                                                                     AMD_CG_STATE_UNGATE);
1334                 /* XXX handle errors */
1335                 r = adev->ip_blocks[i].funcs->suspend(adev);
1336                 /* XXX handle errors */
1337         }
1338
1339         return 0;
1340 }
1341
1342 static int amdgpu_resume(struct amdgpu_device *adev)
1343 {
1344         int i, r;
1345
1346         for (i = 0; i < adev->num_ip_blocks; i++) {
1347                 if (!adev->ip_block_status[i].valid)
1348                         continue;
1349                 r = adev->ip_blocks[i].funcs->resume(adev);
1350                 if (r)
1351                         return r;
1352         }
1353
1354         return 0;
1355 }
1356
1357 /**
1358  * amdgpu_device_init - initialize the driver
1359  *
1360  * @adev: amdgpu_device pointer
1361  * @pdev: drm dev pointer
1362  * @pdev: pci dev pointer
1363  * @flags: driver flags
1364  *
1365  * Initializes the driver info and hw (all asics).
1366  * Returns 0 for success or an error on failure.
1367  * Called at driver startup.
1368  */
1369 int amdgpu_device_init(struct amdgpu_device *adev,
1370                        struct drm_device *ddev,
1371                        struct pci_dev *pdev,
1372                        uint32_t flags)
1373 {
1374         int r, i;
1375         bool runtime = false;
1376
1377         adev->shutdown = false;
1378         adev->dev = &pdev->dev;
1379         adev->ddev = ddev;
1380         adev->pdev = pdev;
1381         adev->flags = flags;
1382         adev->asic_type = flags & AMD_ASIC_MASK;
1383         adev->is_atom_bios = false;
1384         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1385         adev->mc.gtt_size = 512 * 1024 * 1024;
1386         adev->accel_working = false;
1387         adev->num_rings = 0;
1388         adev->mman.buffer_funcs = NULL;
1389         adev->mman.buffer_funcs_ring = NULL;
1390         adev->vm_manager.vm_pte_funcs = NULL;
1391         adev->vm_manager.vm_pte_funcs_ring = NULL;
1392         adev->gart.gart_funcs = NULL;
1393         adev->fence_context = fence_context_alloc(AMDGPU_MAX_RINGS);
1394
1395         adev->smc_rreg = &amdgpu_invalid_rreg;
1396         adev->smc_wreg = &amdgpu_invalid_wreg;
1397         adev->pcie_rreg = &amdgpu_invalid_rreg;
1398         adev->pcie_wreg = &amdgpu_invalid_wreg;
1399         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
1400         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
1401         adev->didt_rreg = &amdgpu_invalid_rreg;
1402         adev->didt_wreg = &amdgpu_invalid_wreg;
1403         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
1404         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
1405
1406         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1407                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
1408                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1409
1410         /* mutex initialization are all done here so we
1411          * can recall function without having locking issues */
1412         mutex_init(&adev->ring_lock);
1413         atomic_set(&adev->irq.ih.lock, 0);
1414         mutex_init(&adev->gem.mutex);
1415         mutex_init(&adev->pm.mutex);
1416         mutex_init(&adev->gfx.gpu_clock_mutex);
1417         mutex_init(&adev->srbm_mutex);
1418         mutex_init(&adev->grbm_idx_mutex);
1419         init_rwsem(&adev->exclusive_lock);
1420         mutex_init(&adev->mn_lock);
1421         hash_init(adev->mn_hash);
1422
1423         amdgpu_check_arguments(adev);
1424
1425         /* Registers mapping */
1426         /* TODO: block userspace mapping of io register */
1427         spin_lock_init(&adev->mmio_idx_lock);
1428         spin_lock_init(&adev->smc_idx_lock);
1429         spin_lock_init(&adev->pcie_idx_lock);
1430         spin_lock_init(&adev->uvd_ctx_idx_lock);
1431         spin_lock_init(&adev->didt_idx_lock);
1432         spin_lock_init(&adev->audio_endpt_idx_lock);
1433
1434         adev->rmmio_base = pci_resource_start(adev->pdev, 5);
1435         adev->rmmio_size = pci_resource_len(adev->pdev, 5);
1436         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
1437         if (adev->rmmio == NULL) {
1438                 return -ENOMEM;
1439         }
1440         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
1441         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
1442
1443         /* doorbell bar mapping */
1444         amdgpu_doorbell_init(adev);
1445
1446         /* io port mapping */
1447         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1448                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
1449                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
1450                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
1451                         break;
1452                 }
1453         }
1454         if (adev->rio_mem == NULL)
1455                 DRM_ERROR("Unable to find PCI I/O BAR\n");
1456
1457         /* early init functions */
1458         r = amdgpu_early_init(adev);
1459         if (r)
1460                 return r;
1461
1462         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
1463         /* this will fail for cards that aren't VGA class devices, just
1464          * ignore it */
1465         vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
1466
1467         if (amdgpu_runtime_pm == 1)
1468                 runtime = true;
1469         if (amdgpu_device_is_px(ddev))
1470                 runtime = true;
1471         vga_switcheroo_register_client(adev->pdev, &amdgpu_switcheroo_ops, runtime);
1472         if (runtime)
1473                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
1474
1475         /* Read BIOS */
1476         if (!amdgpu_get_bios(adev))
1477                 return -EINVAL;
1478         /* Must be an ATOMBIOS */
1479         if (!adev->is_atom_bios) {
1480                 dev_err(adev->dev, "Expecting atombios for GPU\n");
1481                 return -EINVAL;
1482         }
1483         r = amdgpu_atombios_init(adev);
1484         if (r)
1485                 return r;
1486
1487         /* Post card if necessary */
1488         if (!amdgpu_card_posted(adev)) {
1489                 if (!adev->bios) {
1490                         dev_err(adev->dev, "Card not posted and no BIOS - ignoring\n");
1491                         return -EINVAL;
1492                 }
1493                 DRM_INFO("GPU not posted. posting now...\n");
1494                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
1495         }
1496
1497         /* Initialize clocks */
1498         r = amdgpu_atombios_get_clock_info(adev);
1499         if (r)
1500                 return r;
1501         /* init i2c buses */
1502         amdgpu_atombios_i2c_init(adev);
1503
1504         /* Fence driver */
1505         r = amdgpu_fence_driver_init(adev);
1506         if (r)
1507                 return r;
1508
1509         /* init the mode config */
1510         drm_mode_config_init(adev->ddev);
1511
1512         r = amdgpu_init(adev);
1513         if (r) {
1514                 amdgpu_fini(adev);
1515                 return r;
1516         }
1517
1518         adev->accel_working = true;
1519
1520         amdgpu_fbdev_init(adev);
1521
1522         r = amdgpu_ib_pool_init(adev);
1523         if (r) {
1524                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
1525                 return r;
1526         }
1527
1528         r = amdgpu_ib_ring_tests(adev);
1529         if (r)
1530                 DRM_ERROR("ib ring test failed (%d).\n", r);
1531
1532         r = amdgpu_gem_debugfs_init(adev);
1533         if (r) {
1534                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1535         }
1536
1537         r = amdgpu_debugfs_regs_init(adev);
1538         if (r) {
1539                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
1540         }
1541
1542         if ((amdgpu_testing & 1)) {
1543                 if (adev->accel_working)
1544                         amdgpu_test_moves(adev);
1545                 else
1546                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
1547         }
1548         if ((amdgpu_testing & 2)) {
1549                 if (adev->accel_working)
1550                         amdgpu_test_syncing(adev);
1551                 else
1552                         DRM_INFO("amdgpu: acceleration disabled, skipping sync tests\n");
1553         }
1554         if (amdgpu_benchmarking) {
1555                 if (adev->accel_working)
1556                         amdgpu_benchmark(adev, amdgpu_benchmarking);
1557                 else
1558                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
1559         }
1560
1561         /* enable clockgating, etc. after ib tests, etc. since some blocks require
1562          * explicit gating rather than handling it automatically.
1563          */
1564         r = amdgpu_late_init(adev);
1565         if (r)
1566                 return r;
1567
1568         return 0;
1569 }
1570
1571 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev);
1572
1573 /**
1574  * amdgpu_device_fini - tear down the driver
1575  *
1576  * @adev: amdgpu_device pointer
1577  *
1578  * Tear down the driver info (all asics).
1579  * Called at driver shutdown.
1580  */
1581 void amdgpu_device_fini(struct amdgpu_device *adev)
1582 {
1583         int r;
1584
1585         DRM_INFO("amdgpu: finishing device.\n");
1586         adev->shutdown = true;
1587         /* evict vram memory */
1588         amdgpu_bo_evict_vram(adev);
1589         amdgpu_ib_pool_fini(adev);
1590         amdgpu_fence_driver_fini(adev);
1591         amdgpu_fbdev_fini(adev);
1592         r = amdgpu_fini(adev);
1593         kfree(adev->ip_block_status);
1594         adev->ip_block_status = NULL;
1595         adev->accel_working = false;
1596         /* free i2c buses */
1597         amdgpu_i2c_fini(adev);
1598         amdgpu_atombios_fini(adev);
1599         kfree(adev->bios);
1600         adev->bios = NULL;
1601         vga_switcheroo_unregister_client(adev->pdev);
1602         vga_client_register(adev->pdev, NULL, NULL, NULL);
1603         if (adev->rio_mem)
1604                 pci_iounmap(adev->pdev, adev->rio_mem);
1605         adev->rio_mem = NULL;
1606         iounmap(adev->rmmio);
1607         adev->rmmio = NULL;
1608         amdgpu_doorbell_fini(adev);
1609         amdgpu_debugfs_regs_cleanup(adev);
1610         amdgpu_debugfs_remove_files(adev);
1611 }
1612
1613
1614 /*
1615  * Suspend & resume.
1616  */
1617 /**
1618  * amdgpu_suspend_kms - initiate device suspend
1619  *
1620  * @pdev: drm dev pointer
1621  * @state: suspend state
1622  *
1623  * Puts the hw in the suspend state (all asics).
1624  * Returns 0 for success or an error on failure.
1625  * Called at driver suspend.
1626  */
1627 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
1628 {
1629         struct amdgpu_device *adev;
1630         struct drm_crtc *crtc;
1631         struct drm_connector *connector;
1632         int r;
1633
1634         if (dev == NULL || dev->dev_private == NULL) {
1635                 return -ENODEV;
1636         }
1637
1638         adev = dev->dev_private;
1639
1640         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1641                 return 0;
1642
1643         drm_kms_helper_poll_disable(dev);
1644
1645         /* turn off display hw */
1646         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1647                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1648         }
1649
1650         /* unpin the front buffers */
1651         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1652                 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
1653                 struct amdgpu_bo *robj;
1654
1655                 if (rfb == NULL || rfb->obj == NULL) {
1656                         continue;
1657                 }
1658                 robj = gem_to_amdgpu_bo(rfb->obj);
1659                 /* don't unpin kernel fb objects */
1660                 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
1661                         r = amdgpu_bo_reserve(robj, false);
1662                         if (r == 0) {
1663                                 amdgpu_bo_unpin(robj);
1664                                 amdgpu_bo_unreserve(robj);
1665                         }
1666                 }
1667         }
1668         /* evict vram memory */
1669         amdgpu_bo_evict_vram(adev);
1670
1671         amdgpu_fence_driver_suspend(adev);
1672
1673         r = amdgpu_suspend(adev);
1674
1675         /* evict remaining vram memory */
1676         amdgpu_bo_evict_vram(adev);
1677
1678         pci_save_state(dev->pdev);
1679         if (suspend) {
1680                 /* Shut down the device */
1681                 pci_disable_device(dev->pdev);
1682                 pci_set_power_state(dev->pdev, PCI_D3hot);
1683         }
1684
1685         if (fbcon) {
1686                 console_lock();
1687                 amdgpu_fbdev_set_suspend(adev, 1);
1688                 console_unlock();
1689         }
1690         return 0;
1691 }
1692
1693 /**
1694  * amdgpu_resume_kms - initiate device resume
1695  *
1696  * @pdev: drm dev pointer
1697  *
1698  * Bring the hw back to operating state (all asics).
1699  * Returns 0 for success or an error on failure.
1700  * Called at driver resume.
1701  */
1702 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1703 {
1704         struct drm_connector *connector;
1705         struct amdgpu_device *adev = dev->dev_private;
1706         int r;
1707
1708         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1709                 return 0;
1710
1711         if (fbcon) {
1712                 console_lock();
1713         }
1714         if (resume) {
1715                 pci_set_power_state(dev->pdev, PCI_D0);
1716                 pci_restore_state(dev->pdev);
1717                 if (pci_enable_device(dev->pdev)) {
1718                         if (fbcon)
1719                                 console_unlock();
1720                         return -1;
1721                 }
1722         }
1723
1724         /* post card */
1725         amdgpu_atom_asic_init(adev->mode_info.atom_context);
1726
1727         r = amdgpu_resume(adev);
1728
1729         amdgpu_fence_driver_resume(adev);
1730
1731         r = amdgpu_ib_ring_tests(adev);
1732         if (r)
1733                 DRM_ERROR("ib ring test failed (%d).\n", r);
1734
1735         r = amdgpu_late_init(adev);
1736         if (r)
1737                 return r;
1738
1739         /* blat the mode back in */
1740         if (fbcon) {
1741                 drm_helper_resume_force_mode(dev);
1742                 /* turn on display hw */
1743                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1744                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1745                 }
1746         }
1747
1748         drm_kms_helper_poll_enable(dev);
1749
1750         if (fbcon) {
1751                 amdgpu_fbdev_set_suspend(adev, 0);
1752                 console_unlock();
1753         }
1754
1755         return 0;
1756 }
1757
1758 /**
1759  * amdgpu_gpu_reset - reset the asic
1760  *
1761  * @adev: amdgpu device pointer
1762  *
1763  * Attempt the reset the GPU if it has hung (all asics).
1764  * Returns 0 for success or an error on failure.
1765  */
1766 int amdgpu_gpu_reset(struct amdgpu_device *adev)
1767 {
1768         unsigned ring_sizes[AMDGPU_MAX_RINGS];
1769         uint32_t *ring_data[AMDGPU_MAX_RINGS];
1770
1771         bool saved = false;
1772
1773         int i, r;
1774         int resched;
1775
1776         down_write(&adev->exclusive_lock);
1777
1778         if (!adev->needs_reset) {
1779                 up_write(&adev->exclusive_lock);
1780                 return 0;
1781         }
1782
1783         adev->needs_reset = false;
1784         atomic_inc(&adev->gpu_reset_counter);
1785
1786         /* block TTM */
1787         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
1788
1789         r = amdgpu_suspend(adev);
1790
1791         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1792                 struct amdgpu_ring *ring = adev->rings[i];
1793                 if (!ring)
1794                         continue;
1795
1796                 ring_sizes[i] = amdgpu_ring_backup(ring, &ring_data[i]);
1797                 if (ring_sizes[i]) {
1798                         saved = true;
1799                         dev_info(adev->dev, "Saved %d dwords of commands "
1800                                  "on ring %d.\n", ring_sizes[i], i);
1801                 }
1802         }
1803
1804 retry:
1805         r = amdgpu_asic_reset(adev);
1806         if (!r) {
1807                 dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
1808                 r = amdgpu_resume(adev);
1809         }
1810
1811         if (!r) {
1812                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1813                         struct amdgpu_ring *ring = adev->rings[i];
1814                         if (!ring)
1815                                 continue;
1816
1817                         amdgpu_ring_restore(ring, ring_sizes[i], ring_data[i]);
1818                         ring_sizes[i] = 0;
1819                         ring_data[i] = NULL;
1820                 }
1821
1822                 r = amdgpu_ib_ring_tests(adev);
1823                 if (r) {
1824                         dev_err(adev->dev, "ib ring test failed (%d).\n", r);
1825                         if (saved) {
1826                                 saved = false;
1827                                 r = amdgpu_suspend(adev);
1828                                 goto retry;
1829                         }
1830                 }
1831         } else {
1832                 amdgpu_fence_driver_force_completion(adev);
1833                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1834                         if (adev->rings[i])
1835                                 kfree(ring_data[i]);
1836                 }
1837         }
1838
1839         drm_helper_resume_force_mode(adev->ddev);
1840
1841         ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
1842         if (r) {
1843                 /* bad news, how to tell it to userspace ? */
1844                 dev_info(adev->dev, "GPU reset failed\n");
1845         }
1846
1847         up_write(&adev->exclusive_lock);
1848         return r;
1849 }
1850
1851
1852 /*
1853  * Debugfs
1854  */
1855 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1856                              struct drm_info_list *files,
1857                              unsigned nfiles)
1858 {
1859         unsigned i;
1860
1861         for (i = 0; i < adev->debugfs_count; i++) {
1862                 if (adev->debugfs[i].files == files) {
1863                         /* Already registered */
1864                         return 0;
1865                 }
1866         }
1867
1868         i = adev->debugfs_count + 1;
1869         if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
1870                 DRM_ERROR("Reached maximum number of debugfs components.\n");
1871                 DRM_ERROR("Report so we increase "
1872                           "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
1873                 return -EINVAL;
1874         }
1875         adev->debugfs[adev->debugfs_count].files = files;
1876         adev->debugfs[adev->debugfs_count].num_files = nfiles;
1877         adev->debugfs_count = i;
1878 #if defined(CONFIG_DEBUG_FS)
1879         drm_debugfs_create_files(files, nfiles,
1880                                  adev->ddev->control->debugfs_root,
1881                                  adev->ddev->control);
1882         drm_debugfs_create_files(files, nfiles,
1883                                  adev->ddev->primary->debugfs_root,
1884                                  adev->ddev->primary);
1885 #endif
1886         return 0;
1887 }
1888
1889 static void amdgpu_debugfs_remove_files(struct amdgpu_device *adev)
1890 {
1891 #if defined(CONFIG_DEBUG_FS)
1892         unsigned i;
1893
1894         for (i = 0; i < adev->debugfs_count; i++) {
1895                 drm_debugfs_remove_files(adev->debugfs[i].files,
1896                                          adev->debugfs[i].num_files,
1897                                          adev->ddev->control);
1898                 drm_debugfs_remove_files(adev->debugfs[i].files,
1899                                          adev->debugfs[i].num_files,
1900                                          adev->ddev->primary);
1901         }
1902 #endif
1903 }
1904
1905 #if defined(CONFIG_DEBUG_FS)
1906
1907 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
1908                                         size_t size, loff_t *pos)
1909 {
1910         struct amdgpu_device *adev = f->f_inode->i_private;
1911         ssize_t result = 0;
1912         int r;
1913
1914         if (size & 0x3 || *pos & 0x3)
1915                 return -EINVAL;
1916
1917         while (size) {
1918                 uint32_t value;
1919
1920                 if (*pos > adev->rmmio_size)
1921                         return result;
1922
1923                 value = RREG32(*pos >> 2);
1924                 r = put_user(value, (uint32_t *)buf);
1925                 if (r)
1926                         return r;
1927
1928                 result += 4;
1929                 buf += 4;
1930                 *pos += 4;
1931                 size -= 4;
1932         }
1933
1934         return result;
1935 }
1936
1937 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
1938                                          size_t size, loff_t *pos)
1939 {
1940         struct amdgpu_device *adev = f->f_inode->i_private;
1941         ssize_t result = 0;
1942         int r;
1943
1944         if (size & 0x3 || *pos & 0x3)
1945                 return -EINVAL;
1946
1947         while (size) {
1948                 uint32_t value;
1949
1950                 if (*pos > adev->rmmio_size)
1951                         return result;
1952
1953                 r = get_user(value, (uint32_t *)buf);
1954                 if (r)
1955                         return r;
1956
1957                 WREG32(*pos >> 2, value);
1958
1959                 result += 4;
1960                 buf += 4;
1961                 *pos += 4;
1962                 size -= 4;
1963         }
1964
1965         return result;
1966 }
1967
1968 static const struct file_operations amdgpu_debugfs_regs_fops = {
1969         .owner = THIS_MODULE,
1970         .read = amdgpu_debugfs_regs_read,
1971         .write = amdgpu_debugfs_regs_write,
1972         .llseek = default_llseek
1973 };
1974
1975 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
1976 {
1977         struct drm_minor *minor = adev->ddev->primary;
1978         struct dentry *ent, *root = minor->debugfs_root;
1979
1980         ent = debugfs_create_file("amdgpu_regs", S_IFREG | S_IRUGO, root,
1981                                   adev, &amdgpu_debugfs_regs_fops);
1982         if (IS_ERR(ent))
1983                 return PTR_ERR(ent);
1984         i_size_write(ent->d_inode, adev->rmmio_size);
1985         adev->debugfs_regs = ent;
1986
1987         return 0;
1988 }
1989
1990 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
1991 {
1992         debugfs_remove(adev->debugfs_regs);
1993         adev->debugfs_regs = NULL;
1994 }
1995
1996 int amdgpu_debugfs_init(struct drm_minor *minor)
1997 {
1998         return 0;
1999 }
2000
2001 void amdgpu_debugfs_cleanup(struct drm_minor *minor)
2002 {
2003 }
2004 #else
2005 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
2006 {
2007         return 0;
2008 }
2009 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
2010 #endif