5 * \author Gareth Hughes <gareth@valinux.com>
9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
10 * All Rights Reserved.
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
33 #include <drm/amdgpu_drm.h>
34 #include <drm/drm_gem.h>
35 #include "amdgpu_drv.h"
37 #include <drm/drm_pciids.h>
38 #include <linux/console.h>
39 #include <linux/module.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/vga_switcheroo.h>
42 #include "drm_crtc_helper.h"
45 #include "amdgpu_irq.h"
47 #include "amdgpu_amdkfd.h"
51 * - 3.0.0 - initial driver
53 #define KMS_DRIVER_MAJOR 3
54 #define KMS_DRIVER_MINOR 0
55 #define KMS_DRIVER_PATCHLEVEL 0
57 int amdgpu_vram_limit = 0;
58 int amdgpu_gart_size = -1; /* auto */
59 int amdgpu_benchmarking = 0;
60 int amdgpu_testing = 0;
61 int amdgpu_audio = -1;
62 int amdgpu_disp_priority = 0;
63 int amdgpu_hw_i2c = 0;
64 int amdgpu_pcie_gen2 = -1;
66 int amdgpu_lockup_timeout = 10000;
68 int amdgpu_smc_load_fw = 1;
70 int amdgpu_runtime_pm = -1;
71 int amdgpu_hard_reset = 0;
72 unsigned amdgpu_ip_block_mask = 0xffffffff;
74 int amdgpu_deep_color = 0;
75 int amdgpu_vm_size = 8;
76 int amdgpu_vm_block_size = -1;
77 int amdgpu_exp_hw_support = 0;
78 int amdgpu_enable_scheduler = 0;
79 int amdgpu_sched_jobs = 16;
81 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
82 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
84 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
85 module_param_named(gartsize, amdgpu_gart_size, int, 0600);
87 MODULE_PARM_DESC(benchmark, "Run benchmark");
88 module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
90 MODULE_PARM_DESC(test, "Run tests");
91 module_param_named(test, amdgpu_testing, int, 0444);
93 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
94 module_param_named(audio, amdgpu_audio, int, 0444);
96 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
97 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
99 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
100 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
102 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
103 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
105 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
106 module_param_named(msi, amdgpu_msi, int, 0444);
108 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)");
109 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
111 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
112 module_param_named(dpm, amdgpu_dpm, int, 0444);
114 MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)");
115 module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444);
117 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
118 module_param_named(aspm, amdgpu_aspm, int, 0444);
120 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
121 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
123 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
124 module_param_named(hard_reset, amdgpu_hard_reset, int, 0444);
126 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
127 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
129 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
130 module_param_named(bapm, amdgpu_bapm, int, 0444);
132 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
133 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
135 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 8GB)");
136 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
138 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
139 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
141 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
142 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
144 MODULE_PARM_DESC(enable_scheduler, "enable SW GPU scheduler (1 = enable, 0 = disable ((default))");
145 module_param_named(enable_scheduler, amdgpu_enable_scheduler, int, 0444);
147 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 16)");
148 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
150 static struct pci_device_id pciidlist[] = {
151 #ifdef CONFIG_DRM_AMDGPU_CIK
153 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
154 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
155 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
156 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
157 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
158 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
159 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
160 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
161 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
162 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
163 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
164 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
165 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
166 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
167 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
168 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
169 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
170 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
171 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
172 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
173 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
174 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
176 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
177 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
178 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
179 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
180 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
181 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
182 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
183 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
184 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
185 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
186 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
188 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
189 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
190 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
191 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
192 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
193 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
194 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
195 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
196 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
197 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
198 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
199 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
201 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
202 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
203 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
204 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
205 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
206 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
207 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
208 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
209 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
210 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
211 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
212 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
213 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
214 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
215 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
216 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
218 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
219 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
220 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
221 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
222 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
223 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
224 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
225 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
226 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
227 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
228 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
229 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
230 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
231 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
232 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
233 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
236 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
237 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
238 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
239 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
240 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
242 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
243 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
244 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
245 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
246 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
247 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
248 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
249 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
250 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
252 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
254 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
255 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
256 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
257 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
258 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
263 MODULE_DEVICE_TABLE(pci, pciidlist);
265 static struct drm_driver kms_driver;
267 static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev)
269 struct apertures_struct *ap;
270 bool primary = false;
272 ap = alloc_apertures(1);
276 ap->ranges[0].base = pci_resource_start(pdev, 0);
277 ap->ranges[0].size = pci_resource_len(pdev, 0);
280 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
282 remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary);
288 static int amdgpu_pci_probe(struct pci_dev *pdev,
289 const struct pci_device_id *ent)
291 unsigned long flags = ent->driver_data;
294 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
295 DRM_INFO("This hardware requires experimental hardware support.\n"
296 "See modparam exp_hw_support\n");
300 /* Get rid of things like offb */
301 ret = amdgpu_kick_out_firmware_fb(pdev);
305 return drm_get_pci_dev(pdev, ent, &kms_driver);
309 amdgpu_pci_remove(struct pci_dev *pdev)
311 struct drm_device *dev = pci_get_drvdata(pdev);
316 static int amdgpu_pmops_suspend(struct device *dev)
318 struct pci_dev *pdev = to_pci_dev(dev);
319 struct drm_device *drm_dev = pci_get_drvdata(pdev);
320 return amdgpu_suspend_kms(drm_dev, true, true);
323 static int amdgpu_pmops_resume(struct device *dev)
325 struct pci_dev *pdev = to_pci_dev(dev);
326 struct drm_device *drm_dev = pci_get_drvdata(pdev);
327 return amdgpu_resume_kms(drm_dev, true, true);
330 static int amdgpu_pmops_freeze(struct device *dev)
332 struct pci_dev *pdev = to_pci_dev(dev);
333 struct drm_device *drm_dev = pci_get_drvdata(pdev);
334 return amdgpu_suspend_kms(drm_dev, false, true);
337 static int amdgpu_pmops_thaw(struct device *dev)
339 struct pci_dev *pdev = to_pci_dev(dev);
340 struct drm_device *drm_dev = pci_get_drvdata(pdev);
341 return amdgpu_resume_kms(drm_dev, false, true);
344 static int amdgpu_pmops_runtime_suspend(struct device *dev)
346 struct pci_dev *pdev = to_pci_dev(dev);
347 struct drm_device *drm_dev = pci_get_drvdata(pdev);
350 if (!amdgpu_device_is_px(drm_dev)) {
351 pm_runtime_forbid(dev);
355 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
356 drm_kms_helper_poll_disable(drm_dev);
357 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
359 ret = amdgpu_suspend_kms(drm_dev, false, false);
360 pci_save_state(pdev);
361 pci_disable_device(pdev);
362 pci_ignore_hotplug(pdev);
363 pci_set_power_state(pdev, PCI_D3cold);
364 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
369 static int amdgpu_pmops_runtime_resume(struct device *dev)
371 struct pci_dev *pdev = to_pci_dev(dev);
372 struct drm_device *drm_dev = pci_get_drvdata(pdev);
375 if (!amdgpu_device_is_px(drm_dev))
378 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
380 pci_set_power_state(pdev, PCI_D0);
381 pci_restore_state(pdev);
382 ret = pci_enable_device(pdev);
385 pci_set_master(pdev);
387 ret = amdgpu_resume_kms(drm_dev, false, false);
388 drm_kms_helper_poll_enable(drm_dev);
389 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
390 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
394 static int amdgpu_pmops_runtime_idle(struct device *dev)
396 struct pci_dev *pdev = to_pci_dev(dev);
397 struct drm_device *drm_dev = pci_get_drvdata(pdev);
398 struct drm_crtc *crtc;
400 if (!amdgpu_device_is_px(drm_dev)) {
401 pm_runtime_forbid(dev);
405 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
407 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
412 pm_runtime_mark_last_busy(dev);
413 pm_runtime_autosuspend(dev);
414 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
418 long amdgpu_drm_ioctl(struct file *filp,
419 unsigned int cmd, unsigned long arg)
421 struct drm_file *file_priv = filp->private_data;
422 struct drm_device *dev;
424 dev = file_priv->minor->dev;
425 ret = pm_runtime_get_sync(dev->dev);
429 ret = drm_ioctl(filp, cmd, arg);
431 pm_runtime_mark_last_busy(dev->dev);
432 pm_runtime_put_autosuspend(dev->dev);
436 static const struct dev_pm_ops amdgpu_pm_ops = {
437 .suspend = amdgpu_pmops_suspend,
438 .resume = amdgpu_pmops_resume,
439 .freeze = amdgpu_pmops_freeze,
440 .thaw = amdgpu_pmops_thaw,
441 .poweroff = amdgpu_pmops_freeze,
442 .restore = amdgpu_pmops_resume,
443 .runtime_suspend = amdgpu_pmops_runtime_suspend,
444 .runtime_resume = amdgpu_pmops_runtime_resume,
445 .runtime_idle = amdgpu_pmops_runtime_idle,
448 static const struct file_operations amdgpu_driver_kms_fops = {
449 .owner = THIS_MODULE,
451 .release = drm_release,
452 .unlocked_ioctl = amdgpu_drm_ioctl,
457 .compat_ioctl = amdgpu_kms_compat_ioctl,
461 static struct drm_driver kms_driver = {
464 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
465 DRIVER_PRIME | DRIVER_RENDER,
467 .load = amdgpu_driver_load_kms,
468 .open = amdgpu_driver_open_kms,
469 .preclose = amdgpu_driver_preclose_kms,
470 .postclose = amdgpu_driver_postclose_kms,
471 .lastclose = amdgpu_driver_lastclose_kms,
472 .set_busid = drm_pci_set_busid,
473 .unload = amdgpu_driver_unload_kms,
474 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
475 .enable_vblank = amdgpu_enable_vblank_kms,
476 .disable_vblank = amdgpu_disable_vblank_kms,
477 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms,
478 .get_scanout_position = amdgpu_get_crtc_scanoutpos,
479 #if defined(CONFIG_DEBUG_FS)
480 .debugfs_init = amdgpu_debugfs_init,
481 .debugfs_cleanup = amdgpu_debugfs_cleanup,
483 .irq_preinstall = amdgpu_irq_preinstall,
484 .irq_postinstall = amdgpu_irq_postinstall,
485 .irq_uninstall = amdgpu_irq_uninstall,
486 .irq_handler = amdgpu_irq_handler,
487 .ioctls = amdgpu_ioctls_kms,
488 .gem_free_object = amdgpu_gem_object_free,
489 .gem_open_object = amdgpu_gem_object_open,
490 .gem_close_object = amdgpu_gem_object_close,
491 .dumb_create = amdgpu_mode_dumb_create,
492 .dumb_map_offset = amdgpu_mode_dumb_mmap,
493 .dumb_destroy = drm_gem_dumb_destroy,
494 .fops = &amdgpu_driver_kms_fops,
496 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
497 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
498 .gem_prime_export = amdgpu_gem_prime_export,
499 .gem_prime_import = drm_gem_prime_import,
500 .gem_prime_pin = amdgpu_gem_prime_pin,
501 .gem_prime_unpin = amdgpu_gem_prime_unpin,
502 .gem_prime_res_obj = amdgpu_gem_prime_res_obj,
503 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table,
504 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table,
505 .gem_prime_vmap = amdgpu_gem_prime_vmap,
506 .gem_prime_vunmap = amdgpu_gem_prime_vunmap,
511 .major = KMS_DRIVER_MAJOR,
512 .minor = KMS_DRIVER_MINOR,
513 .patchlevel = KMS_DRIVER_PATCHLEVEL,
516 static struct drm_driver *driver;
517 static struct pci_driver *pdriver;
519 static struct pci_driver amdgpu_kms_pci_driver = {
521 .id_table = pciidlist,
522 .probe = amdgpu_pci_probe,
523 .remove = amdgpu_pci_remove,
524 .driver.pm = &amdgpu_pm_ops,
527 static int __init amdgpu_init(void)
529 #ifdef CONFIG_VGA_CONSOLE
530 if (vgacon_text_force()) {
531 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
535 DRM_INFO("amdgpu kernel modesetting enabled.\n");
536 driver = &kms_driver;
537 pdriver = &amdgpu_kms_pci_driver;
538 driver->driver_features |= DRIVER_MODESET;
539 driver->num_ioctls = amdgpu_max_kms_ioctl;
540 amdgpu_register_atpx_handler();
542 amdgpu_amdkfd_init();
544 /* let modprobe override vga console setting */
545 return drm_pci_init(driver, pdriver);
548 static void __exit amdgpu_exit(void)
550 amdgpu_amdkfd_fini();
551 drm_pci_exit(driver, pdriver);
552 amdgpu_unregister_atpx_handler();
555 module_init(amdgpu_init);
556 module_exit(amdgpu_exit);
558 MODULE_AUTHOR(DRIVER_AUTHOR);
559 MODULE_DESCRIPTION(DRIVER_DESC);
560 MODULE_LICENSE("GPL and additional rights");