2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_trace.h"
35 * GPUVM is similar to the legacy gart on older asics, however
36 * rather than there being a single global gart table
37 * for the entire GPU, there are multiple VM page tables active
38 * at any given time. The VM page tables can contain a mix
39 * vram pages and system memory pages and system memory pages
40 * can be mapped as snooped (cached system pages) or unsnooped
41 * (uncached system pages).
42 * Each VM has an ID associated with it and there is a page table
43 * associated with each VMID. When execting a command buffer,
44 * the kernel tells the the ring what VMID to use for that command
45 * buffer. VMIDs are allocated dynamically as commands are submitted.
46 * The userspace drivers maintain their own address space and the kernel
47 * sets up their pages tables accordingly when they submit their
48 * command buffers and a VMID is assigned.
49 * Cayman/Trinity support up to 8 active VMs at any given time;
54 * amdgpu_vm_num_pde - return the number of page directory entries
56 * @adev: amdgpu_device pointer
58 * Calculate the number of page directory entries (cayman+).
60 static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev)
62 return adev->vm_manager.max_pfn >> amdgpu_vm_block_size;
66 * amdgpu_vm_directory_size - returns the size of the page directory in bytes
68 * @adev: amdgpu_device pointer
70 * Calculate the size of the page directory in bytes (cayman+).
72 static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev)
74 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8);
78 * amdgpu_vm_get_bos - add the vm BOs to a validation list
80 * @vm: vm providing the BOs
81 * @head: head of validation list
83 * Add the page directory to the list of BOs to
84 * validate for command submission (cayman+).
86 struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
88 struct list_head *head)
90 struct amdgpu_bo_list_entry *list;
93 mutex_lock(&vm->mutex);
94 list = drm_malloc_ab(vm->max_pde_used + 2,
95 sizeof(struct amdgpu_bo_list_entry));
97 mutex_unlock(&vm->mutex);
101 /* add the vm page table to the list */
102 list[0].robj = vm->page_directory;
103 list[0].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM;
104 list[0].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM;
105 list[0].priority = 0;
106 list[0].tv.bo = &vm->page_directory->tbo;
107 list[0].tv.shared = true;
108 list_add(&list[0].tv.head, head);
110 for (i = 0, idx = 1; i <= vm->max_pde_used; i++) {
111 if (!vm->page_tables[i].bo)
114 list[idx].robj = vm->page_tables[i].bo;
115 list[idx].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM;
116 list[idx].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM;
117 list[idx].priority = 0;
118 list[idx].tv.bo = &list[idx].robj->tbo;
119 list[idx].tv.shared = true;
120 list_add(&list[idx++].tv.head, head);
122 mutex_unlock(&vm->mutex);
128 * amdgpu_vm_grab_id - allocate the next free VMID
130 * @vm: vm to allocate id for
131 * @ring: ring we want to submit job to
132 * @sync: sync object where we add dependencies
134 * Allocate an id for the vm, adding fences to the sync obj as necessary.
136 * Global mutex must be locked!
138 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
139 struct amdgpu_sync *sync)
141 struct amdgpu_fence *best[AMDGPU_MAX_RINGS] = {};
142 struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx];
143 struct amdgpu_device *adev = ring->adev;
145 unsigned choices[2] = {};
148 /* check if the id is still valid */
149 if (vm_id->id && vm_id->last_id_use &&
150 vm_id->last_id_use == adev->vm_manager.active[vm_id->id])
153 /* we definately need to flush */
154 vm_id->pd_gpu_addr = ~0ll;
156 /* skip over VMID 0, since it is the system VM */
157 for (i = 1; i < adev->vm_manager.nvm; ++i) {
158 struct amdgpu_fence *fence = adev->vm_manager.active[i];
161 /* found a free one */
163 trace_amdgpu_vm_grab_id(i, ring->idx);
167 if (amdgpu_fence_is_earlier(fence, best[fence->ring->idx])) {
168 best[fence->ring->idx] = fence;
169 choices[fence->ring == ring ? 0 : 1] = i;
173 for (i = 0; i < 2; ++i) {
175 struct amdgpu_fence *fence;
177 fence = adev->vm_manager.active[choices[i]];
178 vm_id->id = choices[i];
180 trace_amdgpu_vm_grab_id(choices[i], ring->idx);
181 return amdgpu_sync_fence(ring->adev, sync, &fence->base);
185 /* should never happen */
191 * amdgpu_vm_flush - hardware flush the vm
193 * @ring: ring to use for flush
194 * @vm: vm we want to flush
195 * @updates: last vm update that we waited for
197 * Flush the vm (cayman+).
199 * Global and local mutex must be locked!
201 void amdgpu_vm_flush(struct amdgpu_ring *ring,
202 struct amdgpu_vm *vm,
203 struct amdgpu_fence *updates)
205 uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
206 struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx];
207 struct amdgpu_fence *flushed_updates = vm_id->flushed_updates;
209 if (pd_addr != vm_id->pd_gpu_addr || !flushed_updates ||
210 (updates && amdgpu_fence_is_earlier(flushed_updates, updates))) {
212 trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id->id);
213 vm_id->flushed_updates = amdgpu_fence_ref(
214 amdgpu_fence_later(flushed_updates, updates));
215 amdgpu_fence_unref(&flushed_updates);
216 vm_id->pd_gpu_addr = pd_addr;
217 amdgpu_ring_emit_vm_flush(ring, vm_id->id, vm_id->pd_gpu_addr);
222 * amdgpu_vm_fence - remember fence for vm
224 * @adev: amdgpu_device pointer
225 * @vm: vm we want to fence
226 * @fence: fence to remember
228 * Fence the vm (cayman+).
229 * Set the fence used to protect page table and id.
231 * Global and local mutex must be locked!
233 void amdgpu_vm_fence(struct amdgpu_device *adev,
234 struct amdgpu_vm *vm,
235 struct amdgpu_fence *fence)
237 unsigned ridx = fence->ring->idx;
238 unsigned vm_id = vm->ids[ridx].id;
240 amdgpu_fence_unref(&adev->vm_manager.active[vm_id]);
241 adev->vm_manager.active[vm_id] = amdgpu_fence_ref(fence);
243 amdgpu_fence_unref(&vm->ids[ridx].last_id_use);
244 vm->ids[ridx].last_id_use = amdgpu_fence_ref(fence);
248 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
251 * @bo: requested buffer object
253 * Find @bo inside the requested vm (cayman+).
254 * Search inside the @bos vm list for the requested vm
255 * Returns the found bo_va or NULL if none is found
257 * Object has to be reserved!
259 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
260 struct amdgpu_bo *bo)
262 struct amdgpu_bo_va *bo_va;
264 list_for_each_entry(bo_va, &bo->va, bo_list) {
265 if (bo_va->vm == vm) {
273 * amdgpu_vm_update_pages - helper to call the right asic function
275 * @adev: amdgpu_device pointer
276 * @ib: indirect buffer to fill with commands
277 * @pe: addr of the page entry
278 * @addr: dst addr to write into pe
279 * @count: number of page entries to update
280 * @incr: increase next addr by incr bytes
281 * @flags: hw access flags
282 * @gtt_flags: GTT hw access flags
284 * Traces the parameters and calls the right asic functions
285 * to setup the page table using the DMA.
287 static void amdgpu_vm_update_pages(struct amdgpu_device *adev,
288 struct amdgpu_ib *ib,
289 uint64_t pe, uint64_t addr,
290 unsigned count, uint32_t incr,
291 uint32_t flags, uint32_t gtt_flags)
293 trace_amdgpu_vm_set_page(pe, addr, count, incr, flags);
295 if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) {
296 uint64_t src = adev->gart.table_addr + (addr >> 12) * 8;
297 amdgpu_vm_copy_pte(adev, ib, pe, src, count);
299 } else if ((flags & AMDGPU_PTE_SYSTEM) || (count < 3)) {
300 amdgpu_vm_write_pte(adev, ib, pe, addr,
304 amdgpu_vm_set_pte_pde(adev, ib, pe, addr,
309 static int amdgpu_vm_free_job(
310 struct amdgpu_cs_parser *sched_job)
313 for (i = 0; i < sched_job->num_ibs; i++)
314 amdgpu_ib_free(sched_job->adev, &sched_job->ibs[i]);
315 kfree(sched_job->ibs);
320 * amdgpu_vm_clear_bo - initially clear the page dir/table
322 * @adev: amdgpu_device pointer
325 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
326 struct amdgpu_bo *bo)
328 struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
329 struct fence *fence = NULL;
330 struct amdgpu_ib *ib;
335 r = amdgpu_bo_reserve(bo, false);
339 r = reservation_object_reserve_shared(bo->tbo.resv);
343 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
345 goto error_unreserve;
347 addr = amdgpu_bo_gpu_offset(bo);
348 entries = amdgpu_bo_size(bo) / 8;
350 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
352 goto error_unreserve;
354 r = amdgpu_ib_get(ring, NULL, entries * 2 + 64, ib);
360 amdgpu_vm_update_pages(adev, ib, addr, 0, entries, 0, 0, 0);
361 amdgpu_vm_pad_ib(adev, ib);
362 WARN_ON(ib->length_dw > 64);
363 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
365 AMDGPU_FENCE_OWNER_VM,
368 amdgpu_bo_fence(bo, fence, true);
370 if (amdgpu_enable_scheduler) {
371 amdgpu_bo_unreserve(bo);
375 amdgpu_ib_free(adev, ib);
379 amdgpu_bo_unreserve(bo);
384 * amdgpu_vm_map_gart - get the physical address of a gart page
386 * @adev: amdgpu_device pointer
387 * @addr: the unmapped addr
389 * Look up the physical address of the page that the pte resolves
391 * Returns the physical address of the page.
393 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr)
397 /* page table offset */
398 result = adev->gart.pages_addr[addr >> PAGE_SHIFT];
400 /* in case cpu page size != gpu page size*/
401 result |= addr & (~PAGE_MASK);
407 * amdgpu_vm_update_pdes - make sure that page directory is valid
409 * @adev: amdgpu_device pointer
411 * @start: start of GPU address range
412 * @end: end of GPU address range
414 * Allocates new page tables if necessary
415 * and updates the page directory (cayman+).
416 * Returns 0 for success, error for failure.
418 * Global and local mutex must be locked!
420 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
421 struct amdgpu_vm *vm)
423 struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
424 struct amdgpu_bo *pd = vm->page_directory;
425 uint64_t pd_addr = amdgpu_bo_gpu_offset(pd);
426 uint32_t incr = AMDGPU_VM_PTE_COUNT * 8;
427 uint64_t last_pde = ~0, last_pt = ~0;
428 unsigned count = 0, pt_idx, ndw;
429 struct amdgpu_ib *ib;
430 struct fence *fence = NULL;
437 /* assume the worst case */
438 ndw += vm->max_pde_used * 6;
440 /* update too big for an IB */
444 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
448 r = amdgpu_ib_get(ring, NULL, ndw * 4, ib);
453 /* walk over the address space and update the page directory */
454 for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
455 struct amdgpu_bo *bo = vm->page_tables[pt_idx].bo;
461 pt = amdgpu_bo_gpu_offset(bo);
462 if (vm->page_tables[pt_idx].addr == pt)
464 vm->page_tables[pt_idx].addr = pt;
466 pde = pd_addr + pt_idx * 8;
467 if (((last_pde + 8 * count) != pde) ||
468 ((last_pt + incr * count) != pt)) {
471 amdgpu_vm_update_pages(adev, ib, last_pde,
472 last_pt, count, incr,
473 AMDGPU_PTE_VALID, 0);
485 amdgpu_vm_update_pages(adev, ib, last_pde, last_pt, count,
486 incr, AMDGPU_PTE_VALID, 0);
488 if (ib->length_dw != 0) {
489 amdgpu_vm_pad_ib(adev, ib);
490 amdgpu_sync_resv(adev, &ib->sync, pd->tbo.resv, AMDGPU_FENCE_OWNER_VM);
491 WARN_ON(ib->length_dw > ndw);
492 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
494 AMDGPU_FENCE_OWNER_VM,
498 amdgpu_bo_fence(pd, fence, true);
502 if (!amdgpu_enable_scheduler || ib->length_dw == 0) {
503 amdgpu_ib_free(adev, ib);
510 amdgpu_ib_free(adev, ib);
516 * amdgpu_vm_frag_ptes - add fragment information to PTEs
518 * @adev: amdgpu_device pointer
519 * @ib: IB for the update
520 * @pe_start: first PTE to handle
521 * @pe_end: last PTE to handle
522 * @addr: addr those PTEs should point to
523 * @flags: hw mapping flags
524 * @gtt_flags: GTT hw mapping flags
526 * Global and local mutex must be locked!
528 static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
529 struct amdgpu_ib *ib,
530 uint64_t pe_start, uint64_t pe_end,
531 uint64_t addr, uint32_t flags,
535 * The MC L1 TLB supports variable sized pages, based on a fragment
536 * field in the PTE. When this field is set to a non-zero value, page
537 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
538 * flags are considered valid for all PTEs within the fragment range
539 * and corresponding mappings are assumed to be physically contiguous.
541 * The L1 TLB can store a single PTE for the whole fragment,
542 * significantly increasing the space available for translation
543 * caching. This leads to large improvements in throughput when the
544 * TLB is under pressure.
546 * The L2 TLB distributes small and large fragments into two
547 * asymmetric partitions. The large fragment cache is significantly
548 * larger. Thus, we try to use large fragments wherever possible.
549 * Userspace can support this by aligning virtual base address and
550 * allocation size to the fragment size.
553 /* SI and newer are optimized for 64KB */
554 uint64_t frag_flags = AMDGPU_PTE_FRAG_64KB;
555 uint64_t frag_align = 0x80;
557 uint64_t frag_start = ALIGN(pe_start, frag_align);
558 uint64_t frag_end = pe_end & ~(frag_align - 1);
562 /* system pages are non continuously */
563 if ((flags & AMDGPU_PTE_SYSTEM) || !(flags & AMDGPU_PTE_VALID) ||
564 (frag_start >= frag_end)) {
566 count = (pe_end - pe_start) / 8;
567 amdgpu_vm_update_pages(adev, ib, pe_start, addr, count,
568 AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags);
572 /* handle the 4K area at the beginning */
573 if (pe_start != frag_start) {
574 count = (frag_start - pe_start) / 8;
575 amdgpu_vm_update_pages(adev, ib, pe_start, addr, count,
576 AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags);
577 addr += AMDGPU_GPU_PAGE_SIZE * count;
580 /* handle the area in the middle */
581 count = (frag_end - frag_start) / 8;
582 amdgpu_vm_update_pages(adev, ib, frag_start, addr, count,
583 AMDGPU_GPU_PAGE_SIZE, flags | frag_flags,
586 /* handle the 4K area at the end */
587 if (frag_end != pe_end) {
588 addr += AMDGPU_GPU_PAGE_SIZE * count;
589 count = (pe_end - frag_end) / 8;
590 amdgpu_vm_update_pages(adev, ib, frag_end, addr, count,
591 AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags);
596 * amdgpu_vm_update_ptes - make sure that page tables are valid
598 * @adev: amdgpu_device pointer
600 * @start: start of GPU address range
601 * @end: end of GPU address range
602 * @dst: destination address to map to
603 * @flags: mapping flags
605 * Update the page tables in the range @start - @end (cayman+).
607 * Global and local mutex must be locked!
609 static int amdgpu_vm_update_ptes(struct amdgpu_device *adev,
610 struct amdgpu_vm *vm,
611 struct amdgpu_ib *ib,
612 uint64_t start, uint64_t end,
613 uint64_t dst, uint32_t flags,
616 uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
617 uint64_t last_pte = ~0, last_dst = ~0;
621 /* walk over the address space and update the page tables */
622 for (addr = start; addr < end; ) {
623 uint64_t pt_idx = addr >> amdgpu_vm_block_size;
624 struct amdgpu_bo *pt = vm->page_tables[pt_idx].bo;
629 amdgpu_sync_resv(adev, &ib->sync, pt->tbo.resv,
630 AMDGPU_FENCE_OWNER_VM);
631 r = reservation_object_reserve_shared(pt->tbo.resv);
635 if ((addr & ~mask) == (end & ~mask))
638 nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
640 pte = amdgpu_bo_gpu_offset(pt);
641 pte += (addr & mask) * 8;
643 if ((last_pte + 8 * count) != pte) {
646 amdgpu_vm_frag_ptes(adev, ib, last_pte,
647 last_pte + 8 * count,
660 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
664 amdgpu_vm_frag_ptes(adev, ib, last_pte,
665 last_pte + 8 * count,
666 last_dst, flags, gtt_flags);
673 * amdgpu_vm_fence_pts - fence page tables after an update
676 * @start: start of GPU address range
677 * @end: end of GPU address range
678 * @fence: fence to use
680 * Fence the page tables in the range @start - @end (cayman+).
682 * Global and local mutex must be locked!
684 static void amdgpu_vm_fence_pts(struct amdgpu_vm *vm,
685 uint64_t start, uint64_t end,
690 start >>= amdgpu_vm_block_size;
691 end >>= amdgpu_vm_block_size;
693 for (i = start; i <= end; ++i)
694 amdgpu_bo_fence(vm->page_tables[i].bo, fence, true);
698 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
700 * @adev: amdgpu_device pointer
702 * @mapping: mapped range and flags to use for the update
703 * @addr: addr to set the area to
704 * @gtt_flags: flags as they are used for GTT
705 * @fence: optional resulting fence
707 * Fill in the page table entries for @mapping.
708 * Returns 0 for success, -EINVAL for failure.
710 * Object have to be reserved and mutex must be locked!
712 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
713 struct amdgpu_vm *vm,
714 struct amdgpu_bo_va_mapping *mapping,
715 uint64_t addr, uint32_t gtt_flags,
716 struct fence **fence)
718 struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
719 unsigned nptes, ncmds, ndw;
720 uint32_t flags = gtt_flags;
721 struct amdgpu_ib *ib;
722 struct fence *f = NULL;
725 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
726 * but in case of something, we filter the flags in first place
728 if (!(mapping->flags & AMDGPU_PTE_READABLE))
729 flags &= ~AMDGPU_PTE_READABLE;
730 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
731 flags &= ~AMDGPU_PTE_WRITEABLE;
733 trace_amdgpu_vm_bo_update(mapping);
735 nptes = mapping->it.last - mapping->it.start + 1;
738 * reserve space for one command every (1 << BLOCK_SIZE)
739 * entries or 2k dwords (whatever is smaller)
741 ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1;
746 if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) {
747 /* only copy commands needed */
750 } else if (flags & AMDGPU_PTE_SYSTEM) {
751 /* header for write data commands */
754 /* body of write data command */
758 /* set page commands needed */
761 /* two extra commands for begin/end of fragment */
765 /* update too big for an IB */
769 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
773 r = amdgpu_ib_get(ring, NULL, ndw * 4, ib);
781 if (!(flags & AMDGPU_PTE_VALID)) {
784 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
785 struct amdgpu_fence *f = vm->ids[i].last_id_use;
786 r = amdgpu_sync_fence(adev, &ib->sync, &f->base);
792 r = amdgpu_vm_update_ptes(adev, vm, ib, mapping->it.start,
793 mapping->it.last + 1, addr + mapping->offset,
797 amdgpu_ib_free(adev, ib);
802 amdgpu_vm_pad_ib(adev, ib);
803 WARN_ON(ib->length_dw > ndw);
804 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
806 AMDGPU_FENCE_OWNER_VM,
811 amdgpu_vm_fence_pts(vm, mapping->it.start,
812 mapping->it.last + 1, f);
815 *fence = fence_get(f);
818 if (!amdgpu_enable_scheduler) {
819 amdgpu_ib_free(adev, ib);
825 amdgpu_ib_free(adev, ib);
831 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
833 * @adev: amdgpu_device pointer
834 * @bo_va: requested BO and VM object
837 * Fill in the page table entries for @bo_va.
838 * Returns 0 for success, -EINVAL for failure.
840 * Object have to be reserved and mutex must be locked!
842 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
843 struct amdgpu_bo_va *bo_va,
844 struct ttm_mem_reg *mem)
846 struct amdgpu_vm *vm = bo_va->vm;
847 struct amdgpu_bo_va_mapping *mapping;
853 addr = mem->start << PAGE_SHIFT;
854 if (mem->mem_type != TTM_PL_TT)
855 addr += adev->vm_manager.vram_base_offset;
860 flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
862 spin_lock(&vm->status_lock);
863 if (!list_empty(&bo_va->vm_status))
864 list_splice_init(&bo_va->valids, &bo_va->invalids);
865 spin_unlock(&vm->status_lock);
867 list_for_each_entry(mapping, &bo_va->invalids, list) {
868 r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, addr,
869 flags, &bo_va->last_pt_update);
874 spin_lock(&vm->status_lock);
875 list_splice_init(&bo_va->invalids, &bo_va->valids);
876 list_del_init(&bo_va->vm_status);
878 list_add(&bo_va->vm_status, &vm->cleared);
879 spin_unlock(&vm->status_lock);
885 * amdgpu_vm_clear_freed - clear freed BOs in the PT
887 * @adev: amdgpu_device pointer
890 * Make sure all freed BOs are cleared in the PT.
891 * Returns 0 for success.
893 * PTs have to be reserved and mutex must be locked!
895 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
896 struct amdgpu_vm *vm)
898 struct amdgpu_bo_va_mapping *mapping;
901 while (!list_empty(&vm->freed)) {
902 mapping = list_first_entry(&vm->freed,
903 struct amdgpu_bo_va_mapping, list);
904 list_del(&mapping->list);
906 r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, 0, 0, NULL);
917 * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
919 * @adev: amdgpu_device pointer
922 * Make sure all invalidated BOs are cleared in the PT.
923 * Returns 0 for success.
925 * PTs have to be reserved and mutex must be locked!
927 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
928 struct amdgpu_vm *vm, struct amdgpu_sync *sync)
930 struct amdgpu_bo_va *bo_va = NULL;
933 spin_lock(&vm->status_lock);
934 while (!list_empty(&vm->invalidated)) {
935 bo_va = list_first_entry(&vm->invalidated,
936 struct amdgpu_bo_va, vm_status);
937 spin_unlock(&vm->status_lock);
939 r = amdgpu_vm_bo_update(adev, bo_va, NULL);
943 spin_lock(&vm->status_lock);
945 spin_unlock(&vm->status_lock);
948 r = amdgpu_sync_fence(adev, sync, bo_va->last_pt_update);
954 * amdgpu_vm_bo_add - add a bo to a specific vm
956 * @adev: amdgpu_device pointer
958 * @bo: amdgpu buffer object
960 * Add @bo into the requested vm (cayman+).
961 * Add @bo to the list of bos associated with the vm
962 * Returns newly added bo_va or NULL for failure
964 * Object has to be reserved!
966 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
967 struct amdgpu_vm *vm,
968 struct amdgpu_bo *bo)
970 struct amdgpu_bo_va *bo_va;
972 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
978 bo_va->ref_count = 1;
979 INIT_LIST_HEAD(&bo_va->bo_list);
980 INIT_LIST_HEAD(&bo_va->valids);
981 INIT_LIST_HEAD(&bo_va->invalids);
982 INIT_LIST_HEAD(&bo_va->vm_status);
984 mutex_lock(&vm->mutex);
985 list_add_tail(&bo_va->bo_list, &bo->va);
986 mutex_unlock(&vm->mutex);
992 * amdgpu_vm_bo_map - map bo inside a vm
994 * @adev: amdgpu_device pointer
995 * @bo_va: bo_va to store the address
996 * @saddr: where to map the BO
997 * @offset: requested offset in the BO
998 * @flags: attributes of pages (read/write/valid/etc.)
1000 * Add a mapping of the BO at the specefied addr into the VM.
1001 * Returns 0 for success, error for failure.
1003 * Object has to be reserved and gets unreserved by this function!
1005 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1006 struct amdgpu_bo_va *bo_va,
1007 uint64_t saddr, uint64_t offset,
1008 uint64_t size, uint32_t flags)
1010 struct amdgpu_bo_va_mapping *mapping;
1011 struct amdgpu_vm *vm = bo_va->vm;
1012 struct interval_tree_node *it;
1013 unsigned last_pfn, pt_idx;
1017 /* validate the parameters */
1018 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
1019 size == 0 || size & AMDGPU_GPU_PAGE_MASK) {
1020 amdgpu_bo_unreserve(bo_va->bo);
1024 /* make sure object fit at this offset */
1025 eaddr = saddr + size;
1026 if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) {
1027 amdgpu_bo_unreserve(bo_va->bo);
1031 last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
1032 if (last_pfn > adev->vm_manager.max_pfn) {
1033 dev_err(adev->dev, "va above limit (0x%08X > 0x%08X)\n",
1034 last_pfn, adev->vm_manager.max_pfn);
1035 amdgpu_bo_unreserve(bo_va->bo);
1039 mutex_lock(&vm->mutex);
1041 saddr /= AMDGPU_GPU_PAGE_SIZE;
1042 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1044 it = interval_tree_iter_first(&vm->va, saddr, eaddr - 1);
1046 struct amdgpu_bo_va_mapping *tmp;
1047 tmp = container_of(it, struct amdgpu_bo_va_mapping, it);
1048 /* bo and tmp overlap, invalid addr */
1049 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1050 "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr,
1051 tmp->it.start, tmp->it.last + 1);
1052 amdgpu_bo_unreserve(bo_va->bo);
1057 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1059 amdgpu_bo_unreserve(bo_va->bo);
1064 INIT_LIST_HEAD(&mapping->list);
1065 mapping->it.start = saddr;
1066 mapping->it.last = eaddr - 1;
1067 mapping->offset = offset;
1068 mapping->flags = flags;
1070 list_add(&mapping->list, &bo_va->invalids);
1071 interval_tree_insert(&mapping->it, &vm->va);
1072 trace_amdgpu_vm_bo_map(bo_va, mapping);
1074 /* Make sure the page tables are allocated */
1075 saddr >>= amdgpu_vm_block_size;
1076 eaddr >>= amdgpu_vm_block_size;
1078 BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev));
1080 if (eaddr > vm->max_pde_used)
1081 vm->max_pde_used = eaddr;
1083 amdgpu_bo_unreserve(bo_va->bo);
1085 /* walk over the address space and allocate the page tables */
1086 for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) {
1087 struct amdgpu_bo *pt;
1089 if (vm->page_tables[pt_idx].bo)
1092 /* drop mutex to allocate and clear page table */
1093 mutex_unlock(&vm->mutex);
1095 r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8,
1096 AMDGPU_GPU_PAGE_SIZE, true,
1097 AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &pt);
1101 r = amdgpu_vm_clear_bo(adev, pt);
1103 amdgpu_bo_unref(&pt);
1107 /* aquire mutex again */
1108 mutex_lock(&vm->mutex);
1109 if (vm->page_tables[pt_idx].bo) {
1110 /* someone else allocated the pt in the meantime */
1111 mutex_unlock(&vm->mutex);
1112 amdgpu_bo_unref(&pt);
1113 mutex_lock(&vm->mutex);
1117 vm->page_tables[pt_idx].addr = 0;
1118 vm->page_tables[pt_idx].bo = pt;
1121 mutex_unlock(&vm->mutex);
1125 mutex_lock(&vm->mutex);
1126 list_del(&mapping->list);
1127 interval_tree_remove(&mapping->it, &vm->va);
1128 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1132 mutex_unlock(&vm->mutex);
1137 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1139 * @adev: amdgpu_device pointer
1140 * @bo_va: bo_va to remove the address from
1141 * @saddr: where to the BO is mapped
1143 * Remove a mapping of the BO at the specefied addr from the VM.
1144 * Returns 0 for success, error for failure.
1146 * Object has to be reserved and gets unreserved by this function!
1148 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1149 struct amdgpu_bo_va *bo_va,
1152 struct amdgpu_bo_va_mapping *mapping;
1153 struct amdgpu_vm *vm = bo_va->vm;
1156 saddr /= AMDGPU_GPU_PAGE_SIZE;
1158 list_for_each_entry(mapping, &bo_va->valids, list) {
1159 if (mapping->it.start == saddr)
1163 if (&mapping->list == &bo_va->valids) {
1166 list_for_each_entry(mapping, &bo_va->invalids, list) {
1167 if (mapping->it.start == saddr)
1171 if (&mapping->list == &bo_va->invalids) {
1172 amdgpu_bo_unreserve(bo_va->bo);
1177 mutex_lock(&vm->mutex);
1178 list_del(&mapping->list);
1179 interval_tree_remove(&mapping->it, &vm->va);
1180 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1183 list_add(&mapping->list, &vm->freed);
1186 mutex_unlock(&vm->mutex);
1187 amdgpu_bo_unreserve(bo_va->bo);
1193 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
1195 * @adev: amdgpu_device pointer
1196 * @bo_va: requested bo_va
1198 * Remove @bo_va->bo from the requested vm (cayman+).
1200 * Object have to be reserved!
1202 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
1203 struct amdgpu_bo_va *bo_va)
1205 struct amdgpu_bo_va_mapping *mapping, *next;
1206 struct amdgpu_vm *vm = bo_va->vm;
1208 list_del(&bo_va->bo_list);
1210 mutex_lock(&vm->mutex);
1212 spin_lock(&vm->status_lock);
1213 list_del(&bo_va->vm_status);
1214 spin_unlock(&vm->status_lock);
1216 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
1217 list_del(&mapping->list);
1218 interval_tree_remove(&mapping->it, &vm->va);
1219 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1220 list_add(&mapping->list, &vm->freed);
1222 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
1223 list_del(&mapping->list);
1224 interval_tree_remove(&mapping->it, &vm->va);
1228 fence_put(bo_va->last_pt_update);
1231 mutex_unlock(&vm->mutex);
1235 * amdgpu_vm_bo_invalidate - mark the bo as invalid
1237 * @adev: amdgpu_device pointer
1239 * @bo: amdgpu buffer object
1241 * Mark @bo as invalid (cayman+).
1243 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
1244 struct amdgpu_bo *bo)
1246 struct amdgpu_bo_va *bo_va;
1248 list_for_each_entry(bo_va, &bo->va, bo_list) {
1249 spin_lock(&bo_va->vm->status_lock);
1250 if (list_empty(&bo_va->vm_status))
1251 list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
1252 spin_unlock(&bo_va->vm->status_lock);
1257 * amdgpu_vm_init - initialize a vm instance
1259 * @adev: amdgpu_device pointer
1262 * Init @vm fields (cayman+).
1264 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1266 const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
1267 AMDGPU_VM_PTE_COUNT * 8);
1268 unsigned pd_size, pd_entries, pts_size;
1271 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1273 vm->ids[i].flushed_updates = NULL;
1274 vm->ids[i].last_id_use = NULL;
1276 mutex_init(&vm->mutex);
1278 spin_lock_init(&vm->status_lock);
1279 INIT_LIST_HEAD(&vm->invalidated);
1280 INIT_LIST_HEAD(&vm->cleared);
1281 INIT_LIST_HEAD(&vm->freed);
1283 pd_size = amdgpu_vm_directory_size(adev);
1284 pd_entries = amdgpu_vm_num_pdes(adev);
1286 /* allocate page table array */
1287 pts_size = pd_entries * sizeof(struct amdgpu_vm_pt);
1288 vm->page_tables = kzalloc(pts_size, GFP_KERNEL);
1289 if (vm->page_tables == NULL) {
1290 DRM_ERROR("Cannot allocate memory for page table array\n");
1294 r = amdgpu_bo_create(adev, pd_size, align, true,
1295 AMDGPU_GEM_DOMAIN_VRAM, 0,
1296 NULL, &vm->page_directory);
1300 r = amdgpu_vm_clear_bo(adev, vm->page_directory);
1302 amdgpu_bo_unref(&vm->page_directory);
1303 vm->page_directory = NULL;
1311 * amdgpu_vm_fini - tear down a vm instance
1313 * @adev: amdgpu_device pointer
1316 * Tear down @vm (cayman+).
1317 * Unbind the VM and remove all bos from the vm bo list
1319 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1321 struct amdgpu_bo_va_mapping *mapping, *tmp;
1324 if (!RB_EMPTY_ROOT(&vm->va)) {
1325 dev_err(adev->dev, "still active bo inside vm\n");
1327 rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) {
1328 list_del(&mapping->list);
1329 interval_tree_remove(&mapping->it, &vm->va);
1332 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
1333 list_del(&mapping->list);
1337 for (i = 0; i < amdgpu_vm_num_pdes(adev); i++)
1338 amdgpu_bo_unref(&vm->page_tables[i].bo);
1339 kfree(vm->page_tables);
1341 amdgpu_bo_unref(&vm->page_directory);
1343 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1344 amdgpu_fence_unref(&vm->ids[i].flushed_updates);
1345 amdgpu_fence_unref(&vm->ids[i].last_id_use);
1348 mutex_destroy(&vm->mutex);