2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <drm/amdgpu_drm.h>
31 #include "amdgpu_trace.h"
35 * GPUVM is similar to the legacy gart on older asics, however
36 * rather than there being a single global gart table
37 * for the entire GPU, there are multiple VM page tables active
38 * at any given time. The VM page tables can contain a mix
39 * vram pages and system memory pages and system memory pages
40 * can be mapped as snooped (cached system pages) or unsnooped
41 * (uncached system pages).
42 * Each VM has an ID associated with it and there is a page table
43 * associated with each VMID. When execting a command buffer,
44 * the kernel tells the the ring what VMID to use for that command
45 * buffer. VMIDs are allocated dynamically as commands are submitted.
46 * The userspace drivers maintain their own address space and the kernel
47 * sets up their pages tables accordingly when they submit their
48 * command buffers and a VMID is assigned.
49 * Cayman/Trinity support up to 8 active VMs at any given time;
54 * amdgpu_vm_num_pde - return the number of page directory entries
56 * @adev: amdgpu_device pointer
58 * Calculate the number of page directory entries (cayman+).
60 static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev)
62 return adev->vm_manager.max_pfn >> amdgpu_vm_block_size;
66 * amdgpu_vm_directory_size - returns the size of the page directory in bytes
68 * @adev: amdgpu_device pointer
70 * Calculate the size of the page directory in bytes (cayman+).
72 static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev)
74 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8);
78 * amdgpu_vm_get_bos - add the vm BOs to a validation list
80 * @vm: vm providing the BOs
81 * @head: head of validation list
83 * Add the page directory to the list of BOs to
84 * validate for command submission (cayman+).
86 struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
88 struct list_head *head)
90 struct amdgpu_bo_list_entry *list;
93 mutex_lock(&vm->mutex);
94 list = drm_malloc_ab(vm->max_pde_used + 2,
95 sizeof(struct amdgpu_bo_list_entry));
97 mutex_unlock(&vm->mutex);
101 /* add the vm page table to the list */
102 list[0].robj = vm->page_directory;
103 list[0].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM;
104 list[0].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM;
105 list[0].priority = 0;
106 list[0].tv.bo = &vm->page_directory->tbo;
107 list[0].tv.shared = true;
108 list_add(&list[0].tv.head, head);
110 for (i = 0, idx = 1; i <= vm->max_pde_used; i++) {
111 if (!vm->page_tables[i].bo)
114 list[idx].robj = vm->page_tables[i].bo;
115 list[idx].prefered_domains = AMDGPU_GEM_DOMAIN_VRAM;
116 list[idx].allowed_domains = AMDGPU_GEM_DOMAIN_VRAM;
117 list[idx].priority = 0;
118 list[idx].tv.bo = &list[idx].robj->tbo;
119 list[idx].tv.shared = true;
120 list_add(&list[idx++].tv.head, head);
122 mutex_unlock(&vm->mutex);
128 * amdgpu_vm_grab_id - allocate the next free VMID
130 * @vm: vm to allocate id for
131 * @ring: ring we want to submit job to
132 * @sync: sync object where we add dependencies
134 * Allocate an id for the vm, adding fences to the sync obj as necessary.
136 * Global mutex must be locked!
138 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
139 struct amdgpu_sync *sync)
141 struct amdgpu_fence *best[AMDGPU_MAX_RINGS] = {};
142 struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx];
143 struct amdgpu_device *adev = ring->adev;
145 unsigned choices[2] = {};
148 /* check if the id is still valid */
149 if (vm_id->id && vm_id->last_id_use &&
150 vm_id->last_id_use == adev->vm_manager.active[vm_id->id])
153 /* we definately need to flush */
154 vm_id->pd_gpu_addr = ~0ll;
156 /* skip over VMID 0, since it is the system VM */
157 for (i = 1; i < adev->vm_manager.nvm; ++i) {
158 struct amdgpu_fence *fence = adev->vm_manager.active[i];
161 /* found a free one */
163 trace_amdgpu_vm_grab_id(i, ring->idx);
167 if (amdgpu_fence_is_earlier(fence, best[fence->ring->idx])) {
168 best[fence->ring->idx] = fence;
169 choices[fence->ring == ring ? 0 : 1] = i;
173 for (i = 0; i < 2; ++i) {
175 struct amdgpu_fence *fence;
177 fence = adev->vm_manager.active[choices[i]];
178 vm_id->id = choices[i];
180 trace_amdgpu_vm_grab_id(choices[i], ring->idx);
181 return amdgpu_sync_fence(ring->adev, sync, &fence->base);
185 /* should never happen */
191 * amdgpu_vm_flush - hardware flush the vm
193 * @ring: ring to use for flush
194 * @vm: vm we want to flush
195 * @updates: last vm update that we waited for
197 * Flush the vm (cayman+).
199 * Global and local mutex must be locked!
201 void amdgpu_vm_flush(struct amdgpu_ring *ring,
202 struct amdgpu_vm *vm,
203 struct amdgpu_fence *updates)
205 uint64_t pd_addr = amdgpu_bo_gpu_offset(vm->page_directory);
206 struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx];
207 struct amdgpu_fence *flushed_updates = vm_id->flushed_updates;
209 if (pd_addr != vm_id->pd_gpu_addr || !flushed_updates ||
210 (updates && amdgpu_fence_is_earlier(flushed_updates, updates))) {
212 trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id->id);
213 vm_id->flushed_updates = amdgpu_fence_ref(
214 amdgpu_fence_later(flushed_updates, updates));
215 amdgpu_fence_unref(&flushed_updates);
216 vm_id->pd_gpu_addr = pd_addr;
217 amdgpu_ring_emit_vm_flush(ring, vm_id->id, vm_id->pd_gpu_addr);
222 * amdgpu_vm_fence - remember fence for vm
224 * @adev: amdgpu_device pointer
225 * @vm: vm we want to fence
226 * @fence: fence to remember
228 * Fence the vm (cayman+).
229 * Set the fence used to protect page table and id.
231 * Global and local mutex must be locked!
233 void amdgpu_vm_fence(struct amdgpu_device *adev,
234 struct amdgpu_vm *vm,
235 struct amdgpu_fence *fence)
237 unsigned ridx = fence->ring->idx;
238 unsigned vm_id = vm->ids[ridx].id;
240 amdgpu_fence_unref(&adev->vm_manager.active[vm_id]);
241 adev->vm_manager.active[vm_id] = amdgpu_fence_ref(fence);
243 amdgpu_fence_unref(&vm->ids[ridx].last_id_use);
244 vm->ids[ridx].last_id_use = amdgpu_fence_ref(fence);
248 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
251 * @bo: requested buffer object
253 * Find @bo inside the requested vm (cayman+).
254 * Search inside the @bos vm list for the requested vm
255 * Returns the found bo_va or NULL if none is found
257 * Object has to be reserved!
259 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
260 struct amdgpu_bo *bo)
262 struct amdgpu_bo_va *bo_va;
264 list_for_each_entry(bo_va, &bo->va, bo_list) {
265 if (bo_va->vm == vm) {
273 * amdgpu_vm_update_pages - helper to call the right asic function
275 * @adev: amdgpu_device pointer
276 * @ib: indirect buffer to fill with commands
277 * @pe: addr of the page entry
278 * @addr: dst addr to write into pe
279 * @count: number of page entries to update
280 * @incr: increase next addr by incr bytes
281 * @flags: hw access flags
282 * @gtt_flags: GTT hw access flags
284 * Traces the parameters and calls the right asic functions
285 * to setup the page table using the DMA.
287 static void amdgpu_vm_update_pages(struct amdgpu_device *adev,
288 struct amdgpu_ib *ib,
289 uint64_t pe, uint64_t addr,
290 unsigned count, uint32_t incr,
291 uint32_t flags, uint32_t gtt_flags)
293 trace_amdgpu_vm_set_page(pe, addr, count, incr, flags);
295 if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) {
296 uint64_t src = adev->gart.table_addr + (addr >> 12) * 8;
297 amdgpu_vm_copy_pte(adev, ib, pe, src, count);
299 } else if ((flags & AMDGPU_PTE_SYSTEM) || (count < 3)) {
300 amdgpu_vm_write_pte(adev, ib, pe, addr,
304 amdgpu_vm_set_pte_pde(adev, ib, pe, addr,
309 static int amdgpu_vm_free_job(
310 struct amdgpu_cs_parser *sched_job)
313 for (i = 0; i < sched_job->num_ibs; i++)
314 amdgpu_ib_free(sched_job->adev, &sched_job->ibs[i]);
315 kfree(sched_job->ibs);
319 static int amdgpu_vm_run_job(
320 struct amdgpu_cs_parser *sched_job)
322 amdgpu_bo_fence(sched_job->job_param.vm.bo,
323 sched_job->ibs[sched_job->num_ibs -1].fence, true);
328 * amdgpu_vm_clear_bo - initially clear the page dir/table
330 * @adev: amdgpu_device pointer
333 static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
334 struct amdgpu_bo *bo)
336 struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
337 struct amdgpu_cs_parser *sched_job = NULL;
338 struct amdgpu_ib *ib;
343 r = amdgpu_bo_reserve(bo, false);
347 r = reservation_object_reserve_shared(bo->tbo.resv);
351 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
353 goto error_unreserve;
355 addr = amdgpu_bo_gpu_offset(bo);
356 entries = amdgpu_bo_size(bo) / 8;
358 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
360 goto error_unreserve;
362 r = amdgpu_ib_get(ring, NULL, entries * 2 + 64, ib);
368 amdgpu_vm_update_pages(adev, ib, addr, 0, entries, 0, 0, 0);
369 amdgpu_vm_pad_ib(adev, ib);
370 WARN_ON(ib->length_dw > 64);
372 if (amdgpu_enable_scheduler) {
375 sched_job = amdgpu_cs_parser_create(adev, AMDGPU_FENCE_OWNER_VM,
376 adev->kernel_ctx, ib, 1);
379 sched_job->job_param.vm.bo = bo;
380 sched_job->run_job = amdgpu_vm_run_job;
381 sched_job->free_job = amdgpu_vm_free_job;
382 v_seq = atomic64_inc_return(&adev->kernel_ctx->rings[ring->idx].c_entity.last_queued_v_seq);
383 ib->sequence = v_seq;
384 amd_sched_push_job(ring->scheduler,
385 &adev->kernel_ctx->rings[ring->idx].c_entity,
387 r = amd_sched_wait_emit(&adev->kernel_ctx->rings[ring->idx].c_entity,
392 DRM_ERROR("emit timeout\n");
394 amdgpu_bo_unreserve(bo);
397 r = amdgpu_ib_schedule(adev, 1, ib, AMDGPU_FENCE_OWNER_VM);
400 amdgpu_bo_fence(bo, ib->fence, true);
404 amdgpu_ib_free(adev, ib);
408 amdgpu_bo_unreserve(bo);
413 * amdgpu_vm_map_gart - get the physical address of a gart page
415 * @adev: amdgpu_device pointer
416 * @addr: the unmapped addr
418 * Look up the physical address of the page that the pte resolves
420 * Returns the physical address of the page.
422 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr)
426 /* page table offset */
427 result = adev->gart.pages_addr[addr >> PAGE_SHIFT];
429 /* in case cpu page size != gpu page size*/
430 result |= addr & (~PAGE_MASK);
436 * amdgpu_vm_update_pdes - make sure that page directory is valid
438 * @adev: amdgpu_device pointer
440 * @start: start of GPU address range
441 * @end: end of GPU address range
443 * Allocates new page tables if necessary
444 * and updates the page directory (cayman+).
445 * Returns 0 for success, error for failure.
447 * Global and local mutex must be locked!
449 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
450 struct amdgpu_vm *vm)
452 struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
453 struct amdgpu_bo *pd = vm->page_directory;
454 uint64_t pd_addr = amdgpu_bo_gpu_offset(pd);
455 uint32_t incr = AMDGPU_VM_PTE_COUNT * 8;
456 uint64_t last_pde = ~0, last_pt = ~0;
457 unsigned count = 0, pt_idx, ndw;
458 struct amdgpu_ib *ib;
459 struct amdgpu_cs_parser *sched_job = NULL;
466 /* assume the worst case */
467 ndw += vm->max_pde_used * 6;
469 /* update too big for an IB */
473 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
477 r = amdgpu_ib_get(ring, NULL, ndw * 4, ib);
482 /* walk over the address space and update the page directory */
483 for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
484 struct amdgpu_bo *bo = vm->page_tables[pt_idx].bo;
490 pt = amdgpu_bo_gpu_offset(bo);
491 if (vm->page_tables[pt_idx].addr == pt)
493 vm->page_tables[pt_idx].addr = pt;
495 pde = pd_addr + pt_idx * 8;
496 if (((last_pde + 8 * count) != pde) ||
497 ((last_pt + incr * count) != pt)) {
500 amdgpu_vm_update_pages(adev, ib, last_pde,
501 last_pt, count, incr,
502 AMDGPU_PTE_VALID, 0);
514 amdgpu_vm_update_pages(adev, ib, last_pde, last_pt, count,
515 incr, AMDGPU_PTE_VALID, 0);
517 if (ib->length_dw != 0) {
518 amdgpu_vm_pad_ib(adev, ib);
519 amdgpu_sync_resv(adev, &ib->sync, pd->tbo.resv, AMDGPU_FENCE_OWNER_VM);
520 WARN_ON(ib->length_dw > ndw);
522 if (amdgpu_enable_scheduler) {
525 sched_job = amdgpu_cs_parser_create(adev, AMDGPU_FENCE_OWNER_VM,
530 sched_job->job_param.vm.bo = pd;
531 sched_job->run_job = amdgpu_vm_run_job;
532 sched_job->free_job = amdgpu_vm_free_job;
533 v_seq = atomic64_inc_return(&adev->kernel_ctx->rings[ring->idx].c_entity.last_queued_v_seq);
534 ib->sequence = v_seq;
535 amd_sched_push_job(ring->scheduler,
536 &adev->kernel_ctx->rings[ring->idx].c_entity,
538 r = amd_sched_wait_emit(&adev->kernel_ctx->rings[ring->idx].c_entity,
543 DRM_ERROR("emit timeout\n");
545 r = amdgpu_ib_schedule(adev, 1, ib, AMDGPU_FENCE_OWNER_VM);
547 amdgpu_ib_free(adev, ib);
550 amdgpu_bo_fence(pd, ib->fence, true);
554 if (!amdgpu_enable_scheduler || ib->length_dw == 0) {
555 amdgpu_ib_free(adev, ib);
564 amdgpu_ib_free(adev, ib);
570 * amdgpu_vm_frag_ptes - add fragment information to PTEs
572 * @adev: amdgpu_device pointer
573 * @ib: IB for the update
574 * @pe_start: first PTE to handle
575 * @pe_end: last PTE to handle
576 * @addr: addr those PTEs should point to
577 * @flags: hw mapping flags
578 * @gtt_flags: GTT hw mapping flags
580 * Global and local mutex must be locked!
582 static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
583 struct amdgpu_ib *ib,
584 uint64_t pe_start, uint64_t pe_end,
585 uint64_t addr, uint32_t flags,
589 * The MC L1 TLB supports variable sized pages, based on a fragment
590 * field in the PTE. When this field is set to a non-zero value, page
591 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
592 * flags are considered valid for all PTEs within the fragment range
593 * and corresponding mappings are assumed to be physically contiguous.
595 * The L1 TLB can store a single PTE for the whole fragment,
596 * significantly increasing the space available for translation
597 * caching. This leads to large improvements in throughput when the
598 * TLB is under pressure.
600 * The L2 TLB distributes small and large fragments into two
601 * asymmetric partitions. The large fragment cache is significantly
602 * larger. Thus, we try to use large fragments wherever possible.
603 * Userspace can support this by aligning virtual base address and
604 * allocation size to the fragment size.
607 /* SI and newer are optimized for 64KB */
608 uint64_t frag_flags = AMDGPU_PTE_FRAG_64KB;
609 uint64_t frag_align = 0x80;
611 uint64_t frag_start = ALIGN(pe_start, frag_align);
612 uint64_t frag_end = pe_end & ~(frag_align - 1);
616 /* system pages are non continuously */
617 if ((flags & AMDGPU_PTE_SYSTEM) || !(flags & AMDGPU_PTE_VALID) ||
618 (frag_start >= frag_end)) {
620 count = (pe_end - pe_start) / 8;
621 amdgpu_vm_update_pages(adev, ib, pe_start, addr, count,
622 AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags);
626 /* handle the 4K area at the beginning */
627 if (pe_start != frag_start) {
628 count = (frag_start - pe_start) / 8;
629 amdgpu_vm_update_pages(adev, ib, pe_start, addr, count,
630 AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags);
631 addr += AMDGPU_GPU_PAGE_SIZE * count;
634 /* handle the area in the middle */
635 count = (frag_end - frag_start) / 8;
636 amdgpu_vm_update_pages(adev, ib, frag_start, addr, count,
637 AMDGPU_GPU_PAGE_SIZE, flags | frag_flags,
640 /* handle the 4K area at the end */
641 if (frag_end != pe_end) {
642 addr += AMDGPU_GPU_PAGE_SIZE * count;
643 count = (pe_end - frag_end) / 8;
644 amdgpu_vm_update_pages(adev, ib, frag_end, addr, count,
645 AMDGPU_GPU_PAGE_SIZE, flags, gtt_flags);
650 * amdgpu_vm_update_ptes - make sure that page tables are valid
652 * @adev: amdgpu_device pointer
654 * @start: start of GPU address range
655 * @end: end of GPU address range
656 * @dst: destination address to map to
657 * @flags: mapping flags
659 * Update the page tables in the range @start - @end (cayman+).
661 * Global and local mutex must be locked!
663 static int amdgpu_vm_update_ptes(struct amdgpu_device *adev,
664 struct amdgpu_vm *vm,
665 struct amdgpu_ib *ib,
666 uint64_t start, uint64_t end,
667 uint64_t dst, uint32_t flags,
670 uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
671 uint64_t last_pte = ~0, last_dst = ~0;
675 /* walk over the address space and update the page tables */
676 for (addr = start; addr < end; ) {
677 uint64_t pt_idx = addr >> amdgpu_vm_block_size;
678 struct amdgpu_bo *pt = vm->page_tables[pt_idx].bo;
683 amdgpu_sync_resv(adev, &ib->sync, pt->tbo.resv,
684 AMDGPU_FENCE_OWNER_VM);
685 r = reservation_object_reserve_shared(pt->tbo.resv);
689 if ((addr & ~mask) == (end & ~mask))
692 nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
694 pte = amdgpu_bo_gpu_offset(pt);
695 pte += (addr & mask) * 8;
697 if ((last_pte + 8 * count) != pte) {
700 amdgpu_vm_frag_ptes(adev, ib, last_pte,
701 last_pte + 8 * count,
714 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
718 amdgpu_vm_frag_ptes(adev, ib, last_pte,
719 last_pte + 8 * count,
720 last_dst, flags, gtt_flags);
727 * amdgpu_vm_fence_pts - fence page tables after an update
730 * @start: start of GPU address range
731 * @end: end of GPU address range
732 * @fence: fence to use
734 * Fence the page tables in the range @start - @end (cayman+).
736 * Global and local mutex must be locked!
738 static void amdgpu_vm_fence_pts(struct amdgpu_vm *vm,
739 uint64_t start, uint64_t end,
740 struct amdgpu_fence *fence)
744 start >>= amdgpu_vm_block_size;
745 end >>= amdgpu_vm_block_size;
747 for (i = start; i <= end; ++i)
748 amdgpu_bo_fence(vm->page_tables[i].bo, fence, true);
751 static int amdgpu_vm_bo_update_mapping_run_job(
752 struct amdgpu_cs_parser *sched_job)
754 struct amdgpu_fence **fence = sched_job->job_param.vm_mapping.fence;
755 amdgpu_vm_fence_pts(sched_job->job_param.vm_mapping.vm,
756 sched_job->job_param.vm_mapping.start,
757 sched_job->job_param.vm_mapping.last + 1,
758 sched_job->ibs[sched_job->num_ibs -1].fence);
760 amdgpu_fence_unref(fence);
761 *fence = amdgpu_fence_ref(sched_job->ibs[sched_job->num_ibs -1].fence);
766 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
768 * @adev: amdgpu_device pointer
770 * @mapping: mapped range and flags to use for the update
771 * @addr: addr to set the area to
772 * @gtt_flags: flags as they are used for GTT
773 * @fence: optional resulting fence
775 * Fill in the page table entries for @mapping.
776 * Returns 0 for success, -EINVAL for failure.
778 * Object have to be reserved and mutex must be locked!
780 static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
781 struct amdgpu_vm *vm,
782 struct amdgpu_bo_va_mapping *mapping,
783 uint64_t addr, uint32_t gtt_flags,
784 struct amdgpu_fence **fence)
786 struct amdgpu_ring *ring = adev->vm_manager.vm_pte_funcs_ring;
787 unsigned nptes, ncmds, ndw;
788 uint32_t flags = gtt_flags;
789 struct amdgpu_ib *ib;
790 struct amdgpu_cs_parser *sched_job = NULL;
793 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
794 * but in case of something, we filter the flags in first place
796 if (!(mapping->flags & AMDGPU_PTE_READABLE))
797 flags &= ~AMDGPU_PTE_READABLE;
798 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
799 flags &= ~AMDGPU_PTE_WRITEABLE;
801 trace_amdgpu_vm_bo_update(mapping);
803 nptes = mapping->it.last - mapping->it.start + 1;
806 * reserve space for one command every (1 << BLOCK_SIZE)
807 * entries or 2k dwords (whatever is smaller)
809 ncmds = (nptes >> min(amdgpu_vm_block_size, 11)) + 1;
814 if ((flags & AMDGPU_PTE_SYSTEM) && (flags == gtt_flags)) {
815 /* only copy commands needed */
818 } else if (flags & AMDGPU_PTE_SYSTEM) {
819 /* header for write data commands */
822 /* body of write data command */
826 /* set page commands needed */
829 /* two extra commands for begin/end of fragment */
833 /* update too big for an IB */
837 ib = kzalloc(sizeof(struct amdgpu_ib), GFP_KERNEL);
841 r = amdgpu_ib_get(ring, NULL, ndw * 4, ib);
849 if (!(flags & AMDGPU_PTE_VALID)) {
852 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
853 struct amdgpu_fence *f = vm->ids[i].last_id_use;
854 r = amdgpu_sync_fence(adev, &ib->sync, &f->base);
860 r = amdgpu_vm_update_ptes(adev, vm, ib, mapping->it.start,
861 mapping->it.last + 1, addr + mapping->offset,
865 amdgpu_ib_free(adev, ib);
870 amdgpu_vm_pad_ib(adev, ib);
871 WARN_ON(ib->length_dw > ndw);
873 if (amdgpu_enable_scheduler) {
876 sched_job = amdgpu_cs_parser_create(adev, AMDGPU_FENCE_OWNER_VM,
877 adev->kernel_ctx, ib, 1);
880 sched_job->job_param.vm_mapping.vm = vm;
881 sched_job->job_param.vm_mapping.start = mapping->it.start;
882 sched_job->job_param.vm_mapping.last = mapping->it.last;
883 sched_job->job_param.vm_mapping.fence = fence;
884 sched_job->run_job = amdgpu_vm_bo_update_mapping_run_job;
885 sched_job->free_job = amdgpu_vm_free_job;
886 v_seq = atomic64_inc_return(&adev->kernel_ctx->rings[ring->idx].c_entity.last_queued_v_seq);
887 ib->sequence = v_seq;
888 amd_sched_push_job(ring->scheduler,
889 &adev->kernel_ctx->rings[ring->idx].c_entity,
891 r = amd_sched_wait_emit(&adev->kernel_ctx->rings[ring->idx].c_entity,
896 DRM_ERROR("emit timeout\n");
898 r = amdgpu_ib_schedule(adev, 1, ib, AMDGPU_FENCE_OWNER_VM);
900 amdgpu_ib_free(adev, ib);
904 amdgpu_vm_fence_pts(vm, mapping->it.start,
905 mapping->it.last + 1, ib->fence);
907 amdgpu_fence_unref(fence);
908 *fence = amdgpu_fence_ref(ib->fence);
911 amdgpu_ib_free(adev, ib);
919 amdgpu_ib_free(adev, ib);
925 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
927 * @adev: amdgpu_device pointer
928 * @bo_va: requested BO and VM object
931 * Fill in the page table entries for @bo_va.
932 * Returns 0 for success, -EINVAL for failure.
934 * Object have to be reserved and mutex must be locked!
936 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
937 struct amdgpu_bo_va *bo_va,
938 struct ttm_mem_reg *mem)
940 struct amdgpu_vm *vm = bo_va->vm;
941 struct amdgpu_bo_va_mapping *mapping;
947 addr = mem->start << PAGE_SHIFT;
948 if (mem->mem_type != TTM_PL_TT)
949 addr += adev->vm_manager.vram_base_offset;
954 if (addr == bo_va->addr)
957 flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
959 list_for_each_entry(mapping, &bo_va->mappings, list) {
960 r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, addr,
961 flags, &bo_va->last_pt_update);
967 spin_lock(&vm->status_lock);
968 list_del_init(&bo_va->vm_status);
969 spin_unlock(&vm->status_lock);
975 * amdgpu_vm_clear_freed - clear freed BOs in the PT
977 * @adev: amdgpu_device pointer
980 * Make sure all freed BOs are cleared in the PT.
981 * Returns 0 for success.
983 * PTs have to be reserved and mutex must be locked!
985 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
986 struct amdgpu_vm *vm)
988 struct amdgpu_bo_va_mapping *mapping;
991 while (!list_empty(&vm->freed)) {
992 mapping = list_first_entry(&vm->freed,
993 struct amdgpu_bo_va_mapping, list);
994 list_del(&mapping->list);
996 r = amdgpu_vm_bo_update_mapping(adev, vm, mapping, 0, 0, NULL);
1007 * amdgpu_vm_clear_invalids - clear invalidated BOs in the PT
1009 * @adev: amdgpu_device pointer
1012 * Make sure all invalidated BOs are cleared in the PT.
1013 * Returns 0 for success.
1015 * PTs have to be reserved and mutex must be locked!
1017 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev,
1018 struct amdgpu_vm *vm, struct amdgpu_sync *sync)
1020 struct amdgpu_bo_va *bo_va = NULL;
1023 spin_lock(&vm->status_lock);
1024 while (!list_empty(&vm->invalidated)) {
1025 bo_va = list_first_entry(&vm->invalidated,
1026 struct amdgpu_bo_va, vm_status);
1027 spin_unlock(&vm->status_lock);
1029 r = amdgpu_vm_bo_update(adev, bo_va, NULL);
1033 spin_lock(&vm->status_lock);
1035 spin_unlock(&vm->status_lock);
1038 r = amdgpu_sync_fence(adev, sync, &bo_va->last_pt_update->base);
1044 * amdgpu_vm_bo_add - add a bo to a specific vm
1046 * @adev: amdgpu_device pointer
1048 * @bo: amdgpu buffer object
1050 * Add @bo into the requested vm (cayman+).
1051 * Add @bo to the list of bos associated with the vm
1052 * Returns newly added bo_va or NULL for failure
1054 * Object has to be reserved!
1056 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1057 struct amdgpu_vm *vm,
1058 struct amdgpu_bo *bo)
1060 struct amdgpu_bo_va *bo_va;
1062 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1063 if (bo_va == NULL) {
1069 bo_va->ref_count = 1;
1070 INIT_LIST_HEAD(&bo_va->bo_list);
1071 INIT_LIST_HEAD(&bo_va->mappings);
1072 INIT_LIST_HEAD(&bo_va->vm_status);
1074 mutex_lock(&vm->mutex);
1075 list_add_tail(&bo_va->bo_list, &bo->va);
1076 mutex_unlock(&vm->mutex);
1082 * amdgpu_vm_bo_map - map bo inside a vm
1084 * @adev: amdgpu_device pointer
1085 * @bo_va: bo_va to store the address
1086 * @saddr: where to map the BO
1087 * @offset: requested offset in the BO
1088 * @flags: attributes of pages (read/write/valid/etc.)
1090 * Add a mapping of the BO at the specefied addr into the VM.
1091 * Returns 0 for success, error for failure.
1093 * Object has to be reserved and gets unreserved by this function!
1095 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1096 struct amdgpu_bo_va *bo_va,
1097 uint64_t saddr, uint64_t offset,
1098 uint64_t size, uint32_t flags)
1100 struct amdgpu_bo_va_mapping *mapping;
1101 struct amdgpu_vm *vm = bo_va->vm;
1102 struct interval_tree_node *it;
1103 unsigned last_pfn, pt_idx;
1107 /* validate the parameters */
1108 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
1109 size == 0 || size & AMDGPU_GPU_PAGE_MASK) {
1110 amdgpu_bo_unreserve(bo_va->bo);
1114 /* make sure object fit at this offset */
1115 eaddr = saddr + size;
1116 if ((saddr >= eaddr) || (offset + size > amdgpu_bo_size(bo_va->bo))) {
1117 amdgpu_bo_unreserve(bo_va->bo);
1121 last_pfn = eaddr / AMDGPU_GPU_PAGE_SIZE;
1122 if (last_pfn > adev->vm_manager.max_pfn) {
1123 dev_err(adev->dev, "va above limit (0x%08X > 0x%08X)\n",
1124 last_pfn, adev->vm_manager.max_pfn);
1125 amdgpu_bo_unreserve(bo_va->bo);
1129 mutex_lock(&vm->mutex);
1131 saddr /= AMDGPU_GPU_PAGE_SIZE;
1132 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1134 it = interval_tree_iter_first(&vm->va, saddr, eaddr - 1);
1136 struct amdgpu_bo_va_mapping *tmp;
1137 tmp = container_of(it, struct amdgpu_bo_va_mapping, it);
1138 /* bo and tmp overlap, invalid addr */
1139 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1140 "0x%010lx-0x%010lx\n", bo_va->bo, saddr, eaddr,
1141 tmp->it.start, tmp->it.last + 1);
1142 amdgpu_bo_unreserve(bo_va->bo);
1147 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1149 amdgpu_bo_unreserve(bo_va->bo);
1154 INIT_LIST_HEAD(&mapping->list);
1155 mapping->it.start = saddr;
1156 mapping->it.last = eaddr - 1;
1157 mapping->offset = offset;
1158 mapping->flags = flags;
1160 list_add(&mapping->list, &bo_va->mappings);
1161 interval_tree_insert(&mapping->it, &vm->va);
1162 trace_amdgpu_vm_bo_map(bo_va, mapping);
1166 /* Make sure the page tables are allocated */
1167 saddr >>= amdgpu_vm_block_size;
1168 eaddr >>= amdgpu_vm_block_size;
1170 BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev));
1172 if (eaddr > vm->max_pde_used)
1173 vm->max_pde_used = eaddr;
1175 amdgpu_bo_unreserve(bo_va->bo);
1177 /* walk over the address space and allocate the page tables */
1178 for (pt_idx = saddr; pt_idx <= eaddr; ++pt_idx) {
1179 struct amdgpu_bo *pt;
1181 if (vm->page_tables[pt_idx].bo)
1184 /* drop mutex to allocate and clear page table */
1185 mutex_unlock(&vm->mutex);
1187 r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8,
1188 AMDGPU_GPU_PAGE_SIZE, true,
1189 AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &pt);
1193 r = amdgpu_vm_clear_bo(adev, pt);
1195 amdgpu_bo_unref(&pt);
1199 /* aquire mutex again */
1200 mutex_lock(&vm->mutex);
1201 if (vm->page_tables[pt_idx].bo) {
1202 /* someone else allocated the pt in the meantime */
1203 mutex_unlock(&vm->mutex);
1204 amdgpu_bo_unref(&pt);
1205 mutex_lock(&vm->mutex);
1209 vm->page_tables[pt_idx].addr = 0;
1210 vm->page_tables[pt_idx].bo = pt;
1213 mutex_unlock(&vm->mutex);
1217 mutex_lock(&vm->mutex);
1218 list_del(&mapping->list);
1219 interval_tree_remove(&mapping->it, &vm->va);
1220 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1224 mutex_unlock(&vm->mutex);
1229 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1231 * @adev: amdgpu_device pointer
1232 * @bo_va: bo_va to remove the address from
1233 * @saddr: where to the BO is mapped
1235 * Remove a mapping of the BO at the specefied addr from the VM.
1236 * Returns 0 for success, error for failure.
1238 * Object has to be reserved and gets unreserved by this function!
1240 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1241 struct amdgpu_bo_va *bo_va,
1244 struct amdgpu_bo_va_mapping *mapping;
1245 struct amdgpu_vm *vm = bo_va->vm;
1247 saddr /= AMDGPU_GPU_PAGE_SIZE;
1249 list_for_each_entry(mapping, &bo_va->mappings, list) {
1250 if (mapping->it.start == saddr)
1254 if (&mapping->list == &bo_va->mappings) {
1255 amdgpu_bo_unreserve(bo_va->bo);
1259 mutex_lock(&vm->mutex);
1260 list_del(&mapping->list);
1261 interval_tree_remove(&mapping->it, &vm->va);
1262 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1265 /* clear the old address */
1266 list_add(&mapping->list, &vm->freed);
1270 mutex_unlock(&vm->mutex);
1271 amdgpu_bo_unreserve(bo_va->bo);
1277 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
1279 * @adev: amdgpu_device pointer
1280 * @bo_va: requested bo_va
1282 * Remove @bo_va->bo from the requested vm (cayman+).
1284 * Object have to be reserved!
1286 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
1287 struct amdgpu_bo_va *bo_va)
1289 struct amdgpu_bo_va_mapping *mapping, *next;
1290 struct amdgpu_vm *vm = bo_va->vm;
1292 list_del(&bo_va->bo_list);
1294 mutex_lock(&vm->mutex);
1296 spin_lock(&vm->status_lock);
1297 list_del(&bo_va->vm_status);
1298 spin_unlock(&vm->status_lock);
1300 list_for_each_entry_safe(mapping, next, &bo_va->mappings, list) {
1301 list_del(&mapping->list);
1302 interval_tree_remove(&mapping->it, &vm->va);
1303 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1305 list_add(&mapping->list, &vm->freed);
1309 amdgpu_fence_unref(&bo_va->last_pt_update);
1312 mutex_unlock(&vm->mutex);
1316 * amdgpu_vm_bo_invalidate - mark the bo as invalid
1318 * @adev: amdgpu_device pointer
1320 * @bo: amdgpu buffer object
1322 * Mark @bo as invalid (cayman+).
1324 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
1325 struct amdgpu_bo *bo)
1327 struct amdgpu_bo_va *bo_va;
1329 list_for_each_entry(bo_va, &bo->va, bo_list) {
1331 spin_lock(&bo_va->vm->status_lock);
1332 list_del(&bo_va->vm_status);
1333 list_add(&bo_va->vm_status, &bo_va->vm->invalidated);
1334 spin_unlock(&bo_va->vm->status_lock);
1340 * amdgpu_vm_init - initialize a vm instance
1342 * @adev: amdgpu_device pointer
1345 * Init @vm fields (cayman+).
1347 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1349 const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
1350 AMDGPU_VM_PTE_COUNT * 8);
1351 unsigned pd_size, pd_entries, pts_size;
1354 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1356 vm->ids[i].flushed_updates = NULL;
1357 vm->ids[i].last_id_use = NULL;
1359 mutex_init(&vm->mutex);
1361 spin_lock_init(&vm->status_lock);
1362 INIT_LIST_HEAD(&vm->invalidated);
1363 INIT_LIST_HEAD(&vm->freed);
1365 pd_size = amdgpu_vm_directory_size(adev);
1366 pd_entries = amdgpu_vm_num_pdes(adev);
1368 /* allocate page table array */
1369 pts_size = pd_entries * sizeof(struct amdgpu_vm_pt);
1370 vm->page_tables = kzalloc(pts_size, GFP_KERNEL);
1371 if (vm->page_tables == NULL) {
1372 DRM_ERROR("Cannot allocate memory for page table array\n");
1376 r = amdgpu_bo_create(adev, pd_size, align, true,
1377 AMDGPU_GEM_DOMAIN_VRAM, 0,
1378 NULL, &vm->page_directory);
1382 r = amdgpu_vm_clear_bo(adev, vm->page_directory);
1384 amdgpu_bo_unref(&vm->page_directory);
1385 vm->page_directory = NULL;
1393 * amdgpu_vm_fini - tear down a vm instance
1395 * @adev: amdgpu_device pointer
1398 * Tear down @vm (cayman+).
1399 * Unbind the VM and remove all bos from the vm bo list
1401 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1403 struct amdgpu_bo_va_mapping *mapping, *tmp;
1406 if (!RB_EMPTY_ROOT(&vm->va)) {
1407 dev_err(adev->dev, "still active bo inside vm\n");
1409 rbtree_postorder_for_each_entry_safe(mapping, tmp, &vm->va, it.rb) {
1410 list_del(&mapping->list);
1411 interval_tree_remove(&mapping->it, &vm->va);
1414 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
1415 list_del(&mapping->list);
1419 for (i = 0; i < amdgpu_vm_num_pdes(adev); i++)
1420 amdgpu_bo_unref(&vm->page_tables[i].bo);
1421 kfree(vm->page_tables);
1423 amdgpu_bo_unref(&vm->page_directory);
1425 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
1426 amdgpu_fence_unref(&vm->ids[i].flushed_updates);
1427 amdgpu_fence_unref(&vm->ids[i].last_id_use);
1430 mutex_destroy(&vm->mutex);