drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include "drmP.h"
  25 #include "amdgpu.h"
  26 #include "amdgpu_ih.h"
  27 #include "amdgpu_gfx.h"
  28 #include "cikd.h"
  29 #include "cik.h"
  30 #include "atom.h"
  31 #include "amdgpu_ucode.h"
  32 #include "clearstate_ci.h"
  33
  34 #include "uvd/uvd_4_2_d.h"
  35
  36 #include "dce/dce_8_0_d.h"
  37 #include "dce/dce_8_0_sh_mask.h"
  38
  39 #include "bif/bif_4_1_d.h"
  40 #include "bif/bif_4_1_sh_mask.h"
  41
  42 #include "gca/gfx_7_0_d.h"
  43 #include "gca/gfx_7_2_enum.h"
  44 #include "gca/gfx_7_2_sh_mask.h"
  45
  46 #include "gmc/gmc_7_0_d.h"
  47 #include "gmc/gmc_7_0_sh_mask.h"
  48
  49 #include "oss/oss_2_0_d.h"
  50 #include "oss/oss_2_0_sh_mask.h"
  51
  52 #define GFX7_NUM_GFX_RINGS     1
  53 #define GFX7_NUM_COMPUTE_RINGS 8
  54
  55 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  56 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  57 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev);
  58 int gfx_v7_0_get_cu_info(struct amdgpu_device *, struct amdgpu_cu_info *);
  59
  60 MODULE_FIRMWARE("radeon/bonaire_pfp.bin");
  61 MODULE_FIRMWARE("radeon/bonaire_me.bin");
  62 MODULE_FIRMWARE("radeon/bonaire_ce.bin");
  63 MODULE_FIRMWARE("radeon/bonaire_rlc.bin");
  64 MODULE_FIRMWARE("radeon/bonaire_mec.bin");
  65
  66 MODULE_FIRMWARE("radeon/hawaii_pfp.bin");
  67 MODULE_FIRMWARE("radeon/hawaii_me.bin");
  68 MODULE_FIRMWARE("radeon/hawaii_ce.bin");
  69 MODULE_FIRMWARE("radeon/hawaii_rlc.bin");
  70 MODULE_FIRMWARE("radeon/hawaii_mec.bin");
  71
  72 MODULE_FIRMWARE("radeon/kaveri_pfp.bin");
  73 MODULE_FIRMWARE("radeon/kaveri_me.bin");
  74 MODULE_FIRMWARE("radeon/kaveri_ce.bin");
  75 MODULE_FIRMWARE("radeon/kaveri_rlc.bin");
  76 MODULE_FIRMWARE("radeon/kaveri_mec.bin");
  77 MODULE_FIRMWARE("radeon/kaveri_mec2.bin");
  78
  79 MODULE_FIRMWARE("radeon/kabini_pfp.bin");
  80 MODULE_FIRMWARE("radeon/kabini_me.bin");
  81 MODULE_FIRMWARE("radeon/kabini_ce.bin");
  82 MODULE_FIRMWARE("radeon/kabini_rlc.bin");
  83 MODULE_FIRMWARE("radeon/kabini_mec.bin");
  84
  85 MODULE_FIRMWARE("radeon/mullins_pfp.bin");
  86 MODULE_FIRMWARE("radeon/mullins_me.bin");
  87 MODULE_FIRMWARE("radeon/mullins_ce.bin");
  88 MODULE_FIRMWARE("radeon/mullins_rlc.bin");
  89 MODULE_FIRMWARE("radeon/mullins_mec.bin");
  90
  91 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
  92 {
  93         {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
  94         {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
  95         {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
  96         {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
  97         {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
  98         {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
  99         {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
 100         {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
 101         {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
 102         {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
 103         {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
 104         {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
 105         {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
 106         {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
 107         {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
 108         {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
 109 };
 110
 111 static const u32 spectre_rlc_save_restore_register_list[] =
 112 {
 113         (0x0e00 << 16) | (0xc12c >> 2),
 114         0x00000000,
 115         (0x0e00 << 16) | (0xc140 >> 2),
 116         0x00000000,
 117         (0x0e00 << 16) | (0xc150 >> 2),
 118         0x00000000,
 119         (0x0e00 << 16) | (0xc15c >> 2),
 120         0x00000000,
 121         (0x0e00 << 16) | (0xc168 >> 2),
 122         0x00000000,
 123         (0x0e00 << 16) | (0xc170 >> 2),
 124         0x00000000,
 125         (0x0e00 << 16) | (0xc178 >> 2),
 126         0x00000000,
 127         (0x0e00 << 16) | (0xc204 >> 2),
 128         0x00000000,
 129         (0x0e00 << 16) | (0xc2b4 >> 2),
 130         0x00000000,
 131         (0x0e00 << 16) | (0xc2b8 >> 2),
 132         0x00000000,
 133         (0x0e00 << 16) | (0xc2bc >> 2),
 134         0x00000000,
 135         (0x0e00 << 16) | (0xc2c0 >> 2),
 136         0x00000000,
 137         (0x0e00 << 16) | (0x8228 >> 2),
 138         0x00000000,
 139         (0x0e00 << 16) | (0x829c >> 2),
 140         0x00000000,
 141         (0x0e00 << 16) | (0x869c >> 2),
 142         0x00000000,
 143         (0x0600 << 16) | (0x98f4 >> 2),
 144         0x00000000,
 145         (0x0e00 << 16) | (0x98f8 >> 2),
 146         0x00000000,
 147         (0x0e00 << 16) | (0x9900 >> 2),
 148         0x00000000,
 149         (0x0e00 << 16) | (0xc260 >> 2),
 150         0x00000000,
 151         (0x0e00 << 16) | (0x90e8 >> 2),
 152         0x00000000,
 153         (0x0e00 << 16) | (0x3c000 >> 2),
 154         0x00000000,
 155         (0x0e00 << 16) | (0x3c00c >> 2),
 156         0x00000000,
 157         (0x0e00 << 16) | (0x8c1c >> 2),
 158         0x00000000,
 159         (0x0e00 << 16) | (0x9700 >> 2),
 160         0x00000000,
 161         (0x0e00 << 16) | (0xcd20 >> 2),
 162         0x00000000,
 163         (0x4e00 << 16) | (0xcd20 >> 2),
 164         0x00000000,
 165         (0x5e00 << 16) | (0xcd20 >> 2),
 166         0x00000000,
 167         (0x6e00 << 16) | (0xcd20 >> 2),
 168         0x00000000,
 169         (0x7e00 << 16) | (0xcd20 >> 2),
 170         0x00000000,
 171         (0x8e00 << 16) | (0xcd20 >> 2),
 172         0x00000000,
 173         (0x9e00 << 16) | (0xcd20 >> 2),
 174         0x00000000,
 175         (0xae00 << 16) | (0xcd20 >> 2),
 176         0x00000000,
 177         (0xbe00 << 16) | (0xcd20 >> 2),
 178         0x00000000,
 179         (0x0e00 << 16) | (0x89bc >> 2),
 180         0x00000000,
 181         (0x0e00 << 16) | (0x8900 >> 2),
 182         0x00000000,
 183         0x3,
 184         (0x0e00 << 16) | (0xc130 >> 2),
 185         0x00000000,
 186         (0x0e00 << 16) | (0xc134 >> 2),
 187         0x00000000,
 188         (0x0e00 << 16) | (0xc1fc >> 2),
 189         0x00000000,
 190         (0x0e00 << 16) | (0xc208 >> 2),
 191         0x00000000,
 192         (0x0e00 << 16) | (0xc264 >> 2),
 193         0x00000000,
 194         (0x0e00 << 16) | (0xc268 >> 2),
 195         0x00000000,
 196         (0x0e00 << 16) | (0xc26c >> 2),
 197         0x00000000,
 198         (0x0e00 << 16) | (0xc270 >> 2),
 199         0x00000000,
 200         (0x0e00 << 16) | (0xc274 >> 2),
 201         0x00000000,
 202         (0x0e00 << 16) | (0xc278 >> 2),
 203         0x00000000,
 204         (0x0e00 << 16) | (0xc27c >> 2),
 205         0x00000000,
 206         (0x0e00 << 16) | (0xc280 >> 2),
 207         0x00000000,
 208         (0x0e00 << 16) | (0xc284 >> 2),
 209         0x00000000,
 210         (0x0e00 << 16) | (0xc288 >> 2),
 211         0x00000000,
 212         (0x0e00 << 16) | (0xc28c >> 2),
 213         0x00000000,
 214         (0x0e00 << 16) | (0xc290 >> 2),
 215         0x00000000,
 216         (0x0e00 << 16) | (0xc294 >> 2),
 217         0x00000000,
 218         (0x0e00 << 16) | (0xc298 >> 2),
 219         0x00000000,
 220         (0x0e00 << 16) | (0xc29c >> 2),
 221         0x00000000,
 222         (0x0e00 << 16) | (0xc2a0 >> 2),
 223         0x00000000,
 224         (0x0e00 << 16) | (0xc2a4 >> 2),
 225         0x00000000,
 226         (0x0e00 << 16) | (0xc2a8 >> 2),
 227         0x00000000,
 228         (0x0e00 << 16) | (0xc2ac  >> 2),
 229         0x00000000,
 230         (0x0e00 << 16) | (0xc2b0 >> 2),
 231         0x00000000,
 232         (0x0e00 << 16) | (0x301d0 >> 2),
 233         0x00000000,
 234         (0x0e00 << 16) | (0x30238 >> 2),
 235         0x00000000,
 236         (0x0e00 << 16) | (0x30250 >> 2),
 237         0x00000000,
 238         (0x0e00 << 16) | (0x30254 >> 2),
 239         0x00000000,
 240         (0x0e00 << 16) | (0x30258 >> 2),
 241         0x00000000,
 242         (0x0e00 << 16) | (0x3025c >> 2),
 243         0x00000000,
 244         (0x4e00 << 16) | (0xc900 >> 2),
 245         0x00000000,
 246         (0x5e00 << 16) | (0xc900 >> 2),
 247         0x00000000,
 248         (0x6e00 << 16) | (0xc900 >> 2),
 249         0x00000000,
 250         (0x7e00 << 16) | (0xc900 >> 2),
 251         0x00000000,
 252         (0x8e00 << 16) | (0xc900 >> 2),
 253         0x00000000,
 254         (0x9e00 << 16) | (0xc900 >> 2),
 255         0x00000000,
 256         (0xae00 << 16) | (0xc900 >> 2),
 257         0x00000000,
 258         (0xbe00 << 16) | (0xc900 >> 2),
 259         0x00000000,
 260         (0x4e00 << 16) | (0xc904 >> 2),
 261         0x00000000,
 262         (0x5e00 << 16) | (0xc904 >> 2),
 263         0x00000000,
 264         (0x6e00 << 16) | (0xc904 >> 2),
 265         0x00000000,
 266         (0x7e00 << 16) | (0xc904 >> 2),
 267         0x00000000,
 268         (0x8e00 << 16) | (0xc904 >> 2),
 269         0x00000000,
 270         (0x9e00 << 16) | (0xc904 >> 2),
 271         0x00000000,
 272         (0xae00 << 16) | (0xc904 >> 2),
 273         0x00000000,
 274         (0xbe00 << 16) | (0xc904 >> 2),
 275         0x00000000,
 276         (0x4e00 << 16) | (0xc908 >> 2),
 277         0x00000000,
 278         (0x5e00 << 16) | (0xc908 >> 2),
 279         0x00000000,
 280         (0x6e00 << 16) | (0xc908 >> 2),
 281         0x00000000,
 282         (0x7e00 << 16) | (0xc908 >> 2),
 283         0x00000000,
 284         (0x8e00 << 16) | (0xc908 >> 2),
 285         0x00000000,
 286         (0x9e00 << 16) | (0xc908 >> 2),
 287         0x00000000,
 288         (0xae00 << 16) | (0xc908 >> 2),
 289         0x00000000,
 290         (0xbe00 << 16) | (0xc908 >> 2),
 291         0x00000000,
 292         (0x4e00 << 16) | (0xc90c >> 2),
 293         0x00000000,
 294         (0x5e00 << 16) | (0xc90c >> 2),
 295         0x00000000,
 296         (0x6e00 << 16) | (0xc90c >> 2),
 297         0x00000000,
 298         (0x7e00 << 16) | (0xc90c >> 2),
 299         0x00000000,
 300         (0x8e00 << 16) | (0xc90c >> 2),
 301         0x00000000,
 302         (0x9e00 << 16) | (0xc90c >> 2),
 303         0x00000000,
 304         (0xae00 << 16) | (0xc90c >> 2),
 305         0x00000000,
 306         (0xbe00 << 16) | (0xc90c >> 2),
 307         0x00000000,
 308         (0x4e00 << 16) | (0xc910 >> 2),
 309         0x00000000,
 310         (0x5e00 << 16) | (0xc910 >> 2),
 311         0x00000000,
 312         (0x6e00 << 16) | (0xc910 >> 2),
 313         0x00000000,
 314         (0x7e00 << 16) | (0xc910 >> 2),
 315         0x00000000,
 316         (0x8e00 << 16) | (0xc910 >> 2),
 317         0x00000000,
 318         (0x9e00 << 16) | (0xc910 >> 2),
 319         0x00000000,
 320         (0xae00 << 16) | (0xc910 >> 2),
 321         0x00000000,
 322         (0xbe00 << 16) | (0xc910 >> 2),
 323         0x00000000,
 324         (0x0e00 << 16) | (0xc99c >> 2),
 325         0x00000000,
 326         (0x0e00 << 16) | (0x9834 >> 2),
 327         0x00000000,
 328         (0x0000 << 16) | (0x30f00 >> 2),
 329         0x00000000,
 330         (0x0001 << 16) | (0x30f00 >> 2),
 331         0x00000000,
 332         (0x0000 << 16) | (0x30f04 >> 2),
 333         0x00000000,
 334         (0x0001 << 16) | (0x30f04 >> 2),
 335         0x00000000,
 336         (0x0000 << 16) | (0x30f08 >> 2),
 337         0x00000000,
 338         (0x0001 << 16) | (0x30f08 >> 2),
 339         0x00000000,
 340         (0x0000 << 16) | (0x30f0c >> 2),
 341         0x00000000,
 342         (0x0001 << 16) | (0x30f0c >> 2),
 343         0x00000000,
 344         (0x0600 << 16) | (0x9b7c >> 2),
 345         0x00000000,
 346         (0x0e00 << 16) | (0x8a14 >> 2),
 347         0x00000000,
 348         (0x0e00 << 16) | (0x8a18 >> 2),
 349         0x00000000,
 350         (0x0600 << 16) | (0x30a00 >> 2),
 351         0x00000000,
 352         (0x0e00 << 16) | (0x8bf0 >> 2),
 353         0x00000000,
 354         (0x0e00 << 16) | (0x8bcc >> 2),
 355         0x00000000,
 356         (0x0e00 << 16) | (0x8b24 >> 2),
 357         0x00000000,
 358         (0x0e00 << 16) | (0x30a04 >> 2),
 359         0x00000000,
 360         (0x0600 << 16) | (0x30a10 >> 2),
 361         0x00000000,
 362         (0x0600 << 16) | (0x30a14 >> 2),
 363         0x00000000,
 364         (0x0600 << 16) | (0x30a18 >> 2),
 365         0x00000000,
 366         (0x0600 << 16) | (0x30a2c >> 2),
 367         0x00000000,
 368         (0x0e00 << 16) | (0xc700 >> 2),
 369         0x00000000,
 370         (0x0e00 << 16) | (0xc704 >> 2),
 371         0x00000000,
 372         (0x0e00 << 16) | (0xc708 >> 2),
 373         0x00000000,
 374         (0x0e00 << 16) | (0xc768 >> 2),
 375         0x00000000,
 376         (0x0400 << 16) | (0xc770 >> 2),
 377         0x00000000,
 378         (0x0400 << 16) | (0xc774 >> 2),
 379         0x00000000,
 380         (0x0400 << 16) | (0xc778 >> 2),
 381         0x00000000,
 382         (0x0400 << 16) | (0xc77c >> 2),
 383         0x00000000,
 384         (0x0400 << 16) | (0xc780 >> 2),
 385         0x00000000,
 386         (0x0400 << 16) | (0xc784 >> 2),
 387         0x00000000,
 388         (0x0400 << 16) | (0xc788 >> 2),
 389         0x00000000,
 390         (0x0400 << 16) | (0xc78c >> 2),
 391         0x00000000,
 392         (0x0400 << 16) | (0xc798 >> 2),
 393         0x00000000,
 394         (0x0400 << 16) | (0xc79c >> 2),
 395         0x00000000,
 396         (0x0400 << 16) | (0xc7a0 >> 2),
 397         0x00000000,
 398         (0x0400 << 16) | (0xc7a4 >> 2),
 399         0x00000000,
 400         (0x0400 << 16) | (0xc7a8 >> 2),
 401         0x00000000,
 402         (0x0400 << 16) | (0xc7ac >> 2),
 403         0x00000000,
 404         (0x0400 << 16) | (0xc7b0 >> 2),
 405         0x00000000,
 406         (0x0400 << 16) | (0xc7b4 >> 2),
 407         0x00000000,
 408         (0x0e00 << 16) | (0x9100 >> 2),
 409         0x00000000,
 410         (0x0e00 << 16) | (0x3c010 >> 2),
 411         0x00000000,
 412         (0x0e00 << 16) | (0x92a8 >> 2),
 413         0x00000000,
 414         (0x0e00 << 16) | (0x92ac >> 2),
 415         0x00000000,
 416         (0x0e00 << 16) | (0x92b4 >> 2),
 417         0x00000000,
 418         (0x0e00 << 16) | (0x92b8 >> 2),
 419         0x00000000,
 420         (0x0e00 << 16) | (0x92bc >> 2),
 421         0x00000000,
 422         (0x0e00 << 16) | (0x92c0 >> 2),
 423         0x00000000,
 424         (0x0e00 << 16) | (0x92c4 >> 2),
 425         0x00000000,
 426         (0x0e00 << 16) | (0x92c8 >> 2),
 427         0x00000000,
 428         (0x0e00 << 16) | (0x92cc >> 2),
 429         0x00000000,
 430         (0x0e00 << 16) | (0x92d0 >> 2),
 431         0x00000000,
 432         (0x0e00 << 16) | (0x8c00 >> 2),
 433         0x00000000,
 434         (0x0e00 << 16) | (0x8c04 >> 2),
 435         0x00000000,
 436         (0x0e00 << 16) | (0x8c20 >> 2),
 437         0x00000000,
 438         (0x0e00 << 16) | (0x8c38 >> 2),
 439         0x00000000,
 440         (0x0e00 << 16) | (0x8c3c >> 2),
 441         0x00000000,
 442         (0x0e00 << 16) | (0xae00 >> 2),
 443         0x00000000,
 444         (0x0e00 << 16) | (0x9604 >> 2),
 445         0x00000000,
 446         (0x0e00 << 16) | (0xac08 >> 2),
 447         0x00000000,
 448         (0x0e00 << 16) | (0xac0c >> 2),
 449         0x00000000,
 450         (0x0e00 << 16) | (0xac10 >> 2),
 451         0x00000000,
 452         (0x0e00 << 16) | (0xac14 >> 2),
 453         0x00000000,
 454         (0x0e00 << 16) | (0xac58 >> 2),
 455         0x00000000,
 456         (0x0e00 << 16) | (0xac68 >> 2),
 457         0x00000000,
 458         (0x0e00 << 16) | (0xac6c >> 2),
 459         0x00000000,
 460         (0x0e00 << 16) | (0xac70 >> 2),
 461         0x00000000,
 462         (0x0e00 << 16) | (0xac74 >> 2),
 463         0x00000000,
 464         (0x0e00 << 16) | (0xac78 >> 2),
 465         0x00000000,
 466         (0x0e00 << 16) | (0xac7c >> 2),
 467         0x00000000,
 468         (0x0e00 << 16) | (0xac80 >> 2),
 469         0x00000000,
 470         (0x0e00 << 16) | (0xac84 >> 2),
 471         0x00000000,
 472         (0x0e00 << 16) | (0xac88 >> 2),
 473         0x00000000,
 474         (0x0e00 << 16) | (0xac8c >> 2),
 475         0x00000000,
 476         (0x0e00 << 16) | (0x970c >> 2),
 477         0x00000000,
 478         (0x0e00 << 16) | (0x9714 >> 2),
 479         0x00000000,
 480         (0x0e00 << 16) | (0x9718 >> 2),
 481         0x00000000,
 482         (0x0e00 << 16) | (0x971c >> 2),
 483         0x00000000,
 484         (0x0e00 << 16) | (0x31068 >> 2),
 485         0x00000000,
 486         (0x4e00 << 16) | (0x31068 >> 2),
 487         0x00000000,
 488         (0x5e00 << 16) | (0x31068 >> 2),
 489         0x00000000,
 490         (0x6e00 << 16) | (0x31068 >> 2),
 491         0x00000000,
 492         (0x7e00 << 16) | (0x31068 >> 2),
 493         0x00000000,
 494         (0x8e00 << 16) | (0x31068 >> 2),
 495         0x00000000,
 496         (0x9e00 << 16) | (0x31068 >> 2),
 497         0x00000000,
 498         (0xae00 << 16) | (0x31068 >> 2),
 499         0x00000000,
 500         (0xbe00 << 16) | (0x31068 >> 2),
 501         0x00000000,
 502         (0x0e00 << 16) | (0xcd10 >> 2),
 503         0x00000000,
 504         (0x0e00 << 16) | (0xcd14 >> 2),
 505         0x00000000,
 506         (0x0e00 << 16) | (0x88b0 >> 2),
 507         0x00000000,
 508         (0x0e00 << 16) | (0x88b4 >> 2),
 509         0x00000000,
 510         (0x0e00 << 16) | (0x88b8 >> 2),
 511         0x00000000,
 512         (0x0e00 << 16) | (0x88bc >> 2),
 513         0x00000000,
 514         (0x0400 << 16) | (0x89c0 >> 2),
 515         0x00000000,
 516         (0x0e00 << 16) | (0x88c4 >> 2),
 517         0x00000000,
 518         (0x0e00 << 16) | (0x88c8 >> 2),
 519         0x00000000,
 520         (0x0e00 << 16) | (0x88d0 >> 2),
 521         0x00000000,
 522         (0x0e00 << 16) | (0x88d4 >> 2),
 523         0x00000000,
 524         (0x0e00 << 16) | (0x88d8 >> 2),
 525         0x00000000,
 526         (0x0e00 << 16) | (0x8980 >> 2),
 527         0x00000000,
 528         (0x0e00 << 16) | (0x30938 >> 2),
 529         0x00000000,
 530         (0x0e00 << 16) | (0x3093c >> 2),
 531         0x00000000,
 532         (0x0e00 << 16) | (0x30940 >> 2),
 533         0x00000000,
 534         (0x0e00 << 16) | (0x89a0 >> 2),
 535         0x00000000,
 536         (0x0e00 << 16) | (0x30900 >> 2),
 537         0x00000000,
 538         (0x0e00 << 16) | (0x30904 >> 2),
 539         0x00000000,
 540         (0x0e00 << 16) | (0x89b4 >> 2),
 541         0x00000000,
 542         (0x0e00 << 16) | (0x3c210 >> 2),
 543         0x00000000,
 544         (0x0e00 << 16) | (0x3c214 >> 2),
 545         0x00000000,
 546         (0x0e00 << 16) | (0x3c218 >> 2),
 547         0x00000000,
 548         (0x0e00 << 16) | (0x8904 >> 2),
 549         0x00000000,
 550         0x5,
 551         (0x0e00 << 16) | (0x8c28 >> 2),
 552         (0x0e00 << 16) | (0x8c2c >> 2),
 553         (0x0e00 << 16) | (0x8c30 >> 2),
 554         (0x0e00 << 16) | (0x8c34 >> 2),
 555         (0x0e00 << 16) | (0x9600 >> 2),
 556 };
 557
 558 static const u32 kalindi_rlc_save_restore_register_list[] =
 559 {
 560         (0x0e00 << 16) | (0xc12c >> 2),
 561         0x00000000,
 562         (0x0e00 << 16) | (0xc140 >> 2),
 563         0x00000000,
 564         (0x0e00 << 16) | (0xc150 >> 2),
 565         0x00000000,
 566         (0x0e00 << 16) | (0xc15c >> 2),
 567         0x00000000,
 568         (0x0e00 << 16) | (0xc168 >> 2),
 569         0x00000000,
 570         (0x0e00 << 16) | (0xc170 >> 2),
 571         0x00000000,
 572         (0x0e00 << 16) | (0xc204 >> 2),
 573         0x00000000,
 574         (0x0e00 << 16) | (0xc2b4 >> 2),
 575         0x00000000,
 576         (0x0e00 << 16) | (0xc2b8 >> 2),
 577         0x00000000,
 578         (0x0e00 << 16) | (0xc2bc >> 2),
 579         0x00000000,
 580         (0x0e00 << 16) | (0xc2c0 >> 2),
 581         0x00000000,
 582         (0x0e00 << 16) | (0x8228 >> 2),
 583         0x00000000,
 584         (0x0e00 << 16) | (0x829c >> 2),
 585         0x00000000,
 586         (0x0e00 << 16) | (0x869c >> 2),
 587         0x00000000,
 588         (0x0600 << 16) | (0x98f4 >> 2),
 589         0x00000000,
 590         (0x0e00 << 16) | (0x98f8 >> 2),
 591         0x00000000,
 592         (0x0e00 << 16) | (0x9900 >> 2),
 593         0x00000000,
 594         (0x0e00 << 16) | (0xc260 >> 2),
 595         0x00000000,
 596         (0x0e00 << 16) | (0x90e8 >> 2),
 597         0x00000000,
 598         (0x0e00 << 16) | (0x3c000 >> 2),
 599         0x00000000,
 600         (0x0e00 << 16) | (0x3c00c >> 2),
 601         0x00000000,
 602         (0x0e00 << 16) | (0x8c1c >> 2),
 603         0x00000000,
 604         (0x0e00 << 16) | (0x9700 >> 2),
 605         0x00000000,
 606         (0x0e00 << 16) | (0xcd20 >> 2),
 607         0x00000000,
 608         (0x4e00 << 16) | (0xcd20 >> 2),
 609         0x00000000,
 610         (0x5e00 << 16) | (0xcd20 >> 2),
 611         0x00000000,
 612         (0x6e00 << 16) | (0xcd20 >> 2),
 613         0x00000000,
 614         (0x7e00 << 16) | (0xcd20 >> 2),
 615         0x00000000,
 616         (0x0e00 << 16) | (0x89bc >> 2),
 617         0x00000000,
 618         (0x0e00 << 16) | (0x8900 >> 2),
 619         0x00000000,
 620         0x3,
 621         (0x0e00 << 16) | (0xc130 >> 2),
 622         0x00000000,
 623         (0x0e00 << 16) | (0xc134 >> 2),
 624         0x00000000,
 625         (0x0e00 << 16) | (0xc1fc >> 2),
 626         0x00000000,
 627         (0x0e00 << 16) | (0xc208 >> 2),
 628         0x00000000,
 629         (0x0e00 << 16) | (0xc264 >> 2),
 630         0x00000000,
 631         (0x0e00 << 16) | (0xc268 >> 2),
 632         0x00000000,
 633         (0x0e00 << 16) | (0xc26c >> 2),
 634         0x00000000,
 635         (0x0e00 << 16) | (0xc270 >> 2),
 636         0x00000000,
 637         (0x0e00 << 16) | (0xc274 >> 2),
 638         0x00000000,
 639         (0x0e00 << 16) | (0xc28c >> 2),
 640         0x00000000,
 641         (0x0e00 << 16) | (0xc290 >> 2),
 642         0x00000000,
 643         (0x0e00 << 16) | (0xc294 >> 2),
 644         0x00000000,
 645         (0x0e00 << 16) | (0xc298 >> 2),
 646         0x00000000,
 647         (0x0e00 << 16) | (0xc2a0 >> 2),
 648         0x00000000,
 649         (0x0e00 << 16) | (0xc2a4 >> 2),
 650         0x00000000,
 651         (0x0e00 << 16) | (0xc2a8 >> 2),
 652         0x00000000,
 653         (0x0e00 << 16) | (0xc2ac >> 2),
 654         0x00000000,
 655         (0x0e00 << 16) | (0x301d0 >> 2),
 656         0x00000000,
 657         (0x0e00 << 16) | (0x30238 >> 2),
 658         0x00000000,
 659         (0x0e00 << 16) | (0x30250 >> 2),
 660         0x00000000,
 661         (0x0e00 << 16) | (0x30254 >> 2),
 662         0x00000000,
 663         (0x0e00 << 16) | (0x30258 >> 2),
 664         0x00000000,
 665         (0x0e00 << 16) | (0x3025c >> 2),
 666         0x00000000,
 667         (0x4e00 << 16) | (0xc900 >> 2),
 668         0x00000000,
 669         (0x5e00 << 16) | (0xc900 >> 2),
 670         0x00000000,
 671         (0x6e00 << 16) | (0xc900 >> 2),
 672         0x00000000,
 673         (0x7e00 << 16) | (0xc900 >> 2),
 674         0x00000000,
 675         (0x4e00 << 16) | (0xc904 >> 2),
 676         0x00000000,
 677         (0x5e00 << 16) | (0xc904 >> 2),
 678         0x00000000,
 679         (0x6e00 << 16) | (0xc904 >> 2),
 680         0x00000000,
 681         (0x7e00 << 16) | (0xc904 >> 2),
 682         0x00000000,
 683         (0x4e00 << 16) | (0xc908 >> 2),
 684         0x00000000,
 685         (0x5e00 << 16) | (0xc908 >> 2),
 686         0x00000000,
 687         (0x6e00 << 16) | (0xc908 >> 2),
 688         0x00000000,
 689         (0x7e00 << 16) | (0xc908 >> 2),
 690         0x00000000,
 691         (0x4e00 << 16) | (0xc90c >> 2),
 692         0x00000000,
 693         (0x5e00 << 16) | (0xc90c >> 2),
 694         0x00000000,
 695         (0x6e00 << 16) | (0xc90c >> 2),
 696         0x00000000,
 697         (0x7e00 << 16) | (0xc90c >> 2),
 698         0x00000000,
 699         (0x4e00 << 16) | (0xc910 >> 2),
 700         0x00000000,
 701         (0x5e00 << 16) | (0xc910 >> 2),
 702         0x00000000,
 703         (0x6e00 << 16) | (0xc910 >> 2),
 704         0x00000000,
 705         (0x7e00 << 16) | (0xc910 >> 2),
 706         0x00000000,
 707         (0x0e00 << 16) | (0xc99c >> 2),
 708         0x00000000,
 709         (0x0e00 << 16) | (0x9834 >> 2),
 710         0x00000000,
 711         (0x0000 << 16) | (0x30f00 >> 2),
 712         0x00000000,
 713         (0x0000 << 16) | (0x30f04 >> 2),
 714         0x00000000,
 715         (0x0000 << 16) | (0x30f08 >> 2),
 716         0x00000000,
 717         (0x0000 << 16) | (0x30f0c >> 2),
 718         0x00000000,
 719         (0x0600 << 16) | (0x9b7c >> 2),
 720         0x00000000,
 721         (0x0e00 << 16) | (0x8a14 >> 2),
 722         0x00000000,
 723         (0x0e00 << 16) | (0x8a18 >> 2),
 724         0x00000000,
 725         (0x0600 << 16) | (0x30a00 >> 2),
 726         0x00000000,
 727         (0x0e00 << 16) | (0x8bf0 >> 2),
 728         0x00000000,
 729         (0x0e00 << 16) | (0x8bcc >> 2),
 730         0x00000000,
 731         (0x0e00 << 16) | (0x8b24 >> 2),
 732         0x00000000,
 733         (0x0e00 << 16) | (0x30a04 >> 2),
 734         0x00000000,
 735         (0x0600 << 16) | (0x30a10 >> 2),
 736         0x00000000,
 737         (0x0600 << 16) | (0x30a14 >> 2),
 738         0x00000000,
 739         (0x0600 << 16) | (0x30a18 >> 2),
 740         0x00000000,
 741         (0x0600 << 16) | (0x30a2c >> 2),
 742         0x00000000,
 743         (0x0e00 << 16) | (0xc700 >> 2),
 744         0x00000000,
 745         (0x0e00 << 16) | (0xc704 >> 2),
 746         0x00000000,
 747         (0x0e00 << 16) | (0xc708 >> 2),
 748         0x00000000,
 749         (0x0e00 << 16) | (0xc768 >> 2),
 750         0x00000000,
 751         (0x0400 << 16) | (0xc770 >> 2),
 752         0x00000000,
 753         (0x0400 << 16) | (0xc774 >> 2),
 754         0x00000000,
 755         (0x0400 << 16) | (0xc798 >> 2),
 756         0x00000000,
 757         (0x0400 << 16) | (0xc79c >> 2),
 758         0x00000000,
 759         (0x0e00 << 16) | (0x9100 >> 2),
 760         0x00000000,
 761         (0x0e00 << 16) | (0x3c010 >> 2),
 762         0x00000000,
 763         (0x0e00 << 16) | (0x8c00 >> 2),
 764         0x00000000,
 765         (0x0e00 << 16) | (0x8c04 >> 2),
 766         0x00000000,
 767         (0x0e00 << 16) | (0x8c20 >> 2),
 768         0x00000000,
 769         (0x0e00 << 16) | (0x8c38 >> 2),
 770         0x00000000,
 771         (0x0e00 << 16) | (0x8c3c >> 2),
 772         0x00000000,
 773         (0x0e00 << 16) | (0xae00 >> 2),
 774         0x00000000,
 775         (0x0e00 << 16) | (0x9604 >> 2),
 776         0x00000000,
 777         (0x0e00 << 16) | (0xac08 >> 2),
 778         0x00000000,
 779         (0x0e00 << 16) | (0xac0c >> 2),
 780         0x00000000,
 781         (0x0e00 << 16) | (0xac10 >> 2),
 782         0x00000000,
 783         (0x0e00 << 16) | (0xac14 >> 2),
 784         0x00000000,
 785         (0x0e00 << 16) | (0xac58 >> 2),
 786         0x00000000,
 787         (0x0e00 << 16) | (0xac68 >> 2),
 788         0x00000000,
 789         (0x0e00 << 16) | (0xac6c >> 2),
 790         0x00000000,
 791         (0x0e00 << 16) | (0xac70 >> 2),
 792         0x00000000,
 793         (0x0e00 << 16) | (0xac74 >> 2),
 794         0x00000000,
 795         (0x0e00 << 16) | (0xac78 >> 2),
 796         0x00000000,
 797         (0x0e00 << 16) | (0xac7c >> 2),
 798         0x00000000,
 799         (0x0e00 << 16) | (0xac80 >> 2),
 800         0x00000000,
 801         (0x0e00 << 16) | (0xac84 >> 2),
 802         0x00000000,
 803         (0x0e00 << 16) | (0xac88 >> 2),
 804         0x00000000,
 805         (0x0e00 << 16) | (0xac8c >> 2),
 806         0x00000000,
 807         (0x0e00 << 16) | (0x970c >> 2),
 808         0x00000000,
 809         (0x0e00 << 16) | (0x9714 >> 2),
 810         0x00000000,
 811         (0x0e00 << 16) | (0x9718 >> 2),
 812         0x00000000,
 813         (0x0e00 << 16) | (0x971c >> 2),
 814         0x00000000,
 815         (0x0e00 << 16) | (0x31068 >> 2),
 816         0x00000000,
 817         (0x4e00 << 16) | (0x31068 >> 2),
 818         0x00000000,
 819         (0x5e00 << 16) | (0x31068 >> 2),
 820         0x00000000,
 821         (0x6e00 << 16) | (0x31068 >> 2),
 822         0x00000000,
 823         (0x7e00 << 16) | (0x31068 >> 2),
 824         0x00000000,
 825         (0x0e00 << 16) | (0xcd10 >> 2),
 826         0x00000000,
 827         (0x0e00 << 16) | (0xcd14 >> 2),
 828         0x00000000,
 829         (0x0e00 << 16) | (0x88b0 >> 2),
 830         0x00000000,
 831         (0x0e00 << 16) | (0x88b4 >> 2),
 832         0x00000000,
 833         (0x0e00 << 16) | (0x88b8 >> 2),
 834         0x00000000,
 835         (0x0e00 << 16) | (0x88bc >> 2),
 836         0x00000000,
 837         (0x0400 << 16) | (0x89c0 >> 2),
 838         0x00000000,
 839         (0x0e00 << 16) | (0x88c4 >> 2),
 840         0x00000000,
 841         (0x0e00 << 16) | (0x88c8 >> 2),
 842         0x00000000,
 843         (0x0e00 << 16) | (0x88d0 >> 2),
 844         0x00000000,
 845         (0x0e00 << 16) | (0x88d4 >> 2),
 846         0x00000000,
 847         (0x0e00 << 16) | (0x88d8 >> 2),
 848         0x00000000,
 849         (0x0e00 << 16) | (0x8980 >> 2),
 850         0x00000000,
 851         (0x0e00 << 16) | (0x30938 >> 2),
 852         0x00000000,
 853         (0x0e00 << 16) | (0x3093c >> 2),
 854         0x00000000,
 855         (0x0e00 << 16) | (0x30940 >> 2),
 856         0x00000000,
 857         (0x0e00 << 16) | (0x89a0 >> 2),
 858         0x00000000,
 859         (0x0e00 << 16) | (0x30900 >> 2),
 860         0x00000000,
 861         (0x0e00 << 16) | (0x30904 >> 2),
 862         0x00000000,
 863         (0x0e00 << 16) | (0x89b4 >> 2),
 864         0x00000000,
 865         (0x0e00 << 16) | (0x3e1fc >> 2),
 866         0x00000000,
 867         (0x0e00 << 16) | (0x3c210 >> 2),
 868         0x00000000,
 869         (0x0e00 << 16) | (0x3c214 >> 2),
 870         0x00000000,
 871         (0x0e00 << 16) | (0x3c218 >> 2),
 872         0x00000000,
 873         (0x0e00 << 16) | (0x8904 >> 2),
 874         0x00000000,
 875         0x5,
 876         (0x0e00 << 16) | (0x8c28 >> 2),
 877         (0x0e00 << 16) | (0x8c2c >> 2),
 878         (0x0e00 << 16) | (0x8c30 >> 2),
 879         (0x0e00 << 16) | (0x8c34 >> 2),
 880         (0x0e00 << 16) | (0x9600 >> 2),
 881 };
 882
 883 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev);
 884 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
 885 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev);
 886 static void gfx_v7_0_init_pg(struct amdgpu_device *adev);
 887
 888 /*
 889  * Core functions
 890  */
 891 /**
 892  * gfx_v7_0_init_microcode - load ucode images from disk
 893  *
 894  * @adev: amdgpu_device pointer
 895  *
 896  * Use the firmware interface to load the ucode images into
 897  * the driver (not loaded into hw).
 898  * Returns 0 on success, error on failure.
 899  */
 900 static int gfx_v7_0_init_microcode(struct amdgpu_device *adev)
 901 {
 902         const char *chip_name;
 903         char fw_name[30];
 904         int err;
 905
 906         DRM_DEBUG("\n");
 907
 908         switch (adev->asic_type) {
 909         case CHIP_BONAIRE:
 910                 chip_name = "bonaire";
 911                 break;
 912         case CHIP_HAWAII:
 913                 chip_name = "hawaii";
 914                 break;
 915         case CHIP_KAVERI:
 916                 chip_name = "kaveri";
 917                 break;
 918         case CHIP_KABINI:
 919                 chip_name = "kabini";
 920                 break;
 921         case CHIP_MULLINS:
 922                 chip_name = "mullins";
 923                 break;
 924         default: BUG();
 925         }
 926
 927         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 928         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 929         if (err)
 930                 goto out;
 931         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 932         if (err)
 933                 goto out;
 934
 935         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 936         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 937         if (err)
 938                 goto out;
 939         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 940         if (err)
 941                 goto out;
 942
 943         snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
 944         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 945         if (err)
 946                 goto out;
 947         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 948         if (err)
 949                 goto out;
 950
 951         snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
 952         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 953         if (err)
 954                 goto out;
 955         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 956         if (err)
 957                 goto out;
 958
 959         if (adev->asic_type == CHIP_KAVERI) {
 960                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec2.bin", chip_name);
 961                 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 962                 if (err)
 963                         goto out;
 964                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 965                 if (err)
 966                         goto out;
 967         }
 968
 969         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
 970         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 971         if (err)
 972                 goto out;
 973         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 974
 975 out:
 976         if (err) {
 977                 printk(KERN_ERR
 978                        "gfx7: Failed to load firmware \"%s\"\n",
 979                        fw_name);
 980                 release_firmware(adev->gfx.pfp_fw);
 981                 adev->gfx.pfp_fw = NULL;
 982                 release_firmware(adev->gfx.me_fw);
 983                 adev->gfx.me_fw = NULL;
 984                 release_firmware(adev->gfx.ce_fw);
 985                 adev->gfx.ce_fw = NULL;
 986                 release_firmware(adev->gfx.mec_fw);
 987                 adev->gfx.mec_fw = NULL;
 988                 release_firmware(adev->gfx.mec2_fw);
 989                 adev->gfx.mec2_fw = NULL;
 990                 release_firmware(adev->gfx.rlc_fw);
 991                 adev->gfx.rlc_fw = NULL;
 992         }
 993         return err;
 994 }
 995
 996 /**
 997  * gfx_v7_0_tiling_mode_table_init - init the hw tiling table
 998  *
 999  * @adev: amdgpu_device pointer
1000  *
1001  * Starting with SI, the tiling setup is done globally in a
1002  * set of 32 tiling modes.  Rather than selecting each set of
1003  * parameters per surface as on older asics, we just select
1004  * which index in the tiling table we want to use, and the
1005  * surface uses those parameters (CIK).
1006  */
1007 static void gfx_v7_0_tiling_mode_table_init(struct amdgpu_device *adev)
1008 {
1009         const u32 num_tile_mode_states = 32;
1010         const u32 num_secondary_tile_mode_states = 16;
1011         u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
1012
1013         switch (adev->gfx.config.mem_row_size_in_kb) {
1014         case 1:
1015                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1016                 break;
1017         case 2:
1018         default:
1019                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1020                 break;
1021         case 4:
1022                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1023                 break;
1024         }
1025
1026         switch (adev->asic_type) {
1027         case CHIP_BONAIRE:
1028                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1029                         switch (reg_offset) {
1030                         case 0:
1031                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1032                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1033                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1034                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1035                                 break;
1036                         case 1:
1037                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1038                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1039                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1040                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1041                                 break;
1042                         case 2:
1043                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1044                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1045                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1046                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1047                                 break;
1048                         case 3:
1049                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1050                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1051                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1052                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1053                                 break;
1054                         case 4:
1055                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1056                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1057                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1058                                                 TILE_SPLIT(split_equal_to_row_size));
1059                                 break;
1060                         case 5:
1061                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1062                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1063                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1064                                 break;
1065                         case 6:
1066                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1067                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1068                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1069                                                 TILE_SPLIT(split_equal_to_row_size));
1070                                 break;
1071                         case 7:
1072                                 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1073                                 break;
1074
1075                         case 8:
1076                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1077                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16));
1078                                 break;
1079                         case 9:
1080                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1081                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1082                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1083                                 break;
1084                         case 10:
1085                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1086                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1087                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1088                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1089                                 break;
1090                         case 11:
1091                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1092                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1093                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1094                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1095                                 break;
1096                         case 12:
1097                                 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1098                                 break;
1099                         case 13:
1100                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1101                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1102                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1103                                 break;
1104                         case 14:
1105                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1106                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1107                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1108                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1109                                 break;
1110                         case 15:
1111                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1112                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1113                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1114                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1115                                 break;
1116                         case 16:
1117                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1118                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1119                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1120                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1121                                 break;
1122                         case 17:
1123                                 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1124                                 break;
1125                         case 18:
1126                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1127                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1128                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1129                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1130                                 break;
1131                         case 19:
1132                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1133                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1134                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1135                                 break;
1136                         case 20:
1137                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1138                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1139                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1140                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1141                                 break;
1142                         case 21:
1143                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1144                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1145                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1146                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1147                                 break;
1148                         case 22:
1149                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1150                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1151                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1152                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1153                                 break;
1154                         case 23:
1155                                 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1156                                 break;
1157                         case 24:
1158                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1159                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1160                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1161                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1162                                 break;
1163                         case 25:
1164                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1165                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1166                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1167                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1168                                 break;
1169                         case 26:
1170                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1171                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1172                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1173                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1174                                 break;
1175                         case 27:
1176                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1177                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1178                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1179                                 break;
1180                         case 28:
1181                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1182                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1183                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1184                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1185                                 break;
1186                         case 29:
1187                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1188                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1189                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1190                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1191                                 break;
1192                         case 30:
1193                                 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1194                                 break;
1195                         default:
1196                                 gb_tile_moden = 0;
1197                                 break;
1198                         }
1199                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1200                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1201                 }
1202                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1203                         switch (reg_offset) {
1204                         case 0:
1205                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1206                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1207                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1208                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1209                                 break;
1210                         case 1:
1211                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1212                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1213                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1214                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1215                                 break;
1216                         case 2:
1217                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1218                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1219                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1220                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1221                                 break;
1222                         case 3:
1223                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1224                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1225                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1226                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1227                                 break;
1228                         case 4:
1229                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1230                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1231                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1232                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1233                                 break;
1234                         case 5:
1235                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1236                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1237                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1238                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1239                                 break;
1240                         case 6:
1241                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1242                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1243                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1244                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1245                                 break;
1246                         case 8:
1247                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1248                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1249                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1250                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1251                                 break;
1252                         case 9:
1253                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1254                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1255                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1256                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1257                                 break;
1258                         case 10:
1259                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1260                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1261                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1262                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1263                                 break;
1264                         case 11:
1265                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1266                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1267                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1268                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1269                                 break;
1270                         case 12:
1271                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1272                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1273                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1274                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1275                                 break;
1276                         case 13:
1277                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1278                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1279                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1280                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1281                                 break;
1282                         case 14:
1283                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1284                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1285                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1286                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1287                                 break;
1288                         default:
1289                                 gb_tile_moden = 0;
1290                                 break;
1291                         }
1292                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1293                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1294                 }
1295                 break;
1296         case CHIP_HAWAII:
1297                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1298                         switch (reg_offset) {
1299                         case 0:
1300                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1301                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1302                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1303                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1304                                 break;
1305                         case 1:
1306                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1307                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1308                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1309                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1310                                 break;
1311                         case 2:
1312                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1313                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1314                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1315                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1316                                 break;
1317                         case 3:
1318                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1319                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1320                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1321                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1322                                 break;
1323                         case 4:
1324                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1325                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1326                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1327                                                 TILE_SPLIT(split_equal_to_row_size));
1328                                 break;
1329                         case 5:
1330                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1331                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1332                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1333                                                 TILE_SPLIT(split_equal_to_row_size));
1334                                 break;
1335                         case 6:
1336                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1337                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1338                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1339                                                 TILE_SPLIT(split_equal_to_row_size));
1340                                 break;
1341                         case 7:
1342                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1343                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1344                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1345                                                 TILE_SPLIT(split_equal_to_row_size));
1346                                 break;
1347
1348                         case 8:
1349                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1350                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
1351                                 break;
1352                         case 9:
1353                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1354                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1355                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1356                                 break;
1357                         case 10:
1358                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1359                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1360                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1361                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1362                                 break;
1363                         case 11:
1364                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1365                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1366                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1367                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1368                                 break;
1369                         case 12:
1370                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1371                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1372                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1373                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1374                                 break;
1375                         case 13:
1376                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1377                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1378                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1379                                 break;
1380                         case 14:
1381                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1382                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1383                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1384                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1385                                 break;
1386                         case 15:
1387                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1388                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1389                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1390                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1391                                 break;
1392                         case 16:
1393                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1394                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1395                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1396                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1397                                 break;
1398                         case 17:
1399                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1400                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1401                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1402                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1403                                 break;
1404                         case 18:
1405                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1406                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1407                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1408                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1409                                 break;
1410                         case 19:
1411                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1412                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1413                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1414                                 break;
1415                         case 20:
1416                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1417                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1418                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1419                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1420                                 break;
1421                         case 21:
1422                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1423                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1424                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1425                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1426                                 break;
1427                         case 22:
1428                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1429                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1430                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1431                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1432                                 break;
1433                         case 23:
1434                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1435                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1436                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1437                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1438                                 break;
1439                         case 24:
1440                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1441                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1442                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1443                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1444                                 break;
1445                         case 25:
1446                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1447                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1448                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1449                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1450                                 break;
1451                         case 26:
1452                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1453                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1454                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1455                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1456                                 break;
1457                         case 27:
1458                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1459                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1460                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1461                                 break;
1462                         case 28:
1463                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1464                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1465                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1466                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1467                                 break;
1468                         case 29:
1469                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1470                                                 PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
1471                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1472                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1473                                 break;
1474                         case 30:
1475                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1476                                                 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1477                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1478                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1479                                 break;
1480                         default:
1481                                 gb_tile_moden = 0;
1482                                 break;
1483                         }
1484                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1485                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1486                 }
1487                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1488                         switch (reg_offset) {
1489                         case 0:
1490                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1491                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1492                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1493                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1494                                 break;
1495                         case 1:
1496                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1497                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1498                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1499                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1500                                 break;
1501                         case 2:
1502                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1503                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1504                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1505                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1506                                 break;
1507                         case 3:
1508                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1509                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1510                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1511                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1512                                 break;
1513                         case 4:
1514                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1515                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1516                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1517                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1518                                 break;
1519                         case 5:
1520                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1521                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1522                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1523                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1524                                 break;
1525                         case 6:
1526                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1527                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1528                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1529                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1530                                 break;
1531                         case 8:
1532                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1533                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1534                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1535                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1536                                 break;
1537                         case 9:
1538                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1539                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1540                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1541                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1542                                 break;
1543                         case 10:
1544                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1545                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1546                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1547                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1548                                 break;
1549                         case 11:
1550                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1551                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1552                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1553                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1554                                 break;
1555                         case 12:
1556                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1557                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1558                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1559                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1560                                 break;
1561                         case 13:
1562                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1563                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1564                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1565                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1566                                 break;
1567                         case 14:
1568                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1569                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1570                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1571                                                 NUM_BANKS(ADDR_SURF_4_BANK));
1572                                 break;
1573                         default:
1574                                 gb_tile_moden = 0;
1575                                 break;
1576                         }
1577                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1578                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1579                 }
1580                 break;
1581         case CHIP_KABINI:
1582         case CHIP_KAVERI:
1583         case CHIP_MULLINS:
1584         default:
1585                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1586                         switch (reg_offset) {
1587                         case 0:
1588                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1589                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1590                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1591                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1592                                 break;
1593                         case 1:
1594                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1595                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1596                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1597                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1598                                 break;
1599                         case 2:
1600                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1601                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1602                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1603                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1604                                 break;
1605                         case 3:
1606                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1607                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1608                                                 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1609                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1610                                 break;
1611                         case 4:
1612                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1613                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1614                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1615                                                 TILE_SPLIT(split_equal_to_row_size));
1616                                 break;
1617                         case 5:
1618                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1619                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1620                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1621                                 break;
1622                         case 6:
1623                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1624                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1625                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1626                                                 TILE_SPLIT(split_equal_to_row_size));
1627                                 break;
1628                         case 7:
1629                                 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1630                                 break;
1631
1632                         case 8:
1633                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1634                                                 PIPE_CONFIG(ADDR_SURF_P2));
1635                                 break;
1636                         case 9:
1637                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1638                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1639                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1640                                 break;
1641                         case 10:
1642                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1643                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1644                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1645                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1646                                 break;
1647                         case 11:
1648                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1649                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1650                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1651                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1652                                 break;
1653                         case 12:
1654                                 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1655                                 break;
1656                         case 13:
1657                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1658                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1659                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1660                                 break;
1661                         case 14:
1662                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1663                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1664                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1665                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1666                                 break;
1667                         case 15:
1668                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1669                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1670                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1671                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1672                                 break;
1673                         case 16:
1674                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1675                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1676                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1677                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1678                                 break;
1679                         case 17:
1680                                 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1681                                 break;
1682                         case 18:
1683                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1684                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1685                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1686                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1687                                 break;
1688                         case 19:
1689                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1690                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1691                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING));
1692                                 break;
1693                         case 20:
1694                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1695                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1696                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1697                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1698                                 break;
1699                         case 21:
1700                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1701                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1702                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1703                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1704                                 break;
1705                         case 22:
1706                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1707                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1708                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1709                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1710                                 break;
1711                         case 23:
1712                                 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1713                                 break;
1714                         case 24:
1715                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1716                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1717                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1718                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1719                                 break;
1720                         case 25:
1721                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1722                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1723                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1724                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1725                                 break;
1726                         case 26:
1727                                 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1728                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1729                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1730                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1731                                 break;
1732                         case 27:
1733                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1734                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1735                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1736                                 break;
1737                         case 28:
1738                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1739                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1740                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1741                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1742                                 break;
1743                         case 29:
1744                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1745                                                 PIPE_CONFIG(ADDR_SURF_P2) |
1746                                                 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1747                                                 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1748                                 break;
1749                         case 30:
1750                                 gb_tile_moden = (TILE_SPLIT(split_equal_to_row_size));
1751                                 break;
1752                         default:
1753                                 gb_tile_moden = 0;
1754                                 break;
1755                         }
1756                         adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1757                         WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1758                 }
1759                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1760                         switch (reg_offset) {
1761                         case 0:
1762                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1763                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1764                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1765                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1766                                 break;
1767                         case 1:
1768                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1769                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1770                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1771                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1772                                 break;
1773                         case 2:
1774                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1775                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1776                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1777                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1778                                 break;
1779                         case 3:
1780                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1781                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1782                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1783                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1784                                 break;
1785                         case 4:
1786                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1787                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1788                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1789                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1790                                 break;
1791                         case 5:
1792                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1793                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1794                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1795                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1796                                 break;
1797                         case 6:
1798                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1799                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1800                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1801                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1802                                 break;
1803                         case 8:
1804                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1805                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1806                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1807                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1808                                 break;
1809                         case 9:
1810                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1811                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1812                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1813                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1814                                 break;
1815                         case 10:
1816                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1817                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1818                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1819                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1820                                 break;
1821                         case 11:
1822                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1823                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1824                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1825                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1826                                 break;
1827                         case 12:
1828                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1829                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1830                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1831                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1832                                 break;
1833                         case 13:
1834                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1835                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1836                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1837                                                 NUM_BANKS(ADDR_SURF_16_BANK));
1838                                 break;
1839                         case 14:
1840                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1841                                                 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1842                                                 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1843                                                 NUM_BANKS(ADDR_SURF_8_BANK));
1844                                 break;
1845                         default:
1846                                 gb_tile_moden = 0;
1847                                 break;
1848                         }
1849                         adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1850                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1851                 }
1852                 break;
1853         }
1854 }
1855
1856 /**
1857  * gfx_v7_0_select_se_sh - select which SE, SH to address
1858  *
1859  * @adev: amdgpu_device pointer
1860  * @se_num: shader engine to address
1861  * @sh_num: sh block to address
1862  *
1863  * Select which SE, SH combinations to address. Certain
1864  * registers are instanced per SE or SH.  0xffffffff means
1865  * broadcast to all SEs or SHs (CIK).
1866  */
1867 void gfx_v7_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
1868 {
1869         u32 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK;
1870
1871         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1872                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1873                         GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1874         else if (se_num == 0xffffffff)
1875                 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1876                         (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1877         else if (sh_num == 0xffffffff)
1878                 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1879                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1880         else
1881                 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1882                         (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1883         WREG32(mmGRBM_GFX_INDEX, data);
1884 }
1885
1886 /**
1887  * gfx_v7_0_create_bitmask - create a bitmask
1888  *
1889  * @bit_width: length of the mask
1890  *
1891  * create a variable length bit mask (CIK).
1892  * Returns the bitmask.
1893  */
1894 static u32 gfx_v7_0_create_bitmask(u32 bit_width)
1895 {
1896         u32 i, mask = 0;
1897
1898         for (i = 0; i < bit_width; i++) {
1899                 mask <<= 1;
1900                 mask |= 1;
1901         }
1902         return mask;
1903 }
1904
1905 /**
1906  * gfx_v7_0_get_rb_disabled - computes the mask of disabled RBs
1907  *
1908  * @adev: amdgpu_device pointer
1909  * @max_rb_num: max RBs (render backends) for the asic
1910  * @se_num: number of SEs (shader engines) for the asic
1911  * @sh_per_se: number of SH blocks per SE for the asic
1912  *
1913  * Calculates the bitmask of disabled RBs (CIK).
1914  * Returns the disabled RB bitmask.
1915  */
1916 static u32 gfx_v7_0_get_rb_disabled(struct amdgpu_device *adev,
1917                                     u32 max_rb_num_per_se,
1918                                     u32 sh_per_se)
1919 {
1920         u32 data, mask;
1921
1922         data = RREG32(mmCC_RB_BACKEND_DISABLE);
1923         if (data & 1)
1924                 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1925         else
1926                 data = 0;
1927
1928         data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1929
1930         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1931
1932         mask = gfx_v7_0_create_bitmask(max_rb_num_per_se / sh_per_se);
1933
1934         return data & mask;
1935 }
1936
1937 /**
1938  * gfx_v7_0_setup_rb - setup the RBs on the asic
1939  *
1940  * @adev: amdgpu_device pointer
1941  * @se_num: number of SEs (shader engines) for the asic
1942  * @sh_per_se: number of SH blocks per SE for the asic
1943  * @max_rb_num: max RBs (render backends) for the asic
1944  *
1945  * Configures per-SE/SH RB registers (CIK).
1946  */
1947 static void gfx_v7_0_setup_rb(struct amdgpu_device *adev,
1948                               u32 se_num, u32 sh_per_se,
1949                               u32 max_rb_num_per_se)
1950 {
1951         int i, j;
1952         u32 data, mask;
1953         u32 disabled_rbs = 0;
1954         u32 enabled_rbs = 0;
1955
1956         mutex_lock(&adev->grbm_idx_mutex);
1957         for (i = 0; i < se_num; i++) {
1958                 for (j = 0; j < sh_per_se; j++) {
1959                         gfx_v7_0_select_se_sh(adev, i, j);
1960                         data = gfx_v7_0_get_rb_disabled(adev, max_rb_num_per_se, sh_per_se);
1961                         if (adev->asic_type == CHIP_HAWAII)
1962                                 disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
1963                         else
1964                                 disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH);
1965                 }
1966         }
1967         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
1968         mutex_unlock(&adev->grbm_idx_mutex);
1969
1970         mask = 1;
1971         for (i = 0; i < max_rb_num_per_se * se_num; i++) {
1972                 if (!(disabled_rbs & mask))
1973                         enabled_rbs |= mask;
1974                 mask <<= 1;
1975         }
1976
1977         adev->gfx.config.backend_enable_mask = enabled_rbs;
1978
1979         mutex_lock(&adev->grbm_idx_mutex);
1980         for (i = 0; i < se_num; i++) {
1981                 gfx_v7_0_select_se_sh(adev, i, 0xffffffff);
1982                 data = 0;
1983                 for (j = 0; j < sh_per_se; j++) {
1984                         switch (enabled_rbs & 3) {
1985                         case 0:
1986                                 if (j == 0)
1987                                         data |= (RASTER_CONFIG_RB_MAP_3 <<
1988                                                 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1989                                 else
1990                                         data |= (RASTER_CONFIG_RB_MAP_0 <<
1991                                                 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
1992                                 break;
1993                         case 1:
1994                                 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1995                                 break;
1996                         case 2:
1997                                 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1998                                 break;
1999                         case 3:
2000                         default:
2001                                 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
2002                                 break;
2003                         }
2004                         enabled_rbs >>= 2;
2005                 }
2006                 WREG32(mmPA_SC_RASTER_CONFIG, data);
2007         }
2008         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2009         mutex_unlock(&adev->grbm_idx_mutex);
2010 }
2011
2012 /**
2013  * gfx_v7_0_gpu_init - setup the 3D engine
2014  *
2015  * @adev: amdgpu_device pointer
2016  *
2017  * Configures the 3D engine and tiling configuration
2018  * registers so that the 3D engine is usable.
2019  */
2020 static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
2021 {
2022         u32 gb_addr_config;
2023         u32 mc_shared_chmap, mc_arb_ramcfg;
2024         u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
2025         u32 sh_mem_cfg;
2026         u32 tmp;
2027         int i;
2028
2029         switch (adev->asic_type) {
2030         case CHIP_BONAIRE:
2031                 adev->gfx.config.max_shader_engines = 2;
2032                 adev->gfx.config.max_tile_pipes = 4;
2033                 adev->gfx.config.max_cu_per_sh = 7;
2034                 adev->gfx.config.max_sh_per_se = 1;
2035                 adev->gfx.config.max_backends_per_se = 2;
2036                 adev->gfx.config.max_texture_channel_caches = 4;
2037                 adev->gfx.config.max_gprs = 256;
2038                 adev->gfx.config.max_gs_threads = 32;
2039                 adev->gfx.config.max_hw_contexts = 8;
2040
2041                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2042                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2043                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2044                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2045                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
2046                 break;
2047         case CHIP_HAWAII:
2048                 adev->gfx.config.max_shader_engines = 4;
2049                 adev->gfx.config.max_tile_pipes = 16;
2050                 adev->gfx.config.max_cu_per_sh = 11;
2051                 adev->gfx.config.max_sh_per_se = 1;
2052                 adev->gfx.config.max_backends_per_se = 4;
2053                 adev->gfx.config.max_texture_channel_caches = 16;
2054                 adev->gfx.config.max_gprs = 256;
2055                 adev->gfx.config.max_gs_threads = 32;
2056                 adev->gfx.config.max_hw_contexts = 8;
2057
2058                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2059                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2060                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2061                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2062                 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
2063                 break;
2064         case CHIP_KAVERI:
2065                 adev->gfx.config.max_shader_engines = 1;
2066                 adev->gfx.config.max_tile_pipes = 4;
2067                 if ((adev->pdev->device == 0x1304) ||
2068                     (adev->pdev->device == 0x1305) ||
2069                     (adev->pdev->device == 0x130C) ||
2070                     (adev->pdev->device == 0x130F) ||
2071                     (adev->pdev->device == 0x1310) ||
2072                     (adev->pdev->device == 0x1311) ||
2073                     (adev->pdev->device == 0x131C)) {
2074                         adev->gfx.config.max_cu_per_sh = 8;
2075                         adev->gfx.config.max_backends_per_se = 2;
2076                 } else if ((adev->pdev->device == 0x1309) ||
2077                            (adev->pdev->device == 0x130A) ||
2078                            (adev->pdev->device == 0x130D) ||
2079                            (adev->pdev->device == 0x1313) ||
2080                            (adev->pdev->device == 0x131D)) {
2081                         adev->gfx.config.max_cu_per_sh = 6;
2082                         adev->gfx.config.max_backends_per_se = 2;
2083                 } else if ((adev->pdev->device == 0x1306) ||
2084                            (adev->pdev->device == 0x1307) ||
2085                            (adev->pdev->device == 0x130B) ||
2086                            (adev->pdev->device == 0x130E) ||
2087                            (adev->pdev->device == 0x1315) ||
2088                            (adev->pdev->device == 0x131B)) {
2089                         adev->gfx.config.max_cu_per_sh = 4;
2090                         adev->gfx.config.max_backends_per_se = 1;
2091                 } else {
2092                         adev->gfx.config.max_cu_per_sh = 3;
2093                         adev->gfx.config.max_backends_per_se = 1;
2094                 }
2095                 adev->gfx.config.max_sh_per_se = 1;
2096                 adev->gfx.config.max_texture_channel_caches = 4;
2097                 adev->gfx.config.max_gprs = 256;
2098                 adev->gfx.config.max_gs_threads = 16;
2099                 adev->gfx.config.max_hw_contexts = 8;
2100
2101                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2102                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2103                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2104                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2105                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
2106                 break;
2107         case CHIP_KABINI:
2108         case CHIP_MULLINS:
2109         default:
2110                 adev->gfx.config.max_shader_engines = 1;
2111                 adev->gfx.config.max_tile_pipes = 2;
2112                 adev->gfx.config.max_cu_per_sh = 2;
2113                 adev->gfx.config.max_sh_per_se = 1;
2114                 adev->gfx.config.max_backends_per_se = 1;
2115                 adev->gfx.config.max_texture_channel_caches = 2;
2116                 adev->gfx.config.max_gprs = 256;
2117                 adev->gfx.config.max_gs_threads = 16;
2118                 adev->gfx.config.max_hw_contexts = 8;
2119
2120                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
2121                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
2122                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
2123                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
2124                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
2125                 break;
2126         }
2127
2128         WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
2129
2130         mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
2131         adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
2132         mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
2133
2134         adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
2135         adev->gfx.config.mem_max_burst_length_bytes = 256;
2136         if (adev->flags & AMDGPU_IS_APU) {
2137                 /* Get memory bank mapping mode. */
2138                 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
2139                 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2140                 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2141
2142                 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
2143                 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
2144                 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
2145
2146                 /* Validate settings in case only one DIMM installed. */
2147                 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
2148                         dimm00_addr_map = 0;
2149                 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
2150                         dimm01_addr_map = 0;
2151                 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
2152                         dimm10_addr_map = 0;
2153                 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
2154                         dimm11_addr_map = 0;
2155
2156                 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
2157                 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
2158                 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
2159                         adev->gfx.config.mem_row_size_in_kb = 2;
2160                 else
2161                         adev->gfx.config.mem_row_size_in_kb = 1;
2162         } else {
2163                 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
2164                 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
2165                 if (adev->gfx.config.mem_row_size_in_kb > 4)
2166                         adev->gfx.config.mem_row_size_in_kb = 4;
2167         }
2168         /* XXX use MC settings? */
2169         adev->gfx.config.shader_engine_tile_size = 32;
2170         adev->gfx.config.num_gpus = 1;
2171         adev->gfx.config.multi_gpu_tile_size = 64;
2172
2173         /* fix up row size */
2174         gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
2175         switch (adev->gfx.config.mem_row_size_in_kb) {
2176         case 1:
2177         default:
2178                 gb_addr_config |= (0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
2179                 break;
2180         case 2:
2181                 gb_addr_config |= (1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
2182                 break;
2183         case 4:
2184                 gb_addr_config |= (2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT);
2185                 break;
2186         }
2187         adev->gfx.config.gb_addr_config = gb_addr_config;
2188
2189         WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
2190         WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
2191         WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
2192         WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70);
2193         WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70);
2194         WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
2195         WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
2196         WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
2197
2198         gfx_v7_0_tiling_mode_table_init(adev);
2199
2200         gfx_v7_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
2201                           adev->gfx.config.max_sh_per_se,
2202                           adev->gfx.config.max_backends_per_se);
2203
2204         /* set HW defaults for 3D engine */
2205         WREG32(mmCP_MEQ_THRESHOLDS,
2206                         (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
2207                         (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
2208
2209         mutex_lock(&adev->grbm_idx_mutex);
2210         /*
2211          * making sure that the following register writes will be broadcasted
2212          * to all the shaders
2213          */
2214         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2215
2216         /* XXX SH_MEM regs */
2217         /* where to put LDS, scratch, GPUVM in FSA64 space */
2218         sh_mem_cfg = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
2219                                    SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2220
2221         mutex_lock(&adev->srbm_mutex);
2222         for (i = 0; i < 16; i++) {
2223                 cik_srbm_select(adev, 0, 0, 0, i);
2224                 /* CP and shaders */
2225                 WREG32(mmSH_MEM_CONFIG, sh_mem_cfg);
2226                 WREG32(mmSH_MEM_APE1_BASE, 1);
2227                 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2228                 WREG32(mmSH_MEM_BASES, 0);
2229         }
2230         cik_srbm_select(adev, 0, 0, 0, 0);
2231         mutex_unlock(&adev->srbm_mutex);
2232
2233         WREG32(mmSX_DEBUG_1, 0x20);
2234
2235         WREG32(mmTA_CNTL_AUX, 0x00010000);
2236
2237         tmp = RREG32(mmSPI_CONFIG_CNTL);
2238         tmp |= 0x03000000;
2239         WREG32(mmSPI_CONFIG_CNTL, tmp);
2240
2241         WREG32(mmSQ_CONFIG, 1);
2242
2243         WREG32(mmDB_DEBUG, 0);
2244
2245         tmp = RREG32(mmDB_DEBUG2) & ~0xf00fffff;
2246         tmp |= 0x00000400;
2247         WREG32(mmDB_DEBUG2, tmp);
2248
2249         tmp = RREG32(mmDB_DEBUG3) & ~0x0002021c;
2250         tmp |= 0x00020200;
2251         WREG32(mmDB_DEBUG3, tmp);
2252
2253         tmp = RREG32(mmCB_HW_CONTROL) & ~0x00010000;
2254         tmp |= 0x00018208;
2255         WREG32(mmCB_HW_CONTROL, tmp);
2256
2257         WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
2258
2259         WREG32(mmPA_SC_FIFO_SIZE,
2260                 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
2261                 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
2262                 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
2263                 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
2264
2265         WREG32(mmVGT_NUM_INSTANCES, 1);
2266
2267         WREG32(mmCP_PERFMON_CNTL, 0);
2268
2269         WREG32(mmSQ_CONFIG, 0);
2270
2271         WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS,
2272                 ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
2273                 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
2274
2275         WREG32(mmVGT_CACHE_INVALIDATION,
2276                 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
2277                 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
2278
2279         WREG32(mmVGT_GS_VERTEX_REUSE, 16);
2280         WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
2281
2282         WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
2283                         (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
2284         WREG32(mmPA_SC_ENHANCE, PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK);
2285         mutex_unlock(&adev->grbm_idx_mutex);
2286
2287         udelay(50);
2288 }
2289
2290 /*
2291  * GPU scratch registers helpers function.
2292  */
2293 /**
2294  * gfx_v7_0_scratch_init - setup driver info for CP scratch regs
2295  *
2296  * @adev: amdgpu_device pointer
2297  *
2298  * Set up the number and offset of the CP scratch registers.
2299  * NOTE: use of CP scratch registers is a legacy inferface and
2300  * is not used by default on newer asics (r6xx+).  On newer asics,
2301  * memory buffers are used for fences rather than scratch regs.
2302  */
2303 static void gfx_v7_0_scratch_init(struct amdgpu_device *adev)
2304 {
2305         int i;
2306
2307         adev->gfx.scratch.num_reg = 7;
2308         adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
2309         for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
2310                 adev->gfx.scratch.free[i] = true;
2311                 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
2312         }
2313 }
2314
2315 /**
2316  * gfx_v7_0_ring_test_ring - basic gfx ring test
2317  *
2318  * @adev: amdgpu_device pointer
2319  * @ring: amdgpu_ring structure holding ring information
2320  *
2321  * Allocate a scratch register and write to it using the gfx ring (CIK).
2322  * Provides a basic gfx ring test to verify that the ring is working.
2323  * Used by gfx_v7_0_cp_gfx_resume();
2324  * Returns 0 on success, error on failure.
2325  */
2326 static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring)
2327 {
2328         struct amdgpu_device *adev = ring->adev;
2329         uint32_t scratch;
2330         uint32_t tmp = 0;
2331         unsigned i;
2332         int r;
2333
2334         r = amdgpu_gfx_scratch_get(adev, &scratch);
2335         if (r) {
2336                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
2337                 return r;
2338         }
2339         WREG32(scratch, 0xCAFEDEAD);
2340         r = amdgpu_ring_lock(ring, 3);
2341         if (r) {
2342                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
2343                 amdgpu_gfx_scratch_free(adev, scratch);
2344                 return r;
2345         }
2346         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2347         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2348         amdgpu_ring_write(ring, 0xDEADBEEF);
2349         amdgpu_ring_unlock_commit(ring);
2350
2351         for (i = 0; i < adev->usec_timeout; i++) {
2352                 tmp = RREG32(scratch);
2353                 if (tmp == 0xDEADBEEF)
2354                         break;
2355                 DRM_UDELAY(1);
2356         }
2357         if (i < adev->usec_timeout) {
2358                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2359         } else {
2360                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
2361                           ring->idx, scratch, tmp);
2362                 r = -EINVAL;
2363         }
2364         amdgpu_gfx_scratch_free(adev, scratch);
2365         return r;
2366 }
2367
2368 /**
2369  * gfx_v7_0_ring_emit_hdp - emit an hdp flush on the cp
2370  *
2371  * @adev: amdgpu_device pointer
2372  * @ridx: amdgpu ring index
2373  *
2374  * Emits an hdp flush on the cp.
2375  */
2376 static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
2377 {
2378         u32 ref_and_mask;
2379
2380         if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
2381                 switch (ring->me) {
2382                 case 1:
2383                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
2384                         break;
2385                 case 2:
2386                         ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
2387                         break;
2388                 default:
2389                         return;
2390                 }
2391         } else {
2392                 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
2393         }
2394
2395         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2396         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
2397                                  WAIT_REG_MEM_FUNCTION(3) |  /* == */
2398                                  WAIT_REG_MEM_ENGINE(1)));   /* pfp */
2399         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
2400         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
2401         amdgpu_ring_write(ring, ref_and_mask);
2402         amdgpu_ring_write(ring, ref_and_mask);
2403         amdgpu_ring_write(ring, 0x20); /* poll interval */
2404 }
2405
2406 /**
2407  * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2408  *
2409  * @adev: amdgpu_device pointer
2410  * @fence: amdgpu fence object
2411  *
2412  * Emits a fence sequnce number on the gfx ring and flushes
2413  * GPU caches.
2414  */
2415 static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
2416                                          u64 seq, bool write64bit)
2417 {
2418         /* Workaround for cache flush problems. First send a dummy EOP
2419          * event down the pipe with seq one below.
2420          */
2421         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2422         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2423                                  EOP_TC_ACTION_EN |
2424                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2425                                  EVENT_INDEX(5)));
2426         amdgpu_ring_write(ring, addr & 0xfffffffc);
2427         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2428                                 DATA_SEL(1) | INT_SEL(0));
2429         amdgpu_ring_write(ring, lower_32_bits(seq - 1));
2430         amdgpu_ring_write(ring, upper_32_bits(seq - 1));
2431
2432         /* Then send the real EOP event down the pipe. */
2433         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2434         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2435                                  EOP_TC_ACTION_EN |
2436                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2437                                  EVENT_INDEX(5)));
2438         amdgpu_ring_write(ring, addr & 0xfffffffc);
2439         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
2440                                 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(2));
2441         amdgpu_ring_write(ring, lower_32_bits(seq));
2442         amdgpu_ring_write(ring, upper_32_bits(seq));
2443 }
2444
2445 /**
2446  * gfx_v7_0_ring_emit_fence_compute - emit a fence on the compute ring
2447  *
2448  * @adev: amdgpu_device pointer
2449  * @fence: amdgpu fence object
2450  *
2451  * Emits a fence sequnce number on the compute ring and flushes
2452  * GPU caches.
2453  */
2454 static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
2455                                              u64 addr, u64 seq,
2456                                              bool write64bits)
2457 {
2458         /* RELEASE_MEM - flush caches, send int */
2459         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2460         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
2461                                  EOP_TC_ACTION_EN |
2462                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
2463                                  EVENT_INDEX(5)));
2464         amdgpu_ring_write(ring, DATA_SEL(write64bits ? 2 : 1) | INT_SEL(2));
2465         amdgpu_ring_write(ring, addr & 0xfffffffc);
2466         amdgpu_ring_write(ring, upper_32_bits(addr));
2467         amdgpu_ring_write(ring, lower_32_bits(seq));
2468         amdgpu_ring_write(ring, upper_32_bits(seq));
2469 }
2470
2471 /**
2472  * gfx_v7_0_ring_emit_semaphore - emit a semaphore on the CP ring
2473  *
2474  * @ring: amdgpu ring buffer object
2475  * @semaphore: amdgpu semaphore object
2476  * @emit_wait: Is this a sempahore wait?
2477  *
2478  * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
2479  * from running ahead of semaphore waits.
2480  */
2481 static bool gfx_v7_0_ring_emit_semaphore(struct amdgpu_ring *ring,
2482                                          struct amdgpu_semaphore *semaphore,
2483                                          bool emit_wait)
2484 {
2485         uint64_t addr = semaphore->gpu_addr;
2486         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2487
2488         amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2489         amdgpu_ring_write(ring, addr & 0xffffffff);
2490         amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
2491
2492         if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
2493                 /* Prevent the PFP from running ahead of the semaphore wait */
2494                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2495                 amdgpu_ring_write(ring, 0x0);
2496         }
2497
2498         return true;
2499 }
2500
2501 /*
2502  * IB stuff
2503  */
2504 /**
2505  * gfx_v7_0_ring_emit_ib - emit an IB (Indirect Buffer) on the ring
2506  *
2507  * @ring: amdgpu_ring structure holding ring information
2508  * @ib: amdgpu indirect buffer object
2509  *
2510  * Emits an DE (drawing engine) or CE (constant engine) IB
2511  * on the gfx ring.  IBs are usually generated by userspace
2512  * acceleration drivers and submitted to the kernel for
2513  * sheduling on the ring.  This function schedules the IB
2514  * on the gfx ring for execution by the GPU.
2515  */
2516 static void gfx_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
2517                                   struct amdgpu_ib *ib)
2518 {
2519         bool need_ctx_switch = ring->current_ctx != ib->ctx;
2520         u32 header, control = 0;
2521         u32 next_rptr = ring->wptr + 5;
2522
2523         /* drop the CE preamble IB for the same context */
2524         if ((ring->type == AMDGPU_RING_TYPE_GFX) &&
2525             (ib->flags & AMDGPU_IB_FLAG_PREAMBLE) &&
2526             !need_ctx_switch)
2527                 return;
2528
2529         if (ring->type == AMDGPU_RING_TYPE_COMPUTE)
2530                 control |= INDIRECT_BUFFER_VALID;
2531
2532         if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX)
2533                 next_rptr += 2;
2534
2535         next_rptr += 4;
2536         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2537         amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
2538         amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2539         amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2540         amdgpu_ring_write(ring, next_rptr);
2541
2542         /* insert SWITCH_BUFFER packet before first IB in the ring frame */
2543         if (need_ctx_switch && ring->type == AMDGPU_RING_TYPE_GFX) {
2544                 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2545                 amdgpu_ring_write(ring, 0);
2546         }
2547
2548         if (ib->flags & AMDGPU_IB_FLAG_CE)
2549                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2550         else
2551                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
2552
2553         control |= ib->length_dw |
2554                 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
2555
2556         amdgpu_ring_write(ring, header);
2557         amdgpu_ring_write(ring,
2558 #ifdef __BIG_ENDIAN
2559                           (2 << 0) |
2560 #endif
2561                           (ib->gpu_addr & 0xFFFFFFFC));
2562         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
2563         amdgpu_ring_write(ring, control);
2564 }
2565
2566 /**
2567  * gfx_v7_0_ring_test_ib - basic ring IB test
2568  *
2569  * @ring: amdgpu_ring structure holding ring information
2570  *
2571  * Allocate an IB and execute it on the gfx ring (CIK).
2572  * Provides a basic gfx ring test to verify that IBs are working.
2573  * Returns 0 on success, error on failure.
2574  */
2575 static int gfx_v7_0_ring_test_ib(struct amdgpu_ring *ring)
2576 {
2577         struct amdgpu_device *adev = ring->adev;
2578         struct amdgpu_ib ib;
2579         uint32_t scratch;
2580         uint32_t tmp = 0;
2581         unsigned i;
2582         int r;
2583
2584         r = amdgpu_gfx_scratch_get(adev, &scratch);
2585         if (r) {
2586                 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
2587                 return r;
2588         }
2589         WREG32(scratch, 0xCAFEDEAD);
2590         r = amdgpu_ib_get(ring, NULL, 256, &ib);
2591         if (r) {
2592                 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
2593                 amdgpu_gfx_scratch_free(adev, scratch);
2594                 return r;
2595         }
2596         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
2597         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
2598         ib.ptr[2] = 0xDEADBEEF;
2599         ib.length_dw = 3;
2600         r = amdgpu_ib_schedule(adev, 1, &ib, AMDGPU_FENCE_OWNER_UNDEFINED);
2601         if (r) {
2602                 amdgpu_gfx_scratch_free(adev, scratch);
2603                 amdgpu_ib_free(adev, &ib);
2604                 DRM_ERROR("amdgpu: failed to schedule ib (%d).\n", r);
2605                 return r;
2606         }
2607         r = amdgpu_fence_wait(ib.fence, false);
2608         if (r) {
2609                 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
2610                 amdgpu_gfx_scratch_free(adev, scratch);
2611                 amdgpu_ib_free(adev, &ib);
2612                 return r;
2613         }
2614         for (i = 0; i < adev->usec_timeout; i++) {
2615                 tmp = RREG32(scratch);
2616                 if (tmp == 0xDEADBEEF)
2617                         break;
2618                 DRM_UDELAY(1);
2619         }
2620         if (i < adev->usec_timeout) {
2621                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
2622                          ib.fence->ring->idx, i);
2623         } else {
2624                 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
2625                           scratch, tmp);
2626                 r = -EINVAL;
2627         }
2628         amdgpu_gfx_scratch_free(adev, scratch);
2629         amdgpu_ib_free(adev, &ib);
2630         return r;
2631 }
2632
2633 /*
2634  * CP.
2635  * On CIK, gfx and compute now have independant command processors.
2636  *
2637  * GFX
2638  * Gfx consists of a single ring and can process both gfx jobs and
2639  * compute jobs.  The gfx CP consists of three microengines (ME):
2640  * PFP - Pre-Fetch Parser
2641  * ME - Micro Engine
2642  * CE - Constant Engine
2643  * The PFP and ME make up what is considered the Drawing Engine (DE).
2644  * The CE is an asynchronous engine used for updating buffer desciptors
2645  * used by the DE so that they can be loaded into cache in parallel
2646  * while the DE is processing state update packets.
2647  *
2648  * Compute
2649  * The compute CP consists of two microengines (ME):
2650  * MEC1 - Compute MicroEngine 1
2651  * MEC2 - Compute MicroEngine 2
2652  * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
2653  * The queues are exposed to userspace and are programmed directly
2654  * by the compute runtime.
2655  */
2656 /**
2657  * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2658  *
2659  * @adev: amdgpu_device pointer
2660  * @enable: enable or disable the MEs
2661  *
2662  * Halts or unhalts the gfx MEs.
2663  */
2664 static void gfx_v7_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2665 {
2666         int i;
2667
2668         if (enable) {
2669                 WREG32(mmCP_ME_CNTL, 0);
2670         } else {
2671                 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK));
2672                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2673                         adev->gfx.gfx_ring[i].ready = false;
2674         }
2675         udelay(50);
2676 }
2677
2678 /**
2679  * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2680  *
2681  * @adev: amdgpu_device pointer
2682  *
2683  * Loads the gfx PFP, ME, and CE ucode.
2684  * Returns 0 for success, -EINVAL if the ucode is not available.
2685  */
2686 static int gfx_v7_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2687 {
2688         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2689         const struct gfx_firmware_header_v1_0 *ce_hdr;
2690         const struct gfx_firmware_header_v1_0 *me_hdr;
2691         const __le32 *fw_data;
2692         unsigned i, fw_size;
2693
2694         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2695                 return -EINVAL;
2696
2697         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2698         ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2699         me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2700
2701         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2702         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2703         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2704         adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version);
2705         adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version);
2706         adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version);
2707
2708         gfx_v7_0_cp_gfx_enable(adev, false);
2709
2710         /* PFP */
2711         fw_data = (const __le32 *)
2712                 (adev->gfx.pfp_fw->data +
2713                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2714         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2715         WREG32(mmCP_PFP_UCODE_ADDR, 0);
2716         for (i = 0; i < fw_size; i++)
2717                 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2718         WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2719
2720         /* CE */
2721         fw_data = (const __le32 *)
2722                 (adev->gfx.ce_fw->data +
2723                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2724         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2725         WREG32(mmCP_CE_UCODE_ADDR, 0);
2726         for (i = 0; i < fw_size; i++)
2727                 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2728         WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2729
2730         /* ME */
2731         fw_data = (const __le32 *)
2732                 (adev->gfx.me_fw->data +
2733                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2734         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2735         WREG32(mmCP_ME_RAM_WADDR, 0);
2736         for (i = 0; i < fw_size; i++)
2737                 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2738         WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2739
2740         return 0;
2741 }
2742
2743 /**
2744  * gfx_v7_0_cp_gfx_start - start the gfx ring
2745  *
2746  * @adev: amdgpu_device pointer
2747  *
2748  * Enables the ring and loads the clear state context and other
2749  * packets required to init the ring.
2750  * Returns 0 for success, error for failure.
2751  */
2752 static int gfx_v7_0_cp_gfx_start(struct amdgpu_device *adev)
2753 {
2754         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2755         const struct cs_section_def *sect = NULL;
2756         const struct cs_extent_def *ext = NULL;
2757         int r, i;
2758
2759         /* init the CP */
2760         WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2761         WREG32(mmCP_ENDIAN_SWAP, 0);
2762         WREG32(mmCP_DEVICE_ID, 1);
2763
2764         gfx_v7_0_cp_gfx_enable(adev, true);
2765
2766         r = amdgpu_ring_lock(ring, gfx_v7_0_get_csb_size(adev) + 8);
2767         if (r) {
2768                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2769                 return r;
2770         }
2771
2772         /* init the CE partitions.  CE only used for gfx on CIK */
2773         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2774         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2775         amdgpu_ring_write(ring, 0x8000);
2776         amdgpu_ring_write(ring, 0x8000);
2777
2778         /* clear state buffer */
2779         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2780         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2781
2782         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2783         amdgpu_ring_write(ring, 0x80000000);
2784         amdgpu_ring_write(ring, 0x80000000);
2785
2786         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2787                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2788                         if (sect->id == SECT_CONTEXT) {
2789                                 amdgpu_ring_write(ring,
2790                                                   PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2791                                 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2792                                 for (i = 0; i < ext->reg_count; i++)
2793                                         amdgpu_ring_write(ring, ext->extent[i]);
2794                         }
2795                 }
2796         }
2797
2798         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2799         amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2800         switch (adev->asic_type) {
2801         case CHIP_BONAIRE:
2802                 amdgpu_ring_write(ring, 0x16000012);
2803                 amdgpu_ring_write(ring, 0x00000000);
2804                 break;
2805         case CHIP_KAVERI:
2806                 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2807                 amdgpu_ring_write(ring, 0x00000000);
2808                 break;
2809         case CHIP_KABINI:
2810         case CHIP_MULLINS:
2811                 amdgpu_ring_write(ring, 0x00000000); /* XXX */
2812                 amdgpu_ring_write(ring, 0x00000000);
2813                 break;
2814         case CHIP_HAWAII:
2815                 amdgpu_ring_write(ring, 0x3a00161a);
2816                 amdgpu_ring_write(ring, 0x0000002e);
2817                 break;
2818         default:
2819                 amdgpu_ring_write(ring, 0x00000000);
2820                 amdgpu_ring_write(ring, 0x00000000);
2821                 break;
2822         }
2823
2824         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2825         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2826
2827         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2828         amdgpu_ring_write(ring, 0);
2829
2830         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2831         amdgpu_ring_write(ring, 0x00000316);
2832         amdgpu_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
2833         amdgpu_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
2834
2835         amdgpu_ring_unlock_commit(ring);
2836
2837         return 0;
2838 }
2839
2840 /**
2841  * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2842  *
2843  * @adev: amdgpu_device pointer
2844  *
2845  * Program the location and size of the gfx ring buffer
2846  * and test it to make sure it's working.
2847  * Returns 0 for success, error for failure.
2848  */
2849 static int gfx_v7_0_cp_gfx_resume(struct amdgpu_device *adev)
2850 {
2851         struct amdgpu_ring *ring;
2852         u32 tmp;
2853         u32 rb_bufsz;
2854         u64 rb_addr, rptr_addr;
2855         int r;
2856
2857         WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2858         if (adev->asic_type != CHIP_HAWAII)
2859                 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2860
2861         /* Set the write pointer delay */
2862         WREG32(mmCP_RB_WPTR_DELAY, 0);
2863
2864         /* set the RB to use vmid 0 */
2865         WREG32(mmCP_RB_VMID, 0);
2866
2867         WREG32(mmSCRATCH_ADDR, 0);
2868
2869         /* ring 0 - compute and gfx */
2870         /* Set ring buffer size */
2871         ring = &adev->gfx.gfx_ring[0];
2872         rb_bufsz = order_base_2(ring->ring_size / 8);
2873         tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2874 #ifdef __BIG_ENDIAN
2875         tmp |= BUF_SWAP_32BIT;
2876 #endif
2877         WREG32(mmCP_RB0_CNTL, tmp);
2878
2879         /* Initialize the ring buffer's read and write pointers */
2880         WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2881         ring->wptr = 0;
2882         WREG32(mmCP_RB0_WPTR, ring->wptr);
2883
2884         /* set the wb address wether it's enabled or not */
2885         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2886         WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2887         WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2888
2889         /* scratch register shadowing is no longer supported */
2890         WREG32(mmSCRATCH_UMSK, 0);
2891
2892         mdelay(1);
2893         WREG32(mmCP_RB0_CNTL, tmp);
2894
2895         rb_addr = ring->gpu_addr >> 8;
2896         WREG32(mmCP_RB0_BASE, rb_addr);
2897         WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2898
2899         /* start the ring */
2900         gfx_v7_0_cp_gfx_start(adev);
2901         ring->ready = true;
2902         r = amdgpu_ring_test_ring(ring);
2903         if (r) {
2904                 ring->ready = false;
2905                 return r;
2906         }
2907
2908         return 0;
2909 }
2910
2911 static u32 gfx_v7_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
2912 {
2913         u32 rptr;
2914
2915         rptr = ring->adev->wb.wb[ring->rptr_offs];
2916
2917         return rptr;
2918 }
2919
2920 static u32 gfx_v7_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
2921 {
2922         struct amdgpu_device *adev = ring->adev;
2923         u32 wptr;
2924
2925         wptr = RREG32(mmCP_RB0_WPTR);
2926
2927         return wptr;
2928 }
2929
2930 static void gfx_v7_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2931 {
2932         struct amdgpu_device *adev = ring->adev;
2933
2934         WREG32(mmCP_RB0_WPTR, ring->wptr);
2935         (void)RREG32(mmCP_RB0_WPTR);
2936 }
2937
2938 static u32 gfx_v7_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
2939 {
2940         u32 rptr;
2941
2942         rptr = ring->adev->wb.wb[ring->rptr_offs];
2943
2944         return rptr;
2945 }
2946
2947 static u32 gfx_v7_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
2948 {
2949         u32 wptr;
2950
2951         /* XXX check if swapping is necessary on BE */
2952         wptr = ring->adev->wb.wb[ring->wptr_offs];
2953
2954         return wptr;
2955 }
2956
2957 static void gfx_v7_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2958 {
2959         struct amdgpu_device *adev = ring->adev;
2960
2961         /* XXX check if swapping is necessary on BE */
2962         adev->wb.wb[ring->wptr_offs] = ring->wptr;
2963         WDOORBELL32(ring->doorbell_index, ring->wptr);
2964 }
2965
2966 /**
2967  * gfx_v7_0_cp_compute_enable - enable/disable the compute CP MEs
2968  *
2969  * @adev: amdgpu_device pointer
2970  * @enable: enable or disable the MEs
2971  *
2972  * Halts or unhalts the compute MEs.
2973  */
2974 static void gfx_v7_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2975 {
2976         int i;
2977
2978         if (enable) {
2979                 WREG32(mmCP_MEC_CNTL, 0);
2980         } else {
2981                 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2982                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2983                         adev->gfx.compute_ring[i].ready = false;
2984         }
2985         udelay(50);
2986 }
2987
2988 /**
2989  * gfx_v7_0_cp_compute_load_microcode - load the compute CP ME ucode
2990  *
2991  * @adev: amdgpu_device pointer
2992  *
2993  * Loads the compute MEC1&2 ucode.
2994  * Returns 0 for success, -EINVAL if the ucode is not available.
2995  */
2996 static int gfx_v7_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2997 {
2998         const struct gfx_firmware_header_v1_0 *mec_hdr;
2999         const __le32 *fw_data;
3000         unsigned i, fw_size;
3001
3002         if (!adev->gfx.mec_fw)
3003                 return -EINVAL;
3004
3005         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3006         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3007         adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version);
3008
3009         gfx_v7_0_cp_compute_enable(adev, false);
3010
3011         /* MEC1 */
3012         fw_data = (const __le32 *)
3013                 (adev->gfx.mec_fw->data +
3014                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
3015         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
3016         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
3017         for (i = 0; i < fw_size; i++)
3018                 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++));
3019         WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
3020
3021         if (adev->asic_type == CHIP_KAVERI) {
3022                 const struct gfx_firmware_header_v1_0 *mec2_hdr;
3023
3024                 if (!adev->gfx.mec2_fw)
3025                         return -EINVAL;
3026
3027                 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3028                 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
3029                 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version);
3030
3031                 /* MEC2 */
3032                 fw_data = (const __le32 *)
3033                         (adev->gfx.mec2_fw->data +
3034                          le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
3035                 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
3036                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
3037                 for (i = 0; i < fw_size; i++)
3038                         WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++));
3039                 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
3040         }
3041
3042         return 0;
3043 }
3044
3045 /**
3046  * gfx_v7_0_cp_compute_start - start the compute queues
3047  *
3048  * @adev: amdgpu_device pointer
3049  *
3050  * Enable the compute queues.
3051  * Returns 0 for success, error for failure.
3052  */
3053 static int gfx_v7_0_cp_compute_start(struct amdgpu_device *adev)
3054 {
3055         gfx_v7_0_cp_compute_enable(adev, true);
3056
3057         return 0;
3058 }
3059
3060 /**
3061  * gfx_v7_0_cp_compute_fini - stop the compute queues
3062  *
3063  * @adev: amdgpu_device pointer
3064  *
3065  * Stop the compute queues and tear down the driver queue
3066  * info.
3067  */
3068 static void gfx_v7_0_cp_compute_fini(struct amdgpu_device *adev)
3069 {
3070         int i, r;
3071
3072         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3073                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3074
3075                 if (ring->mqd_obj) {
3076                         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3077                         if (unlikely(r != 0))
3078                                 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
3079
3080                         amdgpu_bo_unpin(ring->mqd_obj);
3081                         amdgpu_bo_unreserve(ring->mqd_obj);
3082
3083                         amdgpu_bo_unref(&ring->mqd_obj);
3084                         ring->mqd_obj = NULL;
3085                 }
3086         }
3087 }
3088
3089 static void gfx_v7_0_mec_fini(struct amdgpu_device *adev)
3090 {
3091         int r;
3092
3093         if (adev->gfx.mec.hpd_eop_obj) {
3094                 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
3095                 if (unlikely(r != 0))
3096                         dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
3097                 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
3098                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
3099
3100                 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
3101                 adev->gfx.mec.hpd_eop_obj = NULL;
3102         }
3103 }
3104
3105 #define MEC_HPD_SIZE 2048
3106
3107 static int gfx_v7_0_mec_init(struct amdgpu_device *adev)
3108 {
3109         int r;
3110         u32 *hpd;
3111
3112         /*
3113          * KV:    2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
3114          * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
3115          * Nonetheless, we assign only 1 pipe because all other pipes will
3116          * be handled by KFD
3117          */
3118         adev->gfx.mec.num_mec = 1;
3119         adev->gfx.mec.num_pipe = 1;
3120         adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
3121
3122         if (adev->gfx.mec.hpd_eop_obj == NULL) {
3123                 r = amdgpu_bo_create(adev,
3124                                      adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
3125                                      PAGE_SIZE, true,
3126                                      AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3127                                      &adev->gfx.mec.hpd_eop_obj);
3128                 if (r) {
3129                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
3130                         return r;
3131                 }
3132         }
3133
3134         r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
3135         if (unlikely(r != 0)) {
3136                 gfx_v7_0_mec_fini(adev);
3137                 return r;
3138         }
3139         r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
3140                           &adev->gfx.mec.hpd_eop_gpu_addr);
3141         if (r) {
3142                 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
3143                 gfx_v7_0_mec_fini(adev);
3144                 return r;
3145         }
3146         r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
3147         if (r) {
3148                 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
3149                 gfx_v7_0_mec_fini(adev);
3150                 return r;
3151         }
3152
3153         /* clear memory.  Not sure if this is required or not */
3154         memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
3155
3156         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
3157         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
3158
3159         return 0;
3160 }
3161
3162 struct hqd_registers
3163 {
3164         u32 cp_mqd_base_addr;
3165         u32 cp_mqd_base_addr_hi;
3166         u32 cp_hqd_active;
3167         u32 cp_hqd_vmid;
3168         u32 cp_hqd_persistent_state;
3169         u32 cp_hqd_pipe_priority;
3170         u32 cp_hqd_queue_priority;
3171         u32 cp_hqd_quantum;
3172         u32 cp_hqd_pq_base;
3173         u32 cp_hqd_pq_base_hi;
3174         u32 cp_hqd_pq_rptr;
3175         u32 cp_hqd_pq_rptr_report_addr;
3176         u32 cp_hqd_pq_rptr_report_addr_hi;
3177         u32 cp_hqd_pq_wptr_poll_addr;
3178         u32 cp_hqd_pq_wptr_poll_addr_hi;
3179         u32 cp_hqd_pq_doorbell_control;
3180         u32 cp_hqd_pq_wptr;
3181         u32 cp_hqd_pq_control;
3182         u32 cp_hqd_ib_base_addr;
3183         u32 cp_hqd_ib_base_addr_hi;
3184         u32 cp_hqd_ib_rptr;
3185         u32 cp_hqd_ib_control;
3186         u32 cp_hqd_iq_timer;
3187         u32 cp_hqd_iq_rptr;
3188         u32 cp_hqd_dequeue_request;
3189         u32 cp_hqd_dma_offload;
3190         u32 cp_hqd_sema_cmd;
3191         u32 cp_hqd_msg_type;
3192         u32 cp_hqd_atomic0_preop_lo;
3193         u32 cp_hqd_atomic0_preop_hi;
3194         u32 cp_hqd_atomic1_preop_lo;
3195         u32 cp_hqd_atomic1_preop_hi;
3196         u32 cp_hqd_hq_scheduler0;
3197         u32 cp_hqd_hq_scheduler1;
3198         u32 cp_mqd_control;
3199 };
3200
3201 struct bonaire_mqd
3202 {
3203         u32 header;
3204         u32 dispatch_initiator;
3205         u32 dimensions[3];
3206         u32 start_idx[3];
3207         u32 num_threads[3];
3208         u32 pipeline_stat_enable;
3209         u32 perf_counter_enable;
3210         u32 pgm[2];
3211         u32 tba[2];
3212         u32 tma[2];
3213         u32 pgm_rsrc[2];
3214         u32 vmid;
3215         u32 resource_limits;
3216         u32 static_thread_mgmt01[2];
3217         u32 tmp_ring_size;
3218         u32 static_thread_mgmt23[2];
3219         u32 restart[3];
3220         u32 thread_trace_enable;
3221         u32 reserved1;
3222         u32 user_data[16];
3223         u32 vgtcs_invoke_count[2];
3224         struct hqd_registers queue_state;
3225         u32 dequeue_cntr;
3226         u32 interrupt_queue[64];
3227 };
3228
3229 /**
3230  * gfx_v7_0_cp_compute_resume - setup the compute queue registers
3231  *
3232  * @adev: amdgpu_device pointer
3233  *
3234  * Program the compute queues and test them to make sure they
3235  * are working.
3236  * Returns 0 for success, error for failure.
3237  */
3238 static int gfx_v7_0_cp_compute_resume(struct amdgpu_device *adev)
3239 {
3240         int r, i, j;
3241         u32 tmp;
3242         bool use_doorbell = true;
3243         u64 hqd_gpu_addr;
3244         u64 mqd_gpu_addr;
3245         u64 eop_gpu_addr;
3246         u64 wb_gpu_addr;
3247         u32 *buf;
3248         struct bonaire_mqd *mqd;
3249
3250         r = gfx_v7_0_cp_compute_start(adev);
3251         if (r)
3252                 return r;
3253
3254         /* fix up chicken bits */
3255         tmp = RREG32(mmCP_CPF_DEBUG);
3256         tmp |= (1 << 23);
3257         WREG32(mmCP_CPF_DEBUG, tmp);
3258
3259         /* init the pipes */
3260         mutex_lock(&adev->srbm_mutex);
3261         for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
3262                 int me = (i < 4) ? 1 : 2;
3263                 int pipe = (i < 4) ? i : (i - 4);
3264
3265                 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2);
3266
3267                 cik_srbm_select(adev, me, pipe, 0, 0);
3268
3269                 /* write the EOP addr */
3270                 WREG32(mmCP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
3271                 WREG32(mmCP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
3272
3273                 /* set the VMID assigned */
3274                 WREG32(mmCP_HPD_EOP_VMID, 0);
3275
3276                 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3277                 tmp = RREG32(mmCP_HPD_EOP_CONTROL);
3278                 tmp &= ~CP_HPD_EOP_CONTROL__EOP_SIZE_MASK;
3279                 tmp |= order_base_2(MEC_HPD_SIZE / 8);
3280                 WREG32(mmCP_HPD_EOP_CONTROL, tmp);
3281         }
3282         cik_srbm_select(adev, 0, 0, 0, 0);
3283         mutex_unlock(&adev->srbm_mutex);
3284
3285         /* init the queues.  Just two for now. */
3286         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3287                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3288
3289                 if (ring->mqd_obj == NULL) {
3290                         r = amdgpu_bo_create(adev,
3291                                              sizeof(struct bonaire_mqd),
3292                                              PAGE_SIZE, true,
3293                                              AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3294                                              &ring->mqd_obj);
3295                         if (r) {
3296                                 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3297                                 return r;
3298                         }
3299                 }
3300
3301                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3302                 if (unlikely(r != 0)) {
3303                         gfx_v7_0_cp_compute_fini(adev);
3304                         return r;
3305                 }
3306                 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3307                                   &mqd_gpu_addr);
3308                 if (r) {
3309                         dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3310                         gfx_v7_0_cp_compute_fini(adev);
3311                         return r;
3312                 }
3313                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3314                 if (r) {
3315                         dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3316                         gfx_v7_0_cp_compute_fini(adev);
3317                         return r;
3318                 }
3319
3320                 /* init the mqd struct */
3321                 memset(buf, 0, sizeof(struct bonaire_mqd));
3322
3323                 mqd = (struct bonaire_mqd *)buf;
3324                 mqd->header = 0xC0310800;
3325                 mqd->static_thread_mgmt01[0] = 0xffffffff;
3326                 mqd->static_thread_mgmt01[1] = 0xffffffff;
3327                 mqd->static_thread_mgmt23[0] = 0xffffffff;
3328                 mqd->static_thread_mgmt23[1] = 0xffffffff;
3329
3330                 mutex_lock(&adev->srbm_mutex);
3331                 cik_srbm_select(adev, ring->me,
3332                                 ring->pipe,
3333                                 ring->queue, 0);
3334
3335                 /* disable wptr polling */
3336                 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3337                 tmp &= ~CP_PQ_WPTR_POLL_CNTL__EN_MASK;
3338                 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3339
3340                 /* enable doorbell? */
3341                 mqd->queue_state.cp_hqd_pq_doorbell_control =
3342                         RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3343                 if (use_doorbell)
3344                         mqd->queue_state.cp_hqd_pq_doorbell_control |= CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3345                 else
3346                         mqd->queue_state.cp_hqd_pq_doorbell_control &= ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3347                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3348                        mqd->queue_state.cp_hqd_pq_doorbell_control);
3349
3350                 /* disable the queue if it's active */
3351                 mqd->queue_state.cp_hqd_dequeue_request = 0;
3352                 mqd->queue_state.cp_hqd_pq_rptr = 0;
3353                 mqd->queue_state.cp_hqd_pq_wptr= 0;
3354                 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3355                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3356                         for (j = 0; j < adev->usec_timeout; j++) {
3357                                 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3358                                         break;
3359                                 udelay(1);
3360                         }
3361                         WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
3362                         WREG32(mmCP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
3363                         WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
3364                 }
3365
3366                 /* set the pointer to the MQD */
3367                 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
3368                 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3369                 WREG32(mmCP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
3370                 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
3371                 /* set MQD vmid to 0 */
3372                 mqd->queue_state.cp_mqd_control = RREG32(mmCP_MQD_CONTROL);
3373                 mqd->queue_state.cp_mqd_control &= ~CP_MQD_CONTROL__VMID_MASK;
3374                 WREG32(mmCP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
3375
3376                 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3377                 hqd_gpu_addr = ring->gpu_addr >> 8;
3378                 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
3379                 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3380                 WREG32(mmCP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
3381                 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
3382
3383                 /* set up the HQD, this is similar to CP_RB0_CNTL */
3384                 mqd->queue_state.cp_hqd_pq_control = RREG32(mmCP_HQD_PQ_CONTROL);
3385                 mqd->queue_state.cp_hqd_pq_control &=
3386                         ~(CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK |
3387                                         CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK);
3388
3389                 mqd->queue_state.cp_hqd_pq_control |=
3390                         order_base_2(ring->ring_size / 8);
3391                 mqd->queue_state.cp_hqd_pq_control |=
3392                         (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8);
3393 #ifdef __BIG_ENDIAN
3394                 mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT;
3395 #endif
3396                 mqd->queue_state.cp_hqd_pq_control &=
3397                         ~(CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK |
3398                                 CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK |
3399                                 CP_HQD_PQ_CONTROL__PQ_VOLATILE_MASK);
3400                 mqd->queue_state.cp_hqd_pq_control |=
3401                         CP_HQD_PQ_CONTROL__PRIV_STATE_MASK |
3402                         CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK; /* assuming kernel queue control */
3403                 WREG32(mmCP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
3404
3405                 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3406                 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3407                 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3408                 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3409                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
3410                 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3411                        mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
3412
3413                 /* set the wb address wether it's enabled or not */
3414                 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3415                 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
3416                 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
3417                         upper_32_bits(wb_gpu_addr) & 0xffff;
3418                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3419                        mqd->queue_state.cp_hqd_pq_rptr_report_addr);
3420                 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3421                        mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
3422
3423                 /* enable the doorbell if requested */
3424                 if (use_doorbell) {
3425                         mqd->queue_state.cp_hqd_pq_doorbell_control =
3426                                 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3427                         mqd->queue_state.cp_hqd_pq_doorbell_control &=
3428                                 ~CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK;
3429                         mqd->queue_state.cp_hqd_pq_doorbell_control |=
3430                                 (ring->doorbell_index <<
3431                                  CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT);
3432                         mqd->queue_state.cp_hqd_pq_doorbell_control |=
3433                                 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK;
3434                         mqd->queue_state.cp_hqd_pq_doorbell_control &=
3435                                 ~(CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK |
3436                                 CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK);
3437
3438                 } else {
3439                         mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
3440                 }
3441                 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3442                        mqd->queue_state.cp_hqd_pq_doorbell_control);
3443
3444                 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3445                 ring->wptr = 0;
3446                 mqd->queue_state.cp_hqd_pq_wptr = ring->wptr;
3447                 WREG32(mmCP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
3448                 mqd->queue_state.cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3449
3450                 /* set the vmid for the queue */
3451                 mqd->queue_state.cp_hqd_vmid = 0;
3452                 WREG32(mmCP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
3453
3454                 /* activate the queue */
3455                 mqd->queue_state.cp_hqd_active = 1;
3456                 WREG32(mmCP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
3457
3458                 cik_srbm_select(adev, 0, 0, 0, 0);
3459                 mutex_unlock(&adev->srbm_mutex);
3460
3461                 amdgpu_bo_kunmap(ring->mqd_obj);
3462                 amdgpu_bo_unreserve(ring->mqd_obj);
3463
3464                 ring->ready = true;
3465                 r = amdgpu_ring_test_ring(ring);
3466                 if (r)
3467                         ring->ready = false;
3468         }
3469
3470         return 0;
3471 }
3472
3473 static void gfx_v7_0_cp_enable(struct amdgpu_device *adev, bool enable)
3474 {
3475         gfx_v7_0_cp_gfx_enable(adev, enable);
3476         gfx_v7_0_cp_compute_enable(adev, enable);
3477 }
3478
3479 static int gfx_v7_0_cp_load_microcode(struct amdgpu_device *adev)
3480 {
3481         int r;
3482
3483         r = gfx_v7_0_cp_gfx_load_microcode(adev);
3484         if (r)
3485                 return r;
3486         r = gfx_v7_0_cp_compute_load_microcode(adev);
3487         if (r)
3488                 return r;
3489
3490         return 0;
3491 }
3492
3493 static void gfx_v7_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
3494                                                bool enable)
3495 {
3496         u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
3497
3498         if (enable)
3499                 tmp |= (CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3500                                 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3501         else
3502                 tmp &= ~(CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK |
3503                                 CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK);
3504         WREG32(mmCP_INT_CNTL_RING0, tmp);
3505 }
3506
3507 static int gfx_v7_0_cp_resume(struct amdgpu_device *adev)
3508 {
3509         int r;
3510
3511         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3512
3513         r = gfx_v7_0_cp_load_microcode(adev);
3514         if (r)
3515                 return r;
3516
3517         r = gfx_v7_0_cp_gfx_resume(adev);
3518         if (r)
3519                 return r;
3520         r = gfx_v7_0_cp_compute_resume(adev);
3521         if (r)
3522                 return r;
3523
3524         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3525
3526         return 0;
3527 }
3528
3529 static void gfx_v7_0_ce_sync_me(struct amdgpu_ring *ring)
3530 {
3531         struct amdgpu_device *adev = ring->adev;
3532         u64 gpu_addr = adev->wb.gpu_addr + adev->gfx.ce_sync_offs * 4;
3533
3534         /* instruct DE to set a magic number */
3535         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3536         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3537                                                          WRITE_DATA_DST_SEL(5)));
3538         amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
3539         amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
3540         amdgpu_ring_write(ring, 1);
3541
3542         /* let CE wait till condition satisfied */
3543         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3544         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3545                                                          WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
3546                                                          WAIT_REG_MEM_FUNCTION(3) |  /* == */
3547                                                          WAIT_REG_MEM_ENGINE(2)));   /* ce */
3548         amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
3549         amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
3550         amdgpu_ring_write(ring, 1);
3551         amdgpu_ring_write(ring, 0xffffffff);
3552         amdgpu_ring_write(ring, 4); /* poll interval */
3553
3554         /* instruct CE to reset wb of ce_sync to zero */
3555         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3556         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
3557                                                          WRITE_DATA_DST_SEL(5) |
3558                                                          WR_CONFIRM));
3559         amdgpu_ring_write(ring, gpu_addr & 0xfffffffc);
3560         amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xffffffff);
3561         amdgpu_ring_write(ring, 0);
3562 }
3563
3564 /*
3565  * vm
3566  * VMID 0 is the physical GPU addresses as used by the kernel.
3567  * VMIDs 1-15 are used for userspace clients and are handled
3568  * by the amdgpu vm/hsa code.
3569  */
3570 /**
3571  * gfx_v7_0_ring_emit_vm_flush - cik vm flush using the CP
3572  *
3573  * @adev: amdgpu_device pointer
3574  *
3575  * Update the page table base and flush the VM TLB
3576  * using the CP (CIK).
3577  */
3578 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
3579                                         unsigned vm_id, uint64_t pd_addr)
3580 {
3581         int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
3582
3583         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3584         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
3585                                  WRITE_DATA_DST_SEL(0)));
3586         if (vm_id < 8) {
3587                 amdgpu_ring_write(ring,
3588                                   (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
3589         } else {
3590                 amdgpu_ring_write(ring,
3591                                   (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
3592         }
3593         amdgpu_ring_write(ring, 0);
3594         amdgpu_ring_write(ring, pd_addr >> 12);
3595
3596         /* update SH_MEM_* regs */
3597         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3598         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3599                                  WRITE_DATA_DST_SEL(0)));
3600         amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
3601         amdgpu_ring_write(ring, 0);
3602         amdgpu_ring_write(ring, VMID(vm_id));
3603
3604         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));
3605         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3606                                  WRITE_DATA_DST_SEL(0)));
3607         amdgpu_ring_write(ring, mmSH_MEM_BASES);
3608         amdgpu_ring_write(ring, 0);
3609
3610         amdgpu_ring_write(ring, 0); /* SH_MEM_BASES */
3611         amdgpu_ring_write(ring, 0); /* SH_MEM_CONFIG */
3612         amdgpu_ring_write(ring, 1); /* SH_MEM_APE1_BASE */
3613         amdgpu_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */
3614
3615         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3616         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3617                                  WRITE_DATA_DST_SEL(0)));
3618         amdgpu_ring_write(ring, mmSRBM_GFX_CNTL);
3619         amdgpu_ring_write(ring, 0);
3620         amdgpu_ring_write(ring, VMID(0));
3621
3622
3623         /* bits 0-15 are the VM contexts0-15 */
3624         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3625         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3626                                  WRITE_DATA_DST_SEL(0)));
3627         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3628         amdgpu_ring_write(ring, 0);
3629         amdgpu_ring_write(ring, 1 << vm_id);
3630
3631         /* wait for the invalidate to complete */
3632         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3633         amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
3634                                  WAIT_REG_MEM_FUNCTION(0) |  /* always */
3635                                  WAIT_REG_MEM_ENGINE(0))); /* me */
3636         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
3637         amdgpu_ring_write(ring, 0);
3638         amdgpu_ring_write(ring, 0); /* ref */
3639         amdgpu_ring_write(ring, 0); /* mask */
3640         amdgpu_ring_write(ring, 0x20); /* poll interval */
3641
3642         /* compute doesn't have PFP */
3643         if (usepfp) {
3644                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
3645                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3646                 amdgpu_ring_write(ring, 0x0);
3647
3648                 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
3649                 gfx_v7_0_ce_sync_me(ring);
3650         }
3651 }
3652
3653 /*
3654  * RLC
3655  * The RLC is a multi-purpose microengine that handles a
3656  * variety of functions.
3657  */
3658 static void gfx_v7_0_rlc_fini(struct amdgpu_device *adev)
3659 {
3660         int r;
3661
3662         /* save restore block */
3663         if (adev->gfx.rlc.save_restore_obj) {
3664                 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3665                 if (unlikely(r != 0))
3666                         dev_warn(adev->dev, "(%d) reserve RLC sr bo failed\n", r);
3667                 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj);
3668                 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3669
3670                 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj);
3671                 adev->gfx.rlc.save_restore_obj = NULL;
3672         }
3673
3674         /* clear state block */
3675         if (adev->gfx.rlc.clear_state_obj) {
3676                 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3677                 if (unlikely(r != 0))
3678                         dev_warn(adev->dev, "(%d) reserve RLC c bo failed\n", r);
3679                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
3680                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3681
3682                 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj);
3683                 adev->gfx.rlc.clear_state_obj = NULL;
3684         }
3685
3686         /* clear state block */
3687         if (adev->gfx.rlc.cp_table_obj) {
3688                 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3689                 if (unlikely(r != 0))
3690                         dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3691                 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj);
3692                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3693
3694                 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj);
3695                 adev->gfx.rlc.cp_table_obj = NULL;
3696         }
3697 }
3698
3699 static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3700 {
3701         const u32 *src_ptr;
3702         volatile u32 *dst_ptr;
3703         u32 dws, i;
3704         const struct cs_section_def *cs_data;
3705         int r;
3706
3707         /* allocate rlc buffers */
3708         if (adev->flags & AMDGPU_IS_APU) {
3709                 if (adev->asic_type == CHIP_KAVERI) {
3710                         adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3711                         adev->gfx.rlc.reg_list_size =
3712                                 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
3713                 } else {
3714                         adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;
3715                         adev->gfx.rlc.reg_list_size =
3716                                 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
3717                 }
3718         }
3719         adev->gfx.rlc.cs_data = ci_cs_data;
3720         adev->gfx.rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4;
3721
3722         src_ptr = adev->gfx.rlc.reg_list;
3723         dws = adev->gfx.rlc.reg_list_size;
3724         dws += (5 * 16) + 48 + 48 + 64;
3725
3726         cs_data = adev->gfx.rlc.cs_data;
3727
3728         if (src_ptr) {
3729                 /* save restore block */
3730                 if (adev->gfx.rlc.save_restore_obj == NULL) {
3731                         r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
3732                                              AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->gfx.rlc.save_restore_obj);
3733                         if (r) {
3734                                 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n", r);
3735                                 return r;
3736                         }
3737                 }
3738
3739                 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false);
3740                 if (unlikely(r != 0)) {
3741                         gfx_v7_0_rlc_fini(adev);
3742                         return r;
3743                 }
3744                 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM,
3745                                   &adev->gfx.rlc.save_restore_gpu_addr);
3746                 if (r) {
3747                         amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3748                         dev_warn(adev->dev, "(%d) pin RLC sr bo failed\n", r);
3749                         gfx_v7_0_rlc_fini(adev);
3750                         return r;
3751                 }
3752
3753                 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr);
3754                 if (r) {
3755                         dev_warn(adev->dev, "(%d) map RLC sr bo failed\n", r);
3756                         gfx_v7_0_rlc_fini(adev);
3757                         return r;
3758                 }
3759                 /* write the sr buffer */
3760                 dst_ptr = adev->gfx.rlc.sr_ptr;
3761                 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
3762                         dst_ptr[i] = cpu_to_le32(src_ptr[i]);
3763                 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
3764                 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
3765         }
3766
3767         if (cs_data) {
3768                 /* clear state block */
3769                 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev);
3770
3771                 if (adev->gfx.rlc.clear_state_obj == NULL) {
3772                         r = amdgpu_bo_create(adev, dws * 4, PAGE_SIZE, true,
3773                                              AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->gfx.rlc.clear_state_obj);
3774                         if (r) {
3775                                 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
3776                                 gfx_v7_0_rlc_fini(adev);
3777                                 return r;
3778                         }
3779                 }
3780                 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
3781                 if (unlikely(r != 0)) {
3782                         gfx_v7_0_rlc_fini(adev);
3783                         return r;
3784                 }
3785                 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM,
3786                                   &adev->gfx.rlc.clear_state_gpu_addr);
3787                 if (r) {
3788                         amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3789                         dev_warn(adev->dev, "(%d) pin RLC c bo failed\n", r);
3790                         gfx_v7_0_rlc_fini(adev);
3791                         return r;
3792                 }
3793
3794                 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr);
3795                 if (r) {
3796                         dev_warn(adev->dev, "(%d) map RLC c bo failed\n", r);
3797                         gfx_v7_0_rlc_fini(adev);
3798                         return r;
3799                 }
3800                 /* set up the cs buffer */
3801                 dst_ptr = adev->gfx.rlc.cs_ptr;
3802                 gfx_v7_0_get_csb_buffer(adev, dst_ptr);
3803                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
3804                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
3805         }
3806
3807         if (adev->gfx.rlc.cp_table_size) {
3808                 if (adev->gfx.rlc.cp_table_obj == NULL) {
3809                         r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true,
3810                                              AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->gfx.rlc.cp_table_obj);
3811                         if (r) {
3812                                 dev_warn(adev->dev, "(%d) create RLC cp table bo failed\n", r);
3813                                 gfx_v7_0_rlc_fini(adev);
3814                                 return r;
3815                         }
3816                 }
3817
3818                 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false);
3819                 if (unlikely(r != 0)) {
3820                         dev_warn(adev->dev, "(%d) reserve RLC cp table bo failed\n", r);
3821                         gfx_v7_0_rlc_fini(adev);
3822                         return r;
3823                 }
3824                 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM,
3825                                   &adev->gfx.rlc.cp_table_gpu_addr);
3826                 if (r) {
3827                         amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3828                         dev_warn(adev->dev, "(%d) pin RLC cp_table bo failed\n", r);
3829                         gfx_v7_0_rlc_fini(adev);
3830                         return r;
3831                 }
3832                 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr);
3833                 if (r) {
3834                         dev_warn(adev->dev, "(%d) map RLC cp table bo failed\n", r);
3835                         gfx_v7_0_rlc_fini(adev);
3836                         return r;
3837                 }
3838
3839                 gfx_v7_0_init_cp_pg_table(adev);
3840
3841                 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
3842                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
3843
3844         }
3845
3846         return 0;
3847 }
3848
3849 static void gfx_v7_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
3850 {
3851         u32 tmp;
3852
3853         tmp = RREG32(mmRLC_LB_CNTL);
3854         if (enable)
3855                 tmp |= RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3856         else
3857                 tmp &= ~RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK;
3858         WREG32(mmRLC_LB_CNTL, tmp);
3859 }
3860
3861 static void gfx_v7_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
3862 {
3863         u32 i, j, k;
3864         u32 mask;
3865
3866         mutex_lock(&adev->grbm_idx_mutex);
3867         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3868                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3869                         gfx_v7_0_select_se_sh(adev, i, j);
3870                         for (k = 0; k < adev->usec_timeout; k++) {
3871                                 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
3872                                         break;
3873                                 udelay(1);
3874                         }
3875                 }
3876         }
3877         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3878         mutex_unlock(&adev->grbm_idx_mutex);
3879
3880         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
3881                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
3882                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
3883                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
3884         for (k = 0; k < adev->usec_timeout; k++) {
3885                 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3886                         break;
3887                 udelay(1);
3888         }
3889 }
3890
3891 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
3892 {
3893         u32 tmp;
3894
3895         tmp = RREG32(mmRLC_CNTL);
3896         if (tmp != rlc)
3897                 WREG32(mmRLC_CNTL, rlc);
3898 }
3899
3900 static u32 gfx_v7_0_halt_rlc(struct amdgpu_device *adev)
3901 {
3902         u32 data, orig;
3903
3904         orig = data = RREG32(mmRLC_CNTL);
3905
3906         if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
3907                 u32 i;
3908
3909                 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
3910                 WREG32(mmRLC_CNTL, data);
3911
3912                 for (i = 0; i < adev->usec_timeout; i++) {
3913                         if ((RREG32(mmRLC_GPM_STAT) & RLC_GPM_STAT__RLC_BUSY_MASK) == 0)
3914                                 break;
3915                         udelay(1);
3916                 }
3917
3918                 gfx_v7_0_wait_for_rlc_serdes(adev);
3919         }
3920
3921         return orig;
3922 }
3923
3924 void gfx_v7_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3925 {
3926         u32 tmp, i, mask;
3927
3928         tmp = 0x1 | (1 << 1);
3929         WREG32(mmRLC_GPR_REG2, tmp);
3930
3931         mask = RLC_GPM_STAT__GFX_POWER_STATUS_MASK |
3932                 RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK;
3933         for (i = 0; i < adev->usec_timeout; i++) {
3934                 if ((RREG32(mmRLC_GPM_STAT) & mask) == mask)
3935                         break;
3936                 udelay(1);
3937         }
3938
3939         for (i = 0; i < adev->usec_timeout; i++) {
3940                 if ((RREG32(mmRLC_GPR_REG2) & 0x1) == 0)
3941                         break;
3942                 udelay(1);
3943         }
3944 }
3945
3946 void gfx_v7_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3947 {
3948         u32 tmp;
3949
3950         tmp = 0x1 | (0 << 1);
3951         WREG32(mmRLC_GPR_REG2, tmp);
3952 }
3953
3954 /**
3955  * gfx_v7_0_rlc_stop - stop the RLC ME
3956  *
3957  * @adev: amdgpu_device pointer
3958  *
3959  * Halt the RLC ME (MicroEngine) (CIK).
3960  */
3961 void gfx_v7_0_rlc_stop(struct amdgpu_device *adev)
3962 {
3963         WREG32(mmRLC_CNTL, 0);
3964
3965         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
3966
3967         gfx_v7_0_wait_for_rlc_serdes(adev);
3968 }
3969
3970 /**
3971  * gfx_v7_0_rlc_start - start the RLC ME
3972  *
3973  * @adev: amdgpu_device pointer
3974  *
3975  * Unhalt the RLC ME (MicroEngine) (CIK).
3976  */
3977 static void gfx_v7_0_rlc_start(struct amdgpu_device *adev)
3978 {
3979         WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
3980
3981         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
3982
3983         udelay(50);
3984 }
3985
3986 static void gfx_v7_0_rlc_reset(struct amdgpu_device *adev)
3987 {
3988         u32 tmp = RREG32(mmGRBM_SOFT_RESET);
3989
3990         tmp |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3991         WREG32(mmGRBM_SOFT_RESET, tmp);
3992         udelay(50);
3993         tmp &= ~GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
3994         WREG32(mmGRBM_SOFT_RESET, tmp);
3995         udelay(50);
3996 }
3997
3998 /**
3999  * gfx_v7_0_rlc_resume - setup the RLC hw
4000  *
4001  * @adev: amdgpu_device pointer
4002  *
4003  * Initialize the RLC registers, load the ucode,
4004  * and start the RLC (CIK).
4005  * Returns 0 for success, -EINVAL if the ucode is not available.
4006  */
4007 static int gfx_v7_0_rlc_resume(struct amdgpu_device *adev)
4008 {
4009         const struct rlc_firmware_header_v1_0 *hdr;
4010         const __le32 *fw_data;
4011         unsigned i, fw_size;
4012         u32 tmp;
4013
4014         if (!adev->gfx.rlc_fw)
4015                 return -EINVAL;
4016
4017         hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
4018         amdgpu_ucode_print_rlc_hdr(&hdr->header);
4019         adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version);
4020
4021         gfx_v7_0_rlc_stop(adev);
4022
4023         /* disable CG */
4024         tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc;
4025         WREG32(mmRLC_CGCG_CGLS_CTRL, tmp);
4026
4027         gfx_v7_0_rlc_reset(adev);
4028
4029         gfx_v7_0_init_pg(adev);
4030
4031         WREG32(mmRLC_LB_CNTR_INIT, 0);
4032         WREG32(mmRLC_LB_CNTR_MAX, 0x00008000);
4033
4034         mutex_lock(&adev->grbm_idx_mutex);
4035         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4036         WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
4037         WREG32(mmRLC_LB_PARAMS, 0x00600408);
4038         WREG32(mmRLC_LB_CNTL, 0x80000004);
4039         mutex_unlock(&adev->grbm_idx_mutex);
4040
4041         WREG32(mmRLC_MC_CNTL, 0);
4042         WREG32(mmRLC_UCODE_CNTL, 0);
4043
4044         fw_data = (const __le32 *)
4045                 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4046         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
4047         WREG32(mmRLC_GPM_UCODE_ADDR, 0);
4048         for (i = 0; i < fw_size; i++)
4049                 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
4050         WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
4051
4052         /* XXX - find out what chips support lbpw */
4053         gfx_v7_0_enable_lbpw(adev, false);
4054
4055         if (adev->asic_type == CHIP_BONAIRE)
4056                 WREG32(mmRLC_DRIVER_CPDMA_STATUS, 0);
4057
4058         gfx_v7_0_rlc_start(adev);
4059
4060         return 0;
4061 }
4062
4063 static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
4064 {
4065         u32 data, orig, tmp, tmp2;
4066
4067         orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
4068
4069         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGCG)) {
4070                 gfx_v7_0_enable_gui_idle_interrupt(adev, true);
4071
4072                 tmp = gfx_v7_0_halt_rlc(adev);
4073
4074                 mutex_lock(&adev->grbm_idx_mutex);
4075                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4076                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
4077                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
4078                 tmp2 = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
4079                         RLC_SERDES_WR_CTRL__CGCG_OVERRIDE_0_MASK |
4080                         RLC_SERDES_WR_CTRL__CGLS_ENABLE_MASK;
4081                 WREG32(mmRLC_SERDES_WR_CTRL, tmp2);
4082                 mutex_unlock(&adev->grbm_idx_mutex);
4083
4084                 gfx_v7_0_update_rlc(adev, tmp);
4085
4086                 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4087         } else {
4088                 gfx_v7_0_enable_gui_idle_interrupt(adev, false);
4089
4090                 RREG32(mmCB_CGTT_SCLK_CTRL);
4091                 RREG32(mmCB_CGTT_SCLK_CTRL);
4092                 RREG32(mmCB_CGTT_SCLK_CTRL);
4093                 RREG32(mmCB_CGTT_SCLK_CTRL);
4094
4095                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
4096         }
4097
4098         if (orig != data)
4099                 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
4100
4101 }
4102
4103 static void gfx_v7_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
4104 {
4105         u32 data, orig, tmp = 0;
4106
4107         if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGCG)) {
4108                 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) {
4109                         if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CP_LS) {
4110                                 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
4111                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4112                                 if (orig != data)
4113                                         WREG32(mmCP_MEM_SLP_CNTL, data);
4114                         }
4115                 }
4116
4117                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
4118                 data |= 0x00000001;
4119                 data &= 0xfffffffd;
4120                 if (orig != data)
4121                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
4122
4123                 tmp = gfx_v7_0_halt_rlc(adev);
4124
4125                 mutex_lock(&adev->grbm_idx_mutex);
4126                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4127                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
4128                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
4129                 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK |
4130                         RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_0_MASK;
4131                 WREG32(mmRLC_SERDES_WR_CTRL, data);
4132                 mutex_unlock(&adev->grbm_idx_mutex);
4133
4134                 gfx_v7_0_update_rlc(adev, tmp);
4135
4136                 if (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS) {
4137                         orig = data = RREG32(mmCGTS_SM_CTRL_REG);
4138                         data &= ~CGTS_SM_CTRL_REG__SM_MODE_MASK;
4139                         data |= (0x2 << CGTS_SM_CTRL_REG__SM_MODE__SHIFT);
4140                         data |= CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK;
4141                         data &= ~CGTS_SM_CTRL_REG__OVERRIDE_MASK;
4142                         if ((adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_MGLS) &&
4143                             (adev->cg_flags & AMDGPU_CG_SUPPORT_GFX_CGTS_LS))
4144                                 data &= ~CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
4145                         data &= ~CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK;
4146                         data |= CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK;
4147                         data |= (0x96 << CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT);
4148                         if (orig != data)
4149                                 WREG32(mmCGTS_SM_CTRL_REG, data);
4150                 }
4151         } else {
4152                 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
4153                 data |= 0x00000003;
4154                 if (orig != data)
4155                         WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
4156
4157                 data = RREG32(mmRLC_MEM_SLP_CNTL);
4158                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
4159                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
4160                         WREG32(mmRLC_MEM_SLP_CNTL, data);
4161                 }
4162
4163                 data = RREG32(mmCP_MEM_SLP_CNTL);
4164                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
4165                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
4166                         WREG32(mmCP_MEM_SLP_CNTL, data);
4167                 }
4168
4169                 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
4170                 data |= CGTS_SM_CTRL_REG__OVERRIDE_MASK | CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK;
4171                 if (orig != data)
4172                         WREG32(mmCGTS_SM_CTRL_REG, data);
4173
4174                 tmp = gfx_v7_0_halt_rlc(adev);
4175
4176                 mutex_lock(&adev->grbm_idx_mutex);
4177                 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4178                 WREG32(mmRLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
4179                 WREG32(mmRLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
4180                 data = RLC_SERDES_WR_CTRL__BPM_ADDR_MASK | RLC_SERDES_WR_CTRL__MGCG_OVERRIDE_1_MASK;
4181                 WREG32(mmRLC_SERDES_WR_CTRL, data);
4182                 mutex_unlock(&adev->grbm_idx_mutex);
4183
4184                 gfx_v7_0_update_rlc(adev, tmp);
4185         }
4186 }
4187
4188 static void gfx_v7_0_update_cg(struct amdgpu_device *adev,
4189                                bool enable)
4190 {
4191         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
4192         /* order matters! */
4193         if (enable) {
4194                 gfx_v7_0_enable_mgcg(adev, true);
4195                 gfx_v7_0_enable_cgcg(adev, true);
4196         } else {
4197                 gfx_v7_0_enable_cgcg(adev, false);
4198                 gfx_v7_0_enable_mgcg(adev, false);
4199         }
4200         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
4201 }
4202
4203 static void gfx_v7_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
4204                                                 bool enable)
4205 {
4206         u32 data, orig;
4207
4208         orig = data = RREG32(mmRLC_PG_CNTL);
4209         if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS))
4210                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
4211         else
4212                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
4213         if (orig != data)
4214                 WREG32(mmRLC_PG_CNTL, data);
4215 }
4216
4217 static void gfx_v7_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
4218                                                 bool enable)
4219 {
4220         u32 data, orig;
4221
4222         orig = data = RREG32(mmRLC_PG_CNTL);
4223         if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_RLC_SMU_HS))
4224                 data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
4225         else
4226                 data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
4227         if (orig != data)
4228                 WREG32(mmRLC_PG_CNTL, data);
4229 }
4230
4231 static void gfx_v7_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
4232 {
4233         u32 data, orig;
4234
4235         orig = data = RREG32(mmRLC_PG_CNTL);
4236         if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_CP))
4237                 data &= ~0x8000;
4238         else
4239                 data |= 0x8000;
4240         if (orig != data)
4241                 WREG32(mmRLC_PG_CNTL, data);
4242 }
4243
4244 static void gfx_v7_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
4245 {
4246         u32 data, orig;
4247
4248         orig = data = RREG32(mmRLC_PG_CNTL);
4249         if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GDS))
4250                 data &= ~0x2000;
4251         else
4252                 data |= 0x2000;
4253         if (orig != data)
4254                 WREG32(mmRLC_PG_CNTL, data);
4255 }
4256
4257 static void gfx_v7_0_init_cp_pg_table(struct amdgpu_device *adev)
4258 {
4259         const __le32 *fw_data;
4260         volatile u32 *dst_ptr;
4261         int me, i, max_me = 4;
4262         u32 bo_offset = 0;
4263         u32 table_offset, table_size;
4264
4265         if (adev->asic_type == CHIP_KAVERI)
4266                 max_me = 5;
4267
4268         if (adev->gfx.rlc.cp_table_ptr == NULL)
4269                 return;
4270
4271         /* write the cp table buffer */
4272         dst_ptr = adev->gfx.rlc.cp_table_ptr;
4273         for (me = 0; me < max_me; me++) {
4274                 if (me == 0) {
4275                         const struct gfx_firmware_header_v1_0 *hdr =
4276                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
4277                         fw_data = (const __le32 *)
4278                                 (adev->gfx.ce_fw->data +
4279                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4280                         table_offset = le32_to_cpu(hdr->jt_offset);
4281                         table_size = le32_to_cpu(hdr->jt_size);
4282                 } else if (me == 1) {
4283                         const struct gfx_firmware_header_v1_0 *hdr =
4284                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
4285                         fw_data = (const __le32 *)
4286                                 (adev->gfx.pfp_fw->data +
4287                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4288                         table_offset = le32_to_cpu(hdr->jt_offset);
4289                         table_size = le32_to_cpu(hdr->jt_size);
4290                 } else if (me == 2) {
4291                         const struct gfx_firmware_header_v1_0 *hdr =
4292                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
4293                         fw_data = (const __le32 *)
4294                                 (adev->gfx.me_fw->data +
4295                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4296                         table_offset = le32_to_cpu(hdr->jt_offset);
4297                         table_size = le32_to_cpu(hdr->jt_size);
4298                 } else if (me == 3) {
4299                         const struct gfx_firmware_header_v1_0 *hdr =
4300                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4301                         fw_data = (const __le32 *)
4302                                 (adev->gfx.mec_fw->data +
4303                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4304                         table_offset = le32_to_cpu(hdr->jt_offset);
4305                         table_size = le32_to_cpu(hdr->jt_size);
4306                 } else {
4307                         const struct gfx_firmware_header_v1_0 *hdr =
4308                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
4309                         fw_data = (const __le32 *)
4310                                 (adev->gfx.mec2_fw->data +
4311                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4312                         table_offset = le32_to_cpu(hdr->jt_offset);
4313                         table_size = le32_to_cpu(hdr->jt_size);
4314                 }
4315
4316                 for (i = 0; i < table_size; i ++) {
4317                         dst_ptr[bo_offset + i] =
4318                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
4319                 }
4320
4321                 bo_offset += table_size;
4322         }
4323 }
4324
4325 static void gfx_v7_0_enable_gfx_cgpg(struct amdgpu_device *adev,
4326                                      bool enable)
4327 {
4328         u32 data, orig;
4329
4330         if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG)) {
4331                 orig = data = RREG32(mmRLC_PG_CNTL);
4332                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
4333                 if (orig != data)
4334                         WREG32(mmRLC_PG_CNTL, data);
4335
4336                 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
4337                 data |= RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
4338                 if (orig != data)
4339                         WREG32(mmRLC_AUTO_PG_CTRL, data);
4340         } else {
4341                 orig = data = RREG32(mmRLC_PG_CNTL);
4342                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
4343                 if (orig != data)
4344                         WREG32(mmRLC_PG_CNTL, data);
4345
4346                 orig = data = RREG32(mmRLC_AUTO_PG_CTRL);
4347                 data &= ~RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK;
4348                 if (orig != data)
4349                         WREG32(mmRLC_AUTO_PG_CTRL, data);
4350
4351                 data = RREG32(mmDB_RENDER_CONTROL);
4352         }
4353 }
4354
4355 static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev,
4356                                          u32 se, u32 sh)
4357 {
4358         u32 mask = 0, tmp, tmp1;
4359         int i;
4360
4361         gfx_v7_0_select_se_sh(adev, se, sh);
4362         tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4363         tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
4364         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4365
4366         tmp &= 0xffff0000;
4367
4368         tmp |= tmp1;
4369         tmp >>= 16;
4370
4371         for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
4372                 mask <<= 1;
4373                 mask |= 1;
4374         }
4375
4376         return (~tmp) & mask;
4377 }
4378
4379 static void gfx_v7_0_init_ao_cu_mask(struct amdgpu_device *adev)
4380 {
4381         uint32_t tmp, active_cu_number;
4382         struct amdgpu_cu_info cu_info;
4383
4384         gfx_v7_0_get_cu_info(adev, &cu_info);
4385         tmp = cu_info.ao_cu_mask;
4386         active_cu_number = cu_info.number;
4387
4388         WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, tmp);
4389
4390         tmp = RREG32(mmRLC_MAX_PG_CU);
4391         tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
4392         tmp |= (active_cu_number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
4393         WREG32(mmRLC_MAX_PG_CU, tmp);
4394 }
4395
4396 static void gfx_v7_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
4397                                             bool enable)
4398 {
4399         u32 data, orig;
4400
4401         orig = data = RREG32(mmRLC_PG_CNTL);
4402         if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG))
4403                 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
4404         else
4405                 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
4406         if (orig != data)
4407                 WREG32(mmRLC_PG_CNTL, data);
4408 }
4409
4410 static void gfx_v7_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
4411                                              bool enable)
4412 {
4413         u32 data, orig;
4414
4415         orig = data = RREG32(mmRLC_PG_CNTL);
4416         if (enable && (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG))
4417                 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
4418         else
4419                 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
4420         if (orig != data)
4421                 WREG32(mmRLC_PG_CNTL, data);
4422 }
4423
4424 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
4425 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET    0x3D
4426
4427 static void gfx_v7_0_init_gfx_cgpg(struct amdgpu_device *adev)
4428 {
4429         u32 data, orig;
4430         u32 i;
4431
4432         if (adev->gfx.rlc.cs_data) {
4433                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
4434                 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
4435                 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
4436                 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
4437         } else {
4438                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
4439                 for (i = 0; i < 3; i++)
4440                         WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
4441         }
4442         if (adev->gfx.rlc.reg_list) {
4443                 WREG32(mmRLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
4444                 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
4445                         WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
4446         }
4447
4448         orig = data = RREG32(mmRLC_PG_CNTL);
4449         data |= RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK;
4450         if (orig != data)
4451                 WREG32(mmRLC_PG_CNTL, data);
4452
4453         WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
4454         WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
4455
4456         data = RREG32(mmCP_RB_WPTR_POLL_CNTL);
4457         data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
4458         data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4459         WREG32(mmCP_RB_WPTR_POLL_CNTL, data);
4460
4461         data = 0x10101010;
4462         WREG32(mmRLC_PG_DELAY, data);
4463
4464         data = RREG32(mmRLC_PG_DELAY_2);
4465         data &= ~0xff;
4466         data |= 0x3;
4467         WREG32(mmRLC_PG_DELAY_2, data);
4468
4469         data = RREG32(mmRLC_AUTO_PG_CTRL);
4470         data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
4471         data |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
4472         WREG32(mmRLC_AUTO_PG_CTRL, data);
4473
4474 }
4475
4476 static void gfx_v7_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
4477 {
4478         gfx_v7_0_enable_gfx_cgpg(adev, enable);
4479         gfx_v7_0_enable_gfx_static_mgpg(adev, enable);
4480         gfx_v7_0_enable_gfx_dynamic_mgpg(adev, enable);
4481 }
4482
4483 static u32 gfx_v7_0_get_csb_size(struct amdgpu_device *adev)
4484 {
4485         u32 count = 0;
4486         const struct cs_section_def *sect = NULL;
4487         const struct cs_extent_def *ext = NULL;
4488
4489         if (adev->gfx.rlc.cs_data == NULL)
4490                 return 0;
4491
4492         /* begin clear state */
4493         count += 2;
4494         /* context control state */
4495         count += 3;
4496
4497         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4498                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4499                         if (sect->id == SECT_CONTEXT)
4500                                 count += 2 + ext->reg_count;
4501                         else
4502                                 return 0;
4503                 }
4504         }
4505         /* pa_sc_raster_config/pa_sc_raster_config1 */
4506         count += 4;
4507         /* end clear state */
4508         count += 2;
4509         /* clear state */
4510         count += 2;
4511
4512         return count;
4513 }
4514
4515 static void gfx_v7_0_get_csb_buffer(struct amdgpu_device *adev,
4516                                     volatile u32 *buffer)
4517 {
4518         u32 count = 0, i;
4519         const struct cs_section_def *sect = NULL;
4520         const struct cs_extent_def *ext = NULL;
4521
4522         if (adev->gfx.rlc.cs_data == NULL)
4523                 return;
4524         if (buffer == NULL)
4525                 return;
4526
4527         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4528         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4529
4530         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4531         buffer[count++] = cpu_to_le32(0x80000000);
4532         buffer[count++] = cpu_to_le32(0x80000000);
4533
4534         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4535                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4536                         if (sect->id == SECT_CONTEXT) {
4537                                 buffer[count++] =
4538                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4539                                 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
4540                                 for (i = 0; i < ext->reg_count; i++)
4541                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4542                         } else {
4543                                 return;
4544                         }
4545                 }
4546         }
4547
4548         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
4549         buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
4550         switch (adev->asic_type) {
4551         case CHIP_BONAIRE:
4552                 buffer[count++] = cpu_to_le32(0x16000012);
4553                 buffer[count++] = cpu_to_le32(0x00000000);
4554                 break;
4555         case CHIP_KAVERI:
4556                 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4557                 buffer[count++] = cpu_to_le32(0x00000000);
4558                 break;
4559         case CHIP_KABINI:
4560         case CHIP_MULLINS:
4561                 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
4562                 buffer[count++] = cpu_to_le32(0x00000000);
4563                 break;
4564         case CHIP_HAWAII:
4565                 buffer[count++] = cpu_to_le32(0x3a00161a);
4566                 buffer[count++] = cpu_to_le32(0x0000002e);
4567                 break;
4568         default:
4569                 buffer[count++] = cpu_to_le32(0x00000000);
4570                 buffer[count++] = cpu_to_le32(0x00000000);
4571                 break;
4572         }
4573
4574         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4575         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4576
4577         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4578         buffer[count++] = cpu_to_le32(0);
4579 }
4580
4581 static void gfx_v7_0_init_pg(struct amdgpu_device *adev)
4582 {
4583         if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
4584                               AMDGPU_PG_SUPPORT_GFX_SMG |
4585                               AMDGPU_PG_SUPPORT_GFX_DMG |
4586                               AMDGPU_PG_SUPPORT_CP |
4587                               AMDGPU_PG_SUPPORT_GDS |
4588                               AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {
4589                 gfx_v7_0_enable_sclk_slowdown_on_pu(adev, true);
4590                 gfx_v7_0_enable_sclk_slowdown_on_pd(adev, true);
4591                 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {
4592                         gfx_v7_0_init_gfx_cgpg(adev);
4593                         gfx_v7_0_enable_cp_pg(adev, true);
4594                         gfx_v7_0_enable_gds_pg(adev, true);
4595                 }
4596                 gfx_v7_0_init_ao_cu_mask(adev);
4597                 gfx_v7_0_update_gfx_pg(adev, true);
4598         }
4599 }
4600
4601 static void gfx_v7_0_fini_pg(struct amdgpu_device *adev)
4602 {
4603         if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
4604                               AMDGPU_PG_SUPPORT_GFX_SMG |
4605                               AMDGPU_PG_SUPPORT_GFX_DMG |
4606                               AMDGPU_PG_SUPPORT_CP |
4607                               AMDGPU_PG_SUPPORT_GDS |
4608                               AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {
4609                 gfx_v7_0_update_gfx_pg(adev, false);
4610                 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {
4611                         gfx_v7_0_enable_cp_pg(adev, false);
4612                         gfx_v7_0_enable_gds_pg(adev, false);
4613                 }
4614         }
4615 }
4616
4617 /**
4618  * gfx_v7_0_get_gpu_clock_counter - return GPU clock counter snapshot
4619  *
4620  * @adev: amdgpu_device pointer
4621  *
4622  * Fetches a GPU clock counter snapshot (SI).
4623  * Returns the 64 bit clock counter snapshot.
4624  */
4625 uint64_t gfx_v7_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4626 {
4627         uint64_t clock;
4628
4629         mutex_lock(&adev->gfx.gpu_clock_mutex);
4630         WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4631         clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4632                 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4633         mutex_unlock(&adev->gfx.gpu_clock_mutex);
4634         return clock;
4635 }
4636
4637 static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4638                                           uint32_t vmid,
4639                                           uint32_t gds_base, uint32_t gds_size,
4640                                           uint32_t gws_base, uint32_t gws_size,
4641                                           uint32_t oa_base, uint32_t oa_size)
4642 {
4643         gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4644         gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4645
4646         gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4647         gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4648
4649         oa_base = oa_base >> AMDGPU_OA_SHIFT;
4650         oa_size = oa_size >> AMDGPU_OA_SHIFT;
4651
4652         /* GDS Base */
4653         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4654         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4655                                 WRITE_DATA_DST_SEL(0)));
4656         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4657         amdgpu_ring_write(ring, 0);
4658         amdgpu_ring_write(ring, gds_base);
4659
4660         /* GDS Size */
4661         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4662         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4663                                 WRITE_DATA_DST_SEL(0)));
4664         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4665         amdgpu_ring_write(ring, 0);
4666         amdgpu_ring_write(ring, gds_size);
4667
4668         /* GWS */
4669         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4670         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4671                                 WRITE_DATA_DST_SEL(0)));
4672         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4673         amdgpu_ring_write(ring, 0);
4674         amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4675
4676         /* OA */
4677         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4678         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4679                                 WRITE_DATA_DST_SEL(0)));
4680         amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4681         amdgpu_ring_write(ring, 0);
4682         amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4683 }
4684
4685 static int gfx_v7_0_early_init(struct amdgpu_device *adev)
4686 {
4687
4688         adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS;
4689         adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS;
4690         gfx_v7_0_set_ring_funcs(adev);
4691         gfx_v7_0_set_irq_funcs(adev);
4692         gfx_v7_0_set_gds_init(adev);
4693
4694         return 0;
4695 }
4696
4697 static int gfx_v7_0_sw_init(struct amdgpu_device *adev)
4698 {
4699         struct amdgpu_ring *ring;
4700         int i, r;
4701
4702         /* EOP Event */
4703         r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
4704         if (r)
4705                 return r;
4706
4707         /* Privileged reg */
4708         r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
4709         if (r)
4710                 return r;
4711
4712         /* Privileged inst */
4713         r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
4714         if (r)
4715                 return r;
4716
4717         gfx_v7_0_scratch_init(adev);
4718
4719         r = gfx_v7_0_init_microcode(adev);
4720         if (r) {
4721                 DRM_ERROR("Failed to load gfx firmware!\n");
4722                 return r;
4723         }
4724
4725         r = gfx_v7_0_rlc_init(adev);
4726         if (r) {
4727                 DRM_ERROR("Failed to init rlc BOs!\n");
4728                 return r;
4729         }
4730
4731         /* allocate mec buffers */
4732         r = gfx_v7_0_mec_init(adev);
4733         if (r) {
4734                 DRM_ERROR("Failed to init MEC BOs!\n");
4735                 return r;
4736         }
4737
4738         r = amdgpu_wb_get(adev, &adev->gfx.ce_sync_offs);
4739         if (r) {
4740                 DRM_ERROR("(%d) gfx.ce_sync_offs wb alloc failed\n", r);
4741                 return r;
4742         }
4743
4744         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4745                 ring = &adev->gfx.gfx_ring[i];
4746                 ring->ring_obj = NULL;
4747                 sprintf(ring->name, "gfx");
4748                 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
4749                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4750                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
4751                                      AMDGPU_RING_TYPE_GFX);
4752                 if (r)
4753                         return r;
4754         }
4755
4756         /* set up the compute queues */
4757         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4758                 unsigned irq_type;
4759
4760                 /* max 32 queues per MEC */
4761                 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
4762                         DRM_ERROR("Too many (%d) compute rings!\n", i);
4763                         break;
4764                 }
4765                 ring = &adev->gfx.compute_ring[i];
4766                 ring->ring_obj = NULL;
4767                 ring->use_doorbell = true;
4768                 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
4769                 ring->me = 1; /* first MEC */
4770                 ring->pipe = i / 8;
4771                 ring->queue = i % 8;
4772                 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
4773                 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
4774                 /* type-2 packets are deprecated on MEC, use type-3 instead */
4775                 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
4776                                      PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
4777                                      &adev->gfx.eop_irq, irq_type,
4778                                      AMDGPU_RING_TYPE_COMPUTE);
4779                 if (r)
4780                         return r;
4781         }
4782
4783         /* reserve GDS, GWS and OA resource for gfx */
4784         r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
4785                         PAGE_SIZE, true,
4786                         AMDGPU_GEM_DOMAIN_GDS, 0,
4787                         NULL, &adev->gds.gds_gfx_bo);
4788         if (r)
4789                 return r;
4790
4791         r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
4792                 PAGE_SIZE, true,
4793                 AMDGPU_GEM_DOMAIN_GWS, 0,
4794                 NULL, &adev->gds.gws_gfx_bo);
4795         if (r)
4796                 return r;
4797
4798         r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
4799                         PAGE_SIZE, true,
4800                         AMDGPU_GEM_DOMAIN_OA, 0,
4801                         NULL, &adev->gds.oa_gfx_bo);
4802         if (r)
4803                 return r;
4804
4805         return r;
4806 }
4807
4808 static int gfx_v7_0_sw_fini(struct amdgpu_device *adev)
4809 {
4810         int i;
4811
4812         amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
4813         amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
4814         amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
4815
4816         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4817                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4818         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4819                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4820
4821         amdgpu_wb_free(adev, adev->gfx.ce_sync_offs);
4822
4823         gfx_v7_0_cp_compute_fini(adev);
4824         gfx_v7_0_rlc_fini(adev);
4825         gfx_v7_0_mec_fini(adev);
4826
4827         return 0;
4828 }
4829
4830 static int gfx_v7_0_hw_init(struct amdgpu_device *adev)
4831 {
4832         int r;
4833
4834         gfx_v7_0_gpu_init(adev);
4835
4836         /* init rlc */
4837         r = gfx_v7_0_rlc_resume(adev);
4838         if (r)
4839                 return r;
4840
4841         r = gfx_v7_0_cp_resume(adev);
4842         if (r)
4843                 return r;
4844
4845         return r;
4846 }
4847
4848 static int gfx_v7_0_hw_fini(struct amdgpu_device *adev)
4849 {
4850         gfx_v7_0_cp_enable(adev, false);
4851         gfx_v7_0_rlc_stop(adev);
4852         gfx_v7_0_fini_pg(adev);
4853
4854         return 0;
4855 }
4856
4857 static int gfx_v7_0_suspend(struct amdgpu_device *adev)
4858 {
4859         return gfx_v7_0_hw_fini(adev);
4860 }
4861
4862 static int gfx_v7_0_resume(struct amdgpu_device *adev)
4863 {
4864         return gfx_v7_0_hw_init(adev);
4865 }
4866
4867 static bool gfx_v7_0_is_idle(struct amdgpu_device *adev)
4868 {
4869         if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
4870                 return false;
4871         else
4872                 return true;
4873 }
4874
4875 static int gfx_v7_0_wait_for_idle(struct amdgpu_device *adev)
4876 {
4877         unsigned i;
4878         u32 tmp;
4879
4880         for (i = 0; i < adev->usec_timeout; i++) {
4881                 /* read MC_STATUS */
4882                 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
4883
4884                 if (!tmp)
4885                         return 0;
4886                 udelay(1);
4887         }
4888         return -ETIMEDOUT;
4889 }
4890
4891 static void gfx_v7_0_print_status(struct amdgpu_device *adev)
4892 {
4893         int i;
4894
4895         dev_info(adev->dev, "GFX 7.x registers\n");
4896         dev_info(adev->dev, "  GRBM_STATUS=0x%08X\n",
4897                 RREG32(mmGRBM_STATUS));
4898         dev_info(adev->dev, "  GRBM_STATUS2=0x%08X\n",
4899                 RREG32(mmGRBM_STATUS2));
4900         dev_info(adev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
4901                 RREG32(mmGRBM_STATUS_SE0));
4902         dev_info(adev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
4903                 RREG32(mmGRBM_STATUS_SE1));
4904         dev_info(adev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
4905                 RREG32(mmGRBM_STATUS_SE2));
4906         dev_info(adev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
4907                 RREG32(mmGRBM_STATUS_SE3));
4908         dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
4909         dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
4910                  RREG32(mmCP_STALLED_STAT1));
4911         dev_info(adev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
4912                  RREG32(mmCP_STALLED_STAT2));
4913         dev_info(adev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
4914                  RREG32(mmCP_STALLED_STAT3));
4915         dev_info(adev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
4916                  RREG32(mmCP_CPF_BUSY_STAT));
4917         dev_info(adev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
4918                  RREG32(mmCP_CPF_STALLED_STAT1));
4919         dev_info(adev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
4920         dev_info(adev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
4921         dev_info(adev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
4922                  RREG32(mmCP_CPC_STALLED_STAT1));
4923         dev_info(adev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
4924
4925         for (i = 0; i < 32; i++) {
4926                 dev_info(adev->dev, "  GB_TILE_MODE%d=0x%08X\n",
4927                          i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
4928         }
4929         for (i = 0; i < 16; i++) {
4930                 dev_info(adev->dev, "  GB_MACROTILE_MODE%d=0x%08X\n",
4931                          i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
4932         }
4933         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4934                 dev_info(adev->dev, "  se: %d\n", i);
4935                 gfx_v7_0_select_se_sh(adev, i, 0xffffffff);
4936                 dev_info(adev->dev, "  PA_SC_RASTER_CONFIG=0x%08X\n",
4937                          RREG32(mmPA_SC_RASTER_CONFIG));
4938                 dev_info(adev->dev, "  PA_SC_RASTER_CONFIG_1=0x%08X\n",
4939                          RREG32(mmPA_SC_RASTER_CONFIG_1));
4940         }
4941         gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4942
4943         dev_info(adev->dev, "  GB_ADDR_CONFIG=0x%08X\n",
4944                  RREG32(mmGB_ADDR_CONFIG));
4945         dev_info(adev->dev, "  HDP_ADDR_CONFIG=0x%08X\n",
4946                  RREG32(mmHDP_ADDR_CONFIG));
4947         dev_info(adev->dev, "  DMIF_ADDR_CALC=0x%08X\n",
4948                  RREG32(mmDMIF_ADDR_CALC));
4949         dev_info(adev->dev, "  SDMA0_TILING_CONFIG=0x%08X\n",
4950                  RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
4951         dev_info(adev->dev, "  SDMA1_TILING_CONFIG=0x%08X\n",
4952                  RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
4953         dev_info(adev->dev, "  UVD_UDEC_ADDR_CONFIG=0x%08X\n",
4954                  RREG32(mmUVD_UDEC_ADDR_CONFIG));
4955         dev_info(adev->dev, "  UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
4956                  RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
4957         dev_info(adev->dev, "  UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
4958                  RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
4959
4960         dev_info(adev->dev, "  CP_MEQ_THRESHOLDS=0x%08X\n",
4961                  RREG32(mmCP_MEQ_THRESHOLDS));
4962         dev_info(adev->dev, "  SX_DEBUG_1=0x%08X\n",
4963                  RREG32(mmSX_DEBUG_1));
4964         dev_info(adev->dev, "  TA_CNTL_AUX=0x%08X\n",
4965                  RREG32(mmTA_CNTL_AUX));
4966         dev_info(adev->dev, "  SPI_CONFIG_CNTL=0x%08X\n",
4967                  RREG32(mmSPI_CONFIG_CNTL));
4968         dev_info(adev->dev, "  SQ_CONFIG=0x%08X\n",
4969                  RREG32(mmSQ_CONFIG));
4970         dev_info(adev->dev, "  DB_DEBUG=0x%08X\n",
4971                  RREG32(mmDB_DEBUG));
4972         dev_info(adev->dev, "  DB_DEBUG2=0x%08X\n",
4973                  RREG32(mmDB_DEBUG2));
4974         dev_info(adev->dev, "  DB_DEBUG3=0x%08X\n",
4975                  RREG32(mmDB_DEBUG3));
4976         dev_info(adev->dev, "  CB_HW_CONTROL=0x%08X\n",
4977                  RREG32(mmCB_HW_CONTROL));
4978         dev_info(adev->dev, "  SPI_CONFIG_CNTL_1=0x%08X\n",
4979                  RREG32(mmSPI_CONFIG_CNTL_1));
4980         dev_info(adev->dev, "  PA_SC_FIFO_SIZE=0x%08X\n",
4981                  RREG32(mmPA_SC_FIFO_SIZE));
4982         dev_info(adev->dev, "  VGT_NUM_INSTANCES=0x%08X\n",
4983                  RREG32(mmVGT_NUM_INSTANCES));
4984         dev_info(adev->dev, "  CP_PERFMON_CNTL=0x%08X\n",
4985                  RREG32(mmCP_PERFMON_CNTL));
4986         dev_info(adev->dev, "  PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
4987                  RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
4988         dev_info(adev->dev, "  VGT_CACHE_INVALIDATION=0x%08X\n",
4989                  RREG32(mmVGT_CACHE_INVALIDATION));
4990         dev_info(adev->dev, "  VGT_GS_VERTEX_REUSE=0x%08X\n",
4991                  RREG32(mmVGT_GS_VERTEX_REUSE));
4992         dev_info(adev->dev, "  PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
4993                  RREG32(mmPA_SC_LINE_STIPPLE_STATE));
4994         dev_info(adev->dev, "  PA_CL_ENHANCE=0x%08X\n",
4995                  RREG32(mmPA_CL_ENHANCE));
4996         dev_info(adev->dev, "  PA_SC_ENHANCE=0x%08X\n",
4997                  RREG32(mmPA_SC_ENHANCE));
4998
4999         dev_info(adev->dev, "  CP_ME_CNTL=0x%08X\n",
5000                  RREG32(mmCP_ME_CNTL));
5001         dev_info(adev->dev, "  CP_MAX_CONTEXT=0x%08X\n",
5002                  RREG32(mmCP_MAX_CONTEXT));
5003         dev_info(adev->dev, "  CP_ENDIAN_SWAP=0x%08X\n",
5004                  RREG32(mmCP_ENDIAN_SWAP));
5005         dev_info(adev->dev, "  CP_DEVICE_ID=0x%08X\n",
5006                  RREG32(mmCP_DEVICE_ID));
5007
5008         dev_info(adev->dev, "  CP_SEM_WAIT_TIMER=0x%08X\n",
5009                  RREG32(mmCP_SEM_WAIT_TIMER));
5010         if (adev->asic_type != CHIP_HAWAII)
5011                 dev_info(adev->dev, "  CP_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
5012                          RREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL));
5013
5014         dev_info(adev->dev, "  CP_RB_WPTR_DELAY=0x%08X\n",
5015                  RREG32(mmCP_RB_WPTR_DELAY));
5016         dev_info(adev->dev, "  CP_RB_VMID=0x%08X\n",
5017                  RREG32(mmCP_RB_VMID));
5018         dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
5019                  RREG32(mmCP_RB0_CNTL));
5020         dev_info(adev->dev, "  CP_RB0_WPTR=0x%08X\n",
5021                  RREG32(mmCP_RB0_WPTR));
5022         dev_info(adev->dev, "  CP_RB0_RPTR_ADDR=0x%08X\n",
5023                  RREG32(mmCP_RB0_RPTR_ADDR));
5024         dev_info(adev->dev, "  CP_RB0_RPTR_ADDR_HI=0x%08X\n",
5025                  RREG32(mmCP_RB0_RPTR_ADDR_HI));
5026         dev_info(adev->dev, "  CP_RB0_CNTL=0x%08X\n",
5027                  RREG32(mmCP_RB0_CNTL));
5028         dev_info(adev->dev, "  CP_RB0_BASE=0x%08X\n",
5029                  RREG32(mmCP_RB0_BASE));
5030         dev_info(adev->dev, "  CP_RB0_BASE_HI=0x%08X\n",
5031                  RREG32(mmCP_RB0_BASE_HI));
5032         dev_info(adev->dev, "  CP_MEC_CNTL=0x%08X\n",
5033                  RREG32(mmCP_MEC_CNTL));
5034         dev_info(adev->dev, "  CP_CPF_DEBUG=0x%08X\n",
5035                  RREG32(mmCP_CPF_DEBUG));
5036
5037         dev_info(adev->dev, "  SCRATCH_ADDR=0x%08X\n",
5038                  RREG32(mmSCRATCH_ADDR));
5039         dev_info(adev->dev, "  SCRATCH_UMSK=0x%08X\n",
5040                  RREG32(mmSCRATCH_UMSK));
5041
5042         /* init the pipes */
5043         mutex_lock(&adev->srbm_mutex);
5044         for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
5045                 int me = (i < 4) ? 1 : 2;
5046                 int pipe = (i < 4) ? i : (i - 4);
5047                 int queue;
5048
5049                 dev_info(adev->dev, "  me: %d, pipe: %d\n", me, pipe);
5050                 cik_srbm_select(adev, me, pipe, 0, 0);
5051                 dev_info(adev->dev, "  CP_HPD_EOP_BASE_ADDR=0x%08X\n",
5052                          RREG32(mmCP_HPD_EOP_BASE_ADDR));
5053                 dev_info(adev->dev, "  CP_HPD_EOP_BASE_ADDR_HI=0x%08X\n",
5054                          RREG32(mmCP_HPD_EOP_BASE_ADDR_HI));
5055                 dev_info(adev->dev, "  CP_HPD_EOP_VMID=0x%08X\n",
5056                          RREG32(mmCP_HPD_EOP_VMID));
5057                 dev_info(adev->dev, "  CP_HPD_EOP_CONTROL=0x%08X\n",
5058                          RREG32(mmCP_HPD_EOP_CONTROL));
5059
5060                 for (queue = 0; queue < 8; i++) {
5061                         cik_srbm_select(adev, me, pipe, queue, 0);
5062                         dev_info(adev->dev, "  queue: %d\n", queue);
5063                         dev_info(adev->dev, "  CP_PQ_WPTR_POLL_CNTL=0x%08X\n",
5064                                  RREG32(mmCP_PQ_WPTR_POLL_CNTL));
5065                         dev_info(adev->dev, "  CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n",
5066                                  RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL));
5067                         dev_info(adev->dev, "  CP_HQD_ACTIVE=0x%08X\n",
5068                                  RREG32(mmCP_HQD_ACTIVE));
5069                         dev_info(adev->dev, "  CP_HQD_DEQUEUE_REQUEST=0x%08X\n",
5070                                  RREG32(mmCP_HQD_DEQUEUE_REQUEST));
5071                         dev_info(adev->dev, "  CP_HQD_PQ_RPTR=0x%08X\n",
5072                                  RREG32(mmCP_HQD_PQ_RPTR));
5073                         dev_info(adev->dev, "  CP_HQD_PQ_WPTR=0x%08X\n",
5074                                  RREG32(mmCP_HQD_PQ_WPTR));
5075                         dev_info(adev->dev, "  CP_HQD_PQ_BASE=0x%08X\n",
5076                                  RREG32(mmCP_HQD_PQ_BASE));
5077                         dev_info(adev->dev, "  CP_HQD_PQ_BASE_HI=0x%08X\n",
5078                                  RREG32(mmCP_HQD_PQ_BASE_HI));
5079                         dev_info(adev->dev, "  CP_HQD_PQ_CONTROL=0x%08X\n",
5080                                  RREG32(mmCP_HQD_PQ_CONTROL));
5081                         dev_info(adev->dev, "  CP_HQD_PQ_WPTR_POLL_ADDR=0x%08X\n",
5082                                  RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR));
5083                         dev_info(adev->dev, "  CP_HQD_PQ_WPTR_POLL_ADDR_HI=0x%08X\n",
5084                                  RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI));
5085                         dev_info(adev->dev, "  CP_HQD_PQ_RPTR_REPORT_ADDR=0x%08X\n",
5086                                  RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR));
5087                         dev_info(adev->dev, "  CP_HQD_PQ_RPTR_REPORT_ADDR_HI=0x%08X\n",
5088                                  RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI));
5089                         dev_info(adev->dev, "  CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n",
5090                                  RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL));
5091                         dev_info(adev->dev, "  CP_HQD_PQ_WPTR=0x%08X\n",
5092                                  RREG32(mmCP_HQD_PQ_WPTR));
5093                         dev_info(adev->dev, "  CP_HQD_VMID=0x%08X\n",
5094                                  RREG32(mmCP_HQD_VMID));
5095                         dev_info(adev->dev, "  CP_MQD_BASE_ADDR=0x%08X\n",
5096                                  RREG32(mmCP_MQD_BASE_ADDR));
5097                         dev_info(adev->dev, "  CP_MQD_BASE_ADDR_HI=0x%08X\n",
5098                                  RREG32(mmCP_MQD_BASE_ADDR_HI));
5099                         dev_info(adev->dev, "  CP_MQD_CONTROL=0x%08X\n",
5100                                  RREG32(mmCP_MQD_CONTROL));
5101                 }
5102         }
5103         cik_srbm_select(adev, 0, 0, 0, 0);
5104         mutex_unlock(&adev->srbm_mutex);
5105
5106         dev_info(adev->dev, "  CP_INT_CNTL_RING0=0x%08X\n",
5107                  RREG32(mmCP_INT_CNTL_RING0));
5108         dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
5109                  RREG32(mmRLC_LB_CNTL));
5110         dev_info(adev->dev, "  RLC_CNTL=0x%08X\n",
5111                  RREG32(mmRLC_CNTL));
5112         dev_info(adev->dev, "  RLC_CGCG_CGLS_CTRL=0x%08X\n",
5113                  RREG32(mmRLC_CGCG_CGLS_CTRL));
5114         dev_info(adev->dev, "  RLC_LB_CNTR_INIT=0x%08X\n",
5115                  RREG32(mmRLC_LB_CNTR_INIT));
5116         dev_info(adev->dev, "  RLC_LB_CNTR_MAX=0x%08X\n",
5117                  RREG32(mmRLC_LB_CNTR_MAX));
5118         dev_info(adev->dev, "  RLC_LB_INIT_CU_MASK=0x%08X\n",
5119                  RREG32(mmRLC_LB_INIT_CU_MASK));
5120         dev_info(adev->dev, "  RLC_LB_PARAMS=0x%08X\n",
5121                  RREG32(mmRLC_LB_PARAMS));
5122         dev_info(adev->dev, "  RLC_LB_CNTL=0x%08X\n",
5123                  RREG32(mmRLC_LB_CNTL));
5124         dev_info(adev->dev, "  RLC_MC_CNTL=0x%08X\n",
5125                  RREG32(mmRLC_MC_CNTL));
5126         dev_info(adev->dev, "  RLC_UCODE_CNTL=0x%08X\n",
5127                  RREG32(mmRLC_UCODE_CNTL));
5128
5129         if (adev->asic_type == CHIP_BONAIRE)
5130                 dev_info(adev->dev, "  RLC_DRIVER_CPDMA_STATUS=0x%08X\n",
5131                          RREG32(mmRLC_DRIVER_CPDMA_STATUS));
5132
5133         mutex_lock(&adev->srbm_mutex);
5134         for (i = 0; i < 16; i++) {
5135                 cik_srbm_select(adev, 0, 0, 0, i);
5136                 dev_info(adev->dev, "  VM %d:\n", i);
5137                 dev_info(adev->dev, "  SH_MEM_CONFIG=0x%08X\n",
5138                          RREG32(mmSH_MEM_CONFIG));
5139                 dev_info(adev->dev, "  SH_MEM_APE1_BASE=0x%08X\n",
5140                          RREG32(mmSH_MEM_APE1_BASE));
5141                 dev_info(adev->dev, "  SH_MEM_APE1_LIMIT=0x%08X\n",
5142                          RREG32(mmSH_MEM_APE1_LIMIT));
5143                 dev_info(adev->dev, "  SH_MEM_BASES=0x%08X\n",
5144                          RREG32(mmSH_MEM_BASES));
5145         }
5146         cik_srbm_select(adev, 0, 0, 0, 0);
5147         mutex_unlock(&adev->srbm_mutex);
5148 }
5149
5150 static int gfx_v7_0_soft_reset(struct amdgpu_device *adev)
5151 {
5152         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
5153         u32 tmp;
5154
5155         /* GRBM_STATUS */
5156         tmp = RREG32(mmGRBM_STATUS);
5157         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
5158                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
5159                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
5160                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
5161                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
5162                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK))
5163                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK |
5164                         GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK;
5165
5166         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
5167                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK;
5168                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
5169         }
5170
5171         /* GRBM_STATUS2 */
5172         tmp = RREG32(mmGRBM_STATUS2);
5173         if (tmp & GRBM_STATUS2__RLC_BUSY_MASK)
5174                 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK;
5175
5176         /* SRBM_STATUS */
5177         tmp = RREG32(mmSRBM_STATUS);
5178         if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK)
5179                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
5180
5181         if (grbm_soft_reset || srbm_soft_reset) {
5182                 gfx_v7_0_print_status(adev);
5183                 /* disable CG/PG */
5184                 gfx_v7_0_fini_pg(adev);
5185                 gfx_v7_0_update_cg(adev, false);
5186
5187                 /* stop the rlc */
5188                 gfx_v7_0_rlc_stop(adev);
5189
5190                 /* Disable GFX parsing/prefetching */
5191                 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK);
5192
5193                 /* Disable MEC parsing/prefetching */
5194                 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK);
5195
5196                 if (grbm_soft_reset) {
5197                         tmp = RREG32(mmGRBM_SOFT_RESET);
5198                         tmp |= grbm_soft_reset;
5199                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
5200                         WREG32(mmGRBM_SOFT_RESET, tmp);
5201                         tmp = RREG32(mmGRBM_SOFT_RESET);
5202
5203                         udelay(50);
5204
5205                         tmp &= ~grbm_soft_reset;
5206                         WREG32(mmGRBM_SOFT_RESET, tmp);
5207                         tmp = RREG32(mmGRBM_SOFT_RESET);
5208                 }
5209
5210                 if (srbm_soft_reset) {
5211                         tmp = RREG32(mmSRBM_SOFT_RESET);
5212                         tmp |= srbm_soft_reset;
5213                         dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
5214                         WREG32(mmSRBM_SOFT_RESET, tmp);
5215                         tmp = RREG32(mmSRBM_SOFT_RESET);
5216
5217                         udelay(50);
5218
5219                         tmp &= ~srbm_soft_reset;
5220                         WREG32(mmSRBM_SOFT_RESET, tmp);
5221                         tmp = RREG32(mmSRBM_SOFT_RESET);
5222                 }
5223                 /* Wait a little for things to settle down */
5224                 udelay(50);
5225                 gfx_v7_0_print_status(adev);
5226         }
5227         return 0;
5228 }
5229
5230 static void gfx_v7_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
5231                                                  enum amdgpu_interrupt_state state)
5232 {
5233         u32 cp_int_cntl;
5234
5235         switch (state) {
5236         case AMDGPU_IRQ_STATE_DISABLE:
5237                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5238                 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
5239                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5240                 break;
5241         case AMDGPU_IRQ_STATE_ENABLE:
5242                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5243                 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
5244                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5245                 break;
5246         default:
5247                 break;
5248         }
5249 }
5250
5251 static void gfx_v7_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
5252                                                      int me, int pipe,
5253                                                      enum amdgpu_interrupt_state state)
5254 {
5255         u32 mec_int_cntl, mec_int_cntl_reg;
5256
5257         /*
5258          * amdgpu controls only pipe 0 of MEC1. That's why this function only
5259          * handles the setting of interrupts for this specific pipe. All other
5260          * pipes' interrupts are set by amdkfd.
5261          */
5262
5263         if (me == 1) {
5264                 switch (pipe) {
5265                 case 0:
5266                         mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
5267                         break;
5268                 default:
5269                         DRM_DEBUG("invalid pipe %d\n", pipe);
5270                         return;
5271                 }
5272         } else {
5273                 DRM_DEBUG("invalid me %d\n", me);
5274                 return;
5275         }
5276
5277         switch (state) {
5278         case AMDGPU_IRQ_STATE_DISABLE:
5279                 mec_int_cntl = RREG32(mec_int_cntl_reg);
5280                 mec_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
5281                 WREG32(mec_int_cntl_reg, mec_int_cntl);
5282                 break;
5283         case AMDGPU_IRQ_STATE_ENABLE:
5284                 mec_int_cntl = RREG32(mec_int_cntl_reg);
5285                 mec_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
5286                 WREG32(mec_int_cntl_reg, mec_int_cntl);
5287                 break;
5288         default:
5289                 break;
5290         }
5291 }
5292
5293 static int gfx_v7_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
5294                                              struct amdgpu_irq_src *src,
5295                                              unsigned type,
5296                                              enum amdgpu_interrupt_state state)
5297 {
5298         u32 cp_int_cntl;
5299
5300         switch (state) {
5301         case AMDGPU_IRQ_STATE_DISABLE:
5302                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5303                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
5304                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5305                 break;
5306         case AMDGPU_IRQ_STATE_ENABLE:
5307                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5308                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
5309                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5310                 break;
5311         default:
5312                 break;
5313         }
5314
5315         return 0;
5316 }
5317
5318 static int gfx_v7_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5319                                               struct amdgpu_irq_src *src,
5320                                               unsigned type,
5321                                               enum amdgpu_interrupt_state state)
5322 {
5323         u32 cp_int_cntl;
5324
5325         switch (state) {
5326         case AMDGPU_IRQ_STATE_DISABLE:
5327                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5328                 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
5329                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5330                 break;
5331         case AMDGPU_IRQ_STATE_ENABLE:
5332                 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
5333                 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
5334                 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
5335                 break;
5336         default:
5337                 break;
5338         }
5339
5340         return 0;
5341 }
5342
5343 static int gfx_v7_0_set_eop_interrupt_state(struct amdgpu_device *adev,
5344                                             struct amdgpu_irq_src *src,
5345                                             unsigned type,
5346                                             enum amdgpu_interrupt_state state)
5347 {
5348         switch (type) {
5349         case AMDGPU_CP_IRQ_GFX_EOP:
5350                 gfx_v7_0_set_gfx_eop_interrupt_state(adev, state);
5351                 break;
5352         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
5353                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
5354                 break;
5355         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
5356                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
5357                 break;
5358         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
5359                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
5360                 break;
5361         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
5362                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
5363                 break;
5364         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
5365                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
5366                 break;
5367         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
5368                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
5369                 break;
5370         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
5371                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
5372                 break;
5373         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
5374                 gfx_v7_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
5375                 break;
5376         default:
5377                 break;
5378         }
5379         return 0;
5380 }
5381
5382 static int gfx_v7_0_eop_irq(struct amdgpu_device *adev,
5383                             struct amdgpu_irq_src *source,
5384                             struct amdgpu_iv_entry *entry)
5385 {
5386         u8 me_id, pipe_id;
5387         struct amdgpu_ring *ring;
5388         int i;
5389
5390         DRM_DEBUG("IH: CP EOP\n");
5391         me_id = (entry->ring_id & 0x0c) >> 2;
5392         pipe_id = (entry->ring_id & 0x03) >> 0;
5393         switch (me_id) {
5394         case 0:
5395                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5396                 break;
5397         case 1:
5398         case 2:
5399                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5400                         ring = &adev->gfx.compute_ring[i];
5401                         if ((ring->me == me_id) & (ring->pipe == pipe_id))
5402                                 amdgpu_fence_process(ring);
5403                 }
5404                 break;
5405         }
5406         return 0;
5407 }
5408
5409 static int gfx_v7_0_priv_reg_irq(struct amdgpu_device *adev,
5410                                  struct amdgpu_irq_src *source,
5411                                  struct amdgpu_iv_entry *entry)
5412 {
5413         DRM_ERROR("Illegal register access in command stream\n");
5414         schedule_work(&adev->reset_work);
5415         return 0;
5416 }
5417
5418 static int gfx_v7_0_priv_inst_irq(struct amdgpu_device *adev,
5419                                   struct amdgpu_irq_src *source,
5420                                   struct amdgpu_iv_entry *entry)
5421 {
5422         DRM_ERROR("Illegal instruction in command stream\n");
5423         // XXX soft reset the gfx block only
5424         schedule_work(&adev->reset_work);
5425         return 0;
5426 }
5427
5428 static int gfx_v7_0_set_clockgating_state(struct amdgpu_device *adev,
5429                                           enum amdgpu_clockgating_state state)
5430 {
5431         bool gate = false;
5432
5433         if (state == AMDGPU_CG_STATE_GATE)
5434                 gate = true;
5435
5436         gfx_v7_0_enable_gui_idle_interrupt(adev, false);
5437         /* order matters! */
5438         if (gate) {
5439                 gfx_v7_0_enable_mgcg(adev, true);
5440                 gfx_v7_0_enable_cgcg(adev, true);
5441         } else {
5442                 gfx_v7_0_enable_cgcg(adev, false);
5443                 gfx_v7_0_enable_mgcg(adev, false);
5444         }
5445         gfx_v7_0_enable_gui_idle_interrupt(adev, true);
5446
5447         return 0;
5448 }
5449
5450 static int gfx_v7_0_set_powergating_state(struct amdgpu_device *adev,
5451                                           enum amdgpu_powergating_state state)
5452 {
5453         bool gate = false;
5454
5455         if (state == AMDGPU_PG_STATE_GATE)
5456                 gate = true;
5457
5458         if (adev->pg_flags & (AMDGPU_PG_SUPPORT_GFX_PG |
5459                               AMDGPU_PG_SUPPORT_GFX_SMG |
5460                               AMDGPU_PG_SUPPORT_GFX_DMG |
5461                               AMDGPU_PG_SUPPORT_CP |
5462                               AMDGPU_PG_SUPPORT_GDS |
5463                               AMDGPU_PG_SUPPORT_RLC_SMU_HS)) {
5464                 gfx_v7_0_update_gfx_pg(adev, gate);
5465                 if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_PG) {
5466                         gfx_v7_0_enable_cp_pg(adev, gate);
5467                         gfx_v7_0_enable_gds_pg(adev, gate);
5468                 }
5469         }
5470
5471         return 0;
5472 }
5473
5474 const struct amdgpu_ip_funcs gfx_v7_0_ip_funcs = {
5475         .early_init = gfx_v7_0_early_init,
5476         .late_init = NULL,
5477         .sw_init = gfx_v7_0_sw_init,
5478         .sw_fini = gfx_v7_0_sw_fini,
5479         .hw_init = gfx_v7_0_hw_init,
5480         .hw_fini = gfx_v7_0_hw_fini,
5481         .suspend = gfx_v7_0_suspend,
5482         .resume = gfx_v7_0_resume,
5483         .is_idle = gfx_v7_0_is_idle,
5484         .wait_for_idle = gfx_v7_0_wait_for_idle,
5485         .soft_reset = gfx_v7_0_soft_reset,
5486         .print_status = gfx_v7_0_print_status,
5487         .set_clockgating_state = gfx_v7_0_set_clockgating_state,
5488         .set_powergating_state = gfx_v7_0_set_powergating_state,
5489 };
5490
5491 /**
5492  * gfx_v7_0_ring_is_lockup - check if the 3D engine is locked up
5493  *
5494  * @adev: amdgpu_device pointer
5495  * @ring: amdgpu_ring structure holding ring information
5496  *
5497  * Check if the 3D engine is locked up (CIK).
5498  * Returns true if the engine is locked, false if not.
5499  */
5500 static bool gfx_v7_0_ring_is_lockup(struct amdgpu_ring *ring)
5501 {
5502         if (gfx_v7_0_is_idle(ring->adev)) {
5503                 amdgpu_ring_lockup_update(ring);
5504                 return false;
5505         }
5506         return amdgpu_ring_test_lockup(ring);
5507 }
5508
5509 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
5510         .get_rptr = gfx_v7_0_ring_get_rptr_gfx,
5511         .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
5512         .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
5513         .parse_cs = NULL,
5514         .emit_ib = gfx_v7_0_ring_emit_ib,
5515         .emit_fence = gfx_v7_0_ring_emit_fence_gfx,
5516         .emit_semaphore = gfx_v7_0_ring_emit_semaphore,
5517         .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5518         .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5519         .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
5520         .test_ring = gfx_v7_0_ring_test_ring,
5521         .test_ib = gfx_v7_0_ring_test_ib,
5522         .is_lockup = gfx_v7_0_ring_is_lockup,
5523 };
5524
5525 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
5526         .get_rptr = gfx_v7_0_ring_get_rptr_compute,
5527         .get_wptr = gfx_v7_0_ring_get_wptr_compute,
5528         .set_wptr = gfx_v7_0_ring_set_wptr_compute,
5529         .parse_cs = NULL,
5530         .emit_ib = gfx_v7_0_ring_emit_ib,
5531         .emit_fence = gfx_v7_0_ring_emit_fence_compute,
5532         .emit_semaphore = gfx_v7_0_ring_emit_semaphore,
5533         .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush,
5534         .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch,
5535         .test_ring = gfx_v7_0_ring_test_ring,
5536         .test_ib = gfx_v7_0_ring_test_ib,
5537         .is_lockup = gfx_v7_0_ring_is_lockup,
5538 };
5539
5540 static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev)
5541 {
5542         int i;
5543
5544         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5545                 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx;
5546         for (i = 0; i < adev->gfx.num_compute_rings; i++)
5547                 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute;
5548 }
5549
5550 static const struct amdgpu_irq_src_funcs gfx_v7_0_eop_irq_funcs = {
5551         .set = gfx_v7_0_set_eop_interrupt_state,
5552         .process = gfx_v7_0_eop_irq,
5553 };
5554
5555 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_reg_irq_funcs = {
5556         .set = gfx_v7_0_set_priv_reg_fault_state,
5557         .process = gfx_v7_0_priv_reg_irq,
5558 };
5559
5560 static const struct amdgpu_irq_src_funcs gfx_v7_0_priv_inst_irq_funcs = {
5561         .set = gfx_v7_0_set_priv_inst_fault_state,
5562         .process = gfx_v7_0_priv_inst_irq,
5563 };
5564
5565 static void gfx_v7_0_set_irq_funcs(struct amdgpu_device *adev)
5566 {
5567         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
5568         adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs;
5569
5570         adev->gfx.priv_reg_irq.num_types = 1;
5571         adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs;
5572
5573         adev->gfx.priv_inst_irq.num_types = 1;
5574         adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs;
5575 }
5576
5577 static void gfx_v7_0_set_gds_init(struct amdgpu_device *adev)
5578 {
5579         /* init asci gds info */
5580         adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
5581         adev->gds.gws.total_size = 64;
5582         adev->gds.oa.total_size = 16;
5583
5584         if (adev->gds.mem.total_size == 64 * 1024) {
5585                 adev->gds.mem.gfx_partition_size = 4096;
5586                 adev->gds.mem.cs_partition_size = 4096;
5587
5588                 adev->gds.gws.gfx_partition_size = 4;
5589                 adev->gds.gws.cs_partition_size = 4;
5590
5591                 adev->gds.oa.gfx_partition_size = 4;
5592                 adev->gds.oa.cs_partition_size = 1;
5593         } else {
5594                 adev->gds.mem.gfx_partition_size = 1024;
5595                 adev->gds.mem.cs_partition_size = 1024;
5596
5597                 adev->gds.gws.gfx_partition_size = 16;
5598                 adev->gds.gws.cs_partition_size = 16;
5599
5600                 adev->gds.oa.gfx_partition_size = 4;
5601                 adev->gds.oa.cs_partition_size = 4;
5602         }
5603 }
5604
5605
5606 int gfx_v7_0_get_cu_info(struct amdgpu_device *adev,
5607                                                                    struct amdgpu_cu_info *cu_info)
5608 {
5609         int i, j, k, counter, active_cu_number = 0;
5610         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
5611
5612         if (!adev || !cu_info)
5613                 return -EINVAL;
5614
5615         mutex_lock(&adev->grbm_idx_mutex);
5616         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
5617                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
5618                         mask = 1;
5619                         ao_bitmap = 0;
5620                         counter = 0;
5621                         bitmap = gfx_v7_0_get_cu_active_bitmap(adev, i, j);
5622                         cu_info->bitmap[i][j] = bitmap;
5623
5624                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
5625                                 if (bitmap & mask) {
5626                                         if (counter < 2)
5627                                                 ao_bitmap |= mask;
5628                                         counter ++;
5629                                 }
5630                                 mask <<= 1;
5631                         }
5632                         active_cu_number += counter;
5633                         ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
5634                 }
5635         }
5636
5637         cu_info->number = active_cu_number;
5638         cu_info->ao_cu_mask = ao_cu_mask;
5639         mutex_unlock(&adev->grbm_idx_mutex);
5640         return 0;
5641 }