2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
26 #include "amdgpu_gfx.h"
29 #include "amdgpu_ucode.h"
30 #include "clearstate_vi.h"
32 #include "gmc/gmc_8_2_d.h"
33 #include "gmc/gmc_8_2_sh_mask.h"
35 #include "oss/oss_3_0_d.h"
36 #include "oss/oss_3_0_sh_mask.h"
38 #include "bif/bif_5_0_d.h"
39 #include "bif/bif_5_0_sh_mask.h"
41 #include "gca/gfx_8_0_d.h"
42 #include "gca/gfx_8_0_enum.h"
43 #include "gca/gfx_8_0_sh_mask.h"
44 #include "gca/gfx_8_0_enum.h"
46 #include "uvd/uvd_5_0_d.h"
47 #include "uvd/uvd_5_0_sh_mask.h"
49 #include "dce/dce_10_0_d.h"
50 #include "dce/dce_10_0_sh_mask.h"
52 #define GFX8_NUM_GFX_RINGS 1
53 #define GFX8_NUM_COMPUTE_RINGS 8
55 #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001
56 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001
57 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003
59 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
60 #define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
61 #define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
62 #define MICRO_TILE_MODE_NEW(x) ((x) << GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT)
63 #define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
64 #define BANK_WIDTH(x) ((x) << GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT)
65 #define BANK_HEIGHT(x) ((x) << GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT)
66 #define MACRO_TILE_ASPECT(x) ((x) << GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT)
67 #define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT)
69 MODULE_FIRMWARE("amdgpu/carrizo_ce.bin");
70 MODULE_FIRMWARE("amdgpu/carrizo_pfp.bin");
71 MODULE_FIRMWARE("amdgpu/carrizo_me.bin");
72 MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
73 MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
74 MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
76 MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
77 MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
78 MODULE_FIRMWARE("amdgpu/stoney_me.bin");
79 MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
80 MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
82 MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
83 MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
84 MODULE_FIRMWARE("amdgpu/tonga_me.bin");
85 MODULE_FIRMWARE("amdgpu/tonga_mec.bin");
86 MODULE_FIRMWARE("amdgpu/tonga_mec2.bin");
87 MODULE_FIRMWARE("amdgpu/tonga_rlc.bin");
89 MODULE_FIRMWARE("amdgpu/topaz_ce.bin");
90 MODULE_FIRMWARE("amdgpu/topaz_pfp.bin");
91 MODULE_FIRMWARE("amdgpu/topaz_me.bin");
92 MODULE_FIRMWARE("amdgpu/topaz_mec.bin");
93 MODULE_FIRMWARE("amdgpu/topaz_mec2.bin");
94 MODULE_FIRMWARE("amdgpu/topaz_rlc.bin");
96 MODULE_FIRMWARE("amdgpu/fiji_ce.bin");
97 MODULE_FIRMWARE("amdgpu/fiji_pfp.bin");
98 MODULE_FIRMWARE("amdgpu/fiji_me.bin");
99 MODULE_FIRMWARE("amdgpu/fiji_mec.bin");
100 MODULE_FIRMWARE("amdgpu/fiji_mec2.bin");
101 MODULE_FIRMWARE("amdgpu/fiji_rlc.bin");
103 static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
105 {mmGDS_VMID0_BASE, mmGDS_VMID0_SIZE, mmGDS_GWS_VMID0, mmGDS_OA_VMID0},
106 {mmGDS_VMID1_BASE, mmGDS_VMID1_SIZE, mmGDS_GWS_VMID1, mmGDS_OA_VMID1},
107 {mmGDS_VMID2_BASE, mmGDS_VMID2_SIZE, mmGDS_GWS_VMID2, mmGDS_OA_VMID2},
108 {mmGDS_VMID3_BASE, mmGDS_VMID3_SIZE, mmGDS_GWS_VMID3, mmGDS_OA_VMID3},
109 {mmGDS_VMID4_BASE, mmGDS_VMID4_SIZE, mmGDS_GWS_VMID4, mmGDS_OA_VMID4},
110 {mmGDS_VMID5_BASE, mmGDS_VMID5_SIZE, mmGDS_GWS_VMID5, mmGDS_OA_VMID5},
111 {mmGDS_VMID6_BASE, mmGDS_VMID6_SIZE, mmGDS_GWS_VMID6, mmGDS_OA_VMID6},
112 {mmGDS_VMID7_BASE, mmGDS_VMID7_SIZE, mmGDS_GWS_VMID7, mmGDS_OA_VMID7},
113 {mmGDS_VMID8_BASE, mmGDS_VMID8_SIZE, mmGDS_GWS_VMID8, mmGDS_OA_VMID8},
114 {mmGDS_VMID9_BASE, mmGDS_VMID9_SIZE, mmGDS_GWS_VMID9, mmGDS_OA_VMID9},
115 {mmGDS_VMID10_BASE, mmGDS_VMID10_SIZE, mmGDS_GWS_VMID10, mmGDS_OA_VMID10},
116 {mmGDS_VMID11_BASE, mmGDS_VMID11_SIZE, mmGDS_GWS_VMID11, mmGDS_OA_VMID11},
117 {mmGDS_VMID12_BASE, mmGDS_VMID12_SIZE, mmGDS_GWS_VMID12, mmGDS_OA_VMID12},
118 {mmGDS_VMID13_BASE, mmGDS_VMID13_SIZE, mmGDS_GWS_VMID13, mmGDS_OA_VMID13},
119 {mmGDS_VMID14_BASE, mmGDS_VMID14_SIZE, mmGDS_GWS_VMID14, mmGDS_OA_VMID14},
120 {mmGDS_VMID15_BASE, mmGDS_VMID15_SIZE, mmGDS_GWS_VMID15, mmGDS_OA_VMID15}
123 static const u32 golden_settings_tonga_a11[] =
125 mmCB_HW_CONTROL, 0xfffdf3cf, 0x00007208,
126 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
127 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
128 mmGB_GPU_ID, 0x0000000f, 0x00000000,
129 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
130 mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
131 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
132 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
133 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
134 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
135 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
136 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000002fb,
137 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b,
138 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
139 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
142 static const u32 tonga_golden_common_all[] =
144 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
145 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
146 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002A,
147 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
148 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
149 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
150 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
151 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
154 static const u32 tonga_mgcg_cgcg_init[] =
156 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
157 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
158 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
159 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
160 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
161 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
162 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
163 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
164 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
165 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
166 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
167 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
168 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
169 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
170 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
171 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
172 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
173 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
174 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
175 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
176 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
177 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
178 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
179 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
180 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
181 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
182 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
183 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
184 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
185 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
186 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
187 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
188 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
189 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
190 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
191 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
192 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
193 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
194 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
195 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
196 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
197 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
198 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
199 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
200 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
201 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
202 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
203 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
204 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
205 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
206 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
207 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
208 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
209 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
210 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
211 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
212 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
213 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
214 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
215 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
216 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
217 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
218 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
219 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
220 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
221 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
222 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
223 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
224 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
225 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
226 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
227 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
228 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
229 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
230 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
233 static const u32 fiji_golden_common_all[] =
235 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
236 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
237 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
238 mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
239 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
240 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
241 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
242 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
243 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
244 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
247 static const u32 golden_settings_fiji_a10[] =
249 mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
250 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
251 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
252 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
253 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
254 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
255 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
256 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
257 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
258 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
259 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
262 static const u32 fiji_mgcg_cgcg_init[] =
264 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
265 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
266 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
267 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
268 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
269 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
270 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
271 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
272 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
273 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
274 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
275 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
276 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
277 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
278 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
279 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
280 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
281 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
282 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
283 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
284 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
285 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
286 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
287 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
288 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
289 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
290 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
291 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
292 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
293 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
294 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
295 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
296 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
297 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
298 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
301 static const u32 golden_settings_iceland_a11[] =
303 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
304 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
305 mmDB_DEBUG3, 0xc0000000, 0xc0000000,
306 mmGB_GPU_ID, 0x0000000f, 0x00000000,
307 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
308 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
309 mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x00000002,
310 mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
311 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
312 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
313 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
314 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
315 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1,
316 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
317 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010,
320 static const u32 iceland_golden_common_all[] =
322 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
323 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
324 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
325 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
326 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
327 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
328 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
329 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
332 static const u32 iceland_mgcg_cgcg_init[] =
334 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
335 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
336 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
337 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
338 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0xc0000100,
339 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0xc0000100,
340 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0xc0000100,
341 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
342 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
343 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
344 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
345 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
346 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
347 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
348 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
349 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
350 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
351 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
352 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
353 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
354 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
355 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
356 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0xff000100,
357 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
358 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
359 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
360 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
361 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
362 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
363 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
364 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
365 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
366 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
367 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
368 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
369 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
370 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
371 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
372 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
373 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
374 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
375 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
376 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
377 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
378 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
379 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
380 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
381 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
382 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
383 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
384 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
385 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
386 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
387 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x0f840f87,
388 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
389 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
390 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
391 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
392 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
393 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
394 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
395 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
396 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
397 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
400 static const u32 cz_golden_settings_a11[] =
402 mmCB_HW_CONTROL_3, 0x00000040, 0x00000040,
403 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
404 mmGB_GPU_ID, 0x0000000f, 0x00000000,
405 mmPA_SC_ENHANCE, 0xffffffff, 0x00000001,
406 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
407 mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
408 mmTA_CNTL_AUX, 0x000f000f, 0x00010000,
409 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
410 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f3,
411 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001302
414 static const u32 cz_golden_common_all[] =
416 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
417 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000002,
418 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
419 mmGB_ADDR_CONFIG, 0xffffffff, 0x22010001,
420 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
421 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
422 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
423 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
426 static const u32 cz_mgcg_cgcg_init[] =
428 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
429 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
430 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
431 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
432 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
433 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
434 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x00000100,
435 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
436 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
437 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
438 mmCGTT_WD_CLK_CTRL, 0xffffffff, 0x06000100,
439 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100,
440 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100,
441 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100,
442 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100,
443 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100,
444 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100,
445 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100,
446 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100,
447 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100,
448 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100,
449 mmCGTT_SX_CLK_CTRL4, 0xffffffff, 0x00000100,
450 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100,
451 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100,
452 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100,
453 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100,
454 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100,
455 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
456 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
457 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100,
458 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
459 mmCGTS_CU0_SP0_CTRL_REG, 0xffffffff, 0x00010000,
460 mmCGTS_CU0_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
461 mmCGTS_CU0_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
462 mmCGTS_CU0_SP1_CTRL_REG, 0xffffffff, 0x00060005,
463 mmCGTS_CU0_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
464 mmCGTS_CU1_SP0_CTRL_REG, 0xffffffff, 0x00010000,
465 mmCGTS_CU1_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
466 mmCGTS_CU1_TA_CTRL_REG, 0xffffffff, 0x00040007,
467 mmCGTS_CU1_SP1_CTRL_REG, 0xffffffff, 0x00060005,
468 mmCGTS_CU1_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
469 mmCGTS_CU2_SP0_CTRL_REG, 0xffffffff, 0x00010000,
470 mmCGTS_CU2_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
471 mmCGTS_CU2_TA_CTRL_REG, 0xffffffff, 0x00040007,
472 mmCGTS_CU2_SP1_CTRL_REG, 0xffffffff, 0x00060005,
473 mmCGTS_CU2_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
474 mmCGTS_CU3_SP0_CTRL_REG, 0xffffffff, 0x00010000,
475 mmCGTS_CU3_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
476 mmCGTS_CU3_TA_CTRL_REG, 0xffffffff, 0x00040007,
477 mmCGTS_CU3_SP1_CTRL_REG, 0xffffffff, 0x00060005,
478 mmCGTS_CU3_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
479 mmCGTS_CU4_SP0_CTRL_REG, 0xffffffff, 0x00010000,
480 mmCGTS_CU4_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
481 mmCGTS_CU4_TA_SQC_CTRL_REG, 0xffffffff, 0x00040007,
482 mmCGTS_CU4_SP1_CTRL_REG, 0xffffffff, 0x00060005,
483 mmCGTS_CU4_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
484 mmCGTS_CU5_SP0_CTRL_REG, 0xffffffff, 0x00010000,
485 mmCGTS_CU5_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
486 mmCGTS_CU5_TA_CTRL_REG, 0xffffffff, 0x00040007,
487 mmCGTS_CU5_SP1_CTRL_REG, 0xffffffff, 0x00060005,
488 mmCGTS_CU5_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
489 mmCGTS_CU6_SP0_CTRL_REG, 0xffffffff, 0x00010000,
490 mmCGTS_CU6_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
491 mmCGTS_CU6_TA_CTRL_REG, 0xffffffff, 0x00040007,
492 mmCGTS_CU6_SP1_CTRL_REG, 0xffffffff, 0x00060005,
493 mmCGTS_CU6_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
494 mmCGTS_CU7_SP0_CTRL_REG, 0xffffffff, 0x00010000,
495 mmCGTS_CU7_LDS_SQ_CTRL_REG, 0xffffffff, 0x00030002,
496 mmCGTS_CU7_TA_CTRL_REG, 0xffffffff, 0x00040007,
497 mmCGTS_CU7_SP1_CTRL_REG, 0xffffffff, 0x00060005,
498 mmCGTS_CU7_TD_TCP_CTRL_REG, 0xffffffff, 0x00090008,
499 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
500 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
501 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
502 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
505 static const u32 stoney_golden_settings_a11[] =
507 mmDB_DEBUG2, 0xf00fffff, 0x00000400,
508 mmGB_GPU_ID, 0x0000000f, 0x00000000,
509 mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
510 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
511 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
512 mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
513 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
514 mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
515 mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
516 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
519 static const u32 stoney_golden_common_all[] =
521 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
522 mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
523 mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
524 mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
525 mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
526 mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
527 mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
528 mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
531 static const u32 stoney_mgcg_cgcg_init[] =
533 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
534 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
535 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
536 mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
537 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
538 mmATC_MISC_CG, 0xffffffff, 0x000c0200,
541 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
542 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
543 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
545 static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
547 switch (adev->asic_type) {
549 amdgpu_program_register_sequence(adev,
550 iceland_mgcg_cgcg_init,
551 (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
552 amdgpu_program_register_sequence(adev,
553 golden_settings_iceland_a11,
554 (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
555 amdgpu_program_register_sequence(adev,
556 iceland_golden_common_all,
557 (const u32)ARRAY_SIZE(iceland_golden_common_all));
560 amdgpu_program_register_sequence(adev,
562 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
563 amdgpu_program_register_sequence(adev,
564 golden_settings_fiji_a10,
565 (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
566 amdgpu_program_register_sequence(adev,
567 fiji_golden_common_all,
568 (const u32)ARRAY_SIZE(fiji_golden_common_all));
572 amdgpu_program_register_sequence(adev,
573 tonga_mgcg_cgcg_init,
574 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
575 amdgpu_program_register_sequence(adev,
576 golden_settings_tonga_a11,
577 (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
578 amdgpu_program_register_sequence(adev,
579 tonga_golden_common_all,
580 (const u32)ARRAY_SIZE(tonga_golden_common_all));
583 amdgpu_program_register_sequence(adev,
585 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
586 amdgpu_program_register_sequence(adev,
587 cz_golden_settings_a11,
588 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
589 amdgpu_program_register_sequence(adev,
590 cz_golden_common_all,
591 (const u32)ARRAY_SIZE(cz_golden_common_all));
594 amdgpu_program_register_sequence(adev,
595 stoney_mgcg_cgcg_init,
596 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
597 amdgpu_program_register_sequence(adev,
598 stoney_golden_settings_a11,
599 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
600 amdgpu_program_register_sequence(adev,
601 stoney_golden_common_all,
602 (const u32)ARRAY_SIZE(stoney_golden_common_all));
609 static void gfx_v8_0_scratch_init(struct amdgpu_device *adev)
613 adev->gfx.scratch.num_reg = 7;
614 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
615 for (i = 0; i < adev->gfx.scratch.num_reg; i++) {
616 adev->gfx.scratch.free[i] = true;
617 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i;
621 static int gfx_v8_0_ring_test_ring(struct amdgpu_ring *ring)
623 struct amdgpu_device *adev = ring->adev;
629 r = amdgpu_gfx_scratch_get(adev, &scratch);
631 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
634 WREG32(scratch, 0xCAFEDEAD);
635 r = amdgpu_ring_lock(ring, 3);
637 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
639 amdgpu_gfx_scratch_free(adev, scratch);
642 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
643 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
644 amdgpu_ring_write(ring, 0xDEADBEEF);
645 amdgpu_ring_unlock_commit(ring);
647 for (i = 0; i < adev->usec_timeout; i++) {
648 tmp = RREG32(scratch);
649 if (tmp == 0xDEADBEEF)
653 if (i < adev->usec_timeout) {
654 DRM_INFO("ring test on %d succeeded in %d usecs\n",
657 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
658 ring->idx, scratch, tmp);
661 amdgpu_gfx_scratch_free(adev, scratch);
665 static int gfx_v8_0_ring_test_ib(struct amdgpu_ring *ring)
667 struct amdgpu_device *adev = ring->adev;
669 struct fence *f = NULL;
675 r = amdgpu_gfx_scratch_get(adev, &scratch);
677 DRM_ERROR("amdgpu: failed to get scratch reg (%d).\n", r);
680 WREG32(scratch, 0xCAFEDEAD);
681 memset(&ib, 0, sizeof(ib));
682 r = amdgpu_ib_get(ring, NULL, 256, &ib);
684 DRM_ERROR("amdgpu: failed to get ib (%d).\n", r);
687 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
688 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
689 ib.ptr[2] = 0xDEADBEEF;
692 r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, &ib, 1, NULL,
693 AMDGPU_FENCE_OWNER_UNDEFINED,
698 r = fence_wait(f, false);
700 DRM_ERROR("amdgpu: fence wait failed (%d).\n", r);
703 for (i = 0; i < adev->usec_timeout; i++) {
704 tmp = RREG32(scratch);
705 if (tmp == 0xDEADBEEF)
709 if (i < adev->usec_timeout) {
710 DRM_INFO("ib test on ring %d succeeded in %u usecs\n",
714 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
720 amdgpu_ib_free(adev, &ib);
722 amdgpu_gfx_scratch_free(adev, scratch);
726 static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
728 const char *chip_name;
731 struct amdgpu_firmware_info *info = NULL;
732 const struct common_firmware_header *header = NULL;
733 const struct gfx_firmware_header_v1_0 *cp_hdr;
737 switch (adev->asic_type) {
745 chip_name = "carrizo";
751 chip_name = "stoney";
757 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
758 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
761 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
764 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
765 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
766 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
768 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
769 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
772 err = amdgpu_ucode_validate(adev->gfx.me_fw);
775 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
776 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
777 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
779 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
780 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
783 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
786 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
787 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
788 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
790 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
791 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
794 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
795 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
796 adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
797 adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
799 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
800 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
803 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
806 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
807 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
808 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
810 if (adev->asic_type != CHIP_STONEY) {
811 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
812 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
814 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
817 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
818 adev->gfx.mec2_fw->data;
819 adev->gfx.mec2_fw_version =
820 le32_to_cpu(cp_hdr->header.ucode_version);
821 adev->gfx.mec2_feature_version =
822 le32_to_cpu(cp_hdr->ucode_feature_version);
825 adev->gfx.mec2_fw = NULL;
829 if (adev->firmware.smu_load) {
830 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
831 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
832 info->fw = adev->gfx.pfp_fw;
833 header = (const struct common_firmware_header *)info->fw->data;
834 adev->firmware.fw_size +=
835 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
837 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
838 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
839 info->fw = adev->gfx.me_fw;
840 header = (const struct common_firmware_header *)info->fw->data;
841 adev->firmware.fw_size +=
842 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
844 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
845 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
846 info->fw = adev->gfx.ce_fw;
847 header = (const struct common_firmware_header *)info->fw->data;
848 adev->firmware.fw_size +=
849 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
851 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
852 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
853 info->fw = adev->gfx.rlc_fw;
854 header = (const struct common_firmware_header *)info->fw->data;
855 adev->firmware.fw_size +=
856 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
858 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
859 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
860 info->fw = adev->gfx.mec_fw;
861 header = (const struct common_firmware_header *)info->fw->data;
862 adev->firmware.fw_size +=
863 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
865 if (adev->gfx.mec2_fw) {
866 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
867 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
868 info->fw = adev->gfx.mec2_fw;
869 header = (const struct common_firmware_header *)info->fw->data;
870 adev->firmware.fw_size +=
871 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
879 "gfx8: Failed to load firmware \"%s\"\n",
881 release_firmware(adev->gfx.pfp_fw);
882 adev->gfx.pfp_fw = NULL;
883 release_firmware(adev->gfx.me_fw);
884 adev->gfx.me_fw = NULL;
885 release_firmware(adev->gfx.ce_fw);
886 adev->gfx.ce_fw = NULL;
887 release_firmware(adev->gfx.rlc_fw);
888 adev->gfx.rlc_fw = NULL;
889 release_firmware(adev->gfx.mec_fw);
890 adev->gfx.mec_fw = NULL;
891 release_firmware(adev->gfx.mec2_fw);
892 adev->gfx.mec2_fw = NULL;
897 static void gfx_v8_0_mec_fini(struct amdgpu_device *adev)
901 if (adev->gfx.mec.hpd_eop_obj) {
902 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
903 if (unlikely(r != 0))
904 dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
905 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
906 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
908 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
909 adev->gfx.mec.hpd_eop_obj = NULL;
913 #define MEC_HPD_SIZE 2048
915 static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
921 * we assign only 1 pipe because all other pipes will
924 adev->gfx.mec.num_mec = 1;
925 adev->gfx.mec.num_pipe = 1;
926 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8;
928 if (adev->gfx.mec.hpd_eop_obj == NULL) {
929 r = amdgpu_bo_create(adev,
930 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
932 AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
933 &adev->gfx.mec.hpd_eop_obj);
935 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
940 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
941 if (unlikely(r != 0)) {
942 gfx_v8_0_mec_fini(adev);
945 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
946 &adev->gfx.mec.hpd_eop_gpu_addr);
948 dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
949 gfx_v8_0_mec_fini(adev);
952 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
954 dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
955 gfx_v8_0_mec_fini(adev);
959 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
961 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
962 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
967 static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
970 u32 mc_shared_chmap, mc_arb_ramcfg;
971 u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
974 switch (adev->asic_type) {
976 adev->gfx.config.max_shader_engines = 1;
977 adev->gfx.config.max_tile_pipes = 2;
978 adev->gfx.config.max_cu_per_sh = 6;
979 adev->gfx.config.max_sh_per_se = 1;
980 adev->gfx.config.max_backends_per_se = 2;
981 adev->gfx.config.max_texture_channel_caches = 2;
982 adev->gfx.config.max_gprs = 256;
983 adev->gfx.config.max_gs_threads = 32;
984 adev->gfx.config.max_hw_contexts = 8;
986 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
987 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
988 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
989 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
990 gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
993 adev->gfx.config.max_shader_engines = 4;
994 adev->gfx.config.max_tile_pipes = 16;
995 adev->gfx.config.max_cu_per_sh = 16;
996 adev->gfx.config.max_sh_per_se = 1;
997 adev->gfx.config.max_backends_per_se = 4;
998 adev->gfx.config.max_texture_channel_caches = 8;
999 adev->gfx.config.max_gprs = 256;
1000 adev->gfx.config.max_gs_threads = 32;
1001 adev->gfx.config.max_hw_contexts = 8;
1003 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1004 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1005 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1006 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1007 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1010 adev->gfx.config.max_shader_engines = 4;
1011 adev->gfx.config.max_tile_pipes = 8;
1012 adev->gfx.config.max_cu_per_sh = 8;
1013 adev->gfx.config.max_sh_per_se = 1;
1014 adev->gfx.config.max_backends_per_se = 2;
1015 adev->gfx.config.max_texture_channel_caches = 8;
1016 adev->gfx.config.max_gprs = 256;
1017 adev->gfx.config.max_gs_threads = 32;
1018 adev->gfx.config.max_hw_contexts = 8;
1020 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1021 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1022 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1023 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1024 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1027 adev->gfx.config.max_shader_engines = 1;
1028 adev->gfx.config.max_tile_pipes = 2;
1029 adev->gfx.config.max_sh_per_se = 1;
1030 adev->gfx.config.max_backends_per_se = 2;
1032 switch (adev->pdev->revision) {
1040 adev->gfx.config.max_cu_per_sh = 8;
1050 adev->gfx.config.max_cu_per_sh = 6;
1057 adev->gfx.config.max_cu_per_sh = 6;
1066 adev->gfx.config.max_cu_per_sh = 4;
1070 adev->gfx.config.max_texture_channel_caches = 2;
1071 adev->gfx.config.max_gprs = 256;
1072 adev->gfx.config.max_gs_threads = 32;
1073 adev->gfx.config.max_hw_contexts = 8;
1075 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1076 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1077 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1078 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1079 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1082 adev->gfx.config.max_shader_engines = 1;
1083 adev->gfx.config.max_tile_pipes = 2;
1084 adev->gfx.config.max_sh_per_se = 1;
1085 adev->gfx.config.max_backends_per_se = 1;
1087 switch (adev->pdev->revision) {
1094 adev->gfx.config.max_cu_per_sh = 3;
1100 adev->gfx.config.max_cu_per_sh = 2;
1104 adev->gfx.config.max_texture_channel_caches = 2;
1105 adev->gfx.config.max_gprs = 256;
1106 adev->gfx.config.max_gs_threads = 16;
1107 adev->gfx.config.max_hw_contexts = 8;
1109 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1110 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1111 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1112 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1113 gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
1116 adev->gfx.config.max_shader_engines = 2;
1117 adev->gfx.config.max_tile_pipes = 4;
1118 adev->gfx.config.max_cu_per_sh = 2;
1119 adev->gfx.config.max_sh_per_se = 1;
1120 adev->gfx.config.max_backends_per_se = 2;
1121 adev->gfx.config.max_texture_channel_caches = 4;
1122 adev->gfx.config.max_gprs = 256;
1123 adev->gfx.config.max_gs_threads = 32;
1124 adev->gfx.config.max_hw_contexts = 8;
1126 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1127 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1128 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1129 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1130 gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
1134 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1135 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1136 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1138 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1139 adev->gfx.config.mem_max_burst_length_bytes = 256;
1140 if (adev->flags & AMD_IS_APU) {
1141 /* Get memory bank mapping mode. */
1142 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
1143 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1144 dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1146 tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
1147 dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
1148 dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
1150 /* Validate settings in case only one DIMM installed. */
1151 if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
1152 dimm00_addr_map = 0;
1153 if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
1154 dimm01_addr_map = 0;
1155 if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
1156 dimm10_addr_map = 0;
1157 if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
1158 dimm11_addr_map = 0;
1160 /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
1161 /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
1162 if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
1163 adev->gfx.config.mem_row_size_in_kb = 2;
1165 adev->gfx.config.mem_row_size_in_kb = 1;
1167 tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
1168 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1169 if (adev->gfx.config.mem_row_size_in_kb > 4)
1170 adev->gfx.config.mem_row_size_in_kb = 4;
1173 adev->gfx.config.shader_engine_tile_size = 32;
1174 adev->gfx.config.num_gpus = 1;
1175 adev->gfx.config.multi_gpu_tile_size = 64;
1177 /* fix up row size */
1178 switch (adev->gfx.config.mem_row_size_in_kb) {
1181 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
1184 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
1187 gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
1190 adev->gfx.config.gb_addr_config = gb_addr_config;
1193 static int gfx_v8_0_sw_init(void *handle)
1196 struct amdgpu_ring *ring;
1197 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1200 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
1204 /* Privileged reg */
1205 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
1209 /* Privileged inst */
1210 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
1214 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1216 gfx_v8_0_scratch_init(adev);
1218 r = gfx_v8_0_init_microcode(adev);
1220 DRM_ERROR("Failed to load gfx firmware!\n");
1224 r = gfx_v8_0_mec_init(adev);
1226 DRM_ERROR("Failed to init MEC BOs!\n");
1230 /* set up the gfx ring */
1231 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1232 ring = &adev->gfx.gfx_ring[i];
1233 ring->ring_obj = NULL;
1234 sprintf(ring->name, "gfx");
1235 /* no gfx doorbells on iceland */
1236 if (adev->asic_type != CHIP_TOPAZ) {
1237 ring->use_doorbell = true;
1238 ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
1241 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
1242 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
1243 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
1244 AMDGPU_RING_TYPE_GFX);
1249 /* set up the compute queues */
1250 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
1253 /* max 32 queues per MEC */
1254 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
1255 DRM_ERROR("Too many (%d) compute rings!\n", i);
1258 ring = &adev->gfx.compute_ring[i];
1259 ring->ring_obj = NULL;
1260 ring->use_doorbell = true;
1261 ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
1262 ring->me = 1; /* first MEC */
1264 ring->queue = i % 8;
1265 sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
1266 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
1267 /* type-2 packets are deprecated on MEC, use type-3 instead */
1268 r = amdgpu_ring_init(adev, ring, 1024 * 1024,
1269 PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
1270 &adev->gfx.eop_irq, irq_type,
1271 AMDGPU_RING_TYPE_COMPUTE);
1276 /* reserve GDS, GWS and OA resource for gfx */
1277 r = amdgpu_bo_create(adev, adev->gds.mem.gfx_partition_size,
1279 AMDGPU_GEM_DOMAIN_GDS, 0, NULL,
1280 NULL, &adev->gds.gds_gfx_bo);
1284 r = amdgpu_bo_create(adev, adev->gds.gws.gfx_partition_size,
1286 AMDGPU_GEM_DOMAIN_GWS, 0, NULL,
1287 NULL, &adev->gds.gws_gfx_bo);
1291 r = amdgpu_bo_create(adev, adev->gds.oa.gfx_partition_size,
1293 AMDGPU_GEM_DOMAIN_OA, 0, NULL,
1294 NULL, &adev->gds.oa_gfx_bo);
1298 adev->gfx.ce_ram_size = 0x8000;
1300 gfx_v8_0_gpu_early_init(adev);
1305 static int gfx_v8_0_sw_fini(void *handle)
1308 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1310 amdgpu_bo_unref(&adev->gds.oa_gfx_bo);
1311 amdgpu_bo_unref(&adev->gds.gws_gfx_bo);
1312 amdgpu_bo_unref(&adev->gds.gds_gfx_bo);
1314 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1315 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1316 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1317 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1319 gfx_v8_0_mec_fini(adev);
1324 static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
1326 const u32 num_tile_mode_states = 32;
1327 const u32 num_secondary_tile_mode_states = 16;
1328 u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
1330 switch (adev->gfx.config.mem_row_size_in_kb) {
1332 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1336 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1339 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1343 switch (adev->asic_type) {
1345 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1346 switch (reg_offset) {
1348 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1349 PIPE_CONFIG(ADDR_SURF_P2) |
1350 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1351 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1354 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1355 PIPE_CONFIG(ADDR_SURF_P2) |
1356 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1357 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1360 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1361 PIPE_CONFIG(ADDR_SURF_P2) |
1362 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1363 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1366 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1367 PIPE_CONFIG(ADDR_SURF_P2) |
1368 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1369 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1372 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1373 PIPE_CONFIG(ADDR_SURF_P2) |
1374 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1375 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1378 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1379 PIPE_CONFIG(ADDR_SURF_P2) |
1380 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1381 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1384 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1385 PIPE_CONFIG(ADDR_SURF_P2) |
1386 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1387 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1390 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1391 PIPE_CONFIG(ADDR_SURF_P2));
1394 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1395 PIPE_CONFIG(ADDR_SURF_P2) |
1396 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1397 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1400 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1401 PIPE_CONFIG(ADDR_SURF_P2) |
1402 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1403 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1406 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1407 PIPE_CONFIG(ADDR_SURF_P2) |
1408 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1409 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1412 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1413 PIPE_CONFIG(ADDR_SURF_P2) |
1414 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1415 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1418 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1419 PIPE_CONFIG(ADDR_SURF_P2) |
1420 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1421 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1424 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1425 PIPE_CONFIG(ADDR_SURF_P2) |
1426 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1427 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1430 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1431 PIPE_CONFIG(ADDR_SURF_P2) |
1432 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1433 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1436 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1437 PIPE_CONFIG(ADDR_SURF_P2) |
1438 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1439 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1442 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1443 PIPE_CONFIG(ADDR_SURF_P2) |
1444 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1445 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1448 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1449 PIPE_CONFIG(ADDR_SURF_P2) |
1450 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1451 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1454 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1455 PIPE_CONFIG(ADDR_SURF_P2) |
1456 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1457 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1460 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1461 PIPE_CONFIG(ADDR_SURF_P2) |
1462 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1463 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1466 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1467 PIPE_CONFIG(ADDR_SURF_P2) |
1468 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1469 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1472 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1473 PIPE_CONFIG(ADDR_SURF_P2) |
1474 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1475 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1478 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1479 PIPE_CONFIG(ADDR_SURF_P2) |
1480 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1481 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1484 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1485 PIPE_CONFIG(ADDR_SURF_P2) |
1486 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1487 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1490 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1491 PIPE_CONFIG(ADDR_SURF_P2) |
1492 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1493 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1496 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1497 PIPE_CONFIG(ADDR_SURF_P2) |
1498 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1499 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1511 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1512 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1514 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1515 switch (reg_offset) {
1517 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1518 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1519 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1520 NUM_BANKS(ADDR_SURF_8_BANK));
1523 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1524 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1525 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1526 NUM_BANKS(ADDR_SURF_8_BANK));
1529 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1530 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1531 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1532 NUM_BANKS(ADDR_SURF_8_BANK));
1535 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1536 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1537 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1538 NUM_BANKS(ADDR_SURF_8_BANK));
1541 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1544 NUM_BANKS(ADDR_SURF_8_BANK));
1547 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1548 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1549 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1550 NUM_BANKS(ADDR_SURF_8_BANK));
1553 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1556 NUM_BANKS(ADDR_SURF_8_BANK));
1559 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1560 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1561 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1562 NUM_BANKS(ADDR_SURF_16_BANK));
1565 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1566 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1567 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1568 NUM_BANKS(ADDR_SURF_16_BANK));
1571 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1572 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1573 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1574 NUM_BANKS(ADDR_SURF_16_BANK));
1577 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1578 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1579 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1580 NUM_BANKS(ADDR_SURF_16_BANK));
1583 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1584 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1585 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1586 NUM_BANKS(ADDR_SURF_16_BANK));
1589 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1590 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1591 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1592 NUM_BANKS(ADDR_SURF_16_BANK));
1595 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1596 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1597 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1598 NUM_BANKS(ADDR_SURF_8_BANK));
1607 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1608 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1612 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1613 switch (reg_offset) {
1615 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1616 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1617 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1618 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1621 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1622 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1623 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1624 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1627 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1628 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1629 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1630 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1633 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1634 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1635 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1636 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1639 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1640 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1641 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1642 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1645 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1646 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1647 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1648 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1651 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1652 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1653 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1654 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1657 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1658 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1659 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1660 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1663 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1664 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
1667 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1668 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1669 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1670 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1673 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1674 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1675 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1676 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1679 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1680 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1681 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1682 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1685 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1686 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1687 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1688 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1691 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1692 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1693 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1694 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1697 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1698 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1699 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1700 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1703 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1704 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1705 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1706 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1709 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1710 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1711 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1712 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1715 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1716 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1717 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1718 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1721 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1722 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1723 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1724 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1727 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1728 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1729 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1730 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1733 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1734 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1735 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1736 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1739 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
1740 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1741 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1742 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1745 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1746 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1747 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1748 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1751 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
1752 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1753 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1754 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1757 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1758 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1759 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1760 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1763 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1764 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1765 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1766 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1769 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
1770 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1771 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
1772 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
1775 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1776 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1777 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1778 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1781 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1782 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1783 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1784 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1787 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1788 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
1789 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1790 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1793 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1794 PIPE_CONFIG(ADDR_SURF_P4_16x16) |
1795 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1796 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1802 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
1803 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
1805 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1806 switch (reg_offset) {
1808 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1809 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1810 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1811 NUM_BANKS(ADDR_SURF_16_BANK));
1814 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1815 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1816 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1817 NUM_BANKS(ADDR_SURF_16_BANK));
1820 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1821 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1822 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1823 NUM_BANKS(ADDR_SURF_16_BANK));
1826 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1827 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1828 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1829 NUM_BANKS(ADDR_SURF_16_BANK));
1832 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1833 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1834 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1835 NUM_BANKS(ADDR_SURF_16_BANK));
1838 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1839 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1840 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1841 NUM_BANKS(ADDR_SURF_16_BANK));
1844 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1845 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1846 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1847 NUM_BANKS(ADDR_SURF_16_BANK));
1850 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1851 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1852 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1853 NUM_BANKS(ADDR_SURF_16_BANK));
1856 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1857 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1858 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1859 NUM_BANKS(ADDR_SURF_16_BANK));
1862 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1863 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1864 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1865 NUM_BANKS(ADDR_SURF_16_BANK));
1868 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1869 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1870 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1871 NUM_BANKS(ADDR_SURF_16_BANK));
1874 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1875 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1876 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1877 NUM_BANKS(ADDR_SURF_8_BANK));
1880 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1881 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1882 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1883 NUM_BANKS(ADDR_SURF_4_BANK));
1886 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1887 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1888 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1889 NUM_BANKS(ADDR_SURF_4_BANK));
1898 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
1899 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
1903 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1904 switch (reg_offset) {
1906 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1907 PIPE_CONFIG(ADDR_SURF_P2) |
1908 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1909 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1912 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1913 PIPE_CONFIG(ADDR_SURF_P2) |
1914 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1915 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1918 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1919 PIPE_CONFIG(ADDR_SURF_P2) |
1920 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1921 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1924 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1925 PIPE_CONFIG(ADDR_SURF_P2) |
1926 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1927 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1930 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1931 PIPE_CONFIG(ADDR_SURF_P2) |
1932 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1933 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1936 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1937 PIPE_CONFIG(ADDR_SURF_P2) |
1938 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1939 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1942 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1943 PIPE_CONFIG(ADDR_SURF_P2) |
1944 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1945 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
1948 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
1949 PIPE_CONFIG(ADDR_SURF_P2));
1952 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1953 PIPE_CONFIG(ADDR_SURF_P2) |
1954 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1955 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1958 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1959 PIPE_CONFIG(ADDR_SURF_P2) |
1960 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1961 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1964 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1965 PIPE_CONFIG(ADDR_SURF_P2) |
1966 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1967 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1970 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1971 PIPE_CONFIG(ADDR_SURF_P2) |
1972 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1973 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1976 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1977 PIPE_CONFIG(ADDR_SURF_P2) |
1978 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1979 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1982 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
1983 PIPE_CONFIG(ADDR_SURF_P2) |
1984 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1985 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1988 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1989 PIPE_CONFIG(ADDR_SURF_P2) |
1990 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1991 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
1994 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1995 PIPE_CONFIG(ADDR_SURF_P2) |
1996 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1997 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2000 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2001 PIPE_CONFIG(ADDR_SURF_P2) |
2002 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2003 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2006 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2007 PIPE_CONFIG(ADDR_SURF_P2) |
2008 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2009 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2012 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2013 PIPE_CONFIG(ADDR_SURF_P2) |
2014 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2015 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2018 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2019 PIPE_CONFIG(ADDR_SURF_P2) |
2020 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2021 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2024 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2025 PIPE_CONFIG(ADDR_SURF_P2) |
2026 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2027 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2030 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2031 PIPE_CONFIG(ADDR_SURF_P2) |
2032 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2033 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2036 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2037 PIPE_CONFIG(ADDR_SURF_P2) |
2038 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2039 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2042 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2043 PIPE_CONFIG(ADDR_SURF_P2) |
2044 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2045 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2048 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2049 PIPE_CONFIG(ADDR_SURF_P2) |
2050 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2051 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2054 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2055 PIPE_CONFIG(ADDR_SURF_P2) |
2056 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2057 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2069 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
2070 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
2072 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
2073 switch (reg_offset) {
2075 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2076 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2077 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2078 NUM_BANKS(ADDR_SURF_8_BANK));
2081 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2082 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2083 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2084 NUM_BANKS(ADDR_SURF_8_BANK));
2087 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2088 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2089 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2090 NUM_BANKS(ADDR_SURF_8_BANK));
2093 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2094 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2095 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2096 NUM_BANKS(ADDR_SURF_8_BANK));
2099 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2100 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2101 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2102 NUM_BANKS(ADDR_SURF_8_BANK));
2105 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2106 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2107 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2108 NUM_BANKS(ADDR_SURF_8_BANK));
2111 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2112 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2113 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2114 NUM_BANKS(ADDR_SURF_8_BANK));
2117 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2118 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2119 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2120 NUM_BANKS(ADDR_SURF_16_BANK));
2123 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2124 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2125 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2126 NUM_BANKS(ADDR_SURF_16_BANK));
2129 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2130 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2131 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2132 NUM_BANKS(ADDR_SURF_16_BANK));
2135 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2136 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2137 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2138 NUM_BANKS(ADDR_SURF_16_BANK));
2141 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2142 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2143 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2144 NUM_BANKS(ADDR_SURF_16_BANK));
2147 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2148 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2149 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2150 NUM_BANKS(ADDR_SURF_16_BANK));
2153 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2154 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2155 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2156 NUM_BANKS(ADDR_SURF_8_BANK));
2165 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
2166 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
2171 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2172 switch (reg_offset) {
2174 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2175 PIPE_CONFIG(ADDR_SURF_P2) |
2176 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
2177 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2180 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2181 PIPE_CONFIG(ADDR_SURF_P2) |
2182 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
2183 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2186 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2187 PIPE_CONFIG(ADDR_SURF_P2) |
2188 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
2189 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2192 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2193 PIPE_CONFIG(ADDR_SURF_P2) |
2194 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
2195 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2198 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2199 PIPE_CONFIG(ADDR_SURF_P2) |
2200 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2201 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2204 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2205 PIPE_CONFIG(ADDR_SURF_P2) |
2206 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2207 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2210 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2211 PIPE_CONFIG(ADDR_SURF_P2) |
2212 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
2213 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2216 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2217 PIPE_CONFIG(ADDR_SURF_P2));
2220 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2221 PIPE_CONFIG(ADDR_SURF_P2) |
2222 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2223 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2226 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2227 PIPE_CONFIG(ADDR_SURF_P2) |
2228 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2229 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2232 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2233 PIPE_CONFIG(ADDR_SURF_P2) |
2234 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2235 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2238 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2239 PIPE_CONFIG(ADDR_SURF_P2) |
2240 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2241 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2244 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2245 PIPE_CONFIG(ADDR_SURF_P2) |
2246 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2247 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2250 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
2251 PIPE_CONFIG(ADDR_SURF_P2) |
2252 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2253 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2256 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2257 PIPE_CONFIG(ADDR_SURF_P2) |
2258 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2259 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2262 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2263 PIPE_CONFIG(ADDR_SURF_P2) |
2264 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2265 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2268 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
2269 PIPE_CONFIG(ADDR_SURF_P2) |
2270 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2271 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2274 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2275 PIPE_CONFIG(ADDR_SURF_P2) |
2276 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2277 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2280 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
2281 PIPE_CONFIG(ADDR_SURF_P2) |
2282 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2283 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2286 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
2287 PIPE_CONFIG(ADDR_SURF_P2) |
2288 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2289 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2292 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
2293 PIPE_CONFIG(ADDR_SURF_P2) |
2294 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2295 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2298 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
2299 PIPE_CONFIG(ADDR_SURF_P2) |
2300 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2301 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2304 gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
2305 PIPE_CONFIG(ADDR_SURF_P2) |
2306 MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
2307 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
2310 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2311 PIPE_CONFIG(ADDR_SURF_P2) |
2312 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2313 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2316 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2317 PIPE_CONFIG(ADDR_SURF_P2) |
2318 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2319 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2322 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2323 PIPE_CONFIG(ADDR_SURF_P2) |
2324 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2325 SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
2337 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
2338 WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
2340 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
2341 switch (reg_offset) {
2343 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2344 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2345 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2346 NUM_BANKS(ADDR_SURF_8_BANK));
2349 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2350 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2351 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2352 NUM_BANKS(ADDR_SURF_8_BANK));
2355 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2356 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2357 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2358 NUM_BANKS(ADDR_SURF_8_BANK));
2361 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2362 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2363 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2364 NUM_BANKS(ADDR_SURF_8_BANK));
2367 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2368 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2369 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2370 NUM_BANKS(ADDR_SURF_8_BANK));
2373 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2374 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2375 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2376 NUM_BANKS(ADDR_SURF_8_BANK));
2379 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2380 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2381 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2382 NUM_BANKS(ADDR_SURF_8_BANK));
2385 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2386 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2387 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2388 NUM_BANKS(ADDR_SURF_16_BANK));
2391 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2392 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2393 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2394 NUM_BANKS(ADDR_SURF_16_BANK));
2397 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2398 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2399 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2400 NUM_BANKS(ADDR_SURF_16_BANK));
2403 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2404 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2405 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2406 NUM_BANKS(ADDR_SURF_16_BANK));
2409 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2410 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2411 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2412 NUM_BANKS(ADDR_SURF_16_BANK));
2415 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2416 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2417 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2418 NUM_BANKS(ADDR_SURF_16_BANK));
2421 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2422 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2423 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2424 NUM_BANKS(ADDR_SURF_8_BANK));
2433 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
2434 WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
2439 static u32 gfx_v8_0_create_bitmask(u32 bit_width)
2443 for (i = 0; i < bit_width; i++) {
2450 void gfx_v8_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num)
2452 u32 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
2454 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) {
2455 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
2456 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
2457 } else if (se_num == 0xffffffff) {
2458 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
2459 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
2460 } else if (sh_num == 0xffffffff) {
2461 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
2462 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
2464 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
2465 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
2467 WREG32(mmGRBM_GFX_INDEX, data);
2470 static u32 gfx_v8_0_get_rb_disabled(struct amdgpu_device *adev,
2471 u32 max_rb_num_per_se,
2476 data = RREG32(mmCC_RB_BACKEND_DISABLE);
2477 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
2479 data |= RREG32(mmGC_USER_RB_BACKEND_DISABLE);
2481 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
2483 mask = gfx_v8_0_create_bitmask(max_rb_num_per_se / sh_per_se);
2488 static void gfx_v8_0_setup_rb(struct amdgpu_device *adev,
2489 u32 se_num, u32 sh_per_se,
2490 u32 max_rb_num_per_se)
2494 u32 disabled_rbs = 0;
2495 u32 enabled_rbs = 0;
2497 mutex_lock(&adev->grbm_idx_mutex);
2498 for (i = 0; i < se_num; i++) {
2499 for (j = 0; j < sh_per_se; j++) {
2500 gfx_v8_0_select_se_sh(adev, i, j);
2501 data = gfx_v8_0_get_rb_disabled(adev,
2502 max_rb_num_per_se, sh_per_se);
2503 disabled_rbs |= data << ((i * sh_per_se + j) *
2504 RB_BITMAP_WIDTH_PER_SH);
2507 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2508 mutex_unlock(&adev->grbm_idx_mutex);
2511 for (i = 0; i < max_rb_num_per_se * se_num; i++) {
2512 if (!(disabled_rbs & mask))
2513 enabled_rbs |= mask;
2517 adev->gfx.config.backend_enable_mask = enabled_rbs;
2519 mutex_lock(&adev->grbm_idx_mutex);
2520 for (i = 0; i < se_num; i++) {
2521 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
2523 for (j = 0; j < sh_per_se; j++) {
2524 switch (enabled_rbs & 3) {
2527 data |= (RASTER_CONFIG_RB_MAP_3 <<
2528 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
2530 data |= (RASTER_CONFIG_RB_MAP_0 <<
2531 PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT);
2534 data |= (RASTER_CONFIG_RB_MAP_0 <<
2535 (i * sh_per_se + j) * 2);
2538 data |= (RASTER_CONFIG_RB_MAP_3 <<
2539 (i * sh_per_se + j) * 2);
2543 data |= (RASTER_CONFIG_RB_MAP_2 <<
2544 (i * sh_per_se + j) * 2);
2549 WREG32(mmPA_SC_RASTER_CONFIG, data);
2551 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2552 mutex_unlock(&adev->grbm_idx_mutex);
2556 * gfx_v8_0_init_compute_vmid - gart enable
2558 * @rdev: amdgpu_device pointer
2560 * Initialize compute vmid sh_mem registers
2563 #define DEFAULT_SH_MEM_BASES (0x6000)
2564 #define FIRST_COMPUTE_VMID (8)
2565 #define LAST_COMPUTE_VMID (16)
2566 static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
2569 uint32_t sh_mem_config;
2570 uint32_t sh_mem_bases;
2573 * Configure apertures:
2574 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
2575 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
2576 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
2578 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
2580 sh_mem_config = SH_MEM_ADDRESS_MODE_HSA64 <<
2581 SH_MEM_CONFIG__ADDRESS_MODE__SHIFT |
2582 SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
2583 SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT |
2584 MTYPE_CC << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT |
2585 SH_MEM_CONFIG__PRIVATE_ATC_MASK;
2587 mutex_lock(&adev->srbm_mutex);
2588 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
2589 vi_srbm_select(adev, 0, 0, 0, i);
2590 /* CP and shaders */
2591 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
2592 WREG32(mmSH_MEM_APE1_BASE, 1);
2593 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2594 WREG32(mmSH_MEM_BASES, sh_mem_bases);
2596 vi_srbm_select(adev, 0, 0, 0, 0);
2597 mutex_unlock(&adev->srbm_mutex);
2600 static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
2605 tmp = RREG32(mmGRBM_CNTL);
2606 tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
2607 WREG32(mmGRBM_CNTL, tmp);
2609 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2610 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2611 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
2612 WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET,
2613 adev->gfx.config.gb_addr_config & 0x70);
2614 WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET,
2615 adev->gfx.config.gb_addr_config & 0x70);
2616 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2617 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2618 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
2620 gfx_v8_0_tiling_mode_table_init(adev);
2622 gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines,
2623 adev->gfx.config.max_sh_per_se,
2624 adev->gfx.config.max_backends_per_se);
2626 /* XXX SH_MEM regs */
2627 /* where to put LDS, scratch, GPUVM in FSA64 space */
2628 mutex_lock(&adev->srbm_mutex);
2629 for (i = 0; i < 16; i++) {
2630 vi_srbm_select(adev, 0, 0, 0, i);
2631 /* CP and shaders */
2633 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
2634 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
2635 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2636 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2637 WREG32(mmSH_MEM_CONFIG, tmp);
2639 tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
2640 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
2641 tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
2642 SH_MEM_ALIGNMENT_MODE_UNALIGNED);
2643 WREG32(mmSH_MEM_CONFIG, tmp);
2646 WREG32(mmSH_MEM_APE1_BASE, 1);
2647 WREG32(mmSH_MEM_APE1_LIMIT, 0);
2648 WREG32(mmSH_MEM_BASES, 0);
2650 vi_srbm_select(adev, 0, 0, 0, 0);
2651 mutex_unlock(&adev->srbm_mutex);
2653 gfx_v8_0_init_compute_vmid(adev);
2655 mutex_lock(&adev->grbm_idx_mutex);
2657 * making sure that the following register writes will be broadcasted
2658 * to all the shaders
2660 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2662 WREG32(mmPA_SC_FIFO_SIZE,
2663 (adev->gfx.config.sc_prim_fifo_size_frontend <<
2664 PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
2665 (adev->gfx.config.sc_prim_fifo_size_backend <<
2666 PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
2667 (adev->gfx.config.sc_hiz_tile_fifo_size <<
2668 PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
2669 (adev->gfx.config.sc_earlyz_tile_fifo_size <<
2670 PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
2671 mutex_unlock(&adev->grbm_idx_mutex);
2675 static void gfx_v8_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2680 mutex_lock(&adev->grbm_idx_mutex);
2681 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
2682 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
2683 gfx_v8_0_select_se_sh(adev, i, j);
2684 for (k = 0; k < adev->usec_timeout; k++) {
2685 if (RREG32(mmRLC_SERDES_CU_MASTER_BUSY) == 0)
2691 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
2692 mutex_unlock(&adev->grbm_idx_mutex);
2694 mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
2695 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
2696 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
2697 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
2698 for (k = 0; k < adev->usec_timeout; k++) {
2699 if ((RREG32(mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
2705 static void gfx_v8_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2708 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2711 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1);
2712 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1);
2713 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1);
2714 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1);
2716 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 0);
2717 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 0);
2718 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 0);
2719 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 0);
2721 WREG32(mmCP_INT_CNTL_RING0, tmp);
2724 void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
2726 u32 tmp = RREG32(mmRLC_CNTL);
2728 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
2729 WREG32(mmRLC_CNTL, tmp);
2731 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
2733 gfx_v8_0_wait_for_rlc_serdes(adev);
2736 static void gfx_v8_0_rlc_reset(struct amdgpu_device *adev)
2738 u32 tmp = RREG32(mmGRBM_SOFT_RESET);
2740 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2741 WREG32(mmGRBM_SOFT_RESET, tmp);
2743 tmp = REG_SET_FIELD(tmp, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2744 WREG32(mmGRBM_SOFT_RESET, tmp);
2748 static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
2750 u32 tmp = RREG32(mmRLC_CNTL);
2752 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 1);
2753 WREG32(mmRLC_CNTL, tmp);
2755 /* carrizo do enable cp interrupt after cp inited */
2756 if (!(adev->flags & AMD_IS_APU))
2757 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
2762 static int gfx_v8_0_rlc_load_microcode(struct amdgpu_device *adev)
2764 const struct rlc_firmware_header_v2_0 *hdr;
2765 const __le32 *fw_data;
2766 unsigned i, fw_size;
2768 if (!adev->gfx.rlc_fw)
2771 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2772 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2774 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2775 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2776 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2778 WREG32(mmRLC_GPM_UCODE_ADDR, 0);
2779 for (i = 0; i < fw_size; i++)
2780 WREG32(mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2781 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2786 static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev)
2790 gfx_v8_0_rlc_stop(adev);
2793 WREG32(mmRLC_CGCG_CGLS_CTRL, 0);
2796 WREG32(mmRLC_PG_CNTL, 0);
2798 gfx_v8_0_rlc_reset(adev);
2800 if (!adev->firmware.smu_load) {
2801 /* legacy rlc firmware loading */
2802 r = gfx_v8_0_rlc_load_microcode(adev);
2806 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
2807 AMDGPU_UCODE_ID_RLC_G);
2812 gfx_v8_0_rlc_start(adev);
2817 static void gfx_v8_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2820 u32 tmp = RREG32(mmCP_ME_CNTL);
2823 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0);
2824 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0);
2825 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0);
2827 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1);
2828 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1);
2829 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1);
2830 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2831 adev->gfx.gfx_ring[i].ready = false;
2833 WREG32(mmCP_ME_CNTL, tmp);
2837 static int gfx_v8_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2839 const struct gfx_firmware_header_v1_0 *pfp_hdr;
2840 const struct gfx_firmware_header_v1_0 *ce_hdr;
2841 const struct gfx_firmware_header_v1_0 *me_hdr;
2842 const __le32 *fw_data;
2843 unsigned i, fw_size;
2845 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2848 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2849 adev->gfx.pfp_fw->data;
2850 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2851 adev->gfx.ce_fw->data;
2852 me_hdr = (const struct gfx_firmware_header_v1_0 *)
2853 adev->gfx.me_fw->data;
2855 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2856 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2857 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2859 gfx_v8_0_cp_gfx_enable(adev, false);
2862 fw_data = (const __le32 *)
2863 (adev->gfx.pfp_fw->data +
2864 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2865 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2866 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2867 for (i = 0; i < fw_size; i++)
2868 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2869 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2872 fw_data = (const __le32 *)
2873 (adev->gfx.ce_fw->data +
2874 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2875 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2876 WREG32(mmCP_CE_UCODE_ADDR, 0);
2877 for (i = 0; i < fw_size; i++)
2878 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2879 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2882 fw_data = (const __le32 *)
2883 (adev->gfx.me_fw->data +
2884 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2885 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2886 WREG32(mmCP_ME_RAM_WADDR, 0);
2887 for (i = 0; i < fw_size; i++)
2888 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2889 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2894 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev)
2897 const struct cs_section_def *sect = NULL;
2898 const struct cs_extent_def *ext = NULL;
2900 /* begin clear state */
2902 /* context control state */
2905 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2906 for (ext = sect->section; ext->extent != NULL; ++ext) {
2907 if (sect->id == SECT_CONTEXT)
2908 count += 2 + ext->reg_count;
2913 /* pa_sc_raster_config/pa_sc_raster_config1 */
2915 /* end clear state */
2923 static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
2925 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2926 const struct cs_section_def *sect = NULL;
2927 const struct cs_extent_def *ext = NULL;
2931 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2932 WREG32(mmCP_ENDIAN_SWAP, 0);
2933 WREG32(mmCP_DEVICE_ID, 1);
2935 gfx_v8_0_cp_gfx_enable(adev, true);
2937 r = amdgpu_ring_lock(ring, gfx_v8_0_get_csb_size(adev) + 4);
2939 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2943 /* clear state buffer */
2944 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2945 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2947 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2948 amdgpu_ring_write(ring, 0x80000000);
2949 amdgpu_ring_write(ring, 0x80000000);
2951 for (sect = vi_cs_data; sect->section != NULL; ++sect) {
2952 for (ext = sect->section; ext->extent != NULL; ++ext) {
2953 if (sect->id == SECT_CONTEXT) {
2954 amdgpu_ring_write(ring,
2955 PACKET3(PACKET3_SET_CONTEXT_REG,
2957 amdgpu_ring_write(ring,
2958 ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2959 for (i = 0; i < ext->reg_count; i++)
2960 amdgpu_ring_write(ring, ext->extent[i]);
2965 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2966 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2967 switch (adev->asic_type) {
2969 amdgpu_ring_write(ring, 0x16000012);
2970 amdgpu_ring_write(ring, 0x0000002A);
2973 amdgpu_ring_write(ring, 0x3a00161a);
2974 amdgpu_ring_write(ring, 0x0000002e);
2978 amdgpu_ring_write(ring, 0x00000002);
2979 amdgpu_ring_write(ring, 0x00000000);
2982 amdgpu_ring_write(ring, 0x00000000);
2983 amdgpu_ring_write(ring, 0x00000000);
2989 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2990 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2992 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2993 amdgpu_ring_write(ring, 0);
2995 /* init the CE partitions */
2996 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2997 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2998 amdgpu_ring_write(ring, 0x8000);
2999 amdgpu_ring_write(ring, 0x8000);
3001 amdgpu_ring_unlock_commit(ring);
3006 static int gfx_v8_0_cp_gfx_resume(struct amdgpu_device *adev)
3008 struct amdgpu_ring *ring;
3011 u64 rb_addr, rptr_addr;
3014 /* Set the write pointer delay */
3015 WREG32(mmCP_RB_WPTR_DELAY, 0);
3017 /* set the RB to use vmid 0 */
3018 WREG32(mmCP_RB_VMID, 0);
3020 /* Set ring buffer size */
3021 ring = &adev->gfx.gfx_ring[0];
3022 rb_bufsz = order_base_2(ring->ring_size / 8);
3023 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
3024 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
3025 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MTYPE, 3);
3026 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, MIN_IB_AVAILSZ, 1);
3028 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
3030 WREG32(mmCP_RB0_CNTL, tmp);
3032 /* Initialize the ring buffer's read and write pointers */
3033 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
3035 WREG32(mmCP_RB0_WPTR, ring->wptr);
3037 /* set the wb address wether it's enabled or not */
3038 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3039 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
3040 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
3043 WREG32(mmCP_RB0_CNTL, tmp);
3045 rb_addr = ring->gpu_addr >> 8;
3046 WREG32(mmCP_RB0_BASE, rb_addr);
3047 WREG32(mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
3049 /* no gfx doorbells on iceland */
3050 if (adev->asic_type != CHIP_TOPAZ) {
3051 tmp = RREG32(mmCP_RB_DOORBELL_CONTROL);
3052 if (ring->use_doorbell) {
3053 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3054 DOORBELL_OFFSET, ring->doorbell_index);
3055 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3058 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3061 WREG32(mmCP_RB_DOORBELL_CONTROL, tmp);
3063 if (adev->asic_type == CHIP_TONGA) {
3064 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
3065 DOORBELL_RANGE_LOWER,
3066 AMDGPU_DOORBELL_GFX_RING0);
3067 WREG32(mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
3069 WREG32(mmCP_RB_DOORBELL_RANGE_UPPER,
3070 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
3075 /* start the ring */
3076 gfx_v8_0_cp_gfx_start(adev);
3078 r = amdgpu_ring_test_ring(ring);
3080 ring->ready = false;
3087 static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
3092 WREG32(mmCP_MEC_CNTL, 0);
3094 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
3095 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3096 adev->gfx.compute_ring[i].ready = false;
3101 static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev)
3103 gfx_v8_0_cp_compute_enable(adev, true);
3108 static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
3110 const struct gfx_firmware_header_v1_0 *mec_hdr;
3111 const __le32 *fw_data;
3112 unsigned i, fw_size;
3114 if (!adev->gfx.mec_fw)
3117 gfx_v8_0_cp_compute_enable(adev, false);
3119 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3120 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3122 fw_data = (const __le32 *)
3123 (adev->gfx.mec_fw->data +
3124 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
3125 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
3128 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
3129 for (i = 0; i < fw_size; i++)
3130 WREG32(mmCP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data+i));
3131 WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
3133 /* Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
3134 if (adev->gfx.mec2_fw) {
3135 const struct gfx_firmware_header_v1_0 *mec2_hdr;
3137 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
3138 amdgpu_ucode_print_gfx_hdr(&mec2_hdr->header);
3140 fw_data = (const __le32 *)
3141 (adev->gfx.mec2_fw->data +
3142 le32_to_cpu(mec2_hdr->header.ucode_array_offset_bytes));
3143 fw_size = le32_to_cpu(mec2_hdr->header.ucode_size_bytes) / 4;
3145 WREG32(mmCP_MEC_ME2_UCODE_ADDR, 0);
3146 for (i = 0; i < fw_size; i++)
3147 WREG32(mmCP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data+i));
3148 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version);
3155 uint32_t header; /* ordinal0 */
3156 uint32_t compute_dispatch_initiator; /* ordinal1 */
3157 uint32_t compute_dim_x; /* ordinal2 */
3158 uint32_t compute_dim_y; /* ordinal3 */
3159 uint32_t compute_dim_z; /* ordinal4 */
3160 uint32_t compute_start_x; /* ordinal5 */
3161 uint32_t compute_start_y; /* ordinal6 */
3162 uint32_t compute_start_z; /* ordinal7 */
3163 uint32_t compute_num_thread_x; /* ordinal8 */
3164 uint32_t compute_num_thread_y; /* ordinal9 */
3165 uint32_t compute_num_thread_z; /* ordinal10 */
3166 uint32_t compute_pipelinestat_enable; /* ordinal11 */
3167 uint32_t compute_perfcount_enable; /* ordinal12 */
3168 uint32_t compute_pgm_lo; /* ordinal13 */
3169 uint32_t compute_pgm_hi; /* ordinal14 */
3170 uint32_t compute_tba_lo; /* ordinal15 */
3171 uint32_t compute_tba_hi; /* ordinal16 */
3172 uint32_t compute_tma_lo; /* ordinal17 */
3173 uint32_t compute_tma_hi; /* ordinal18 */
3174 uint32_t compute_pgm_rsrc1; /* ordinal19 */
3175 uint32_t compute_pgm_rsrc2; /* ordinal20 */
3176 uint32_t compute_vmid; /* ordinal21 */
3177 uint32_t compute_resource_limits; /* ordinal22 */
3178 uint32_t compute_static_thread_mgmt_se0; /* ordinal23 */
3179 uint32_t compute_static_thread_mgmt_se1; /* ordinal24 */
3180 uint32_t compute_tmpring_size; /* ordinal25 */
3181 uint32_t compute_static_thread_mgmt_se2; /* ordinal26 */
3182 uint32_t compute_static_thread_mgmt_se3; /* ordinal27 */
3183 uint32_t compute_restart_x; /* ordinal28 */
3184 uint32_t compute_restart_y; /* ordinal29 */
3185 uint32_t compute_restart_z; /* ordinal30 */
3186 uint32_t compute_thread_trace_enable; /* ordinal31 */
3187 uint32_t compute_misc_reserved; /* ordinal32 */
3188 uint32_t compute_dispatch_id; /* ordinal33 */
3189 uint32_t compute_threadgroup_id; /* ordinal34 */
3190 uint32_t compute_relaunch; /* ordinal35 */
3191 uint32_t compute_wave_restore_addr_lo; /* ordinal36 */
3192 uint32_t compute_wave_restore_addr_hi; /* ordinal37 */
3193 uint32_t compute_wave_restore_control; /* ordinal38 */
3194 uint32_t reserved9; /* ordinal39 */
3195 uint32_t reserved10; /* ordinal40 */
3196 uint32_t reserved11; /* ordinal41 */
3197 uint32_t reserved12; /* ordinal42 */
3198 uint32_t reserved13; /* ordinal43 */
3199 uint32_t reserved14; /* ordinal44 */
3200 uint32_t reserved15; /* ordinal45 */
3201 uint32_t reserved16; /* ordinal46 */
3202 uint32_t reserved17; /* ordinal47 */
3203 uint32_t reserved18; /* ordinal48 */
3204 uint32_t reserved19; /* ordinal49 */
3205 uint32_t reserved20; /* ordinal50 */
3206 uint32_t reserved21; /* ordinal51 */
3207 uint32_t reserved22; /* ordinal52 */
3208 uint32_t reserved23; /* ordinal53 */
3209 uint32_t reserved24; /* ordinal54 */
3210 uint32_t reserved25; /* ordinal55 */
3211 uint32_t reserved26; /* ordinal56 */
3212 uint32_t reserved27; /* ordinal57 */
3213 uint32_t reserved28; /* ordinal58 */
3214 uint32_t reserved29; /* ordinal59 */
3215 uint32_t reserved30; /* ordinal60 */
3216 uint32_t reserved31; /* ordinal61 */
3217 uint32_t reserved32; /* ordinal62 */
3218 uint32_t reserved33; /* ordinal63 */
3219 uint32_t reserved34; /* ordinal64 */
3220 uint32_t compute_user_data_0; /* ordinal65 */
3221 uint32_t compute_user_data_1; /* ordinal66 */
3222 uint32_t compute_user_data_2; /* ordinal67 */
3223 uint32_t compute_user_data_3; /* ordinal68 */
3224 uint32_t compute_user_data_4; /* ordinal69 */
3225 uint32_t compute_user_data_5; /* ordinal70 */
3226 uint32_t compute_user_data_6; /* ordinal71 */
3227 uint32_t compute_user_data_7; /* ordinal72 */
3228 uint32_t compute_user_data_8; /* ordinal73 */
3229 uint32_t compute_user_data_9; /* ordinal74 */
3230 uint32_t compute_user_data_10; /* ordinal75 */
3231 uint32_t compute_user_data_11; /* ordinal76 */
3232 uint32_t compute_user_data_12; /* ordinal77 */
3233 uint32_t compute_user_data_13; /* ordinal78 */
3234 uint32_t compute_user_data_14; /* ordinal79 */
3235 uint32_t compute_user_data_15; /* ordinal80 */
3236 uint32_t cp_compute_csinvoc_count_lo; /* ordinal81 */
3237 uint32_t cp_compute_csinvoc_count_hi; /* ordinal82 */
3238 uint32_t reserved35; /* ordinal83 */
3239 uint32_t reserved36; /* ordinal84 */
3240 uint32_t reserved37; /* ordinal85 */
3241 uint32_t cp_mqd_query_time_lo; /* ordinal86 */
3242 uint32_t cp_mqd_query_time_hi; /* ordinal87 */
3243 uint32_t cp_mqd_connect_start_time_lo; /* ordinal88 */
3244 uint32_t cp_mqd_connect_start_time_hi; /* ordinal89 */
3245 uint32_t cp_mqd_connect_end_time_lo; /* ordinal90 */
3246 uint32_t cp_mqd_connect_end_time_hi; /* ordinal91 */
3247 uint32_t cp_mqd_connect_end_wf_count; /* ordinal92 */
3248 uint32_t cp_mqd_connect_end_pq_rptr; /* ordinal93 */
3249 uint32_t cp_mqd_connect_end_pq_wptr; /* ordinal94 */
3250 uint32_t cp_mqd_connect_end_ib_rptr; /* ordinal95 */
3251 uint32_t reserved38; /* ordinal96 */
3252 uint32_t reserved39; /* ordinal97 */
3253 uint32_t cp_mqd_save_start_time_lo; /* ordinal98 */
3254 uint32_t cp_mqd_save_start_time_hi; /* ordinal99 */
3255 uint32_t cp_mqd_save_end_time_lo; /* ordinal100 */
3256 uint32_t cp_mqd_save_end_time_hi; /* ordinal101 */
3257 uint32_t cp_mqd_restore_start_time_lo; /* ordinal102 */
3258 uint32_t cp_mqd_restore_start_time_hi; /* ordinal103 */
3259 uint32_t cp_mqd_restore_end_time_lo; /* ordinal104 */
3260 uint32_t cp_mqd_restore_end_time_hi; /* ordinal105 */
3261 uint32_t reserved40; /* ordinal106 */
3262 uint32_t reserved41; /* ordinal107 */
3263 uint32_t gds_cs_ctxsw_cnt0; /* ordinal108 */
3264 uint32_t gds_cs_ctxsw_cnt1; /* ordinal109 */
3265 uint32_t gds_cs_ctxsw_cnt2; /* ordinal110 */
3266 uint32_t gds_cs_ctxsw_cnt3; /* ordinal111 */
3267 uint32_t reserved42; /* ordinal112 */
3268 uint32_t reserved43; /* ordinal113 */
3269 uint32_t cp_pq_exe_status_lo; /* ordinal114 */
3270 uint32_t cp_pq_exe_status_hi; /* ordinal115 */
3271 uint32_t cp_packet_id_lo; /* ordinal116 */
3272 uint32_t cp_packet_id_hi; /* ordinal117 */
3273 uint32_t cp_packet_exe_status_lo; /* ordinal118 */
3274 uint32_t cp_packet_exe_status_hi; /* ordinal119 */
3275 uint32_t gds_save_base_addr_lo; /* ordinal120 */
3276 uint32_t gds_save_base_addr_hi; /* ordinal121 */
3277 uint32_t gds_save_mask_lo; /* ordinal122 */
3278 uint32_t gds_save_mask_hi; /* ordinal123 */
3279 uint32_t ctx_save_base_addr_lo; /* ordinal124 */
3280 uint32_t ctx_save_base_addr_hi; /* ordinal125 */
3281 uint32_t reserved44; /* ordinal126 */
3282 uint32_t reserved45; /* ordinal127 */
3283 uint32_t cp_mqd_base_addr_lo; /* ordinal128 */
3284 uint32_t cp_mqd_base_addr_hi; /* ordinal129 */
3285 uint32_t cp_hqd_active; /* ordinal130 */
3286 uint32_t cp_hqd_vmid; /* ordinal131 */
3287 uint32_t cp_hqd_persistent_state; /* ordinal132 */
3288 uint32_t cp_hqd_pipe_priority; /* ordinal133 */
3289 uint32_t cp_hqd_queue_priority; /* ordinal134 */
3290 uint32_t cp_hqd_quantum; /* ordinal135 */
3291 uint32_t cp_hqd_pq_base_lo; /* ordinal136 */
3292 uint32_t cp_hqd_pq_base_hi; /* ordinal137 */
3293 uint32_t cp_hqd_pq_rptr; /* ordinal138 */
3294 uint32_t cp_hqd_pq_rptr_report_addr_lo; /* ordinal139 */
3295 uint32_t cp_hqd_pq_rptr_report_addr_hi; /* ordinal140 */
3296 uint32_t cp_hqd_pq_wptr_poll_addr; /* ordinal141 */
3297 uint32_t cp_hqd_pq_wptr_poll_addr_hi; /* ordinal142 */
3298 uint32_t cp_hqd_pq_doorbell_control; /* ordinal143 */
3299 uint32_t cp_hqd_pq_wptr; /* ordinal144 */
3300 uint32_t cp_hqd_pq_control; /* ordinal145 */
3301 uint32_t cp_hqd_ib_base_addr_lo; /* ordinal146 */
3302 uint32_t cp_hqd_ib_base_addr_hi; /* ordinal147 */
3303 uint32_t cp_hqd_ib_rptr; /* ordinal148 */
3304 uint32_t cp_hqd_ib_control; /* ordinal149 */
3305 uint32_t cp_hqd_iq_timer; /* ordinal150 */
3306 uint32_t cp_hqd_iq_rptr; /* ordinal151 */
3307 uint32_t cp_hqd_dequeue_request; /* ordinal152 */
3308 uint32_t cp_hqd_dma_offload; /* ordinal153 */
3309 uint32_t cp_hqd_sema_cmd; /* ordinal154 */
3310 uint32_t cp_hqd_msg_type; /* ordinal155 */
3311 uint32_t cp_hqd_atomic0_preop_lo; /* ordinal156 */
3312 uint32_t cp_hqd_atomic0_preop_hi; /* ordinal157 */
3313 uint32_t cp_hqd_atomic1_preop_lo; /* ordinal158 */
3314 uint32_t cp_hqd_atomic1_preop_hi; /* ordinal159 */
3315 uint32_t cp_hqd_hq_status0; /* ordinal160 */
3316 uint32_t cp_hqd_hq_control0; /* ordinal161 */
3317 uint32_t cp_mqd_control; /* ordinal162 */
3318 uint32_t cp_hqd_hq_status1; /* ordinal163 */
3319 uint32_t cp_hqd_hq_control1; /* ordinal164 */
3320 uint32_t cp_hqd_eop_base_addr_lo; /* ordinal165 */
3321 uint32_t cp_hqd_eop_base_addr_hi; /* ordinal166 */
3322 uint32_t cp_hqd_eop_control; /* ordinal167 */
3323 uint32_t cp_hqd_eop_rptr; /* ordinal168 */
3324 uint32_t cp_hqd_eop_wptr; /* ordinal169 */
3325 uint32_t cp_hqd_eop_done_events; /* ordinal170 */
3326 uint32_t cp_hqd_ctx_save_base_addr_lo; /* ordinal171 */
3327 uint32_t cp_hqd_ctx_save_base_addr_hi; /* ordinal172 */
3328 uint32_t cp_hqd_ctx_save_control; /* ordinal173 */
3329 uint32_t cp_hqd_cntl_stack_offset; /* ordinal174 */
3330 uint32_t cp_hqd_cntl_stack_size; /* ordinal175 */
3331 uint32_t cp_hqd_wg_state_offset; /* ordinal176 */
3332 uint32_t cp_hqd_ctx_save_size; /* ordinal177 */
3333 uint32_t cp_hqd_gds_resource_state; /* ordinal178 */
3334 uint32_t cp_hqd_error; /* ordinal179 */
3335 uint32_t cp_hqd_eop_wptr_mem; /* ordinal180 */
3336 uint32_t cp_hqd_eop_dones; /* ordinal181 */
3337 uint32_t reserved46; /* ordinal182 */
3338 uint32_t reserved47; /* ordinal183 */
3339 uint32_t reserved48; /* ordinal184 */
3340 uint32_t reserved49; /* ordinal185 */
3341 uint32_t reserved50; /* ordinal186 */
3342 uint32_t reserved51; /* ordinal187 */
3343 uint32_t reserved52; /* ordinal188 */
3344 uint32_t reserved53; /* ordinal189 */
3345 uint32_t reserved54; /* ordinal190 */
3346 uint32_t reserved55; /* ordinal191 */
3347 uint32_t iqtimer_pkt_header; /* ordinal192 */
3348 uint32_t iqtimer_pkt_dw0; /* ordinal193 */
3349 uint32_t iqtimer_pkt_dw1; /* ordinal194 */
3350 uint32_t iqtimer_pkt_dw2; /* ordinal195 */
3351 uint32_t iqtimer_pkt_dw3; /* ordinal196 */
3352 uint32_t iqtimer_pkt_dw4; /* ordinal197 */
3353 uint32_t iqtimer_pkt_dw5; /* ordinal198 */
3354 uint32_t iqtimer_pkt_dw6; /* ordinal199 */
3355 uint32_t iqtimer_pkt_dw7; /* ordinal200 */
3356 uint32_t iqtimer_pkt_dw8; /* ordinal201 */
3357 uint32_t iqtimer_pkt_dw9; /* ordinal202 */
3358 uint32_t iqtimer_pkt_dw10; /* ordinal203 */
3359 uint32_t iqtimer_pkt_dw11; /* ordinal204 */
3360 uint32_t iqtimer_pkt_dw12; /* ordinal205 */
3361 uint32_t iqtimer_pkt_dw13; /* ordinal206 */
3362 uint32_t iqtimer_pkt_dw14; /* ordinal207 */
3363 uint32_t iqtimer_pkt_dw15; /* ordinal208 */
3364 uint32_t iqtimer_pkt_dw16; /* ordinal209 */
3365 uint32_t iqtimer_pkt_dw17; /* ordinal210 */
3366 uint32_t iqtimer_pkt_dw18; /* ordinal211 */
3367 uint32_t iqtimer_pkt_dw19; /* ordinal212 */
3368 uint32_t iqtimer_pkt_dw20; /* ordinal213 */
3369 uint32_t iqtimer_pkt_dw21; /* ordinal214 */
3370 uint32_t iqtimer_pkt_dw22; /* ordinal215 */
3371 uint32_t iqtimer_pkt_dw23; /* ordinal216 */
3372 uint32_t iqtimer_pkt_dw24; /* ordinal217 */
3373 uint32_t iqtimer_pkt_dw25; /* ordinal218 */
3374 uint32_t iqtimer_pkt_dw26; /* ordinal219 */
3375 uint32_t iqtimer_pkt_dw27; /* ordinal220 */
3376 uint32_t iqtimer_pkt_dw28; /* ordinal221 */
3377 uint32_t iqtimer_pkt_dw29; /* ordinal222 */
3378 uint32_t iqtimer_pkt_dw30; /* ordinal223 */
3379 uint32_t iqtimer_pkt_dw31; /* ordinal224 */
3380 uint32_t reserved56; /* ordinal225 */
3381 uint32_t reserved57; /* ordinal226 */
3382 uint32_t reserved58; /* ordinal227 */
3383 uint32_t set_resources_header; /* ordinal228 */
3384 uint32_t set_resources_dw1; /* ordinal229 */
3385 uint32_t set_resources_dw2; /* ordinal230 */
3386 uint32_t set_resources_dw3; /* ordinal231 */
3387 uint32_t set_resources_dw4; /* ordinal232 */
3388 uint32_t set_resources_dw5; /* ordinal233 */
3389 uint32_t set_resources_dw6; /* ordinal234 */
3390 uint32_t set_resources_dw7; /* ordinal235 */
3391 uint32_t reserved59; /* ordinal236 */
3392 uint32_t reserved60; /* ordinal237 */
3393 uint32_t reserved61; /* ordinal238 */
3394 uint32_t reserved62; /* ordinal239 */
3395 uint32_t reserved63; /* ordinal240 */
3396 uint32_t reserved64; /* ordinal241 */
3397 uint32_t reserved65; /* ordinal242 */
3398 uint32_t reserved66; /* ordinal243 */
3399 uint32_t reserved67; /* ordinal244 */
3400 uint32_t reserved68; /* ordinal245 */
3401 uint32_t reserved69; /* ordinal246 */
3402 uint32_t reserved70; /* ordinal247 */
3403 uint32_t reserved71; /* ordinal248 */
3404 uint32_t reserved72; /* ordinal249 */
3405 uint32_t reserved73; /* ordinal250 */
3406 uint32_t reserved74; /* ordinal251 */
3407 uint32_t reserved75; /* ordinal252 */
3408 uint32_t reserved76; /* ordinal253 */
3409 uint32_t reserved77; /* ordinal254 */
3410 uint32_t reserved78; /* ordinal255 */
3412 uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
3415 static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
3419 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3420 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3422 if (ring->mqd_obj) {
3423 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3424 if (unlikely(r != 0))
3425 dev_warn(adev->dev, "(%d) reserve MQD bo failed\n", r);
3427 amdgpu_bo_unpin(ring->mqd_obj);
3428 amdgpu_bo_unreserve(ring->mqd_obj);
3430 amdgpu_bo_unref(&ring->mqd_obj);
3431 ring->mqd_obj = NULL;
3436 static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
3440 bool use_doorbell = true;
3448 /* init the pipes */
3449 mutex_lock(&adev->srbm_mutex);
3450 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
3451 int me = (i < 4) ? 1 : 2;
3452 int pipe = (i < 4) ? i : (i - 4);
3454 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
3457 vi_srbm_select(adev, me, pipe, 0, 0);
3459 /* write the EOP addr */
3460 WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
3461 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
3463 /* set the VMID assigned */
3464 WREG32(mmCP_HQD_VMID, 0);
3466 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3467 tmp = RREG32(mmCP_HQD_EOP_CONTROL);
3468 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3469 (order_base_2(MEC_HPD_SIZE / 4) - 1));
3470 WREG32(mmCP_HQD_EOP_CONTROL, tmp);
3472 vi_srbm_select(adev, 0, 0, 0, 0);
3473 mutex_unlock(&adev->srbm_mutex);
3475 /* init the queues. Just two for now. */
3476 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3477 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3479 if (ring->mqd_obj == NULL) {
3480 r = amdgpu_bo_create(adev,
3481 sizeof(struct vi_mqd),
3483 AMDGPU_GEM_DOMAIN_GTT, 0, NULL,
3484 NULL, &ring->mqd_obj);
3486 dev_warn(adev->dev, "(%d) create MQD bo failed\n", r);
3491 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3492 if (unlikely(r != 0)) {
3493 gfx_v8_0_cp_compute_fini(adev);
3496 r = amdgpu_bo_pin(ring->mqd_obj, AMDGPU_GEM_DOMAIN_GTT,
3499 dev_warn(adev->dev, "(%d) pin MQD bo failed\n", r);
3500 gfx_v8_0_cp_compute_fini(adev);
3503 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&buf);
3505 dev_warn(adev->dev, "(%d) map MQD bo failed\n", r);
3506 gfx_v8_0_cp_compute_fini(adev);
3510 /* init the mqd struct */
3511 memset(buf, 0, sizeof(struct vi_mqd));
3513 mqd = (struct vi_mqd *)buf;
3514 mqd->header = 0xC0310800;
3515 mqd->compute_pipelinestat_enable = 0x00000001;
3516 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3517 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3518 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3519 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3520 mqd->compute_misc_reserved = 0x00000003;
3522 mutex_lock(&adev->srbm_mutex);
3523 vi_srbm_select(adev, ring->me,
3527 /* disable wptr polling */
3528 tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
3529 tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3530 WREG32(mmCP_PQ_WPTR_POLL_CNTL, tmp);
3532 mqd->cp_hqd_eop_base_addr_lo =
3533 RREG32(mmCP_HQD_EOP_BASE_ADDR);
3534 mqd->cp_hqd_eop_base_addr_hi =
3535 RREG32(mmCP_HQD_EOP_BASE_ADDR_HI);
3537 /* enable doorbell? */
3538 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3540 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3542 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 0);
3544 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, tmp);
3545 mqd->cp_hqd_pq_doorbell_control = tmp;
3547 /* disable the queue if it's active */
3548 mqd->cp_hqd_dequeue_request = 0;
3549 mqd->cp_hqd_pq_rptr = 0;
3550 mqd->cp_hqd_pq_wptr= 0;
3551 if (RREG32(mmCP_HQD_ACTIVE) & 1) {
3552 WREG32(mmCP_HQD_DEQUEUE_REQUEST, 1);
3553 for (j = 0; j < adev->usec_timeout; j++) {
3554 if (!(RREG32(mmCP_HQD_ACTIVE) & 1))
3558 WREG32(mmCP_HQD_DEQUEUE_REQUEST, mqd->cp_hqd_dequeue_request);
3559 WREG32(mmCP_HQD_PQ_RPTR, mqd->cp_hqd_pq_rptr);
3560 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3563 /* set the pointer to the MQD */
3564 mqd->cp_mqd_base_addr_lo = mqd_gpu_addr & 0xfffffffc;
3565 mqd->cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
3566 WREG32(mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo);
3567 WREG32(mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
3569 /* set MQD vmid to 0 */
3570 tmp = RREG32(mmCP_MQD_CONTROL);
3571 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3572 WREG32(mmCP_MQD_CONTROL, tmp);
3573 mqd->cp_mqd_control = tmp;
3575 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3576 hqd_gpu_addr = ring->gpu_addr >> 8;
3577 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3578 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3579 WREG32(mmCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo);
3580 WREG32(mmCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi);
3582 /* set up the HQD, this is similar to CP_RB0_CNTL */
3583 tmp = RREG32(mmCP_HQD_PQ_CONTROL);
3584 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3585 (order_base_2(ring->ring_size / 4) - 1));
3586 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3587 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
3589 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
3591 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3592 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
3593 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3594 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3595 WREG32(mmCP_HQD_PQ_CONTROL, tmp);
3596 mqd->cp_hqd_pq_control = tmp;
3598 /* set the wb address wether it's enabled or not */
3599 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
3600 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3601 mqd->cp_hqd_pq_rptr_report_addr_hi =
3602 upper_32_bits(wb_gpu_addr) & 0xffff;
3603 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR,
3604 mqd->cp_hqd_pq_rptr_report_addr_lo);
3605 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3606 mqd->cp_hqd_pq_rptr_report_addr_hi);
3608 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3609 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3610 mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
3611 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3612 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
3613 WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3614 mqd->cp_hqd_pq_wptr_poll_addr_hi);
3616 /* enable the doorbell if requested */
3618 if ((adev->asic_type == CHIP_CARRIZO) ||
3619 (adev->asic_type == CHIP_FIJI) ||
3620 (adev->asic_type == CHIP_STONEY)) {
3621 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
3622 AMDGPU_DOORBELL_KIQ << 2);
3623 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
3624 AMDGPU_DOORBELL_MEC_RING7 << 2);
3626 tmp = RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL);
3627 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3628 DOORBELL_OFFSET, ring->doorbell_index);
3629 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
3630 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_SOURCE, 0);
3631 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_HIT, 0);
3632 mqd->cp_hqd_pq_doorbell_control = tmp;
3635 mqd->cp_hqd_pq_doorbell_control = 0;
3637 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL,
3638 mqd->cp_hqd_pq_doorbell_control);
3640 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3642 mqd->cp_hqd_pq_wptr = ring->wptr;
3643 WREG32(mmCP_HQD_PQ_WPTR, mqd->cp_hqd_pq_wptr);
3644 mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
3646 /* set the vmid for the queue */
3647 mqd->cp_hqd_vmid = 0;
3648 WREG32(mmCP_HQD_VMID, mqd->cp_hqd_vmid);
3650 tmp = RREG32(mmCP_HQD_PERSISTENT_STATE);
3651 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
3652 WREG32(mmCP_HQD_PERSISTENT_STATE, tmp);
3653 mqd->cp_hqd_persistent_state = tmp;
3655 /* activate the queue */
3656 mqd->cp_hqd_active = 1;
3657 WREG32(mmCP_HQD_ACTIVE, mqd->cp_hqd_active);
3659 vi_srbm_select(adev, 0, 0, 0, 0);
3660 mutex_unlock(&adev->srbm_mutex);
3662 amdgpu_bo_kunmap(ring->mqd_obj);
3663 amdgpu_bo_unreserve(ring->mqd_obj);
3667 tmp = RREG32(mmCP_PQ_STATUS);
3668 tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3669 WREG32(mmCP_PQ_STATUS, tmp);
3672 r = gfx_v8_0_cp_compute_start(adev);
3676 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3677 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3680 r = amdgpu_ring_test_ring(ring);
3682 ring->ready = false;
3688 static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
3692 if (!(adev->flags & AMD_IS_APU))
3693 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
3695 if (!adev->firmware.smu_load) {
3696 /* legacy firmware loading */
3697 r = gfx_v8_0_cp_gfx_load_microcode(adev);
3701 r = gfx_v8_0_cp_compute_load_microcode(adev);
3705 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3706 AMDGPU_UCODE_ID_CP_CE);
3710 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3711 AMDGPU_UCODE_ID_CP_PFP);
3715 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3716 AMDGPU_UCODE_ID_CP_ME);
3720 r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
3721 AMDGPU_UCODE_ID_CP_MEC1);
3726 r = gfx_v8_0_cp_gfx_resume(adev);
3730 r = gfx_v8_0_cp_compute_resume(adev);
3734 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
3739 static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable)
3741 gfx_v8_0_cp_gfx_enable(adev, enable);
3742 gfx_v8_0_cp_compute_enable(adev, enable);
3745 static int gfx_v8_0_hw_init(void *handle)
3748 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3750 gfx_v8_0_init_golden_registers(adev);
3752 gfx_v8_0_gpu_init(adev);
3754 r = gfx_v8_0_rlc_resume(adev);
3758 r = gfx_v8_0_cp_resume(adev);
3765 static int gfx_v8_0_hw_fini(void *handle)
3767 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3769 gfx_v8_0_cp_enable(adev, false);
3770 gfx_v8_0_rlc_stop(adev);
3771 gfx_v8_0_cp_compute_fini(adev);
3776 static int gfx_v8_0_suspend(void *handle)
3778 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3780 return gfx_v8_0_hw_fini(adev);
3783 static int gfx_v8_0_resume(void *handle)
3785 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3787 return gfx_v8_0_hw_init(adev);
3790 static bool gfx_v8_0_is_idle(void *handle)
3792 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3794 if (REG_GET_FIELD(RREG32(mmGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE))
3800 static int gfx_v8_0_wait_for_idle(void *handle)
3804 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3806 for (i = 0; i < adev->usec_timeout; i++) {
3807 /* read MC_STATUS */
3808 tmp = RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK;
3810 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
3817 static void gfx_v8_0_print_status(void *handle)
3820 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3822 dev_info(adev->dev, "GFX 8.x registers\n");
3823 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
3824 RREG32(mmGRBM_STATUS));
3825 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
3826 RREG32(mmGRBM_STATUS2));
3827 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
3828 RREG32(mmGRBM_STATUS_SE0));
3829 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
3830 RREG32(mmGRBM_STATUS_SE1));
3831 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
3832 RREG32(mmGRBM_STATUS_SE2));
3833 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
3834 RREG32(mmGRBM_STATUS_SE3));
3835 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
3836 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
3837 RREG32(mmCP_STALLED_STAT1));
3838 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
3839 RREG32(mmCP_STALLED_STAT2));
3840 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
3841 RREG32(mmCP_STALLED_STAT3));
3842 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
3843 RREG32(mmCP_CPF_BUSY_STAT));
3844 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
3845 RREG32(mmCP_CPF_STALLED_STAT1));
3846 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
3847 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
3848 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
3849 RREG32(mmCP_CPC_STALLED_STAT1));
3850 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
3852 for (i = 0; i < 32; i++) {
3853 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n",
3854 i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
3856 for (i = 0; i < 16; i++) {
3857 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n",
3858 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
3860 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3861 dev_info(adev->dev, " se: %d\n", i);
3862 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
3863 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n",
3864 RREG32(mmPA_SC_RASTER_CONFIG));
3865 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n",
3866 RREG32(mmPA_SC_RASTER_CONFIG_1));
3868 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
3870 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n",
3871 RREG32(mmGB_ADDR_CONFIG));
3872 dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n",
3873 RREG32(mmHDP_ADDR_CONFIG));
3874 dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n",
3875 RREG32(mmDMIF_ADDR_CALC));
3876 dev_info(adev->dev, " SDMA0_TILING_CONFIG=0x%08X\n",
3877 RREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET));
3878 dev_info(adev->dev, " SDMA1_TILING_CONFIG=0x%08X\n",
3879 RREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET));
3880 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
3881 RREG32(mmUVD_UDEC_ADDR_CONFIG));
3882 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
3883 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
3884 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
3885 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
3887 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
3888 RREG32(mmCP_MEQ_THRESHOLDS));
3889 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n",
3890 RREG32(mmSX_DEBUG_1));
3891 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n",
3892 RREG32(mmTA_CNTL_AUX));
3893 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n",
3894 RREG32(mmSPI_CONFIG_CNTL));
3895 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n",
3896 RREG32(mmSQ_CONFIG));
3897 dev_info(adev->dev, " DB_DEBUG=0x%08X\n",
3898 RREG32(mmDB_DEBUG));
3899 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n",
3900 RREG32(mmDB_DEBUG2));
3901 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n",
3902 RREG32(mmDB_DEBUG3));
3903 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n",
3904 RREG32(mmCB_HW_CONTROL));
3905 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n",
3906 RREG32(mmSPI_CONFIG_CNTL_1));
3907 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n",
3908 RREG32(mmPA_SC_FIFO_SIZE));
3909 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n",
3910 RREG32(mmVGT_NUM_INSTANCES));
3911 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n",
3912 RREG32(mmCP_PERFMON_CNTL));
3913 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
3914 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
3915 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n",
3916 RREG32(mmVGT_CACHE_INVALIDATION));
3917 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n",
3918 RREG32(mmVGT_GS_VERTEX_REUSE));
3919 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
3920 RREG32(mmPA_SC_LINE_STIPPLE_STATE));
3921 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n",
3922 RREG32(mmPA_CL_ENHANCE));
3923 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n",
3924 RREG32(mmPA_SC_ENHANCE));
3926 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n",
3927 RREG32(mmCP_ME_CNTL));
3928 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n",
3929 RREG32(mmCP_MAX_CONTEXT));
3930 dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n",
3931 RREG32(mmCP_ENDIAN_SWAP));
3932 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n",
3933 RREG32(mmCP_DEVICE_ID));
3935 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n",
3936 RREG32(mmCP_SEM_WAIT_TIMER));
3938 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n",
3939 RREG32(mmCP_RB_WPTR_DELAY));
3940 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n",
3941 RREG32(mmCP_RB_VMID));
3942 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
3943 RREG32(mmCP_RB0_CNTL));
3944 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n",
3945 RREG32(mmCP_RB0_WPTR));
3946 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n",
3947 RREG32(mmCP_RB0_RPTR_ADDR));
3948 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n",
3949 RREG32(mmCP_RB0_RPTR_ADDR_HI));
3950 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
3951 RREG32(mmCP_RB0_CNTL));
3952 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n",
3953 RREG32(mmCP_RB0_BASE));
3954 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n",
3955 RREG32(mmCP_RB0_BASE_HI));
3956 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n",
3957 RREG32(mmCP_MEC_CNTL));
3958 dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n",
3959 RREG32(mmCP_CPF_DEBUG));
3961 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n",
3962 RREG32(mmSCRATCH_ADDR));
3963 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n",
3964 RREG32(mmSCRATCH_UMSK));
3966 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n",
3967 RREG32(mmCP_INT_CNTL_RING0));
3968 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
3969 RREG32(mmRLC_LB_CNTL));
3970 dev_info(adev->dev, " RLC_CNTL=0x%08X\n",
3971 RREG32(mmRLC_CNTL));
3972 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n",
3973 RREG32(mmRLC_CGCG_CGLS_CTRL));
3974 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n",
3975 RREG32(mmRLC_LB_CNTR_INIT));
3976 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n",
3977 RREG32(mmRLC_LB_CNTR_MAX));
3978 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n",
3979 RREG32(mmRLC_LB_INIT_CU_MASK));
3980 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n",
3981 RREG32(mmRLC_LB_PARAMS));
3982 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
3983 RREG32(mmRLC_LB_CNTL));
3984 dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n",
3985 RREG32(mmRLC_MC_CNTL));
3986 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n",
3987 RREG32(mmRLC_UCODE_CNTL));
3989 mutex_lock(&adev->srbm_mutex);
3990 for (i = 0; i < 16; i++) {
3991 vi_srbm_select(adev, 0, 0, 0, i);
3992 dev_info(adev->dev, " VM %d:\n", i);
3993 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n",
3994 RREG32(mmSH_MEM_CONFIG));
3995 dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n",
3996 RREG32(mmSH_MEM_APE1_BASE));
3997 dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n",
3998 RREG32(mmSH_MEM_APE1_LIMIT));
3999 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n",
4000 RREG32(mmSH_MEM_BASES));
4002 vi_srbm_select(adev, 0, 0, 0, 0);
4003 mutex_unlock(&adev->srbm_mutex);
4006 static int gfx_v8_0_soft_reset(void *handle)
4008 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4010 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4013 tmp = RREG32(mmGRBM_STATUS);
4014 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
4015 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
4016 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
4017 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
4018 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
4019 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
4020 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4021 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4022 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4023 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
4026 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
4027 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4028 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
4029 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4030 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4034 tmp = RREG32(mmGRBM_STATUS2);
4035 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
4036 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
4037 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4040 tmp = RREG32(mmSRBM_STATUS);
4041 if (REG_GET_FIELD(tmp, SRBM_STATUS, GRBM_RQ_PENDING))
4042 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
4043 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
4045 if (grbm_soft_reset || srbm_soft_reset) {
4046 gfx_v8_0_print_status((void *)adev);
4048 gfx_v8_0_rlc_stop(adev);
4050 /* Disable GFX parsing/prefetching */
4051 gfx_v8_0_cp_gfx_enable(adev, false);
4053 /* Disable MEC parsing/prefetching */
4056 if (grbm_soft_reset) {
4057 tmp = RREG32(mmGRBM_SOFT_RESET);
4058 tmp |= grbm_soft_reset;
4059 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4060 WREG32(mmGRBM_SOFT_RESET, tmp);
4061 tmp = RREG32(mmGRBM_SOFT_RESET);
4065 tmp &= ~grbm_soft_reset;
4066 WREG32(mmGRBM_SOFT_RESET, tmp);
4067 tmp = RREG32(mmGRBM_SOFT_RESET);
4070 if (srbm_soft_reset) {
4071 tmp = RREG32(mmSRBM_SOFT_RESET);
4072 tmp |= srbm_soft_reset;
4073 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4074 WREG32(mmSRBM_SOFT_RESET, tmp);
4075 tmp = RREG32(mmSRBM_SOFT_RESET);
4079 tmp &= ~srbm_soft_reset;
4080 WREG32(mmSRBM_SOFT_RESET, tmp);
4081 tmp = RREG32(mmSRBM_SOFT_RESET);
4083 /* Wait a little for things to settle down */
4085 gfx_v8_0_print_status((void *)adev);
4091 * gfx_v8_0_get_gpu_clock_counter - return GPU clock counter snapshot
4093 * @adev: amdgpu_device pointer
4095 * Fetches a GPU clock counter snapshot.
4096 * Returns the 64 bit clock counter snapshot.
4098 uint64_t gfx_v8_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4102 mutex_lock(&adev->gfx.gpu_clock_mutex);
4103 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
4104 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
4105 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
4106 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4110 static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4112 uint32_t gds_base, uint32_t gds_size,
4113 uint32_t gws_base, uint32_t gws_size,
4114 uint32_t oa_base, uint32_t oa_size)
4116 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4117 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4119 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4120 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4122 oa_base = oa_base >> AMDGPU_OA_SHIFT;
4123 oa_size = oa_size >> AMDGPU_OA_SHIFT;
4126 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4127 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4128 WRITE_DATA_DST_SEL(0)));
4129 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_base);
4130 amdgpu_ring_write(ring, 0);
4131 amdgpu_ring_write(ring, gds_base);
4134 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4135 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4136 WRITE_DATA_DST_SEL(0)));
4137 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].mem_size);
4138 amdgpu_ring_write(ring, 0);
4139 amdgpu_ring_write(ring, gds_size);
4142 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4143 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4144 WRITE_DATA_DST_SEL(0)));
4145 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].gws);
4146 amdgpu_ring_write(ring, 0);
4147 amdgpu_ring_write(ring, gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4150 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4151 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4152 WRITE_DATA_DST_SEL(0)));
4153 amdgpu_ring_write(ring, amdgpu_gds_reg_offset[vmid].oa);
4154 amdgpu_ring_write(ring, 0);
4155 amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base));
4158 static int gfx_v8_0_early_init(void *handle)
4160 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4162 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS;
4163 adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS;
4164 gfx_v8_0_set_ring_funcs(adev);
4165 gfx_v8_0_set_irq_funcs(adev);
4166 gfx_v8_0_set_gds_init(adev);
4171 static int gfx_v8_0_set_powergating_state(void *handle,
4172 enum amd_powergating_state state)
4177 static int gfx_v8_0_set_clockgating_state(void *handle,
4178 enum amd_clockgating_state state)
4183 static u32 gfx_v8_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
4187 rptr = ring->adev->wb.wb[ring->rptr_offs];
4192 static u32 gfx_v8_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
4194 struct amdgpu_device *adev = ring->adev;
4197 if (ring->use_doorbell)
4198 /* XXX check if swapping is necessary on BE */
4199 wptr = ring->adev->wb.wb[ring->wptr_offs];
4201 wptr = RREG32(mmCP_RB0_WPTR);
4206 static void gfx_v8_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
4208 struct amdgpu_device *adev = ring->adev;
4210 if (ring->use_doorbell) {
4211 /* XXX check if swapping is necessary on BE */
4212 adev->wb.wb[ring->wptr_offs] = ring->wptr;
4213 WDOORBELL32(ring->doorbell_index, ring->wptr);
4215 WREG32(mmCP_RB0_WPTR, ring->wptr);
4216 (void)RREG32(mmCP_RB0_WPTR);
4220 static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
4222 u32 ref_and_mask, reg_mem_engine;
4224 if (ring->type == AMDGPU_RING_TYPE_COMPUTE) {
4227 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
4230 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
4237 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
4238 reg_mem_engine = WAIT_REG_MEM_ENGINE(1); /* pfp */
4241 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4242 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
4243 WAIT_REG_MEM_FUNCTION(3) | /* == */
4245 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
4246 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
4247 amdgpu_ring_write(ring, ref_and_mask);
4248 amdgpu_ring_write(ring, ref_and_mask);
4249 amdgpu_ring_write(ring, 0x20); /* poll interval */
4252 static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
4253 struct amdgpu_ib *ib)
4255 bool need_ctx_switch = ring->current_ctx != ib->ctx;
4256 u32 header, control = 0;
4257 u32 next_rptr = ring->wptr + 5;
4259 /* drop the CE preamble IB for the same context */
4260 if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && !need_ctx_switch)
4263 if (need_ctx_switch)
4267 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4268 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
4269 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
4270 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
4271 amdgpu_ring_write(ring, next_rptr);
4273 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
4274 if (need_ctx_switch) {
4275 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4276 amdgpu_ring_write(ring, 0);
4279 if (ib->flags & AMDGPU_IB_FLAG_CE)
4280 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
4282 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4284 control |= ib->length_dw |
4285 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
4287 amdgpu_ring_write(ring, header);
4288 amdgpu_ring_write(ring,
4292 (ib->gpu_addr & 0xFFFFFFFC));
4293 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
4294 amdgpu_ring_write(ring, control);
4297 static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4298 struct amdgpu_ib *ib)
4300 u32 header, control = 0;
4301 u32 next_rptr = ring->wptr + 5;
4303 control |= INDIRECT_BUFFER_VALID;
4306 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4307 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM);
4308 amdgpu_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
4309 amdgpu_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
4310 amdgpu_ring_write(ring, next_rptr);
4312 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
4314 control |= ib->length_dw |
4315 (ib->vm ? (ib->vm->ids[ring->idx].id << 24) : 0);
4317 amdgpu_ring_write(ring, header);
4318 amdgpu_ring_write(ring,
4322 (ib->gpu_addr & 0xFFFFFFFC));
4323 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
4324 amdgpu_ring_write(ring, control);
4327 static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
4328 u64 seq, unsigned flags)
4330 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4331 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4333 /* EVENT_WRITE_EOP - flush caches, send int */
4334 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
4335 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
4337 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4339 amdgpu_ring_write(ring, addr & 0xfffffffc);
4340 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
4341 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
4342 amdgpu_ring_write(ring, lower_32_bits(seq));
4343 amdgpu_ring_write(ring, upper_32_bits(seq));
4348 * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring
4350 * @ring: amdgpu ring buffer object
4351 * @semaphore: amdgpu semaphore object
4352 * @emit_wait: Is this a sempahore wait?
4354 * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP
4355 * from running ahead of semaphore waits.
4357 static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring,
4358 struct amdgpu_semaphore *semaphore,
4361 uint64_t addr = semaphore->gpu_addr;
4362 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
4364 if (ring->adev->asic_type == CHIP_TOPAZ ||
4365 ring->adev->asic_type == CHIP_TONGA ||
4366 ring->adev->asic_type == CHIP_FIJI)
4367 /* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */
4370 amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2));
4371 amdgpu_ring_write(ring, lower_32_bits(addr));
4372 amdgpu_ring_write(ring, upper_32_bits(addr));
4373 amdgpu_ring_write(ring, sel);
4376 if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) {
4377 /* Prevent the PFP from running ahead of the semaphore wait */
4378 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4379 amdgpu_ring_write(ring, 0x0);
4385 static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4386 unsigned vm_id, uint64_t pd_addr)
4388 int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX);
4389 uint32_t seq = ring->fence_drv.sync_seq[ring->idx];
4390 uint64_t addr = ring->fence_drv.gpu_addr;
4392 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4393 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
4394 WAIT_REG_MEM_FUNCTION(3))); /* equal */
4395 amdgpu_ring_write(ring, addr & 0xfffffffc);
4396 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
4397 amdgpu_ring_write(ring, seq);
4398 amdgpu_ring_write(ring, 0xffffffff);
4399 amdgpu_ring_write(ring, 4); /* poll interval */
4402 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
4403 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4404 amdgpu_ring_write(ring, 0);
4405 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4406 amdgpu_ring_write(ring, 0);
4409 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4410 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
4411 WRITE_DATA_DST_SEL(0)) |
4414 amdgpu_ring_write(ring,
4415 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
4417 amdgpu_ring_write(ring,
4418 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
4420 amdgpu_ring_write(ring, 0);
4421 amdgpu_ring_write(ring, pd_addr >> 12);
4423 /* bits 0-15 are the VM contexts0-15 */
4424 /* invalidate the cache */
4425 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4426 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4427 WRITE_DATA_DST_SEL(0)));
4428 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4429 amdgpu_ring_write(ring, 0);
4430 amdgpu_ring_write(ring, 1 << vm_id);
4432 /* wait for the invalidate to complete */
4433 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
4434 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */
4435 WAIT_REG_MEM_FUNCTION(0) | /* always */
4436 WAIT_REG_MEM_ENGINE(0))); /* me */
4437 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
4438 amdgpu_ring_write(ring, 0);
4439 amdgpu_ring_write(ring, 0); /* ref */
4440 amdgpu_ring_write(ring, 0); /* mask */
4441 amdgpu_ring_write(ring, 0x20); /* poll interval */
4443 /* compute doesn't have PFP */
4445 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4446 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4447 amdgpu_ring_write(ring, 0x0);
4448 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4449 amdgpu_ring_write(ring, 0);
4450 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4451 amdgpu_ring_write(ring, 0);
4455 static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4457 return ring->adev->wb.wb[ring->rptr_offs];
4460 static u32 gfx_v8_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4462 return ring->adev->wb.wb[ring->wptr_offs];
4465 static void gfx_v8_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4467 struct amdgpu_device *adev = ring->adev;
4469 /* XXX check if swapping is necessary on BE */
4470 adev->wb.wb[ring->wptr_offs] = ring->wptr;
4471 WDOORBELL32(ring->doorbell_index, ring->wptr);
4474 static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
4478 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4479 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4481 /* RELEASE_MEM - flush caches, send int */
4482 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
4483 amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
4485 EOP_TC_WB_ACTION_EN |
4486 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4488 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
4489 amdgpu_ring_write(ring, addr & 0xfffffffc);
4490 amdgpu_ring_write(ring, upper_32_bits(addr));
4491 amdgpu_ring_write(ring, lower_32_bits(seq));
4492 amdgpu_ring_write(ring, upper_32_bits(seq));
4495 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4496 enum amdgpu_interrupt_state state)
4501 case AMDGPU_IRQ_STATE_DISABLE:
4502 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4503 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4504 TIME_STAMP_INT_ENABLE, 0);
4505 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4507 case AMDGPU_IRQ_STATE_ENABLE:
4508 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4510 REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4511 TIME_STAMP_INT_ENABLE, 1);
4512 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4519 static void gfx_v8_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4521 enum amdgpu_interrupt_state state)
4523 u32 mec_int_cntl, mec_int_cntl_reg;
4526 * amdgpu controls only pipe 0 of MEC1. That's why this function only
4527 * handles the setting of interrupts for this specific pipe. All other
4528 * pipes' interrupts are set by amdkfd.
4534 mec_int_cntl_reg = mmCP_ME1_PIPE0_INT_CNTL;
4537 DRM_DEBUG("invalid pipe %d\n", pipe);
4541 DRM_DEBUG("invalid me %d\n", me);
4546 case AMDGPU_IRQ_STATE_DISABLE:
4547 mec_int_cntl = RREG32(mec_int_cntl_reg);
4548 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4549 TIME_STAMP_INT_ENABLE, 0);
4550 WREG32(mec_int_cntl_reg, mec_int_cntl);
4552 case AMDGPU_IRQ_STATE_ENABLE:
4553 mec_int_cntl = RREG32(mec_int_cntl_reg);
4554 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4555 TIME_STAMP_INT_ENABLE, 1);
4556 WREG32(mec_int_cntl_reg, mec_int_cntl);
4563 static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4564 struct amdgpu_irq_src *source,
4566 enum amdgpu_interrupt_state state)
4571 case AMDGPU_IRQ_STATE_DISABLE:
4572 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4573 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4574 PRIV_REG_INT_ENABLE, 0);
4575 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4577 case AMDGPU_IRQ_STATE_ENABLE:
4578 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4579 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4580 PRIV_REG_INT_ENABLE, 0);
4581 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4590 static int gfx_v8_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4591 struct amdgpu_irq_src *source,
4593 enum amdgpu_interrupt_state state)
4598 case AMDGPU_IRQ_STATE_DISABLE:
4599 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4600 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4601 PRIV_INSTR_INT_ENABLE, 0);
4602 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4604 case AMDGPU_IRQ_STATE_ENABLE:
4605 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
4606 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
4607 PRIV_INSTR_INT_ENABLE, 1);
4608 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
4617 static int gfx_v8_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4618 struct amdgpu_irq_src *src,
4620 enum amdgpu_interrupt_state state)
4623 case AMDGPU_CP_IRQ_GFX_EOP:
4624 gfx_v8_0_set_gfx_eop_interrupt_state(adev, state);
4626 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4627 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4629 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4630 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4632 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4633 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4635 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4636 gfx_v8_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4638 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4639 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4641 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4642 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4644 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4645 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4647 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4648 gfx_v8_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4656 static int gfx_v8_0_eop_irq(struct amdgpu_device *adev,
4657 struct amdgpu_irq_src *source,
4658 struct amdgpu_iv_entry *entry)
4661 u8 me_id, pipe_id, queue_id;
4662 struct amdgpu_ring *ring;
4664 DRM_DEBUG("IH: CP EOP\n");
4665 me_id = (entry->ring_id & 0x0c) >> 2;
4666 pipe_id = (entry->ring_id & 0x03) >> 0;
4667 queue_id = (entry->ring_id & 0x70) >> 4;
4671 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4675 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4676 ring = &adev->gfx.compute_ring[i];
4677 /* Per-queue interrupt is supported for MEC starting from VI.
4678 * The interrupt can only be enabled/disabled per pipe instead of per queue.
4680 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4681 amdgpu_fence_process(ring);
4688 static int gfx_v8_0_priv_reg_irq(struct amdgpu_device *adev,
4689 struct amdgpu_irq_src *source,
4690 struct amdgpu_iv_entry *entry)
4692 DRM_ERROR("Illegal register access in command stream\n");
4693 schedule_work(&adev->reset_work);
4697 static int gfx_v8_0_priv_inst_irq(struct amdgpu_device *adev,
4698 struct amdgpu_irq_src *source,
4699 struct amdgpu_iv_entry *entry)
4701 DRM_ERROR("Illegal instruction in command stream\n");
4702 schedule_work(&adev->reset_work);
4706 const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
4707 .early_init = gfx_v8_0_early_init,
4709 .sw_init = gfx_v8_0_sw_init,
4710 .sw_fini = gfx_v8_0_sw_fini,
4711 .hw_init = gfx_v8_0_hw_init,
4712 .hw_fini = gfx_v8_0_hw_fini,
4713 .suspend = gfx_v8_0_suspend,
4714 .resume = gfx_v8_0_resume,
4715 .is_idle = gfx_v8_0_is_idle,
4716 .wait_for_idle = gfx_v8_0_wait_for_idle,
4717 .soft_reset = gfx_v8_0_soft_reset,
4718 .print_status = gfx_v8_0_print_status,
4719 .set_clockgating_state = gfx_v8_0_set_clockgating_state,
4720 .set_powergating_state = gfx_v8_0_set_powergating_state,
4723 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
4724 .get_rptr = gfx_v8_0_ring_get_rptr_gfx,
4725 .get_wptr = gfx_v8_0_ring_get_wptr_gfx,
4726 .set_wptr = gfx_v8_0_ring_set_wptr_gfx,
4728 .emit_ib = gfx_v8_0_ring_emit_ib_gfx,
4729 .emit_fence = gfx_v8_0_ring_emit_fence_gfx,
4730 .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4731 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4732 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
4733 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4734 .test_ring = gfx_v8_0_ring_test_ring,
4735 .test_ib = gfx_v8_0_ring_test_ib,
4736 .insert_nop = amdgpu_ring_insert_nop,
4739 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
4740 .get_rptr = gfx_v8_0_ring_get_rptr_compute,
4741 .get_wptr = gfx_v8_0_ring_get_wptr_compute,
4742 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
4744 .emit_ib = gfx_v8_0_ring_emit_ib_compute,
4745 .emit_fence = gfx_v8_0_ring_emit_fence_compute,
4746 .emit_semaphore = gfx_v8_0_ring_emit_semaphore,
4747 .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush,
4748 .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch,
4749 .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
4750 .test_ring = gfx_v8_0_ring_test_ring,
4751 .test_ib = gfx_v8_0_ring_test_ib,
4752 .insert_nop = amdgpu_ring_insert_nop,
4755 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
4759 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4760 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx;
4762 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4763 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute;
4766 static const struct amdgpu_irq_src_funcs gfx_v8_0_eop_irq_funcs = {
4767 .set = gfx_v8_0_set_eop_interrupt_state,
4768 .process = gfx_v8_0_eop_irq,
4771 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_reg_irq_funcs = {
4772 .set = gfx_v8_0_set_priv_reg_fault_state,
4773 .process = gfx_v8_0_priv_reg_irq,
4776 static const struct amdgpu_irq_src_funcs gfx_v8_0_priv_inst_irq_funcs = {
4777 .set = gfx_v8_0_set_priv_inst_fault_state,
4778 .process = gfx_v8_0_priv_inst_irq,
4781 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev)
4783 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4784 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs;
4786 adev->gfx.priv_reg_irq.num_types = 1;
4787 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs;
4789 adev->gfx.priv_inst_irq.num_types = 1;
4790 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs;
4793 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev)
4795 /* init asci gds info */
4796 adev->gds.mem.total_size = RREG32(mmGDS_VMID0_SIZE);
4797 adev->gds.gws.total_size = 64;
4798 adev->gds.oa.total_size = 16;
4800 if (adev->gds.mem.total_size == 64 * 1024) {
4801 adev->gds.mem.gfx_partition_size = 4096;
4802 adev->gds.mem.cs_partition_size = 4096;
4804 adev->gds.gws.gfx_partition_size = 4;
4805 adev->gds.gws.cs_partition_size = 4;
4807 adev->gds.oa.gfx_partition_size = 4;
4808 adev->gds.oa.cs_partition_size = 1;
4810 adev->gds.mem.gfx_partition_size = 1024;
4811 adev->gds.mem.cs_partition_size = 1024;
4813 adev->gds.gws.gfx_partition_size = 16;
4814 adev->gds.gws.cs_partition_size = 16;
4816 adev->gds.oa.gfx_partition_size = 4;
4817 adev->gds.oa.cs_partition_size = 4;
4821 static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev,
4824 u32 mask = 0, tmp, tmp1;
4827 gfx_v8_0_select_se_sh(adev, se, sh);
4828 tmp = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
4829 tmp1 = RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
4830 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4837 for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) {
4842 return (~tmp) & mask;
4845 int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
4846 struct amdgpu_cu_info *cu_info)
4848 int i, j, k, counter, active_cu_number = 0;
4849 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4851 if (!adev || !cu_info)
4854 mutex_lock(&adev->grbm_idx_mutex);
4855 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4856 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4860 bitmap = gfx_v8_0_get_cu_active_bitmap(adev, i, j);
4861 cu_info->bitmap[i][j] = bitmap;
4863 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4864 if (bitmap & mask) {
4871 active_cu_number += counter;
4872 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4876 cu_info->number = active_cu_number;
4877 cu_info->ao_cu_mask = ao_cu_mask;
4878 mutex_unlock(&adev->grbm_idx_mutex);