2 * Copyright (C) 2012 Russell King
3 * Rewritten from the dovefb driver, and Armada510 manuals.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/component.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
14 #include <drm/drm_crtc_helper.h>
15 #include "armada_crtc.h"
16 #include "armada_drm.h"
17 #include "armada_fb.h"
18 #include "armada_gem.h"
19 #include "armada_hw.h"
21 struct armada_frame_work {
22 struct drm_pending_vblank_event *event;
23 struct armada_regs regs[4];
24 struct drm_framebuffer *old_fb;
36 * A note about interlacing. Let's consider HDMI 1920x1080i.
37 * The timing parameters we have from X are:
38 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
39 * 1920 2448 2492 2640 1080 1084 1094 1125
40 * Which get translated to:
41 * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot
42 * 1920 2448 2492 2640 540 542 547 562
44 * This is how it is defined by CEA-861-D - line and pixel numbers are
45 * referenced to the rising edge of VSYNC and HSYNC. Total clocks per
46 * line: 2640. The odd frame, the first active line is at line 21, and
47 * the even frame, the first active line is 584.
49 * LN: 560 561 562 563 567 568 569
50 * DE: ~~~|____________________________//__________________________
51 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
52 * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________
53 * 22 blanking lines. VSYNC at 1320 (referenced to the HSYNC rising edge).
55 * LN: 1123 1124 1125 1 5 6 7
56 * DE: ~~~|____________________________//__________________________
57 * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____
58 * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________
61 * The Armada LCD Controller line and pixel numbers are, like X timings,
62 * referenced to the top left of the active frame.
64 * So, translating these to our LCD controller:
65 * Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128.
66 * Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448.
67 * Note: Vsync front porch remains constant!
70 * vtotal = mode->crtc_vtotal + 1;
71 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1;
72 * vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2
74 * vtotal = mode->crtc_vtotal;
75 * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay;
76 * vhorizpos = mode->crtc_hsync_start;
78 * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end;
80 * So, we need to reprogram these registers on each vsync event:
81 * LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL
83 * Note: we do not use the frame done interrupts because these appear
84 * to happen too early, and lead to jitter on the display (presumably
85 * they occur at the end of the last active line, before the vsync back
86 * porch, which we're reprogramming.)
90 armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs)
92 while (regs->offset != ~0) {
93 void __iomem *reg = dcrtc->base + regs->offset;
98 val &= readl_relaxed(reg);
99 writel_relaxed(val | regs->val, reg);
104 #define dpms_blanked(dpms) ((dpms) != DRM_MODE_DPMS_ON)
106 static void armada_drm_crtc_update(struct armada_crtc *dcrtc)
110 dumb_ctrl = dcrtc->cfg_dumb_ctrl;
112 if (!dpms_blanked(dcrtc->dpms))
113 dumb_ctrl |= CFG_DUMB_ENA;
116 * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might
117 * be using SPI or GPIO. If we set this to DUMB_BLANK, we will
118 * force LCD_D[23:0] to output blank color, overriding the GPIO or
119 * SPI usage. So leave it as-is unless in DUMB24_RGB888_0 mode.
121 if (dpms_blanked(dcrtc->dpms) &&
122 (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) {
123 dumb_ctrl &= ~DUMB_MASK;
124 dumb_ctrl |= DUMB_BLANK;
128 * The documentation doesn't indicate what the normal state of
129 * the sync signals are. Sebastian Hesselbart kindly probed
130 * these signals on his board to determine their state.
132 * The non-inverted state of the sync signals is active high.
133 * Setting these bits makes the appropriate signal active low.
135 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC)
136 dumb_ctrl |= CFG_INV_CSYNC;
137 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC)
138 dumb_ctrl |= CFG_INV_HSYNC;
139 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC)
140 dumb_ctrl |= CFG_INV_VSYNC;
142 if (dcrtc->dumb_ctrl != dumb_ctrl) {
143 dcrtc->dumb_ctrl = dumb_ctrl;
144 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);
148 static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb,
149 int x, int y, struct armada_regs *regs, bool interlaced)
151 struct armada_gem_object *obj = drm_fb_obj(fb);
152 unsigned pitch = fb->pitches[0];
153 unsigned offset = y * pitch + x * fb->bits_per_pixel / 8;
154 uint32_t addr_odd, addr_even;
157 DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n",
158 pitch, x, y, fb->bits_per_pixel);
160 addr_odd = addr_even = obj->dev_addr + offset;
167 /* write offset, base, and pitch */
168 armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0);
169 armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1);
170 armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH);
175 static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc,
176 struct armada_frame_work *work)
178 struct drm_device *dev = dcrtc->crtc.dev;
182 ret = drm_vblank_get(dev, dcrtc->num);
184 DRM_ERROR("failed to acquire vblank counter\n");
188 spin_lock_irqsave(&dev->event_lock, flags);
189 if (!dcrtc->frame_work)
190 dcrtc->frame_work = work;
193 spin_unlock_irqrestore(&dev->event_lock, flags);
196 drm_vblank_put(dev, dcrtc->num);
201 static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc)
203 struct drm_device *dev = dcrtc->crtc.dev;
204 struct armada_frame_work *work = dcrtc->frame_work;
206 dcrtc->frame_work = NULL;
208 armada_drm_crtc_update_regs(dcrtc, work->regs);
211 drm_send_vblank_event(dev, dcrtc->num, work->event);
213 drm_vblank_put(dev, dcrtc->num);
215 /* Finally, queue the process-half of the cleanup. */
216 __armada_drm_queue_unref_work(dcrtc->crtc.dev, work->old_fb);
220 static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc,
221 struct drm_framebuffer *fb, bool force)
223 struct armada_frame_work *work;
229 /* Display is disabled, so just drop the old fb */
230 drm_framebuffer_unreference(fb);
234 work = kmalloc(sizeof(*work), GFP_KERNEL);
239 armada_reg_queue_end(work->regs, i);
241 if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0)
248 * Oops - just drop the reference immediately and hope for
249 * the best. The worst that will happen is the buffer gets
250 * reused before it has finished being displayed.
252 drm_framebuffer_unreference(fb);
255 static void armada_drm_vblank_off(struct armada_crtc *dcrtc)
257 struct drm_device *dev = dcrtc->crtc.dev;
260 * Tell the DRM core that vblank IRQs aren't going to happen for
261 * a while. This cleans up any pending vblank events for us.
263 drm_vblank_off(dev, dcrtc->num);
265 /* Handle any pending flip event. */
266 spin_lock_irq(&dev->event_lock);
267 if (dcrtc->frame_work)
268 armada_drm_crtc_complete_frame_work(dcrtc);
269 spin_unlock_irq(&dev->event_lock);
272 void armada_drm_crtc_gamma_set(struct drm_crtc *crtc, u16 r, u16 g, u16 b,
277 void armada_drm_crtc_gamma_get(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
282 /* The mode_config.mutex will be held for this call */
283 static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms)
285 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
287 if (dcrtc->dpms != dpms) {
289 armada_drm_crtc_update(dcrtc);
290 if (dpms_blanked(dpms))
291 armada_drm_vblank_off(dcrtc);
296 * Prepare for a mode set. Turn off overlay to ensure that we don't end
297 * up with the overlay size being bigger than the active screen size.
298 * We rely upon X refreshing this state after the mode set has completed.
300 * The mode_config.mutex will be held for this call
302 static void armada_drm_crtc_prepare(struct drm_crtc *crtc)
304 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
305 struct drm_plane *plane;
308 * If we have an overlay plane associated with this CRTC, disable
309 * it before the modeset to avoid its coordinates being outside
310 * the new mode parameters. DRM doesn't provide help with this.
312 plane = dcrtc->plane;
314 struct drm_framebuffer *fb = plane->fb;
316 plane->funcs->disable_plane(plane);
319 drm_framebuffer_unreference(fb);
323 /* The mode_config.mutex will be held for this call */
324 static void armada_drm_crtc_commit(struct drm_crtc *crtc)
326 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
328 if (dcrtc->dpms != DRM_MODE_DPMS_ON) {
329 dcrtc->dpms = DRM_MODE_DPMS_ON;
330 armada_drm_crtc_update(dcrtc);
334 /* The mode_config.mutex will be held for this call */
335 static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc,
336 const struct drm_display_mode *mode, struct drm_display_mode *adj)
338 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
341 /* We can't do interlaced modes if we don't have the SPU_ADV_REG */
342 if (!dcrtc->variant->has_spu_adv_reg &&
343 adj->flags & DRM_MODE_FLAG_INTERLACE)
346 /* Check whether the display mode is possible */
347 ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);
354 static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
356 struct armada_vbl_event *e, *n;
357 void __iomem *base = dcrtc->base;
359 if (stat & DMA_FF_UNDERFLOW)
360 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num);
361 if (stat & GRA_FF_UNDERFLOW)
362 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num);
364 if (stat & VSYNC_IRQ)
365 drm_handle_vblank(dcrtc->crtc.dev, dcrtc->num);
367 spin_lock(&dcrtc->irq_lock);
369 list_for_each_entry_safe(e, n, &dcrtc->vbl_list, node) {
370 list_del_init(&e->node);
371 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
372 e->fn(dcrtc, e->data);
375 if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) {
376 int i = stat & GRA_FRAME_IRQ0 ? 0 : 1;
379 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);
380 writel_relaxed(dcrtc->v[i].spu_v_h_total,
381 base + LCD_SPUT_V_H_TOTAL);
383 val = readl_relaxed(base + LCD_SPU_ADV_REG);
384 val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN);
385 val |= dcrtc->v[i].spu_adv_reg;
386 writel_relaxed(val, base + LCD_SPU_ADV_REG);
389 if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) {
390 writel_relaxed(dcrtc->cursor_hw_pos,
391 base + LCD_SPU_HWC_OVSA_HPXL_VLN);
392 writel_relaxed(dcrtc->cursor_hw_sz,
393 base + LCD_SPU_HWC_HPXL_VLN);
394 armada_updatel(CFG_HWC_ENA,
395 CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA,
396 base + LCD_SPU_DMA_CTRL0);
397 dcrtc->cursor_update = false;
398 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
401 spin_unlock(&dcrtc->irq_lock);
403 if (stat & GRA_FRAME_IRQ) {
404 struct drm_device *dev = dcrtc->crtc.dev;
406 spin_lock(&dev->event_lock);
407 if (dcrtc->frame_work)
408 armada_drm_crtc_complete_frame_work(dcrtc);
409 spin_unlock(&dev->event_lock);
411 wake_up(&dcrtc->frame_wait);
415 static irqreturn_t armada_drm_irq(int irq, void *arg)
417 struct armada_crtc *dcrtc = arg;
418 u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR);
421 * This is rediculous - rather than writing bits to clear, we
422 * have to set the actual status register value. This is racy.
424 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
426 /* Mask out those interrupts we haven't enabled */
427 v = stat & dcrtc->irq_ena;
429 if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) {
430 armada_drm_crtc_irq(dcrtc, stat);
436 /* These are locked by dev->vbl_lock */
437 void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask)
439 if (dcrtc->irq_ena & mask) {
440 dcrtc->irq_ena &= ~mask;
441 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
445 void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask)
447 if ((dcrtc->irq_ena & mask) != mask) {
448 dcrtc->irq_ena |= mask;
449 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
450 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask)
451 writel(0, dcrtc->base + LCD_SPU_IRQ_ISR);
455 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
457 struct drm_display_mode *adj = &dcrtc->crtc.mode;
460 if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709)
461 val |= CFG_CSC_YUV_CCIR709;
462 if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO)
463 val |= CFG_CSC_RGB_STUDIO;
466 * In auto mode, set the colorimetry, based upon the HDMI spec.
467 * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use
468 * ITU601. It may be more appropriate to set this depending on
469 * the source - but what if the graphic frame is YUV and the
470 * video frame is RGB?
472 if ((adj->hdisplay == 1280 && adj->vdisplay == 720 &&
473 !(adj->flags & DRM_MODE_FLAG_INTERLACE)) ||
474 (adj->hdisplay == 1920 && adj->vdisplay == 1080)) {
475 if (dcrtc->csc_yuv_mode == CSC_AUTO)
476 val |= CFG_CSC_YUV_CCIR709;
480 * We assume we're connected to a TV-like device, so the YUV->RGB
481 * conversion should produce a limited range. We should set this
482 * depending on the connectors attached to this CRTC, and what
483 * kind of device they report being connected.
485 if (dcrtc->csc_rgb_mode == CSC_AUTO)
486 val |= CFG_CSC_RGB_STUDIO;
491 /* The mode_config.mutex will be held for this call */
492 static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
493 struct drm_display_mode *mode, struct drm_display_mode *adj,
494 int x, int y, struct drm_framebuffer *old_fb)
496 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
497 struct armada_regs regs[17];
498 uint32_t lm, rm, tm, bm, val, sclk;
503 drm_framebuffer_reference(crtc->primary->fb);
505 interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
507 i = armada_drm_crtc_calc_fb(dcrtc->crtc.primary->fb,
508 x, y, regs, interlaced);
510 rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
511 lm = adj->crtc_htotal - adj->crtc_hsync_end;
512 bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
513 tm = adj->crtc_vtotal - adj->crtc_vsync_end;
515 DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n",
517 adj->crtc_hsync_start,
519 adj->crtc_htotal, lm, rm);
520 DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n",
522 adj->crtc_vsync_start,
524 adj->crtc_vtotal, tm, bm);
526 /* Wait for pending flips to complete */
527 wait_event(dcrtc->frame_wait, !dcrtc->frame_work);
529 drm_vblank_pre_modeset(crtc->dev, dcrtc->num);
533 val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA;
534 if (val != dcrtc->dumb_ctrl) {
535 dcrtc->dumb_ctrl = val;
536 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);
539 /* Now compute the divider for real */
540 dcrtc->variant->compute_clock(dcrtc, adj, &sclk);
542 /* Ensure graphic fifo is enabled */
543 armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1);
544 armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV);
546 if (interlaced ^ dcrtc->interlaced) {
547 if (adj->flags & DRM_MODE_FLAG_INTERLACE)
548 drm_vblank_get(dcrtc->crtc.dev, dcrtc->num);
550 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num);
551 dcrtc->interlaced = interlaced;
554 spin_lock_irqsave(&dcrtc->irq_lock, flags);
556 /* Even interlaced/progressive frame */
557 dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
559 dcrtc->v[1].spu_v_porch = tm << 16 | bm;
560 val = adj->crtc_hsync_start;
561 dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
562 dcrtc->variant->spu_adv_reg;
565 /* Odd interlaced frame */
566 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total +
568 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1;
569 val = adj->crtc_hsync_start - adj->crtc_htotal / 2;
570 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN |
571 dcrtc->variant->spu_adv_reg;
573 dcrtc->v[0] = dcrtc->v[1];
576 val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
578 armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE);
579 armada_reg_queue_set(regs, i, val, LCD_SPU_GRA_HPXL_VLN);
580 armada_reg_queue_set(regs, i, val, LCD_SPU_GZM_HPXL_VLN);
581 armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH);
582 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH);
583 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total,
586 if (dcrtc->variant->has_spu_adv_reg) {
587 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg,
588 ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF |
589 ADV_VSYNCOFFEN, LCD_SPU_ADV_REG);
592 val = CFG_GRA_ENA | CFG_GRA_HSMOOTH;
593 val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt);
594 val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod);
596 if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420)
597 val |= CFG_PALETTE_ENA;
600 val |= CFG_GRA_FTOGGLE;
602 armada_reg_queue_mod(regs, i, val, CFG_GRAFORMAT |
603 CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
604 CFG_SWAPYU | CFG_YUV2RGB) |
605 CFG_PALETTE_ENA | CFG_GRA_FTOGGLE,
608 val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
609 armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1);
611 val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc);
612 armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL);
613 armada_reg_queue_end(regs, i);
615 armada_drm_crtc_update_regs(dcrtc, regs);
616 spin_unlock_irqrestore(&dcrtc->irq_lock, flags);
618 armada_drm_crtc_update(dcrtc);
620 drm_vblank_post_modeset(crtc->dev, dcrtc->num);
621 armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
626 /* The mode_config.mutex will be held for this call */
627 static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
628 struct drm_framebuffer *old_fb)
630 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
631 struct armada_regs regs[4];
634 i = armada_drm_crtc_calc_fb(crtc->primary->fb, crtc->x, crtc->y, regs,
636 armada_reg_queue_end(regs, i);
638 /* Wait for pending flips to complete */
639 wait_event(dcrtc->frame_wait, !dcrtc->frame_work);
641 /* Take a reference to the new fb as we're using it */
642 drm_framebuffer_reference(crtc->primary->fb);
644 /* Update the base in the CRTC */
645 armada_drm_crtc_update_regs(dcrtc, regs);
647 /* Drop our previously held reference */
648 armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms));
653 static void armada_drm_crtc_load_lut(struct drm_crtc *crtc)
657 /* The mode_config.mutex will be held for this call */
658 static void armada_drm_crtc_disable(struct drm_crtc *crtc)
660 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
662 armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
663 armada_drm_crtc_finish_fb(dcrtc, crtc->primary->fb, true);
665 /* Power down most RAMs and FIFOs */
666 writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
667 CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
668 CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
671 static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = {
672 .dpms = armada_drm_crtc_dpms,
673 .prepare = armada_drm_crtc_prepare,
674 .commit = armada_drm_crtc_commit,
675 .mode_fixup = armada_drm_crtc_mode_fixup,
676 .mode_set = armada_drm_crtc_mode_set,
677 .mode_set_base = armada_drm_crtc_mode_set_base,
678 .load_lut = armada_drm_crtc_load_lut,
679 .disable = armada_drm_crtc_disable,
682 static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix,
683 unsigned stride, unsigned width, unsigned height)
688 addr = SRAM_HWC32_RAM1;
689 for (y = 0; y < height; y++) {
690 uint32_t *p = &pix[y * stride];
693 for (x = 0; x < width; x++, p++) {
696 val = (val & 0xff00ff00) |
697 (val & 0x000000ff) << 16 |
698 (val & 0x00ff0000) >> 16;
701 base + LCD_SPU_SRAM_WRDAT);
702 writel_relaxed(addr | SRAM_WRITE,
703 base + LCD_SPU_SRAM_CTRL);
704 readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN);
706 if ((addr & 0x00ff) == 0)
708 if ((addr & 0x30ff) == 0)
709 addr = SRAM_HWC32_RAM2;
714 static void armada_drm_crtc_cursor_tran(void __iomem *base)
718 for (addr = 0; addr < 256; addr++) {
719 /* write the default value */
720 writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);
721 writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,
722 base + LCD_SPU_SRAM_CTRL);
726 static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload)
728 uint32_t xoff, xscr, w = dcrtc->cursor_w, s;
729 uint32_t yoff, yscr, h = dcrtc->cursor_h;
733 * Calculate the visible width and height of the cursor,
734 * screen position, and the position in the cursor bitmap.
736 if (dcrtc->cursor_x < 0) {
737 xoff = -dcrtc->cursor_x;
740 } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) {
742 xscr = dcrtc->cursor_x;
743 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0);
746 xscr = dcrtc->cursor_x;
749 if (dcrtc->cursor_y < 0) {
750 yoff = -dcrtc->cursor_y;
753 } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) {
755 yscr = dcrtc->cursor_y;
756 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0);
759 yscr = dcrtc->cursor_y;
762 /* On interlaced modes, the vertical cursor size must be halved */
764 if (dcrtc->interlaced) {
770 if (!dcrtc->cursor_obj || !h || !w) {
771 spin_lock_irq(&dcrtc->irq_lock);
772 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
773 dcrtc->cursor_update = false;
774 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
775 spin_unlock_irq(&dcrtc->irq_lock);
779 para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1);
780 armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32,
781 dcrtc->base + LCD_SPU_SRAM_PARA1);
784 * Initialize the transparency if the SRAM was powered down.
785 * We must also reload the cursor data as well.
787 if (!(para1 & CFG_CSB_256x32)) {
788 armada_drm_crtc_cursor_tran(dcrtc->base);
792 if (dcrtc->cursor_hw_sz != (h << 16 | w)) {
793 spin_lock_irq(&dcrtc->irq_lock);
794 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
795 dcrtc->cursor_update = false;
796 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
797 spin_unlock_irq(&dcrtc->irq_lock);
801 struct armada_gem_object *obj = dcrtc->cursor_obj;
803 /* Set the top-left corner of the cursor image */
805 pix += yoff * s + xoff;
806 armada_load_cursor_argb(dcrtc->base, pix, s, w, h);
809 /* Reload the cursor position, size and enable in the IRQ handler */
810 spin_lock_irq(&dcrtc->irq_lock);
811 dcrtc->cursor_hw_pos = yscr << 16 | xscr;
812 dcrtc->cursor_hw_sz = h << 16 | w;
813 dcrtc->cursor_update = true;
814 armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA);
815 spin_unlock_irq(&dcrtc->irq_lock);
820 static void cursor_update(void *data)
822 armada_drm_crtc_cursor_update(data, true);
825 static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc,
826 struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h)
828 struct drm_device *dev = crtc->dev;
829 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
830 struct armada_gem_object *obj = NULL;
833 /* If no cursor support, replicate drm's return value */
834 if (!dcrtc->variant->has_spu_adv_reg)
837 if (handle && w > 0 && h > 0) {
838 /* maximum size is 64x32 or 32x64 */
839 if (w > 64 || h > 64 || (w > 32 && h > 32))
842 obj = armada_gem_object_lookup(dev, file, handle);
846 /* Must be a kernel-mapped object */
848 drm_gem_object_unreference_unlocked(&obj->obj);
852 if (obj->obj.size < w * h * 4) {
853 DRM_ERROR("buffer is too small\n");
854 drm_gem_object_unreference_unlocked(&obj->obj);
859 mutex_lock(&dev->struct_mutex);
860 if (dcrtc->cursor_obj) {
861 dcrtc->cursor_obj->update = NULL;
862 dcrtc->cursor_obj->update_data = NULL;
863 drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
865 dcrtc->cursor_obj = obj;
868 ret = armada_drm_crtc_cursor_update(dcrtc, true);
870 obj->update_data = dcrtc;
871 obj->update = cursor_update;
873 mutex_unlock(&dev->struct_mutex);
878 static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
880 struct drm_device *dev = crtc->dev;
881 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
884 /* If no cursor support, replicate drm's return value */
885 if (!dcrtc->variant->has_spu_adv_reg)
888 mutex_lock(&dev->struct_mutex);
891 ret = armada_drm_crtc_cursor_update(dcrtc, false);
892 mutex_unlock(&dev->struct_mutex);
897 static void armada_drm_crtc_destroy(struct drm_crtc *crtc)
899 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
900 struct armada_private *priv = crtc->dev->dev_private;
902 if (dcrtc->cursor_obj)
903 drm_gem_object_unreference(&dcrtc->cursor_obj->obj);
905 priv->dcrtc[dcrtc->num] = NULL;
906 drm_crtc_cleanup(&dcrtc->crtc);
908 if (!IS_ERR(dcrtc->clk))
909 clk_disable_unprepare(dcrtc->clk);
911 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA);
913 of_node_put(dcrtc->crtc.port);
919 * The mode_config lock is held here, to prevent races between this
922 static int armada_drm_crtc_page_flip(struct drm_crtc *crtc,
923 struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
925 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
926 struct armada_frame_work *work;
927 struct drm_device *dev = crtc->dev;
932 /* We don't support changing the pixel format */
933 if (fb->pixel_format != crtc->primary->fb->pixel_format)
936 work = kmalloc(sizeof(*work), GFP_KERNEL);
941 work->old_fb = dcrtc->crtc.primary->fb;
943 i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs,
945 armada_reg_queue_end(work->regs, i);
948 * Hold the old framebuffer for the work - DRM appears to drop our
949 * reference to the old framebuffer in drm_mode_page_flip_ioctl().
951 drm_framebuffer_reference(work->old_fb);
953 ret = armada_drm_crtc_queue_frame_work(dcrtc, work);
956 * Undo our reference above; DRM does not drop the reference
957 * to this object on error, so that's okay.
959 drm_framebuffer_unreference(work->old_fb);
965 * Don't take a reference on the new framebuffer;
966 * drm_mode_page_flip_ioctl() has already grabbed a reference and
967 * will _not_ drop that reference on successful return from this
968 * function. Simply mark this new framebuffer as the current one.
970 dcrtc->crtc.primary->fb = fb;
973 * Finally, if the display is blanked, we won't receive an
974 * interrupt, so complete it now.
976 if (dpms_blanked(dcrtc->dpms)) {
977 spin_lock_irqsave(&dev->event_lock, flags);
978 if (dcrtc->frame_work)
979 armada_drm_crtc_complete_frame_work(dcrtc);
980 spin_unlock_irqrestore(&dev->event_lock, flags);
987 armada_drm_crtc_set_property(struct drm_crtc *crtc,
988 struct drm_property *property, uint64_t val)
990 struct armada_private *priv = crtc->dev->dev_private;
991 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
992 bool update_csc = false;
994 if (property == priv->csc_yuv_prop) {
995 dcrtc->csc_yuv_mode = val;
997 } else if (property == priv->csc_rgb_prop) {
998 dcrtc->csc_rgb_mode = val;
1005 val = dcrtc->spu_iopad_ctrl |
1006 armada_drm_crtc_calculate_csc(dcrtc);
1007 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1013 static struct drm_crtc_funcs armada_crtc_funcs = {
1014 .cursor_set = armada_drm_crtc_cursor_set,
1015 .cursor_move = armada_drm_crtc_cursor_move,
1016 .destroy = armada_drm_crtc_destroy,
1017 .set_config = drm_crtc_helper_set_config,
1018 .page_flip = armada_drm_crtc_page_flip,
1019 .set_property = armada_drm_crtc_set_property,
1022 static struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
1023 { CSC_AUTO, "Auto" },
1024 { CSC_YUV_CCIR601, "CCIR601" },
1025 { CSC_YUV_CCIR709, "CCIR709" },
1028 static struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = {
1029 { CSC_AUTO, "Auto" },
1030 { CSC_RGB_COMPUTER, "Computer system" },
1031 { CSC_RGB_STUDIO, "Studio" },
1034 static int armada_drm_crtc_create_properties(struct drm_device *dev)
1036 struct armada_private *priv = dev->dev_private;
1038 if (priv->csc_yuv_prop)
1041 priv->csc_yuv_prop = drm_property_create_enum(dev, 0,
1042 "CSC_YUV", armada_drm_csc_yuv_enum_list,
1043 ARRAY_SIZE(armada_drm_csc_yuv_enum_list));
1044 priv->csc_rgb_prop = drm_property_create_enum(dev, 0,
1045 "CSC_RGB", armada_drm_csc_rgb_enum_list,
1046 ARRAY_SIZE(armada_drm_csc_rgb_enum_list));
1048 if (!priv->csc_yuv_prop || !priv->csc_rgb_prop)
1054 int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
1055 struct resource *res, int irq, const struct armada_variant *variant,
1056 struct device_node *port)
1058 struct armada_private *priv = drm->dev_private;
1059 struct armada_crtc *dcrtc;
1063 ret = armada_drm_crtc_create_properties(drm);
1067 base = devm_ioremap_resource(dev, res);
1069 return PTR_ERR(base);
1071 dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL);
1073 DRM_ERROR("failed to allocate Armada crtc\n");
1077 if (dev != drm->dev)
1078 dev_set_drvdata(dev, dcrtc);
1080 dcrtc->variant = variant;
1082 dcrtc->num = drm->mode_config.num_crtc;
1083 dcrtc->clk = ERR_PTR(-EINVAL);
1084 dcrtc->csc_yuv_mode = CSC_AUTO;
1085 dcrtc->csc_rgb_mode = CSC_AUTO;
1086 dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0;
1087 dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24;
1088 spin_lock_init(&dcrtc->irq_lock);
1089 dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
1090 INIT_LIST_HEAD(&dcrtc->vbl_list);
1091 init_waitqueue_head(&dcrtc->frame_wait);
1093 /* Initialize some registers which we don't otherwise set */
1094 writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
1095 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);
1096 writel_relaxed(dcrtc->spu_iopad_ctrl,
1097 dcrtc->base + LCD_SPU_IOPAD_CONTROL);
1098 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);
1099 writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |
1100 CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 |
1101 CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1);
1102 writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);
1103 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_GRA_OVSA_HPXL_VLN);
1104 writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);
1105 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);
1107 ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc",
1114 if (dcrtc->variant->init) {
1115 ret = dcrtc->variant->init(dcrtc, dev);
1122 /* Ensure AXI pipeline is enabled */
1123 armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0);
1125 priv->dcrtc[dcrtc->num] = dcrtc;
1127 dcrtc->crtc.port = port;
1128 drm_crtc_init(drm, &dcrtc->crtc, &armada_crtc_funcs);
1129 drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs);
1131 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop,
1132 dcrtc->csc_yuv_mode);
1133 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop,
1134 dcrtc->csc_rgb_mode);
1136 return armada_overlay_plane_create(drm, 1 << dcrtc->num);
1140 armada_lcd_bind(struct device *dev, struct device *master, void *data)
1142 struct platform_device *pdev = to_platform_device(dev);
1143 struct drm_device *drm = data;
1144 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1145 int irq = platform_get_irq(pdev, 0);
1146 const struct armada_variant *variant;
1147 struct device_node *port = NULL;
1152 if (!dev->of_node) {
1153 const struct platform_device_id *id;
1155 id = platform_get_device_id(pdev);
1159 variant = (const struct armada_variant *)id->driver_data;
1161 const struct of_device_id *match;
1162 struct device_node *np, *parent = dev->of_node;
1164 match = of_match_device(dev->driver->of_match_table, dev);
1168 np = of_get_child_by_name(parent, "ports");
1171 port = of_get_child_by_name(parent, "port");
1174 dev_err(dev, "no port node found in %s\n",
1179 variant = match->data;
1182 return armada_drm_crtc_create(drm, dev, res, irq, variant, port);
1186 armada_lcd_unbind(struct device *dev, struct device *master, void *data)
1188 struct armada_crtc *dcrtc = dev_get_drvdata(dev);
1190 armada_drm_crtc_destroy(&dcrtc->crtc);
1193 static const struct component_ops armada_lcd_ops = {
1194 .bind = armada_lcd_bind,
1195 .unbind = armada_lcd_unbind,
1198 static int armada_lcd_probe(struct platform_device *pdev)
1200 return component_add(&pdev->dev, &armada_lcd_ops);
1203 static int armada_lcd_remove(struct platform_device *pdev)
1205 component_del(&pdev->dev, &armada_lcd_ops);
1209 static struct of_device_id armada_lcd_of_match[] = {
1211 .compatible = "marvell,dove-lcd",
1212 .data = &armada510_ops,
1216 MODULE_DEVICE_TABLE(of, armada_lcd_of_match);
1218 static const struct platform_device_id armada_lcd_platform_ids[] = {
1220 .name = "armada-lcd",
1221 .driver_data = (unsigned long)&armada510_ops,
1223 .name = "armada-510-lcd",
1224 .driver_data = (unsigned long)&armada510_ops,
1228 MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids);
1230 struct platform_driver armada_lcd_platform_driver = {
1231 .probe = armada_lcd_probe,
1232 .remove = armada_lcd_remove,
1234 .name = "armada-lcd",
1235 .owner = THIS_MODULE,
1236 .of_match_table = armada_lcd_of_match,
1238 .id_table = armada_lcd_platform_ids,