drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c

   1 /*
   2  * Analogix DP (Display port) core register interface driver.
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5  * Author: Jingoo Han <jg1.han@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include <linux/device.h>
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16 #include <linux/gpio.h>
  17
  18 #include <drm/bridge/analogix_dp.h>
  19
  20 #include "analogix_dp_core.h"
  21 #include "analogix_dp_reg.h"
  22
  23 #define COMMON_INT_MASK_1       0
  24 #define COMMON_INT_MASK_2       0
  25 #define COMMON_INT_MASK_3       0
  26 #define COMMON_INT_MASK_4       (HOTPLUG_CHG | HPD_LOST | PLUG)
  27 #define INT_STA_MASK            INT_HPD
  28
  29 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
  30 {
  31         u32 reg;
  32
  33         if (enable) {
  34                 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
  35                 reg |= HDCP_VIDEO_MUTE;
  36                 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
  37         } else {
  38                 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
  39                 reg &= ~HDCP_VIDEO_MUTE;
  40                 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
  41         }
  42 }
  43
  44 void analogix_dp_stop_video(struct analogix_dp_device *dp)
  45 {
  46         u32 reg;
  47
  48         reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
  49         reg &= ~VIDEO_EN;
  50         writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
  51 }
  52
  53 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
  54 {
  55         u32 reg;
  56
  57         if (enable)
  58                 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
  59                       LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
  60         else
  61                 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
  62                       LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
  63
  64         writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
  65 }
  66
  67 void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
  68 {
  69         u32 reg;
  70
  71         reg = TX_TERMINAL_CTRL_50_OHM;
  72         writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1);
  73
  74         reg = SEL_24M | TX_DVDD_BIT_1_0625V;
  75         writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
  76
  77         if (dp->plat_data && (dp->plat_data->dev_type == ROCKCHIP_DP)) {
  78                 reg = REF_CLK_24M;
  79                 if (dp->plat_data->subdev_type == RK3288_DP ||
  80                     dp->plat_data->subdev_type == RK3368_EDP)
  81                         reg ^= REF_CLK_MASK;
  82
  83                 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
  84                 writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
  85                 writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
  86                 writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
  87                 writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
  88         }
  89
  90         reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
  91         writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
  92
  93         reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
  94                 TX_CUR1_2X | TX_CUR_16_MA;
  95         writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1);
  96
  97         reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
  98                 CH1_AMP_400_MV | CH0_AMP_400_MV;
  99         writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL);
 100 }
 101
 102 void analogix_dp_init_interrupt(struct analogix_dp_device *dp)
 103 {
 104         /* Set interrupt pin assertion polarity as high */
 105         writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL);
 106
 107         /* Clear pending regisers */
 108         writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
 109         writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2);
 110         writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3);
 111         writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
 112         writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA);
 113
 114         /* 0:mask,1: unmask */
 115         writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
 116         writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
 117         writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
 118         writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
 119         writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
 120 }
 121
 122 void analogix_dp_reset(struct analogix_dp_device *dp)
 123 {
 124         u32 reg;
 125
 126         analogix_dp_stop_video(dp);
 127         analogix_dp_enable_video_mute(dp, 0);
 128
 129         reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
 130                 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
 131                 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
 132         writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
 133
 134         reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
 135                 SERDES_FIFO_FUNC_EN_N |
 136                 LS_CLK_DOMAIN_FUNC_EN_N;
 137         writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
 138
 139         usleep_range(20, 30);
 140
 141         analogix_dp_lane_swap(dp, 0);
 142
 143         writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
 144         writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
 145         writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
 146         writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
 147
 148         writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
 149         writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL);
 150
 151         writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L);
 152         writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H);
 153
 154         writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL);
 155
 156         writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST);
 157
 158         writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD);
 159         writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN);
 160
 161         writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH);
 162         writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH);
 163
 164         writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
 165 }
 166
 167 void analogix_dp_swreset(struct analogix_dp_device *dp)
 168 {
 169         writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET);
 170 }
 171
 172 void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
 173 {
 174         u32 reg;
 175
 176         /* 0: mask, 1: unmask */
 177         reg = COMMON_INT_MASK_1;
 178         writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
 179
 180         reg = COMMON_INT_MASK_2;
 181         writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
 182
 183         reg = COMMON_INT_MASK_3;
 184         writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
 185
 186         reg = COMMON_INT_MASK_4;
 187         writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
 188
 189         reg = INT_STA_MASK;
 190         writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
 191 }
 192
 193 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp)
 194 {
 195         u32 reg;
 196
 197         /* 0: mask, 1: unmask */
 198         reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
 199         reg &= ~COMMON_INT_MASK_4;
 200         writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
 201
 202         reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
 203         reg &= ~INT_STA_MASK;
 204         writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
 205 }
 206
 207 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp)
 208 {
 209         u32 reg;
 210
 211         /* 0: mask, 1: unmask */
 212         reg = COMMON_INT_MASK_4;
 213         writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
 214
 215         reg = INT_STA_MASK;
 216         writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
 217 }
 218
 219 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
 220 {
 221         u32 reg;
 222
 223         reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
 224         if (reg & PLL_LOCK)
 225                 return PLL_LOCKED;
 226         else
 227                 return PLL_UNLOCKED;
 228 }
 229
 230 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
 231 {
 232         u32 reg;
 233
 234         if (enable) {
 235                 reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
 236                 reg |= DP_PLL_PD;
 237                 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
 238         } else {
 239                 reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
 240                 reg &= ~DP_PLL_PD;
 241                 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
 242         }
 243 }
 244
 245 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
 246                                        enum analog_power_block block,
 247                                        bool enable)
 248 {
 249         u32 reg;
 250         u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
 251
 252         if (dp->plat_data && (dp->plat_data->dev_type == ROCKCHIP_DP))
 253                 phy_pd_addr = ANALOGIX_DP_PD;
 254
 255         switch (block) {
 256         case AUX_BLOCK:
 257                 if (enable) {
 258                         reg = readl(dp->reg_base + phy_pd_addr);
 259                         reg |= AUX_PD;
 260                         writel(reg, dp->reg_base + phy_pd_addr);
 261                 } else {
 262                         reg = readl(dp->reg_base + phy_pd_addr);
 263                         reg &= ~AUX_PD;
 264                         writel(reg, dp->reg_base + phy_pd_addr);
 265                 }
 266                 break;
 267         case CH0_BLOCK:
 268                 if (enable) {
 269                         reg = readl(dp->reg_base + phy_pd_addr);
 270                         reg |= CH0_PD;
 271                         writel(reg, dp->reg_base + phy_pd_addr);
 272                 } else {
 273                         reg = readl(dp->reg_base + phy_pd_addr);
 274                         reg &= ~CH0_PD;
 275                         writel(reg, dp->reg_base + phy_pd_addr);
 276                 }
 277                 break;
 278         case CH1_BLOCK:
 279                 if (enable) {
 280                         reg = readl(dp->reg_base + phy_pd_addr);
 281                         reg |= CH1_PD;
 282                         writel(reg, dp->reg_base + phy_pd_addr);
 283                 } else {
 284                         reg = readl(dp->reg_base + phy_pd_addr);
 285                         reg &= ~CH1_PD;
 286                         writel(reg, dp->reg_base + phy_pd_addr);
 287                 }
 288                 break;
 289         case CH2_BLOCK:
 290                 if (enable) {
 291                         reg = readl(dp->reg_base + phy_pd_addr);
 292                         reg |= CH2_PD;
 293                         writel(reg, dp->reg_base + phy_pd_addr);
 294                 } else {
 295                         reg = readl(dp->reg_base + phy_pd_addr);
 296                         reg &= ~CH2_PD;
 297                         writel(reg, dp->reg_base + phy_pd_addr);
 298                 }
 299                 break;
 300         case CH3_BLOCK:
 301                 if (enable) {
 302                         reg = readl(dp->reg_base + phy_pd_addr);
 303                         reg |= CH3_PD;
 304                         writel(reg, dp->reg_base + phy_pd_addr);
 305                 } else {
 306                         reg = readl(dp->reg_base + phy_pd_addr);
 307                         reg &= ~CH3_PD;
 308                         writel(reg, dp->reg_base + phy_pd_addr);
 309                 }
 310                 break;
 311         case ANALOG_TOTAL:
 312                 if (enable) {
 313                         reg = readl(dp->reg_base + phy_pd_addr);
 314                         reg |= DP_PHY_PD;
 315                         writel(reg, dp->reg_base + phy_pd_addr);
 316                 } else {
 317                         reg = readl(dp->reg_base + phy_pd_addr);
 318                         reg &= ~DP_PHY_PD;
 319                         writel(reg, dp->reg_base + phy_pd_addr);
 320                 }
 321                 break;
 322         case POWER_ALL:
 323                 if (enable) {
 324                         reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
 325                                 CH1_PD | CH0_PD;
 326                         writel(reg, dp->reg_base + phy_pd_addr);
 327                 } else {
 328                         writel(0x00, dp->reg_base + phy_pd_addr);
 329                 }
 330                 break;
 331         default:
 332                 break;
 333         }
 334 }
 335
 336 void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
 337 {
 338         u32 reg;
 339         int timeout_loop = 0;
 340
 341         analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
 342
 343         reg = PLL_LOCK_CHG;
 344         writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
 345
 346         reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
 347         reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
 348         writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
 349
 350         /* Power up PLL */
 351         if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 352                 analogix_dp_set_pll_power_down(dp, 0);
 353
 354                 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 355                         timeout_loop++;
 356                         if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 357                                 dev_err(dp->dev, "failed to get pll lock status\n");
 358                                 return;
 359                         }
 360                         usleep_range(10, 20);
 361                 }
 362         }
 363
 364         /* Enable Serdes FIFO function and Link symbol clock domain module */
 365         reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
 366         reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
 367                 | AUX_FUNC_EN_N);
 368         writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
 369 }
 370
 371 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
 372 {
 373         u32 reg;
 374
 375         if (gpio_is_valid(dp->hpd_gpio))
 376                 return;
 377
 378         reg = HOTPLUG_CHG | HPD_LOST | PLUG;
 379         writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
 380
 381         reg = INT_HPD;
 382         writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
 383 }
 384
 385 void analogix_dp_init_hpd(struct analogix_dp_device *dp)
 386 {
 387         u32 reg;
 388
 389         if (gpio_is_valid(dp->hpd_gpio))
 390                 return;
 391
 392         analogix_dp_clear_hotplug_interrupts(dp);
 393
 394         reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
 395         reg &= ~(F_HPD | HPD_CTRL);
 396         writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
 397 }
 398
 399 void analogix_dp_force_hpd(struct analogix_dp_device *dp)
 400 {
 401         u32 reg;
 402
 403         reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
 404         reg = (F_HPD | HPD_CTRL);
 405         writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
 406 }
 407
 408 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
 409 {
 410         u32 reg;
 411
 412         if (gpio_is_valid(dp->hpd_gpio)) {
 413                 reg = gpio_get_value(dp->hpd_gpio);
 414                 if (reg)
 415                         return DP_IRQ_TYPE_HP_CABLE_IN;
 416                 else
 417                         return DP_IRQ_TYPE_HP_CABLE_OUT;
 418         } else {
 419                 /* Parse hotplug interrupt status register */
 420                 reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
 421
 422                 if (reg & PLUG)
 423                         return DP_IRQ_TYPE_HP_CABLE_IN;
 424
 425                 if (reg & HPD_LOST)
 426                         return DP_IRQ_TYPE_HP_CABLE_OUT;
 427
 428                 if (reg & HOTPLUG_CHG)
 429                         return DP_IRQ_TYPE_HP_CHANGE;
 430
 431                 return DP_IRQ_TYPE_UNKNOWN;
 432         }
 433 }
 434
 435 void analogix_dp_reset_aux(struct analogix_dp_device *dp)
 436 {
 437         u32 reg;
 438
 439         /* Disable AUX channel module */
 440         reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
 441         reg |= AUX_FUNC_EN_N;
 442         writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
 443 }
 444
 445 void analogix_dp_init_aux(struct analogix_dp_device *dp)
 446 {
 447         u32 reg;
 448
 449         /* Clear inerrupts related to AUX channel */
 450         reg = RPLY_RECEIV | AUX_ERR;
 451         writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
 452
 453         analogix_dp_reset_aux(dp);
 454
 455         /* Disable AUX transaction H/W retry */
 456         if (dp->plat_data && (dp->plat_data->dev_type == ROCKCHIP_DP))
 457                 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
 458                       AUX_HW_RETRY_COUNT_SEL(3) |
 459                       AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 460         else
 461                 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
 462                       AUX_HW_RETRY_COUNT_SEL(0) |
 463                       AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 464         writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
 465
 466         /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
 467         reg = DEFER_CTRL_EN | DEFER_COUNT(1);
 468         writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL);
 469
 470         /* Enable AUX channel module */
 471         reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
 472         reg &= ~AUX_FUNC_EN_N;
 473         writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
 474 }
 475
 476 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp)
 477 {
 478         u32 reg;
 479
 480         if (gpio_is_valid(dp->hpd_gpio)) {
 481                 if (gpio_get_value(dp->hpd_gpio))
 482                         return 0;
 483         } else {
 484                 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
 485                 if (reg & HPD_STATUS)
 486                         return 0;
 487         }
 488
 489         return -EINVAL;
 490 }
 491
 492 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp)
 493 {
 494         u32 reg;
 495
 496         reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
 497         reg &= ~SW_FUNC_EN_N;
 498         writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
 499 }
 500
 501 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
 502 {
 503         int reg;
 504         int retval = 0;
 505         int timeout_loop = 0;
 506
 507         /* Enable AUX CH operation */
 508         reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
 509         reg |= AUX_EN;
 510         writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
 511
 512         /* Is AUX CH command reply received? */
 513         reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
 514         while (!(reg & RPLY_RECEIV)) {
 515                 timeout_loop++;
 516                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 517                         dev_err(dp->dev, "AUX CH command reply failed!\n");
 518                         return -ETIMEDOUT;
 519                 }
 520                 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
 521                 usleep_range(10, 11);
 522         }
 523
 524         /* Clear interrupt source for AUX CH command reply */
 525         writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA);
 526
 527         /* Clear interrupt source for AUX CH access error */
 528         reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
 529         if (reg & AUX_ERR) {
 530                 writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA);
 531                 return -EREMOTEIO;
 532         }
 533
 534         /* Check AUX CH error access status */
 535         reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA);
 536         if ((reg & AUX_STATUS_MASK) != 0) {
 537                 dev_err(dp->dev, "AUX CH error happens: %d\n\n",
 538                         reg & AUX_STATUS_MASK);
 539                 return -EREMOTEIO;
 540         }
 541
 542         return retval;
 543 }
 544
 545 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
 546                                    unsigned int reg_addr,
 547                                    unsigned char data)
 548 {
 549         u32 reg;
 550         int i;
 551         int retval;
 552
 553         for (i = 0; i < 3; i++) {
 554                 /* Clear AUX CH data buffer */
 555                 reg = BUF_CLR;
 556                 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
 557
 558                 /* Select DPCD device address */
 559                 reg = AUX_ADDR_7_0(reg_addr);
 560                 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
 561                 reg = AUX_ADDR_15_8(reg_addr);
 562                 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
 563                 reg = AUX_ADDR_19_16(reg_addr);
 564                 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
 565
 566                 /* Write data buffer */
 567                 reg = (unsigned int)data;
 568                 writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
 569
 570                 /*
 571                  * Set DisplayPort transaction and write 1 byte
 572                  * If bit 3 is 1, DisplayPort transaction.
 573                  * If Bit 3 is 0, I2C transaction.
 574                  */
 575                 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 576                 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
 577
 578                 /* Start AUX transaction */
 579                 retval = analogix_dp_start_aux_transaction(dp);
 580                 if (retval == 0)
 581                         break;
 582
 583                 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 584         }
 585
 586         return retval;
 587 }
 588
 589 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
 590                                     unsigned int reg_addr,
 591                                     unsigned char *data)
 592 {
 593         u32 reg;
 594         int i;
 595         int retval;
 596
 597         for (i = 0; i < 3; i++) {
 598                 /* Clear AUX CH data buffer */
 599                 reg = BUF_CLR;
 600                 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
 601
 602                 /* Select DPCD device address */
 603                 reg = AUX_ADDR_7_0(reg_addr);
 604                 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
 605                 reg = AUX_ADDR_15_8(reg_addr);
 606                 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
 607                 reg = AUX_ADDR_19_16(reg_addr);
 608                 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
 609
 610                 /*
 611                  * Set DisplayPort transaction and read 1 byte
 612                  * If bit 3 is 1, DisplayPort transaction.
 613                  * If Bit 3 is 0, I2C transaction.
 614                  */
 615                 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 616                 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
 617
 618                 /* Start AUX transaction */
 619                 retval = analogix_dp_start_aux_transaction(dp);
 620                 if (retval == 0)
 621                         break;
 622
 623                 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 624         }
 625
 626         /* Read data buffer */
 627         reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
 628         *data = (unsigned char)(reg & 0xff);
 629
 630         return retval;
 631 }
 632
 633 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 634                                     unsigned int reg_addr,
 635                                     unsigned int count,
 636                                     unsigned char data[])
 637 {
 638         u32 reg;
 639         unsigned int start_offset;
 640         unsigned int cur_data_count;
 641         unsigned int cur_data_idx;
 642         int i;
 643         int retval = 0;
 644
 645         /* Clear AUX CH data buffer */
 646         reg = BUF_CLR;
 647         writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
 648
 649         start_offset = 0;
 650         while (start_offset < count) {
 651                 /* Buffer size of AUX CH is 16 * 4bytes */
 652                 if ((count - start_offset) > 16)
 653                         cur_data_count = 16;
 654                 else
 655                         cur_data_count = count - start_offset;
 656
 657                 for (i = 0; i < 3; i++) {
 658                         /* Select DPCD device address */
 659                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 660                         writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
 661                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 662                         writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
 663                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 664                         writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
 665
 666                         for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 667                              cur_data_idx++) {
 668                                 reg = data[start_offset + cur_data_idx];
 669                                 writel(reg, dp->reg_base +
 670                                        ANALOGIX_DP_BUF_DATA_0 +
 671                                        4 * cur_data_idx);
 672                         }
 673
 674                         /*
 675                          * Set DisplayPort transaction and write
 676                          * If bit 3 is 1, DisplayPort transaction.
 677                          * If Bit 3 is 0, I2C transaction.
 678                          */
 679                         reg = AUX_LENGTH(cur_data_count) |
 680                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 681                         writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
 682
 683                         /* Start AUX transaction */
 684                         retval = analogix_dp_start_aux_transaction(dp);
 685                         if (retval == 0)
 686                                 break;
 687
 688                         dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
 689                                 __func__);
 690                 }
 691
 692                 start_offset += cur_data_count;
 693         }
 694
 695         return retval;
 696 }
 697
 698 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
 699                                      unsigned int reg_addr,
 700                                      unsigned int count,
 701                                      unsigned char data[])
 702 {
 703         u32 reg;
 704         unsigned int start_offset;
 705         unsigned int cur_data_count;
 706         unsigned int cur_data_idx;
 707         int i;
 708         int retval = 0;
 709
 710         /* Clear AUX CH data buffer */
 711         reg = BUF_CLR;
 712         writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
 713
 714         start_offset = 0;
 715         while (start_offset < count) {
 716                 /* Buffer size of AUX CH is 16 * 4bytes */
 717                 if ((count - start_offset) > 16)
 718                         cur_data_count = 16;
 719                 else
 720                         cur_data_count = count - start_offset;
 721
 722                 /* AUX CH Request Transaction process */
 723                 for (i = 0; i < 3; i++) {
 724                         /* Select DPCD device address */
 725                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 726                         writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
 727                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 728                         writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
 729                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 730                         writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
 731
 732                         /*
 733                          * Set DisplayPort transaction and read
 734                          * If bit 3 is 1, DisplayPort transaction.
 735                          * If Bit 3 is 0, I2C transaction.
 736                          */
 737                         reg = AUX_LENGTH(cur_data_count) |
 738                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 739                         writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
 740
 741                         /* Start AUX transaction */
 742                         retval = analogix_dp_start_aux_transaction(dp);
 743                         if (retval == 0)
 744                                 break;
 745
 746                         dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
 747                                 __func__);
 748                 }
 749
 750                 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 751                     cur_data_idx++) {
 752                         reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
 753                                                  + 4 * cur_data_idx);
 754                         data[start_offset + cur_data_idx] =
 755                                 (unsigned char)reg;
 756                 }
 757
 758                 start_offset += cur_data_count;
 759         }
 760
 761         return retval;
 762 }
 763
 764 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
 765                                   unsigned int device_addr,
 766                                   unsigned int reg_addr)
 767 {
 768         u32 reg;
 769         int retval;
 770
 771         /* Set EDID device address */
 772         reg = device_addr;
 773         writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
 774         writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
 775         writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
 776
 777         /* Set offset from base address of EDID device */
 778         writel(reg_addr, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
 779
 780         /*
 781          * Set I2C transaction and write address
 782          * If bit 3 is 1, DisplayPort transaction.
 783          * If Bit 3 is 0, I2C transaction.
 784          */
 785         reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
 786                 AUX_TX_COMM_WRITE;
 787         writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
 788
 789         /* Start AUX transaction */
 790         retval = analogix_dp_start_aux_transaction(dp);
 791         if (retval != 0)
 792                 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 793
 794         return retval;
 795 }
 796
 797 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 798                                    unsigned int device_addr,
 799                                    unsigned int reg_addr,
 800                                    unsigned int *data)
 801 {
 802         u32 reg;
 803         int i;
 804         int retval;
 805
 806         for (i = 0; i < 3; i++) {
 807                 /* Clear AUX CH data buffer */
 808                 reg = BUF_CLR;
 809                 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
 810
 811                 /* Select EDID device */
 812                 retval = analogix_dp_select_i2c_device(dp, device_addr,
 813                                                        reg_addr);
 814                 if (retval != 0)
 815                         continue;
 816
 817                 /*
 818                  * Set I2C transaction and read data
 819                  * If bit 3 is 1, DisplayPort transaction.
 820                  * If Bit 3 is 0, I2C transaction.
 821                  */
 822                 reg = AUX_TX_COMM_I2C_TRANSACTION |
 823                         AUX_TX_COMM_READ;
 824                 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
 825
 826                 /* Start AUX transaction */
 827                 retval = analogix_dp_start_aux_transaction(dp);
 828                 if (retval == 0)
 829                         break;
 830
 831                 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 832         }
 833
 834         /* Read data */
 835         if (retval == 0)
 836                 *data = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
 837
 838         return retval;
 839 }
 840
 841 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
 842                                     unsigned int device_addr,
 843                                     unsigned int reg_addr,
 844                                     unsigned int count,
 845                                     unsigned char edid[])
 846 {
 847         u32 reg;
 848         unsigned int i, j;
 849         unsigned int cur_data_idx;
 850         unsigned int defer = 0;
 851         int retval = 0;
 852
 853         for (i = 0; i < count; i += 16) {
 854                 for (j = 0; j < 3; j++) {
 855                         /* Clear AUX CH data buffer */
 856                         reg = BUF_CLR;
 857                         writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
 858
 859                         /* Set normal AUX CH command */
 860                         reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
 861                         reg &= ~ADDR_ONLY;
 862                         writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
 863
 864                         /*
 865                          * If Rx sends defer, Tx sends only reads
 866                          * request without sending address
 867                          */
 868                         if (!defer)
 869                                 retval = analogix_dp_select_i2c_device(dp,
 870                                                 device_addr, reg_addr + i);
 871                         else
 872                                 defer = 0;
 873
 874                         if (retval == 0) {
 875                                 /*
 876                                  * Set I2C transaction and write data
 877                                  * If bit 3 is 1, DisplayPort transaction.
 878                                  * If Bit 3 is 0, I2C transaction.
 879                                  */
 880                                 reg = AUX_LENGTH(16) |
 881                                         AUX_TX_COMM_I2C_TRANSACTION |
 882                                         AUX_TX_COMM_READ;
 883                                 writel(reg, dp->reg_base +
 884                                         ANALOGIX_DP_AUX_CH_CTL_1);
 885
 886                                 /* Start AUX transaction */
 887                                 retval = analogix_dp_start_aux_transaction(dp);
 888                                 if (retval == 0)
 889                                         break;
 890
 891                                 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
 892                                         __func__);
 893                         }
 894                         /* Check if Rx sends defer */
 895                         reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
 896                         if (reg == AUX_RX_COMM_AUX_DEFER ||
 897                             reg == AUX_RX_COMM_I2C_DEFER) {
 898                                 dev_err(dp->dev, "Defer: %d\n\n", reg);
 899                                 defer = 1;
 900                         }
 901                 }
 902
 903                 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
 904                         reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
 905                                                  + 4 * cur_data_idx);
 906                         edid[i + cur_data_idx] = (unsigned char)reg;
 907                 }
 908         }
 909
 910         return retval;
 911 }
 912
 913 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
 914 {
 915         u32 reg;
 916
 917         reg = bwtype;
 918         if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62))
 919                 writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
 920 }
 921
 922 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
 923 {
 924         u32 reg;
 925
 926         reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
 927         *bwtype = reg;
 928 }
 929
 930 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
 931 {
 932         u32 reg;
 933
 934         reg = count;
 935         writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
 936 }
 937
 938 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
 939 {
 940         u32 reg;
 941
 942         reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
 943         *count = reg;
 944 }
 945
 946 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
 947                                       bool enable)
 948 {
 949         u32 reg;
 950
 951         if (enable) {
 952                 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
 953                 reg |= ENHANCED;
 954                 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
 955         } else {
 956                 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
 957                 reg &= ~ENHANCED;
 958                 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
 959         }
 960 }
 961
 962 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
 963                                       enum pattern_set pattern)
 964 {
 965         u32 reg;
 966
 967         switch (pattern) {
 968         case PRBS7:
 969                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
 970                 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
 971                 break;
 972         case D10_2:
 973                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
 974                 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
 975                 break;
 976         case TRAINING_PTN1:
 977                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
 978                 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
 979                 break;
 980         case TRAINING_PTN2:
 981                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
 982                 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
 983                 break;
 984         case DP_NONE:
 985                 reg = SCRAMBLING_ENABLE |
 986                         LINK_QUAL_PATTERN_SET_DISABLE |
 987                         SW_TRAINING_PATTERN_SET_NORMAL;
 988                 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
 989                 break;
 990         default:
 991                 break;
 992         }
 993 }
 994
 995 void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
 996                                         u32 level)
 997 {
 998         u32 reg;
 999
1000         reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
1001         reg &= ~PRE_EMPHASIS_SET_MASK;
1002         reg |= level << PRE_EMPHASIS_SET_SHIFT;
1003         writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
1004 }
1005
1006 void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
1007                                         u32 level)
1008 {
1009         u32 reg;
1010
1011         reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
1012         reg &= ~PRE_EMPHASIS_SET_MASK;
1013         reg |= level << PRE_EMPHASIS_SET_SHIFT;
1014         writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
1015 }
1016
1017 void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
1018                                         u32 level)
1019 {
1020         u32 reg;
1021
1022         reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
1023         reg &= ~PRE_EMPHASIS_SET_MASK;
1024         reg |= level << PRE_EMPHASIS_SET_SHIFT;
1025         writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
1026 }
1027
1028 void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
1029                                         u32 level)
1030 {
1031         u32 reg;
1032
1033         reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
1034         reg &= ~PRE_EMPHASIS_SET_MASK;
1035         reg |= level << PRE_EMPHASIS_SET_SHIFT;
1036         writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
1037 }
1038
1039 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
1040                                          u32 training_lane)
1041 {
1042         u32 reg;
1043
1044         reg = training_lane;
1045         writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
1046 }
1047
1048 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
1049                                          u32 training_lane)
1050 {
1051         u32 reg;
1052
1053         reg = training_lane;
1054         writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
1055 }
1056
1057 void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
1058                                          u32 training_lane)
1059 {
1060         u32 reg;
1061
1062         reg = training_lane;
1063         writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
1064 }
1065
1066 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
1067                                          u32 training_lane)
1068 {
1069         u32 reg;
1070
1071         reg = training_lane;
1072         writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
1073 }
1074
1075 u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
1076 {
1077         u32 reg;
1078
1079         reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
1080         return reg;
1081 }
1082
1083 u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
1084 {
1085         u32 reg;
1086
1087         reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
1088         return reg;
1089 }
1090
1091 u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
1092 {
1093         u32 reg;
1094
1095         reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
1096         return reg;
1097 }
1098
1099 u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
1100 {
1101         u32 reg;
1102
1103         reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
1104         return reg;
1105 }
1106
1107 void analogix_dp_reset_macro(struct analogix_dp_device *dp)
1108 {
1109         u32 reg;
1110
1111         reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST);
1112         reg |= MACRO_RST;
1113         writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
1114
1115         /* 10 us is the minimum reset time. */
1116         usleep_range(10, 20);
1117
1118         reg &= ~MACRO_RST;
1119         writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
1120 }
1121
1122 void analogix_dp_init_video(struct analogix_dp_device *dp)
1123 {
1124         u32 reg;
1125
1126         reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
1127         writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
1128
1129         reg = 0x0;
1130         writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
1131
1132         reg = CHA_CRI(4) | CHA_CTRL;
1133         writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
1134
1135         reg = 0x0;
1136         writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
1137
1138         reg = VID_HRES_TH(2) | VID_VRES_TH(0);
1139         writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8);
1140 }
1141
1142 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
1143 {
1144         u32 reg;
1145
1146         /* Configure the input color depth, color space, dynamic range */
1147         reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
1148                 (dp->video_info.color_depth << IN_BPC_SHIFT) |
1149                 (dp->video_info.color_space << IN_COLOR_F_SHIFT);
1150         writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
1151
1152         /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1153         reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
1154         reg &= ~IN_YC_COEFFI_MASK;
1155         if (dp->video_info.ycbcr_coeff)
1156                 reg |= IN_YC_COEFFI_ITU709;
1157         else
1158                 reg |= IN_YC_COEFFI_ITU601;
1159         writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
1160 }
1161
1162 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
1163 {
1164         u32 reg;
1165
1166         reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
1167         writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
1168
1169         reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
1170
1171         if (!(reg & DET_STA)) {
1172                 dev_dbg(dp->dev, "Input stream clock not detected.\n");
1173                 return -EINVAL;
1174         }
1175
1176         reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
1177         writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
1178
1179         reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
1180         dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
1181
1182         if (reg & CHA_STA) {
1183                 dev_dbg(dp->dev, "Input stream clk is changing\n");
1184                 return -EINVAL;
1185         }
1186
1187         return 0;
1188 }
1189
1190 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
1191                                  enum clock_recovery_m_value_type type,
1192                                  u32 m_value, u32 n_value)
1193 {
1194         u32 reg;
1195
1196         if (type == REGISTER_M) {
1197                 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
1198                 reg |= FIX_M_VID;
1199                 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
1200                 reg = m_value & 0xff;
1201                 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0);
1202                 reg = (m_value >> 8) & 0xff;
1203                 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1);
1204                 reg = (m_value >> 16) & 0xff;
1205                 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2);
1206
1207                 reg = n_value & 0xff;
1208                 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0);
1209                 reg = (n_value >> 8) & 0xff;
1210                 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1);
1211                 reg = (n_value >> 16) & 0xff;
1212                 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2);
1213         } else  {
1214                 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
1215                 reg &= ~FIX_M_VID;
1216                 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
1217
1218                 writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0);
1219                 writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1);
1220                 writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2);
1221         }
1222 }
1223
1224 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type)
1225 {
1226         u32 reg;
1227
1228         if (type == VIDEO_TIMING_FROM_CAPTURE) {
1229                 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1230                 reg &= ~FORMAT_SEL;
1231                 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1232         } else {
1233                 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1234                 reg |= FORMAT_SEL;
1235                 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1236         }
1237 }
1238
1239 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable)
1240 {
1241         u32 reg;
1242
1243         if (enable) {
1244                 reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
1245                 reg &= ~VIDEO_MODE_MASK;
1246                 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1247                 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
1248         } else {
1249                 reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
1250                 reg &= ~VIDEO_MODE_MASK;
1251                 reg |= VIDEO_MODE_SLAVE_MODE;
1252                 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
1253         }
1254 }
1255
1256 void analogix_dp_start_video(struct analogix_dp_device *dp)
1257 {
1258         u32 reg;
1259
1260         reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
1261         reg |= VIDEO_EN;
1262         writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
1263 }
1264
1265 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp)
1266 {
1267         u32 reg;
1268
1269         reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
1270         writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
1271
1272         reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
1273         if (!(reg & STRM_VALID)) {
1274                 dev_dbg(dp->dev, "Input video stream is not detected.\n");
1275                 return -EINVAL;
1276         }
1277
1278         return 0;
1279 }
1280
1281 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
1282 {
1283         u32 reg;
1284
1285         reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
1286         reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
1287         reg |= MASTER_VID_FUNC_EN_N;
1288         writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
1289
1290         reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1291         reg &= ~INTERACE_SCAN_CFG;
1292         reg |= (dp->video_info.interlaced << 2);
1293         writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1294
1295         reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1296         reg &= ~VSYNC_POLARITY_CFG;
1297         reg |= (dp->video_info.v_sync_polarity << 1);
1298         writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1299
1300         reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1301         reg &= ~HSYNC_POLARITY_CFG;
1302         reg |= (dp->video_info.h_sync_polarity << 0);
1303         writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
1304
1305         reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1306         writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
1307 }
1308
1309 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp)
1310 {
1311         u32 reg;
1312
1313         reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
1314         reg &= ~SCRAMBLING_DISABLE;
1315         writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
1316 }
1317
1318 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp)
1319 {
1320         u32 reg;
1321
1322         reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
1323         reg |= SCRAMBLING_DISABLE;
1324         writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
1325 }