drivers/gpu/drm/bridge/dw-hdmi.c

   1 /*
   2  * DesignWare High-Definition Multimedia Interface (HDMI) driver
   3  *
   4  * Copyright (C) 2013-2015 Mentor Graphics Inc.
   5  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   6  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * Designware High-Definition Multimedia Interface (HDMI) driver
  14  *
  15  */
  16 #include <linux/module.h>
  17 #include <linux/irq.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/clk.h>
  21 #include <linux/hdmi.h>
  22 #include <linux/mutex.h>
  23 #include <linux/of_device.h>
  24 #include <linux/spinlock.h>
  25
  26 #include <drm/drm_of.h>
  27 #include <drm/drmP.h>
  28 #include <drm/drm_atomic_helper.h>
  29 #include <drm/drm_crtc_helper.h>
  30 #include <drm/drm_edid.h>
  31 #include <drm/drm_encoder_slave.h>
  32 #include <drm/drm_scdc_helper.h>
  33 #include <drm/bridge/dw_hdmi.h>
  34 #ifdef CONFIG_SWITCH
  35 #include <linux/switch.h>
  36 #endif
  37
  38 #include <uapi/linux/media-bus-format.h>
  39 #include <uapi/linux/videodev2.h>
  40
  41 #include "dw-hdmi.h"
  42 #include "dw-hdmi-audio.h"
  43 #include "dw-hdmi-hdcp.h"
  44
  45 #define HDMI_EDID_LEN           512
  46 #define DDC_SEGMENT_ADDR       0x30
  47
  48 enum hdmi_datamap {
  49         RGB444_8B = 0x01,
  50         RGB444_10B = 0x03,
  51         RGB444_12B = 0x05,
  52         RGB444_16B = 0x07,
  53         YCbCr444_8B = 0x09,
  54         YCbCr444_10B = 0x0B,
  55         YCbCr444_12B = 0x0D,
  56         YCbCr444_16B = 0x0F,
  57         YCbCr422_8B = 0x16,
  58         YCbCr422_10B = 0x14,
  59         YCbCr422_12B = 0x12,
  60 };
  61
  62 /*
  63  * Unless otherwise noted, entries in this table are 100% optimization.
  64  * Values can be obtained from hdmi_compute_n() but that function is
  65  * slow so we pre-compute values we expect to see.
  66  *
  67  * All 32k and 48k values are expected to be the same (due to the way
  68  * the math works) for any rate that's an exact kHz.
  69  */
  70 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = {
  71         { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, },
  72         { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, },
  73         { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  74         { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, },
  75         { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, },
  76         { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
  77         { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
  78         { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
  79         { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  80         { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
  81         { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  82         { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
  83         { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
  84         { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  85         { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, },
  86         { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  87         { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, },
  88         { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
  89         { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
  90         { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, },
  91         { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
  92         { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
  93         { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
  94         { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  95         { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
  96         { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
  97         { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
  98         { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
  99         { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
 100         { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
 101         { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, },
 102         { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
 103         { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
 104         { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
 105         { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
 106         { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
 107         { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
 108
 109         /* For 297 MHz+ HDMI spec have some other rule for setting N */
 110         { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, },
 111         { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, },
 112
 113         /* End of table */
 114         { .tmds = 0,         .n_32k = 0,    .n_44k1 = 0,    .n_48k = 0, },
 115 };
 116
 117 static const u16 csc_coeff_default[3][4] = {
 118         { 0x2000, 0x0000, 0x0000, 0x0000 },
 119         { 0x0000, 0x2000, 0x0000, 0x0000 },
 120         { 0x0000, 0x0000, 0x2000, 0x0000 }
 121 };
 122
 123 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
 124         { 0x2000, 0x6926, 0x74fd, 0x010e },
 125         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
 126         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
 127 };
 128
 129 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
 130         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
 131         { 0x2000, 0x3264, 0x0000, 0x7e6d },
 132         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
 133 };
 134
 135 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
 136         { 0x2591, 0x1322, 0x074b, 0x0000 },
 137         { 0x6535, 0x2000, 0x7acc, 0x0200 },
 138         { 0x6acd, 0x7534, 0x2000, 0x0200 }
 139 };
 140
 141 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
 142         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
 143         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
 144         { 0x6756, 0x78ab, 0x2000, 0x0200 }
 145 };
 146
 147 struct hdmi_vmode {
 148         bool mdataenablepolarity;
 149
 150         unsigned int mpixelclock;
 151         unsigned int mpixelrepetitioninput;
 152         unsigned int mpixelrepetitionoutput;
 153 };
 154
 155 struct hdmi_data_info {
 156         unsigned int enc_in_bus_format;
 157         unsigned int enc_out_bus_format;
 158         unsigned int enc_in_encoding;
 159         unsigned int enc_out_encoding;
 160         unsigned int pix_repet_factor;
 161         struct hdmi_vmode video_mode;
 162 };
 163
 164 struct dw_hdmi_i2c {
 165         struct i2c_adapter      adap;
 166
 167         struct mutex            lock;
 168         struct completion       cmp;
 169         u8                      stat;
 170
 171         u8                      slave_reg;
 172         bool                    is_regaddr;
 173         bool                    is_segment;
 174
 175         unsigned int            scl_high_ns;
 176         unsigned int            scl_low_ns;
 177 };
 178
 179 struct dw_hdmi_phy_data {
 180         enum dw_hdmi_phy_type type;
 181         const char *name;
 182         unsigned int gen;
 183         bool has_svsret;
 184         int (*configure)(struct dw_hdmi *hdmi,
 185                          const struct dw_hdmi_plat_data *pdata,
 186                          unsigned long mpixelclock);
 187 };
 188
 189 struct dw_hdmi {
 190         struct drm_connector connector;
 191         struct drm_encoder *encoder;
 192         struct drm_bridge bridge;
 193         struct platform_device *hdcp_dev;
 194         enum dw_hdmi_devtype dev_type;
 195         unsigned int version;
 196
 197         struct platform_device *audio;
 198         struct device *dev;
 199         struct clk *isfr_clk;
 200         struct clk *iahb_clk;
 201         struct dw_hdmi_i2c *i2c;
 202
 203         struct hdmi_data_info hdmi_data;
 204         const struct dw_hdmi_plat_data *plat_data;
 205         struct dw_hdcp *hdcp;
 206
 207         int vic;
 208
 209         u8 edid[HDMI_EDID_LEN];
 210         bool cable_plugin;
 211
 212         struct {
 213                 const struct dw_hdmi_phy_ops *ops;
 214                 const char *name;
 215                 void *data;
 216                 bool enabled;
 217         } phy;
 218
 219         struct drm_display_mode previous_mode;
 220
 221         struct i2c_adapter *ddc;
 222         void __iomem *regs;
 223         bool sink_is_hdmi;
 224         bool sink_has_audio;
 225         bool hpd_state;
 226
 227         struct delayed_work work;
 228         struct workqueue_struct *workqueue;
 229
 230         struct mutex mutex;             /* for state below and previous_mode */
 231         enum drm_connector_force force; /* mutex-protected force state */
 232         bool disabled;                  /* DRM has disabled our bridge */
 233         bool bridge_is_on;              /* indicates the bridge is on */
 234         bool rxsense;                   /* rxsense state */
 235         u8 phy_mask;                    /* desired phy int mask settings */
 236
 237         spinlock_t audio_lock;
 238         struct mutex audio_mutex;
 239         unsigned int sample_rate;
 240         unsigned int audio_cts;
 241         unsigned int audio_n;
 242         bool audio_enable;
 243
 244 #ifdef CONFIG_SWITCH
 245         struct switch_dev switchdev;
 246 #endif
 247         int irq;
 248
 249         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
 250         u8 (*read)(struct dw_hdmi *hdmi, int offset);
 251 };
 252
 253 #define HDMI_IH_PHY_STAT0_RX_SENSE \
 254         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
 255          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
 256
 257 #define HDMI_PHY_RX_SENSE \
 258         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
 259          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
 260
 261 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
 262 {
 263         writel(val, hdmi->regs + (offset << 2));
 264 }
 265
 266 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
 267 {
 268         return readl(hdmi->regs + (offset << 2));
 269 }
 270
 271 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 272 {
 273         writeb(val, hdmi->regs + offset);
 274 }
 275
 276 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
 277 {
 278         return readb(hdmi->regs + offset);
 279 }
 280
 281 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 282 {
 283         hdmi->write(hdmi, val, offset);
 284 }
 285
 286 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 287 {
 288         return hdmi->read(hdmi, offset);
 289 }
 290
 291 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 292 {
 293         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 294
 295         val |= data & mask;
 296         hdmi_writeb(hdmi, val, reg);
 297 }
 298
 299 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 300                              u8 shift, u8 mask)
 301 {
 302         hdmi_modb(hdmi, data << shift, mask, reg);
 303 }
 304
 305 static void repo_hpd_event(struct work_struct *p_work)
 306 {
 307         struct dw_hdmi *hdmi = container_of(p_work, struct dw_hdmi, work.work);
 308
 309         if (hdmi->bridge.dev)
 310                 drm_helper_hpd_irq_event(hdmi->bridge.dev);
 311 #ifdef CONFIG_SWITCH
 312         if (hdmi->hpd_state)
 313                 switch_set_state(&hdmi->switchdev, 1);
 314         else
 315                 switch_set_state(&hdmi->switchdev, 0);
 316 #endif
 317 }
 318
 319 static bool check_hdmi_irq(struct dw_hdmi *hdmi, int intr_stat,
 320                            int phy_int_pol)
 321 {
 322         int msecs;
 323
 324         /* To determine whether interrupt type is HPD */
 325         if (!(intr_stat & HDMI_IH_PHY_STAT0_HPD))
 326                 return false;
 327
 328         if (phy_int_pol & HDMI_PHY_HPD) {
 329                 dev_dbg(hdmi->dev, "dw hdmi plug in\n");
 330                 msecs = 150;
 331                 hdmi->hpd_state = true;
 332         } else {
 333                 dev_dbg(hdmi->dev, "dw hdmi plug out\n");
 334                 msecs = 20;
 335                 hdmi->hpd_state = false;
 336         }
 337         mod_delayed_work(hdmi->workqueue, &hdmi->work, msecs_to_jiffies(msecs));
 338
 339         return true;
 340 }
 341
 342 static void init_hpd_work(struct dw_hdmi *hdmi)
 343 {
 344         hdmi->workqueue = create_workqueue("hpd_queue");
 345         INIT_DELAYED_WORK(&hdmi->work, repo_hpd_event);
 346 }
 347
 348 static void dw_hdmi_i2c_set_divs(struct dw_hdmi *hdmi)
 349 {
 350         unsigned long clk_rate_khz;
 351         unsigned long low_ns, high_ns;
 352         unsigned long div_low, div_high;
 353
 354         /* Standard-mode */
 355         if (hdmi->i2c->scl_high_ns < 4000)
 356                 high_ns = 4708;
 357         else
 358                 high_ns = hdmi->i2c->scl_high_ns;
 359
 360         if (hdmi->i2c->scl_low_ns < 4700)
 361                 low_ns = 4916;
 362         else
 363                 low_ns = hdmi->i2c->scl_low_ns;
 364
 365         /* Adjust to avoid overflow */
 366         clk_rate_khz = DIV_ROUND_UP(clk_get_rate(hdmi->isfr_clk), 1000);
 367
 368         div_low = (clk_rate_khz * low_ns) / 1000000;
 369         if ((clk_rate_khz * low_ns) % 1000000)
 370                 div_low++;
 371
 372         div_high = (clk_rate_khz * high_ns) / 1000000;
 373         if ((clk_rate_khz * high_ns) % 1000000)
 374                 div_high++;
 375
 376         /* Maximum divider supported by hw is 0xffff */
 377         if (div_low > 0xffff)
 378                 div_low = 0xffff;
 379
 380         if (div_high > 0xffff)
 381                 div_high = 0xffff;
 382
 383         hdmi_writeb(hdmi, div_high & 0xff, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
 384         hdmi_writeb(hdmi, (div_high >> 8) & 0xff,
 385                     HDMI_I2CM_SS_SCL_HCNT_1_ADDR);
 386         hdmi_writeb(hdmi, div_low & 0xff, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
 387         hdmi_writeb(hdmi, (div_low >> 8) & 0xff,
 388                     HDMI_I2CM_SS_SCL_LCNT_1_ADDR);
 389 }
 390
 391 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
 392 {
 393         /* Software reset */
 394         hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
 395
 396         /* Set Standard Mode speed */
 397         hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE,
 398                   HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV);
 399
 400         /* Set done, not acknowledged and arbitration interrupt polarities */
 401         hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
 402         hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
 403                     HDMI_I2CM_CTLINT);
 404
 405         /* Clear DONE and ERROR interrupts */
 406         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 407                     HDMI_IH_I2CM_STAT0);
 408
 409         /* Mute DONE and ERROR interrupts */
 410         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 411                     HDMI_IH_MUTE_I2CM_STAT0);
 412
 413         /* set SDA high level holding time */
 414         hdmi_writeb(hdmi, 0x48, HDMI_I2CM_SDA_HOLD);
 415
 416         dw_hdmi_i2c_set_divs(hdmi);
 417 }
 418
 419 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
 420                             unsigned char *buf, unsigned int length)
 421 {
 422         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 423         int stat;
 424
 425         if (!i2c->is_regaddr) {
 426                 dev_dbg(hdmi->dev, "set read register address to 0\n");
 427                 i2c->slave_reg = 0x00;
 428                 i2c->is_regaddr = true;
 429         }
 430
 431         while (length--) {
 432                 reinit_completion(&i2c->cmp);
 433
 434                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 435                 if (i2c->is_segment)
 436                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
 437                                     HDMI_I2CM_OPERATION);
 438                 else
 439                         hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
 440                                     HDMI_I2CM_OPERATION);
 441
 442                 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 443                 if (!stat)
 444                         return -EAGAIN;
 445
 446                 /* Check for error condition on the bus */
 447                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 448                         return -EIO;
 449
 450                 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
 451         }
 452         i2c->is_segment = false;
 453
 454         return 0;
 455 }
 456
 457 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
 458                              unsigned char *buf, unsigned int length)
 459 {
 460         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 461         int stat;
 462
 463         if (!i2c->is_regaddr) {
 464                 /* Use the first write byte as register address */
 465                 i2c->slave_reg = buf[0];
 466                 length--;
 467                 buf++;
 468                 i2c->is_regaddr = true;
 469         }
 470
 471         while (length--) {
 472                 reinit_completion(&i2c->cmp);
 473
 474                 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
 475                 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
 476                 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
 477                             HDMI_I2CM_OPERATION);
 478
 479         stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
 480                 if (!stat)
 481                         return -EAGAIN;
 482
 483                 /* Check for error condition on the bus */
 484                 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
 485                         return -EIO;
 486         }
 487
 488         return 0;
 489 }
 490
 491 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
 492                             struct i2c_msg *msgs, int num)
 493 {
 494         struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
 495         struct dw_hdmi_i2c *i2c = hdmi->i2c;
 496         u8 addr = msgs[0].addr;
 497         int i, ret = 0;
 498
 499         dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
 500
 501         for (i = 0; i < num; i++) {
 502                 if (msgs[i].len == 0) {
 503                         dev_dbg(hdmi->dev,
 504                                 "unsupported transfer %d/%d, no data\n",
 505                                 i + 1, num);
 506                         return -EOPNOTSUPP;
 507                 }
 508         }
 509
 510         mutex_lock(&i2c->lock);
 511
 512         hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
 513
 514         /* Set slave device address taken from the first I2C message */
 515         if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1)
 516                 addr = DDC_ADDR;
 517         hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
 518
 519         /* Set slave device register address on transfer */
 520         i2c->is_regaddr = false;
 521
 522         /* Set segment pointer for I2C extended read mode operation */
 523         i2c->is_segment = false;
 524
 525         for (i = 0; i < num; i++) {
 526                 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
 527                         i + 1, num, msgs[i].len, msgs[i].flags);
 528                 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
 529                         i2c->is_segment = true;
 530                         hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
 531                         hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
 532                 } else {
 533                         if (msgs[i].flags & I2C_M_RD)
 534                                 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
 535                                                        msgs[i].len);
 536                         else
 537                                 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
 538                                                         msgs[i].len);
 539                 }
 540                 if (ret < 0)
 541                         break;
 542         }
 543
 544         if (!ret)
 545                 ret = num;
 546
 547         /* Mute DONE and ERROR interrupts */
 548         hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
 549                     HDMI_IH_MUTE_I2CM_STAT0);
 550
 551         mutex_unlock(&i2c->lock);
 552
 553         return ret;
 554 }
 555
 556 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
 557 {
 558         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 559 }
 560
 561 static const struct i2c_algorithm dw_hdmi_algorithm = {
 562         .master_xfer    = dw_hdmi_i2c_xfer,
 563         .functionality  = dw_hdmi_i2c_func,
 564 };
 565
 566 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
 567 {
 568         struct i2c_adapter *adap;
 569         struct dw_hdmi_i2c *i2c;
 570         int ret;
 571
 572         i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
 573         if (!i2c)
 574                 return ERR_PTR(-ENOMEM);
 575
 576         mutex_init(&i2c->lock);
 577         init_completion(&i2c->cmp);
 578
 579         adap = &i2c->adap;
 580         adap->class = I2C_CLASS_DDC;
 581         adap->owner = THIS_MODULE;
 582         adap->dev.parent = hdmi->dev;
 583         adap->dev.of_node = hdmi->dev->of_node;
 584         adap->algo = &dw_hdmi_algorithm;
 585         strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
 586         i2c_set_adapdata(adap, hdmi);
 587
 588         ret = i2c_add_adapter(adap);
 589         if (ret) {
 590                 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
 591                 devm_kfree(hdmi->dev, i2c);
 592                 return ERR_PTR(ret);
 593         }
 594
 595         hdmi->i2c = i2c;
 596
 597         dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
 598
 599         return adap;
 600 }
 601
 602 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 603                            unsigned int n)
 604 {
 605         /* Must be set/cleared first */
 606         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 607
 608         /* nshift factor = 0 */
 609         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 610
 611         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 612                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 613         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 614         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 615
 616         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 617         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 618         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 619 }
 620
 621 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi,
 622                                    unsigned long pixel_clk,
 623                                    unsigned long freq)
 624 {
 625         const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
 626         const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
 627         int i;
 628
 629         if (plat_data->tmds_n_table) {
 630                 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
 631                         if (pixel_clk == plat_data->tmds_n_table[i].tmds) {
 632                                 tmds_n = &plat_data->tmds_n_table[i];
 633                                 break;
 634                         }
 635                 }
 636         }
 637
 638         if (tmds_n == NULL) {
 639                 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
 640                         if (pixel_clk == common_tmds_n_table[i].tmds) {
 641                                 tmds_n = &common_tmds_n_table[i];
 642                                 break;
 643                         }
 644                 }
 645         }
 646
 647         if (tmds_n == NULL)
 648                 return -ENOENT;
 649
 650         switch (freq) {
 651         case 32000:
 652                 return tmds_n->n_32k;
 653         case 44100:
 654         case 88200:
 655         case 176400:
 656                 return (freq / 44100) * tmds_n->n_44k1;
 657         case 48000:
 658         case 96000:
 659         case 192000:
 660                 return (freq / 48000) * tmds_n->n_48k;
 661         default:
 662                 return -ENOENT;
 663         }
 664 }
 665
 666 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n,
 667                                 unsigned int pixel_clk)
 668 {
 669         u64 final, diff;
 670         u64 cts;
 671
 672         final = (u64)pixel_clk * n;
 673
 674         cts = final;
 675         do_div(cts, 128 * freq);
 676
 677         diff = final - (u64)cts * (128 * freq);
 678
 679         return diff;
 680 }
 681
 682 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi,
 683                                    unsigned long pixel_clk,
 684                                    unsigned long freq)
 685 {
 686         unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
 687         unsigned int max_n = (128 * freq) / 300;
 688         unsigned int ideal_n = (128 * freq) / 1000;
 689         unsigned int best_n_distance = ideal_n;
 690         unsigned int best_n = 0;
 691         u64 best_diff = U64_MAX;
 692         int n;
 693
 694         /* If the ideal N could satisfy the audio math, then just take it */
 695         if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
 696                 return ideal_n;
 697
 698         for (n = min_n; n <= max_n; n++) {
 699                 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk);
 700
 701                 if (diff < best_diff || (diff == best_diff &&
 702                     abs(n - ideal_n) < best_n_distance)) {
 703                         best_n = n;
 704                         best_diff = diff;
 705                         best_n_distance = abs(best_n - ideal_n);
 706                 }
 707
 708                 /*
 709                  * The best N already satisfy the audio math, and also be
 710                  * the closest value to ideal N, so just cut the loop.
 711                  */
 712                 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance))
 713                         break;
 714         }
 715
 716         return best_n;
 717 }
 718
 719 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk,
 720                                 unsigned long sample_rate)
 721 {
 722         int n;
 723
 724         n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
 725         if (n > 0)
 726                 return n;
 727
 728         dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n",
 729                  pixel_clk);
 730
 731         return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
 732 }
 733
 734 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 735         unsigned long pixel_clk, unsigned int sample_rate)
 736 {
 737         unsigned long ftdms = pixel_clk;
 738         unsigned int n, cts;
 739         u64 tmp;
 740
 741         n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
 742
 743         /*
 744          * Compute the CTS value from the N value.  Note that CTS and N
 745          * can be up to 20 bits in total, so we need 64-bit math.  Also
 746          * note that our TDMS clock is not fully accurate; it is accurate
 747          * to kHz.  This can introduce an unnecessary remainder in the
 748          * calculation below, so we don't try to warn about that.
 749          */
 750         tmp = (u64)ftdms * n;
 751         do_div(tmp, 128 * sample_rate);
 752         cts = tmp;
 753
 754         dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
 755                 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
 756                 n, cts);
 757
 758         spin_lock_irq(&hdmi->audio_lock);
 759         hdmi->audio_n = n;
 760         hdmi->audio_cts = cts;
 761         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
 762         spin_unlock_irq(&hdmi->audio_lock);
 763 }
 764
 765 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 766 {
 767         mutex_lock(&hdmi->audio_mutex);
 768         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
 769         mutex_unlock(&hdmi->audio_mutex);
 770 }
 771
 772 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 773 {
 774         mutex_lock(&hdmi->audio_mutex);
 775         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 776                                  hdmi->sample_rate);
 777         mutex_unlock(&hdmi->audio_mutex);
 778 }
 779
 780 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 781 {
 782         mutex_lock(&hdmi->audio_mutex);
 783         hdmi->sample_rate = rate;
 784         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 785                                  hdmi->sample_rate);
 786         mutex_unlock(&hdmi->audio_mutex);
 787 }
 788 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
 789
 790 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
 791 {
 792         unsigned long flags;
 793
 794         spin_lock_irqsave(&hdmi->audio_lock, flags);
 795         hdmi->audio_enable = true;
 796         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 797         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 798 }
 799 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
 800
 801 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 802 {
 803         unsigned long flags;
 804
 805         spin_lock_irqsave(&hdmi->audio_lock, flags);
 806         hdmi->audio_enable = false;
 807         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
 808         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 809 }
 810 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 811
 812 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format)
 813 {
 814         switch (bus_format) {
 815         case MEDIA_BUS_FMT_RGB888_1X24:
 816         case MEDIA_BUS_FMT_RGB101010_1X30:
 817         case MEDIA_BUS_FMT_RGB121212_1X36:
 818         case MEDIA_BUS_FMT_RGB161616_1X48:
 819                 return true;
 820
 821         default:
 822                 return false;
 823         }
 824 }
 825
 826 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format)
 827 {
 828         switch (bus_format) {
 829         case MEDIA_BUS_FMT_YUV8_1X24:
 830         case MEDIA_BUS_FMT_YUV10_1X30:
 831         case MEDIA_BUS_FMT_YUV12_1X36:
 832         case MEDIA_BUS_FMT_YUV16_1X48:
 833                 return true;
 834
 835         default:
 836                 return false;
 837         }
 838 }
 839
 840 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format)
 841 {
 842         switch (bus_format) {
 843         case MEDIA_BUS_FMT_UYVY8_1X16:
 844         case MEDIA_BUS_FMT_UYVY10_1X20:
 845         case MEDIA_BUS_FMT_UYVY12_1X24:
 846                 return true;
 847
 848         default:
 849                 return false;
 850         }
 851 }
 852
 853 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format)
 854 {
 855         switch (bus_format) {
 856         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 857         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 858         case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
 859         case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
 860                 return true;
 861
 862         default:
 863                 return false;
 864         }
 865 }
 866
 867 static int hdmi_bus_fmt_color_depth(unsigned int bus_format)
 868 {
 869         switch (bus_format) {
 870         case MEDIA_BUS_FMT_RGB888_1X24:
 871         case MEDIA_BUS_FMT_YUV8_1X24:
 872         case MEDIA_BUS_FMT_UYVY8_1X16:
 873         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 874                 return 8;
 875
 876         case MEDIA_BUS_FMT_RGB101010_1X30:
 877         case MEDIA_BUS_FMT_YUV10_1X30:
 878         case MEDIA_BUS_FMT_UYVY10_1X20:
 879         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 880                 return 10;
 881
 882         case MEDIA_BUS_FMT_RGB121212_1X36:
 883         case MEDIA_BUS_FMT_YUV12_1X36:
 884         case MEDIA_BUS_FMT_UYVY12_1X24:
 885         case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
 886                 return 12;
 887
 888         case MEDIA_BUS_FMT_RGB161616_1X48:
 889         case MEDIA_BUS_FMT_YUV16_1X48:
 890         case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
 891                 return 16;
 892
 893         default:
 894                 return 0;
 895         }
 896 }
 897
 898 /*
 899  * this submodule is responsible for the video data synchronization.
 900  * for example, for RGB 4:4:4 input, the data map is defined as
 901  *                      pin{47~40} <==> R[7:0]
 902  *                      pin{31~24} <==> G[7:0]
 903  *                      pin{15~8}  <==> B[7:0]
 904  */
 905 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 906 {
 907         int color_format = 0;
 908         u8 val;
 909
 910         switch (hdmi->hdmi_data.enc_in_bus_format) {
 911         case MEDIA_BUS_FMT_RGB888_1X24:
 912                 color_format = 0x01;
 913                 break;
 914         case MEDIA_BUS_FMT_RGB101010_1X30:
 915                 color_format = 0x03;
 916                 break;
 917         case MEDIA_BUS_FMT_RGB121212_1X36:
 918                 color_format = 0x05;
 919                 break;
 920         case MEDIA_BUS_FMT_RGB161616_1X48:
 921                 color_format = 0x07;
 922                 break;
 923
 924         case MEDIA_BUS_FMT_YUV8_1X24:
 925         case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
 926                 color_format = 0x09;
 927                 break;
 928         case MEDIA_BUS_FMT_YUV10_1X30:
 929         case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
 930                 color_format = 0x0B;
 931                 break;
 932         case MEDIA_BUS_FMT_YUV12_1X36:
 933         case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
 934                 color_format = 0x0D;
 935                 break;
 936         case MEDIA_BUS_FMT_YUV16_1X48:
 937         case MEDIA_BUS_FMT_UYYVYY16_0_5X48:
 938                 color_format = 0x0F;
 939                 break;
 940
 941         case MEDIA_BUS_FMT_UYVY8_1X16:
 942                 color_format = 0x16;
 943                 break;
 944         case MEDIA_BUS_FMT_UYVY10_1X20:
 945                 color_format = 0x14;
 946                 break;
 947         case MEDIA_BUS_FMT_UYVY12_1X24:
 948                 color_format = 0x12;
 949                 break;
 950
 951         default:
 952                 return;
 953         }
 954
 955         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 956                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 957                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 958         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 959
 960         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 961         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 962                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 963                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 964         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 965         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 966         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 967         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 968         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 969         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 970         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 971 }
 972
 973 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 974 {
 975         return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format;
 976 }
 977
 978 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 979 {
 980         if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
 981                 return 0;
 982
 983         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) ||
 984             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format))
 985                 return 1;
 986
 987         return 0;
 988 }
 989
 990 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 991 {
 992         if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format))
 993                 return 0;
 994
 995         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
 996             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
 997                 return 1;
 998
 999         return 0;
1000 }
1001
1002 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
1003 {
1004         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
1005         unsigned i;
1006         u32 csc_scale = 1;
1007
1008         if (is_color_space_conversion(hdmi)) {
1009                 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) {
1010                         if (hdmi->hdmi_data.enc_out_encoding ==
1011                                                 V4L2_YCBCR_ENC_601)
1012                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
1013                         else
1014                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
1015                 } else if (hdmi_bus_fmt_is_rgb(
1016                                         hdmi->hdmi_data.enc_in_bus_format)) {
1017                         if (hdmi->hdmi_data.enc_out_encoding ==
1018                                                 V4L2_YCBCR_ENC_601)
1019                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
1020                         else
1021                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
1022                         csc_scale = 0;
1023                 }
1024         }
1025
1026         /* The CSC registers are sequential, alternating MSB then LSB */
1027         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
1028                 u16 coeff_a = (*csc_coeff)[0][i];
1029                 u16 coeff_b = (*csc_coeff)[1][i];
1030                 u16 coeff_c = (*csc_coeff)[2][i];
1031
1032                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
1033                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
1034                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
1035                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
1036                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
1037                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
1038         }
1039
1040         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
1041                   HDMI_CSC_SCALE);
1042 }
1043
1044 static void hdmi_video_csc(struct dw_hdmi *hdmi)
1045 {
1046         int color_depth = 0;
1047         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
1048         int decimation = 0;
1049
1050         /* YCC422 interpolation to 444 mode */
1051         if (is_color_space_interpolation(hdmi))
1052                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
1053         else if (is_color_space_decimation(hdmi))
1054                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
1055
1056         switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) {
1057         case 8:
1058                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
1059                 break;
1060         case 10:
1061                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
1062                 break;
1063         case 12:
1064                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
1065                 break;
1066         case 16:
1067                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
1068                 break;
1069
1070         default:
1071                 return;
1072         }
1073
1074         /* Configure the CSC registers */
1075         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
1076         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
1077                   HDMI_CSC_SCALE);
1078
1079         dw_hdmi_update_csc_coeffs(hdmi);
1080 }
1081
1082 /*
1083  * HDMI video packetizer is used to packetize the data.
1084  * for example, if input is YCC422 mode or repeater is used,
1085  * data should be repacked this module can be bypassed.
1086  */
1087 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
1088 {
1089         unsigned int color_depth = 0;
1090         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
1091         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
1092         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
1093         u8 val, vp_conf;
1094
1095         if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) ||
1096             hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) ||
1097             hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) {
1098                 switch (hdmi_bus_fmt_color_depth(
1099                                         hdmi->hdmi_data.enc_out_bus_format)) {
1100                 case 8:
1101                         color_depth = 0;
1102                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1103                         break;
1104                 case 10:
1105                         color_depth = 5;
1106                         break;
1107                 case 12:
1108                         color_depth = 6;
1109                         break;
1110                 case 16:
1111                         color_depth = 7;
1112                         break;
1113                 default:
1114                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
1115                 }
1116         } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) {
1117                 switch (hdmi_bus_fmt_color_depth(
1118                                         hdmi->hdmi_data.enc_out_bus_format)) {
1119                 case 0:
1120                 case 8:
1121                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
1122                         break;
1123                 case 10:
1124                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
1125                         break;
1126                 case 12:
1127                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
1128                         break;
1129
1130                 default:
1131                         return;
1132                 }
1133                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
1134         } else {
1135                 return;
1136         }
1137
1138         /* set the packetizer registers */
1139         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
1140                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
1141                 ((hdmi_data->pix_repet_factor <<
1142                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
1143                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
1144         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
1145
1146         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
1147                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
1148
1149         /* Data from pixel repeater block */
1150         if (hdmi_data->pix_repet_factor > 0) {
1151                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
1152                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
1153         } else { /* data from packetizer block */
1154                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
1155                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
1156         }
1157
1158         hdmi_modb(hdmi, vp_conf,
1159                   HDMI_VP_CONF_PR_EN_MASK |
1160                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
1161
1162         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
1163                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
1164
1165         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
1166
1167         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
1168                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1169                           HDMI_VP_CONF_PP_EN_ENABLE |
1170                           HDMI_VP_CONF_YCC422_EN_DISABLE;
1171         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
1172                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
1173                           HDMI_VP_CONF_PP_EN_DISABLE |
1174                           HDMI_VP_CONF_YCC422_EN_ENABLE;
1175         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
1176                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
1177                           HDMI_VP_CONF_PP_EN_DISABLE |
1178                           HDMI_VP_CONF_YCC422_EN_DISABLE;
1179         } else {
1180                 return;
1181         }
1182
1183         hdmi_modb(hdmi, vp_conf,
1184                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
1185                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
1186
1187         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
1188                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
1189                   HDMI_VP_STUFF_PP_STUFFING_MASK |
1190                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
1191
1192         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
1193                   HDMI_VP_CONF);
1194 }
1195
1196 /* -----------------------------------------------------------------------------
1197  * Synopsys PHY Handling
1198  */
1199
1200 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
1201                                        unsigned char bit)
1202 {
1203         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
1204                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
1205 }
1206
1207 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
1208                                         unsigned char bit)
1209 {
1210         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
1211                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
1212 }
1213
1214 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
1215                                        unsigned char bit)
1216 {
1217         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
1218                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
1219 }
1220
1221 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
1222                                      unsigned char bit)
1223 {
1224         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
1225 }
1226
1227 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
1228                                       unsigned char bit)
1229 {
1230         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
1231 }
1232
1233 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
1234 {
1235         u32 val;
1236
1237         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1238                 if (msec-- == 0)
1239                         return false;
1240                 udelay(1000);
1241         }
1242         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1243
1244         return true;
1245 }
1246
1247 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1248                            unsigned char addr)
1249 {
1250         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1251         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1252         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1253                     HDMI_PHY_I2CM_DATAO_1_ADDR);
1254         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1255                     HDMI_PHY_I2CM_DATAO_0_ADDR);
1256         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1257                     HDMI_PHY_I2CM_OPERATION_ADDR);
1258         hdmi_phy_wait_i2c_done(hdmi, 1000);
1259 }
1260 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write);
1261
1262 static int hdmi_phy_i2c_read(struct dw_hdmi *hdmi, unsigned char addr)
1263 {
1264         int val;
1265
1266         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1267         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1268         hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_1_ADDR);
1269         hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_0_ADDR);
1270         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_READ,
1271                     HDMI_PHY_I2CM_OPERATION_ADDR);
1272         hdmi_phy_wait_i2c_done(hdmi, 1000);
1273         val = hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_1_ADDR);
1274         val = (val & 0xff) << 8;
1275         val += hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_0_ADDR) & 0xff;
1276         return val;
1277 }
1278
1279 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1280 {
1281         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1282                          HDMI_PHY_CONF0_PDZ_OFFSET,
1283                          HDMI_PHY_CONF0_PDZ_MASK);
1284 }
1285
1286 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1287 {
1288         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1289                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
1290                          HDMI_PHY_CONF0_ENTMDS_MASK);
1291 }
1292
1293 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable)
1294 {
1295         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1296                          HDMI_PHY_CONF0_SVSRET_OFFSET,
1297                          HDMI_PHY_CONF0_SVSRET_MASK);
1298 }
1299
1300 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1301 {
1302         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1303                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1304                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1305 }
1306
1307 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1308 {
1309         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1310                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1311                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1312 }
1313
1314 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1315 {
1316         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1317                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1318                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1319 }
1320
1321 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1322 {
1323         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1324                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1325                          HDMI_PHY_CONF0_SELDIPIF_MASK);
1326 }
1327
1328 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
1329 {
1330         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1331         unsigned int i;
1332         u16 val;
1333
1334         if (phy->gen == 1) {
1335                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1336                 dw_hdmi_phy_enable_powerdown(hdmi, true);
1337                 return;
1338         }
1339
1340         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1341
1342         /*
1343          * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went
1344          * to low power mode.
1345          */
1346         for (i = 0; i < 5; ++i) {
1347                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1348                 if (!(val & HDMI_PHY_TX_PHY_LOCK))
1349                         break;
1350
1351                 usleep_range(1000, 2000);
1352         }
1353
1354         if (val & HDMI_PHY_TX_PHY_LOCK)
1355                 dev_warn(hdmi->dev, "PHY failed to power down\n");
1356         else
1357                 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i);
1358
1359         dw_hdmi_phy_gen2_pddq(hdmi, 1);
1360 }
1361
1362 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi)
1363 {
1364         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1365         unsigned int i;
1366         u8 val;
1367
1368         if (phy->gen == 1) {
1369                 dw_hdmi_phy_enable_powerdown(hdmi, false);
1370
1371                 /* Toggle TMDS enable. */
1372                 dw_hdmi_phy_enable_tmds(hdmi, 0);
1373                 dw_hdmi_phy_enable_tmds(hdmi, 1);
1374                 return 0;
1375         }
1376
1377         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1378         dw_hdmi_phy_gen2_pddq(hdmi, 0);
1379
1380         /* Wait for PHY PLL lock */
1381         for (i = 0; i < 5; ++i) {
1382                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1383                 if (val)
1384                         break;
1385
1386                 usleep_range(1000, 2000);
1387         }
1388
1389         if (!val) {
1390                 dev_err(hdmi->dev, "PHY PLL failed to lock\n");
1391                 return -ETIMEDOUT;
1392         }
1393
1394         dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i);
1395         return 0;
1396 }
1397
1398 /*
1399  * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available
1400  * information the DWC MHL PHY has the same register layout and is thus also
1401  * supported by this function.
1402  */
1403 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi,
1404                 const struct dw_hdmi_plat_data *pdata,
1405                 unsigned long mpixelclock)
1406 {
1407         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1408         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1409         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1410
1411         /* PLL/MPLL Cfg - always match on final entry */
1412         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1413                 if (mpixelclock <= mpll_config->mpixelclock)
1414                         break;
1415
1416         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1417                 if (mpixelclock <= mpll_config->mpixelclock)
1418                         break;
1419
1420         for (; phy_config->mpixelclock != ~0UL; phy_config++)
1421                 if (mpixelclock <= mpll_config->mpixelclock)
1422                         break;
1423
1424         if (mpll_config->mpixelclock == ~0UL ||
1425             curr_ctrl->mpixelclock == ~0UL ||
1426             phy_config->mpixelclock == ~0UL)
1427                 return -EINVAL;
1428
1429         /*
1430          * RK3399 mpll clock source is vpll, also is vop clock source.
1431          * vpll rate is twice of mpixelclock in YCBCR420 mode, we need
1432          * to enable mpll pre-divider.
1433          */
1434         if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format) &&
1435             (hdmi->dev_type == RK3399_HDMI || hdmi->dev_type == RK3368_HDMI))
1436                 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce | 4,
1437                                       HDMI_3D_TX_PHY_CPCE_CTRL);
1438         else
1439                 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
1440                                       HDMI_3D_TX_PHY_CPCE_CTRL);
1441         dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
1442                               HDMI_3D_TX_PHY_GMPCTRL);
1443         dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
1444                               HDMI_3D_TX_PHY_CURRCTRL);
1445
1446         dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
1447         dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK,
1448                               HDMI_3D_TX_PHY_MSM_CTRL);
1449
1450         dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM);
1451         dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr,
1452                               HDMI_3D_TX_PHY_CKSYMTXCTRL);
1453         dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr,
1454                               HDMI_3D_TX_PHY_VLEVCTRL);
1455
1456         /* Override and disable clock termination. */
1457         dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE,
1458                               HDMI_3D_TX_PHY_CKCALCTRL);
1459         return 0;
1460 }
1461
1462 static int hdmi_phy_configure(struct dw_hdmi *hdmi)
1463 {
1464         const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
1465         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1466         unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock;
1467         u8 tmds_cfg;
1468         int ret;
1469
1470         dw_hdmi_phy_power_off(hdmi);
1471
1472         /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1473         if (hdmi->connector.scdc_present) {
1474                 drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &tmds_cfg);
1475                 if (mpixelclock > 340000000)
1476                         tmds_cfg |= 2;
1477                 else
1478                         tmds_cfg &= 0x1;
1479                 drm_scdc_writeb(hdmi->ddc, SCDC_TMDS_CONFIG, tmds_cfg);
1480         }
1481
1482         /* Leave low power consumption mode by asserting SVSRET. */
1483         if (phy->has_svsret)
1484                 dw_hdmi_phy_enable_svsret(hdmi, 1);
1485
1486         /* PHY reset. The reset signal is active high on Gen2 PHYs. */
1487         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ);
1488         hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ);
1489
1490         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1491
1492         hdmi_phy_test_clear(hdmi, 1);
1493         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1494                     HDMI_PHY_I2CM_SLAVE_ADDR);
1495         hdmi_phy_test_clear(hdmi, 0);
1496
1497         /* Write to the PHY as configured by the platform */
1498         if (pdata->configure_phy)
1499                 ret = pdata->configure_phy(hdmi, pdata, mpixelclock);
1500         else
1501                 ret = phy->configure(hdmi, pdata, mpixelclock);
1502         if (ret) {
1503                 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n",
1504                         mpixelclock);
1505                 return ret;
1506         }
1507
1508         /* Wait for resuming transmission of TMDS clock and data */
1509         if (mpixelclock > 340000000)
1510                 msleep(100);
1511
1512         return dw_hdmi_phy_power_on(hdmi);
1513 }
1514
1515 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data,
1516                             struct drm_display_mode *mode)
1517 {
1518         int i, ret;
1519
1520         /* HDMI Phy spec says to do the phy initialization sequence twice */
1521         for (i = 0; i < 2; i++) {
1522                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1523                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1524
1525                 ret = hdmi_phy_configure(hdmi);
1526                 if (ret)
1527                         return ret;
1528         }
1529
1530         return 0;
1531 }
1532
1533 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
1534 {
1535         dw_hdmi_phy_power_off(hdmi);
1536 }
1537
1538 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
1539                                                       void *data)
1540 {
1541         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1542                 connector_status_connected : connector_status_disconnected;
1543 }
1544 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd);
1545
1546 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = {
1547         .init = dw_hdmi_phy_init,
1548         .disable = dw_hdmi_phy_disable,
1549         .read_hpd = dw_hdmi_phy_read_hpd,
1550 };
1551
1552 /* -----------------------------------------------------------------------------
1553  * HDMI TX Setup
1554  */
1555
1556 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi,
1557                                 const struct drm_display_mode *mode)
1558 {
1559         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1560         u8 vsync_pol, hsync_pol, data_pol, hdmi_dvi;
1561
1562         /* Configure the video polarity */
1563         vsync_pol = mode->flags & DRM_MODE_FLAG_PVSYNC ?
1564                     HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_HIGH :
1565                     HDMI_A_VIDPOLCFG_VSYNCPOL_ACTIVE_LOW;
1566         hsync_pol = mode->flags & DRM_MODE_FLAG_PHSYNC ?
1567                     HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_HIGH :
1568                     HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW;
1569         data_pol = vmode->mdataenablepolarity ?
1570                     HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH :
1571                     HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1572         hdmi_modb(hdmi, vsync_pol | hsync_pol | data_pol,
1573                   HDMI_A_VIDPOLCFG_VSYNCPOL_MASK |
1574                   HDMI_A_VIDPOLCFG_HSYNCPOL_MASK |
1575                   HDMI_A_VIDPOLCFG_DATAENPOL_MASK,
1576                   HDMI_A_VIDPOLCFG);
1577
1578         /* Config the display mode */
1579         hdmi_dvi = hdmi->sink_is_hdmi ? HDMI_A_HDCPCFG0_HDMIDVI_HDMI :
1580                    HDMI_A_HDCPCFG0_HDMIDVI_DVI;
1581         hdmi_modb(hdmi, hdmi_dvi, HDMI_A_HDCPCFG0_HDMIDVI_MASK,
1582                   HDMI_A_HDCPCFG0);
1583
1584         if (hdmi->hdcp)
1585                 hdmi->hdcp->hdcp_start(hdmi->hdcp);
1586 }
1587
1588 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1589 {
1590         struct hdmi_avi_infoframe frame;
1591         u8 val;
1592         bool is_hdmi2 = false;
1593
1594         if ((mode->flags & DRM_MODE_FLAG_420_MASK) ||
1595             hdmi->connector.scdc_present)
1596                 is_hdmi2 = true;
1597         /* Initialise info frame from DRM mode */
1598         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2);
1599
1600         if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format))
1601                 frame.colorspace = HDMI_COLORSPACE_YUV444;
1602         else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format))
1603                 frame.colorspace = HDMI_COLORSPACE_YUV422;
1604         else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format))
1605                 frame.colorspace = HDMI_COLORSPACE_YUV420;
1606         else
1607                 frame.colorspace = HDMI_COLORSPACE_RGB;
1608
1609         /* Set up colorimetry */
1610         switch (hdmi->hdmi_data.enc_out_encoding) {
1611         case V4L2_YCBCR_ENC_601:
1612                 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601)
1613                         frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1614                 else
1615                         frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1616                 frame.extended_colorimetry =
1617                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1618                 break;
1619         case V4L2_YCBCR_ENC_709:
1620                 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709)
1621                         frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1622                 else
1623                         frame.colorimetry = HDMI_COLORIMETRY_ITU_709;
1624                 frame.extended_colorimetry =
1625                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1626                 break;
1627         default: /* Carries no data */
1628                 frame.colorimetry = HDMI_COLORIMETRY_ITU_601;
1629                 frame.extended_colorimetry =
1630                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1631                 break;
1632         }
1633
1634         frame.scan_mode = HDMI_SCAN_MODE_NONE;
1635
1636         /*
1637          * The Designware IP uses a different byte format from standard
1638          * AVI info frames, though generally the bits are in the correct
1639          * bytes.
1640          */
1641
1642         /*
1643          * AVI data byte 1 differences: Colorspace in bits 0,1,7 rather than
1644          * 5,6,7, active aspect present in bit 6 rather than 4.
1645          */
1646         val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 0x3);
1647         if (frame.active_aspect & 15)
1648                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1649         if (frame.top_bar || frame.bottom_bar)
1650                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1651         if (frame.left_bar || frame.right_bar)
1652                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1653         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1654
1655         /* AVI data byte 2 differences: none */
1656         val = ((frame.colorimetry & 0x3) << 6) |
1657               ((frame.picture_aspect & 0x3) << 4) |
1658               (frame.active_aspect & 0xf);
1659         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1660
1661         /* AVI data byte 3 differences: none */
1662         val = ((frame.extended_colorimetry & 0x7) << 4) |
1663               ((frame.quantization_range & 0x3) << 2) |
1664               (frame.nups & 0x3);
1665         if (frame.itc)
1666                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1667         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1668
1669         /* AVI data byte 4 differences: none */
1670         val = frame.video_code & 0x7f;
1671         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1672
1673         /* AVI Data Byte 5- set up input and output pixel repetition */
1674         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1675                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1676                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1677                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1678                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1679                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1680         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1681
1682         /*
1683          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1684          * ycc range in bits 2,3 rather than 6,7
1685          */
1686         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1687               (frame.content_type & 0x3);
1688         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1689
1690         /* AVI Data Bytes 6-13 */
1691         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1692         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1693         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1694         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1695         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1696         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1697         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1698         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1699 }
1700
1701 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1702                                                  struct drm_display_mode *mode)
1703 {
1704         struct hdmi_vendor_infoframe frame;
1705         u8 buffer[10];
1706         ssize_t err;
1707
1708         /* Disable HDMI vendor specific infoframe send */
1709         hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1710                         HDMI_FC_DATAUTO0_VSD_MASK);
1711
1712         err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode);
1713         if (err < 0)
1714                 /*
1715                  * Going into that statement does not means vendor infoframe
1716                  * fails. It just informed us that vendor infoframe is not
1717                  * needed for the selected mode. Only 4k or stereoscopic 3D
1718                  * mode requires vendor infoframe. So just simply return.
1719                  */
1720                 return;
1721
1722         err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1723         if (err < 0) {
1724                 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1725                         err);
1726                 return;
1727         }
1728
1729         /* Set the length of HDMI vendor specific InfoFrame payload */
1730         hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1731
1732         /* Set 24bit IEEE Registration Identifier */
1733         hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1734         hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1735         hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1736
1737         /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1738         hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1739         hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1740
1741         if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1742                 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1743
1744         /* Packet frame interpolation */
1745         hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1746
1747         /* Auto packets per frame and line spacing */
1748         hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1749
1750         /* Configures the Frame Composer On RDRB mode */
1751         hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1752                         HDMI_FC_DATAUTO0_VSD_MASK);
1753 }
1754
1755 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1756                              const struct drm_display_mode *mode)
1757 {
1758         u8 inv_val, bytes;
1759         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1760         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1761         unsigned int hdisplay, vdisplay;
1762
1763         vmode->mpixelclock = mode->crtc_clock * 1000;
1764         if (mode->flags & DRM_MODE_FLAG_420_MASK)
1765                 vmode->mpixelclock /= 2;
1766         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) ==
1767                 DRM_MODE_FLAG_3D_FRAME_PACKING)
1768                 vmode->mpixelclock *= 2;
1769         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1770
1771         /* Set up HDMI_FC_INVIDCONF
1772          * fc_invidconf.HDCP_keepout must be set (1'b1)
1773          * when activate the scrambler feature.
1774          */
1775         inv_val = (vmode->mpixelclock > 340000000 ||
1776                    hdmi->connector.lte_340mcsc_scramble ?
1777                    HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1778                    HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1779
1780         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1781                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1782                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1783
1784         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1785                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1786                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1787
1788         inv_val |= (vmode->mdataenablepolarity ?
1789                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1790                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1791
1792         if (hdmi->vic == 39)
1793                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1794         else
1795                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1796                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1797                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1798
1799         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1800                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1801                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1802
1803         inv_val |= hdmi->sink_is_hdmi ?
1804                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1805                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1806
1807         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1808
1809         hdisplay = mode->hdisplay;
1810         hblank = mode->htotal - mode->hdisplay;
1811         h_de_hs = mode->hsync_start - mode->hdisplay;
1812         hsync_len = mode->hsync_end - mode->hsync_start;
1813
1814         /*
1815          * When we're setting a YCbCr420 mode, we need
1816          * to adjust the horizontal timing to suit.
1817          */
1818         if (mode->flags & DRM_MODE_FLAG_420_MASK) {
1819                 hdisplay /= 2;
1820                 hblank /= 2;
1821                 h_de_hs /= 2;
1822                 hsync_len /= 2;
1823         }
1824
1825         vdisplay = mode->vdisplay;
1826         vblank = mode->vtotal - mode->vdisplay;
1827         v_de_vs = mode->vsync_start - mode->vdisplay;
1828         vsync_len = mode->vsync_end - mode->vsync_start;
1829
1830         /*
1831          * When we're setting an interlaced mode, we need
1832          * to adjust the vertical timing to suit.
1833          */
1834         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1835                 vdisplay /= 2;
1836                 vblank /= 2;
1837                 v_de_vs /= 2;
1838                 vsync_len /= 2;
1839         } else if ((mode->flags & DRM_MODE_FLAG_3D_MASK) ==
1840                 DRM_MODE_FLAG_3D_FRAME_PACKING) {
1841                 vdisplay += mode->vtotal;
1842         }
1843
1844         /* Scrambling Control */
1845         if (hdmi->connector.scdc_present) {
1846                 if (vmode->mpixelclock > 340000000 ||
1847                     hdmi->connector.lte_340mcsc_scramble) {
1848                         drm_scdc_readb(&hdmi->i2c->adap, SCDC_SINK_VERSION,
1849                                        &bytes);
1850                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_SOURCE_VERSION,
1851                                         bytes);
1852                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_TMDS_CONFIG, 1);
1853                         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1854                                     HDMI_MC_SWRSTZ);
1855                         hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1856                 } else {
1857                         hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1858                         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1859                                     HDMI_MC_SWRSTZ);
1860                         drm_scdc_writeb(&hdmi->i2c->adap, SCDC_TMDS_CONFIG, 0);
1861                 }
1862         }
1863
1864         /* Set up horizontal active pixel width */
1865         hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
1866         hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
1867
1868         /* Set up vertical active lines */
1869         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1870         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1871
1872         /* Set up horizontal blanking pixel region width */
1873         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1874         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1875
1876         /* Set up vertical blanking pixel region width */
1877         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1878
1879         /* Set up HSYNC active edge delay width (in pixel clks) */
1880         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1881         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1882
1883         /* Set up VSYNC active edge delay (in lines) */
1884         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1885
1886         /* Set up HSYNC active pulse width (in pixel clks) */
1887         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1888         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1889
1890         /* Set up VSYNC active edge delay (in lines) */
1891         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1892 }
1893
1894 /* HDMI Initialization Step B.4 */
1895 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1896 {
1897         u8 clkdis;
1898
1899         /* control period minimum duration */
1900         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1901         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1902         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1903
1904         /* Set to fill TMDS data channels */
1905         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1906         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1907         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1908
1909         /* Enable pixel clock and tmds data path */
1910         clkdis = 0x7F;
1911         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1912         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1913
1914         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1915         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1916
1917         /* Enable csc path */
1918         if (is_color_space_conversion(hdmi)) {
1919                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1920                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1921         }
1922
1923         /* Enable pixel repetition path */
1924         if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) {
1925                 clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE;
1926                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1927         }
1928
1929         /* Enable color space conversion if needed */
1930         if (is_color_space_conversion(hdmi))
1931                 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH,
1932                             HDMI_MC_FLOWCTRL);
1933         else
1934                 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS,
1935                             HDMI_MC_FLOWCTRL);
1936 }
1937
1938 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1939 {
1940         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1941 }
1942
1943 /* Workaround to clear the overflow condition */
1944 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1945 {
1946         unsigned int count;
1947         unsigned int i;
1948         u8 val;
1949
1950         /*
1951          * Under some circumstances the Frame Composer arithmetic unit can miss
1952          * an FC register write due to being busy processing the previous one.
1953          * The issue can be worked around by issuing a TMDS software reset and
1954          * then write one of the FC registers several times.
1955          *
1956          * The number of iterations matters and depends on the HDMI TX revision
1957          * (and possibly on the platform). So far only i.MX6Q (v1.30a) and
1958          * i.MX6DL (v1.31a) have been identified as needing the workaround, with
1959          * 4 and 1 iterations respectively.
1960          */
1961
1962         switch (hdmi->version) {
1963         case 0x130a:
1964                 count = 4;
1965                 break;
1966         case 0x131a:
1967                 count = 1;
1968                 break;
1969         default:
1970                 return;
1971         }
1972
1973         /* TMDS software reset */
1974         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1975
1976         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1977         for (i = 0; i < count; i++)
1978                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1979 }
1980
1981 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1982 {
1983         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1984         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1985 }
1986
1987 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1988 {
1989         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1990                     HDMI_IH_MUTE_FC_STAT2);
1991 }
1992
1993 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1994 {
1995         int ret;
1996
1997         hdmi_disable_overflow_interrupts(hdmi);
1998
1999         hdmi->vic = drm_match_cea_mode(mode);
2000
2001         if (!hdmi->vic) {
2002                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
2003         } else {
2004                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
2005         }
2006
2007         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
2008             (hdmi->vic == 21) || (hdmi->vic == 22) ||
2009             (hdmi->vic == 2) || (hdmi->vic == 3) ||
2010             (hdmi->vic == 17) || (hdmi->vic == 18))
2011                 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601;
2012         else
2013                 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709;
2014
2015         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2016                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
2017                 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1;
2018         } else {
2019                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
2020                 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
2021         }
2022
2023         if (mode->flags & DRM_MODE_FLAG_420_MASK) {
2024                 hdmi->hdmi_data.enc_in_bus_format =
2025                         MEDIA_BUS_FMT_UYYVYY8_0_5X24;
2026                 hdmi->hdmi_data.enc_out_bus_format =
2027                         MEDIA_BUS_FMT_UYYVYY8_0_5X24;
2028         } else {
2029                 /* TOFIX: Get input format from plat data or fallback to RGB888 */
2030                 if (hdmi->plat_data->input_bus_format)
2031                         hdmi->hdmi_data.enc_in_bus_format =
2032                                 hdmi->plat_data->input_bus_format;
2033                 else
2034                         hdmi->hdmi_data.enc_in_bus_format =
2035                                 MEDIA_BUS_FMT_RGB888_1X24;
2036                 /* TOFIX: Default to RGB888 output format */
2037                 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
2038         }
2039         /* TOFIX: Get input encoding from plat data or fallback to none */
2040         if (hdmi->plat_data->input_bus_encoding)
2041                 hdmi->hdmi_data.enc_in_encoding =
2042                         hdmi->plat_data->input_bus_encoding;
2043         else
2044                 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT;
2045         /*
2046          * According to the dw-hdmi specification 6.4.2
2047          * vp_pr_cd[3:0]:
2048          * 0000b: No pixel repetition (pixel sent only once)
2049          * 0001b: Pixel sent two times (pixel repeated once)
2050          */
2051         hdmi->hdmi_data.pix_repet_factor =
2052                 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0;
2053         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
2054
2055         /* HDMI Initialization Step B.1 */
2056         hdmi_av_composer(hdmi, mode);
2057
2058         /* HDMI Initialization Step B.2 */
2059         dw_hdmi_enable_video_path(hdmi);
2060
2061         /* HDMI Initializateion Step B.3 */
2062         ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode);
2063         if (ret)
2064                 return ret;
2065         hdmi->phy.enabled = true;
2066
2067         if (hdmi->sink_has_audio) {
2068                 dev_dbg(hdmi->dev, "sink has audio support\n");
2069
2070                 /* HDMI Initialization Step E - Configure audio */
2071                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
2072                 hdmi_enable_audio_clk(hdmi);
2073         }
2074
2075         /* not for DVI mode */
2076         if (hdmi->sink_is_hdmi) {
2077                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
2078
2079                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
2080                 hdmi_config_AVI(hdmi, mode);
2081                 hdmi_config_vendor_specific_infoframe(hdmi, mode);
2082         } else {
2083                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
2084         }
2085
2086         hdmi_video_packetize(hdmi);
2087         hdmi_video_csc(hdmi);
2088         hdmi_video_sample(hdmi);
2089         hdmi_tx_hdcp_config(hdmi, mode);
2090         dw_hdmi_clear_overflow(hdmi);
2091         if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
2092                 hdmi_enable_overflow_interrupts(hdmi);
2093
2094         return 0;
2095 }
2096
2097 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
2098 {
2099         u8 ih_mute;
2100
2101         /*
2102          * Boot up defaults are:
2103          * HDMI_IH_MUTE   = 0x03 (disabled)
2104          * HDMI_IH_MUTE_* = 0x00 (enabled)
2105          *
2106          * Disable top level interrupt bits in HDMI block
2107          */
2108         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
2109                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2110                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
2111
2112         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2113
2114         /* by default mask all interrupts */
2115         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
2116         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
2117         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
2118         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
2119         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
2120         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
2121         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
2122         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
2123         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
2124         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
2125         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
2126         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
2127         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
2128         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
2129         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
2130
2131         /* Disable interrupts in the IH_MUTE_* registers */
2132         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
2133         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
2134         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
2135         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
2136         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
2137         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
2138         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
2139         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
2140         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
2141         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
2142
2143         /* Enable top level interrupt bits in HDMI block */
2144         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
2145                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
2146         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
2147 }
2148
2149 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
2150 {
2151         hdmi->bridge_is_on = true;
2152         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
2153 }
2154
2155 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
2156 {
2157         if (hdmi->phy.enabled) {
2158                 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
2159                 hdmi->phy.enabled = false;
2160         }
2161
2162         if (hdmi->hdcp)
2163                 hdmi->hdcp->hdcp_stop(hdmi->hdcp);
2164         hdmi->bridge_is_on = false;
2165 }
2166
2167 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
2168 {
2169         int force = hdmi->force;
2170
2171         if (hdmi->disabled) {
2172                 force = DRM_FORCE_OFF;
2173         } else if (force == DRM_FORCE_UNSPECIFIED) {
2174                 if (hdmi->rxsense)
2175                         force = DRM_FORCE_ON;
2176                 else
2177                         force = DRM_FORCE_OFF;
2178         }
2179
2180         if (force == DRM_FORCE_OFF) {
2181                 if (hdmi->bridge_is_on)
2182                         dw_hdmi_poweroff(hdmi);
2183         } else {
2184                 if (!hdmi->bridge_is_on)
2185                         dw_hdmi_poweron(hdmi);
2186         }
2187 }
2188
2189 /*
2190  * Adjust the detection of RXSENSE according to whether we have a forced
2191  * connection mode enabled, or whether we have been disabled.  There is
2192  * no point processing RXSENSE interrupts if we have a forced connection
2193  * state, or DRM has us disabled.
2194  *
2195  * We also disable rxsense interrupts when we think we're disconnected
2196  * to avoid floating TDMS signals giving false rxsense interrupts.
2197  *
2198  * Note: we still need to listen for HPD interrupts even when DRM has us
2199  * disabled so that we can detect a connect event.
2200  */
2201 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
2202 {
2203         u8 old_mask = hdmi->phy_mask;
2204
2205         if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
2206                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
2207         else
2208                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
2209
2210         if (old_mask != hdmi->phy_mask)
2211                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
2212 }
2213
2214 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
2215                                     struct drm_display_mode *orig_mode,
2216                                     struct drm_display_mode *mode)
2217 {
2218         struct dw_hdmi *hdmi = bridge->driver_private;
2219
2220         mutex_lock(&hdmi->mutex);
2221
2222         /* Store the display mode for plugin/DKMS poweron events */
2223         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
2224
2225         mutex_unlock(&hdmi->mutex);
2226 }
2227
2228 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
2229 {
2230         struct dw_hdmi *hdmi = bridge->driver_private;
2231
2232         mutex_lock(&hdmi->mutex);
2233         hdmi->disabled = true;
2234         dw_hdmi_update_power(hdmi);
2235         dw_hdmi_update_phy_mask(hdmi);
2236         mutex_unlock(&hdmi->mutex);
2237 }
2238
2239 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
2240 {
2241         struct dw_hdmi *hdmi = bridge->driver_private;
2242
2243         mutex_lock(&hdmi->mutex);
2244         hdmi->disabled = false;
2245         dw_hdmi_update_power(hdmi);
2246         dw_hdmi_update_phy_mask(hdmi);
2247         mutex_unlock(&hdmi->mutex);
2248 }
2249
2250 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
2251 {
2252         /* do nothing */
2253 }
2254
2255 static enum drm_connector_status
2256 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
2257 {
2258         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2259                                              connector);
2260
2261         mutex_lock(&hdmi->mutex);
2262         hdmi->force = DRM_FORCE_UNSPECIFIED;
2263         dw_hdmi_update_power(hdmi);
2264         dw_hdmi_update_phy_mask(hdmi);
2265         mutex_unlock(&hdmi->mutex);
2266
2267         return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
2268 }
2269
2270 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
2271 {
2272         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2273                                              connector);
2274         struct edid *edid;
2275         int ret = 0;
2276
2277         if (!hdmi->ddc)
2278                 return 0;
2279
2280         edid = drm_get_edid(connector, hdmi->ddc);
2281         if (edid) {
2282                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
2283                         edid->width_cm, edid->height_cm);
2284
2285                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
2286                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
2287                 drm_mode_connector_update_edid_property(connector, edid);
2288                 ret = drm_add_edid_modes(connector, edid);
2289                 /* Store the ELD */
2290                 drm_edid_to_eld(connector, edid);
2291                 kfree(edid);
2292         } else {
2293                 dev_dbg(hdmi->dev, "failed to get edid\n");
2294         }
2295
2296         return ret;
2297 }
2298
2299 static enum drm_mode_status
2300 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
2301                              struct drm_display_mode *mode)
2302 {
2303         struct dw_hdmi *hdmi = container_of(connector,
2304                                            struct dw_hdmi, connector);
2305         enum drm_mode_status mode_status = MODE_OK;
2306
2307         if (hdmi->plat_data->mode_valid)
2308                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
2309
2310         return mode_status;
2311 }
2312
2313 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
2314                                                            *connector)
2315 {
2316         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2317                                              connector);
2318
2319         return hdmi->encoder;
2320 }
2321
2322 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
2323 {
2324         drm_connector_unregister(connector);
2325         drm_connector_cleanup(connector);
2326 }
2327
2328 static void dw_hdmi_connector_force(struct drm_connector *connector)
2329 {
2330         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2331                                              connector);
2332
2333         mutex_lock(&hdmi->mutex);
2334         hdmi->force = connector->force;
2335         dw_hdmi_update_power(hdmi);
2336         dw_hdmi_update_phy_mask(hdmi);
2337         mutex_unlock(&hdmi->mutex);
2338 }
2339
2340 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
2341         .dpms = drm_helper_connector_dpms,
2342         .fill_modes = drm_helper_probe_single_connector_modes,
2343         .detect = dw_hdmi_connector_detect,
2344         .destroy = dw_hdmi_connector_destroy,
2345         .force = dw_hdmi_connector_force,
2346 };
2347
2348 static const struct drm_connector_funcs dw_hdmi_atomic_connector_funcs = {
2349         .dpms = drm_atomic_helper_connector_dpms,
2350         .fill_modes = drm_helper_probe_single_connector_modes,
2351         .detect = dw_hdmi_connector_detect,
2352         .destroy = dw_hdmi_connector_destroy,
2353         .force = dw_hdmi_connector_force,
2354         .reset = drm_atomic_helper_connector_reset,
2355         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2356         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2357 };
2358
2359 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
2360         .get_modes = dw_hdmi_connector_get_modes,
2361         .mode_valid = dw_hdmi_connector_mode_valid,
2362         .best_encoder = dw_hdmi_connector_best_encoder,
2363 };
2364
2365 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2366         .enable = dw_hdmi_bridge_enable,
2367         .disable = dw_hdmi_bridge_disable,
2368         .pre_enable = dw_hdmi_bridge_nop,
2369         .post_disable = dw_hdmi_bridge_nop,
2370         .mode_set = dw_hdmi_bridge_mode_set,
2371 };
2372
2373 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2374 {
2375         struct dw_hdmi_i2c *i2c = hdmi->i2c;
2376         unsigned int stat;
2377
2378         stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2379         if (!stat)
2380                 return IRQ_NONE;
2381
2382         hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2383
2384         i2c->stat = stat;
2385
2386         complete(&i2c->cmp);
2387
2388         return IRQ_HANDLED;
2389 }
2390
2391 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
2392 {
2393         struct dw_hdmi *hdmi = dev_id;
2394         u8 intr_stat, hdcp_stat;
2395         irqreturn_t ret = IRQ_NONE;
2396
2397         if (hdmi->i2c)
2398                 ret = dw_hdmi_i2c_irq(hdmi);
2399
2400         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2401         if (intr_stat) {
2402                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2403                 return IRQ_WAKE_THREAD;
2404         }
2405
2406         hdcp_stat = hdmi_readb(hdmi, HDMI_A_APIINTSTAT);
2407         if (hdcp_stat) {
2408                 dev_dbg(hdmi->dev, "HDCP irq %#x\n", hdcp_stat);
2409                 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
2410                 return IRQ_WAKE_THREAD;
2411         }
2412
2413         return ret;
2414 }
2415
2416 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
2417 {
2418         struct dw_hdmi *hdmi = dev_id;
2419         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat, hdcp_stat;
2420
2421         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2422         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
2423         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2424
2425         phy_pol_mask = 0;
2426         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2427                 phy_pol_mask |= HDMI_PHY_HPD;
2428         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2429                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2430         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2431                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2432         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2433                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2434         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2435                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2436
2437         if (phy_pol_mask)
2438                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2439
2440         /*
2441          * RX sense tells us whether the TDMS transmitters are detecting
2442          * load - in other words, there's something listening on the
2443          * other end of the link.  Use this to decide whether we should
2444          * power on the phy as HPD may be toggled by the sink to merely
2445          * ask the source to re-read the EDID.
2446          */
2447         if (intr_stat &
2448             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
2449                 mutex_lock(&hdmi->mutex);
2450                 if (!hdmi->bridge_is_on && !hdmi->force) {
2451                         /*
2452                          * If the RX sense status indicates we're disconnected,
2453                          * clear the software rxsense status.
2454                          */
2455                         if (!(phy_stat & HDMI_PHY_RX_SENSE))
2456                                 hdmi->rxsense = false;
2457
2458                         /*
2459                          * Only set the software rxsense status when both
2460                          * rxsense and hpd indicates we're connected.
2461                          * This avoids what seems to be bad behaviour in
2462                          * at least iMX6S versions of the phy.
2463                          */
2464                         if (phy_stat & HDMI_PHY_HPD)
2465                                 hdmi->rxsense = true;
2466
2467                         dw_hdmi_update_power(hdmi);
2468                         dw_hdmi_update_phy_mask(hdmi);
2469                 }
2470                 mutex_unlock(&hdmi->mutex);
2471         }
2472
2473         check_hdmi_irq(hdmi, intr_stat, phy_int_pol);
2474
2475         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
2476         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2477                     HDMI_IH_MUTE_PHY_STAT0);
2478
2479         hdcp_stat = hdmi_readb(hdmi, HDMI_A_APIINTSTAT);
2480         if (hdcp_stat) {
2481                 if (hdmi->hdcp)
2482                         hdmi->hdcp->hdcp_isr(hdmi->hdcp, hdcp_stat);
2483                 hdmi_writeb(hdmi, hdcp_stat, HDMI_A_APIINTCLR);
2484                 hdmi_writeb(hdmi, 0x00, HDMI_A_APIINTMSK);
2485         }
2486
2487         return IRQ_HANDLED;
2488 }
2489
2490 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = {
2491         {
2492                 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY,
2493                 .name = "DWC HDMI TX PHY",
2494                 .gen = 1,
2495         }, {
2496                 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC,
2497                 .name = "DWC MHL PHY + HEAC PHY",
2498                 .gen = 2,
2499                 .has_svsret = true,
2500                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2501         }, {
2502                 .type = DW_HDMI_PHY_DWC_MHL_PHY,
2503                 .name = "DWC MHL PHY",
2504                 .gen = 2,
2505                 .has_svsret = true,
2506                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2507         }, {
2508                 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC,
2509                 .name = "DWC HDMI 3D TX PHY + HEAC PHY",
2510                 .gen = 2,
2511                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2512         }, {
2513                 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY,
2514                 .name = "DWC HDMI 3D TX PHY",
2515                 .gen = 2,
2516                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2517         }, {
2518                 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
2519                 .name = "DWC HDMI 2.0 TX PHY",
2520                 .gen = 2,
2521                 .has_svsret = true,
2522                 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx,
2523         }, {
2524                 .type = DW_HDMI_PHY_VENDOR_PHY,
2525                 .name = "Vendor PHY",
2526         }
2527 };
2528
2529 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi)
2530 {
2531         unsigned int i;
2532         u8 phy_type;
2533
2534         phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID);
2535
2536         /*
2537          * RK3328 phy_type is DW_HDMI_PHY_DWC_HDMI20_TX_PHY,
2538          * but it has a vedor phy.
2539          */
2540         if (phy_type == DW_HDMI_PHY_VENDOR_PHY ||
2541             hdmi->dev_type == RK3328_HDMI) {
2542                 /* Vendor PHYs require support from the glue layer. */
2543                 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) {
2544                         dev_err(hdmi->dev,
2545                                 "Vendor HDMI PHY not supported by glue layer\n");
2546                         return -ENODEV;
2547                 }
2548
2549                 hdmi->phy.ops = hdmi->plat_data->phy_ops;
2550                 hdmi->phy.data = hdmi->plat_data->phy_data;
2551                 hdmi->phy.name = hdmi->plat_data->phy_name;
2552                 return 0;
2553         }
2554
2555         /* Synopsys PHYs are handled internally. */
2556         for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) {
2557                 if (dw_hdmi_phys[i].type == phy_type) {
2558                         hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops;
2559                         hdmi->phy.name = dw_hdmi_phys[i].name;
2560                         hdmi->phy.data = (void *)&dw_hdmi_phys[i];
2561
2562                         if (!dw_hdmi_phys[i].configure &&
2563                             !hdmi->plat_data->configure_phy) {
2564                                 dev_err(hdmi->dev, "%s requires platform support\n",
2565                                         hdmi->phy.name);
2566                                 return -ENODEV;
2567                         }
2568
2569                         return 0;
2570                 }
2571         }
2572
2573         dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type);
2574         return -ENODEV;
2575 }
2576
2577 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
2578 {
2579         struct drm_encoder *encoder = hdmi->encoder;
2580         struct drm_bridge *bridge = &hdmi->bridge;
2581         int ret;
2582
2583         bridge->driver_private = hdmi;
2584         bridge->funcs = &dw_hdmi_bridge_funcs;
2585         ret = drm_bridge_attach(drm, bridge);
2586         if (ret) {
2587                 DRM_ERROR("Failed to initialize bridge with drm\n");
2588                 return -EINVAL;
2589         }
2590
2591         encoder->bridge = bridge;
2592         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
2593         hdmi->connector.port = hdmi->dev->of_node;
2594
2595         drm_connector_helper_add(&hdmi->connector,
2596                                  &dw_hdmi_connector_helper_funcs);
2597
2598         if (drm_core_check_feature(drm, DRIVER_ATOMIC))
2599                 drm_connector_init(drm, &hdmi->connector,
2600                                    &dw_hdmi_atomic_connector_funcs,
2601                                    DRM_MODE_CONNECTOR_HDMIA);
2602         else
2603                 drm_connector_init(drm, &hdmi->connector,
2604                                    &dw_hdmi_connector_funcs,
2605                                    DRM_MODE_CONNECTOR_HDMIA);
2606
2607         drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
2608
2609         return 0;
2610 }
2611
2612 #include <linux/fs.h>
2613 #include <linux/debugfs.h>
2614 #include <linux/seq_file.h>
2615
2616 struct dw_hdmi_reg_table {
2617         int reg_base;
2618         int reg_end;
2619 };
2620
2621 static const struct dw_hdmi_reg_table hdmi_reg_table[] = {
2622         {HDMI_DESIGN_ID, HDMI_CONFIG3_ID},
2623         {HDMI_IH_FC_STAT0, HDMI_IH_MUTE},
2624         {HDMI_TX_INVID0, HDMI_TX_BCBDATA1},
2625         {HDMI_VP_STATUS, HDMI_VP_POL},
2626         {HDMI_FC_INVIDCONF, HDMI_FC_DBGTMDS2},
2627         {HDMI_PHY_CONF0, HDMI_PHY_POL0},
2628         {HDMI_PHY_I2CM_SLAVE_ADDR, HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR},
2629         {HDMI_AUD_CONF0, 0x3624},
2630         {HDMI_MC_SFRDIV, HDMI_MC_HEACPHY_RST},
2631         {HDMI_CSC_CFG, HDMI_CSC_COEF_C4_LSB},
2632         {HDMI_A_HDCPCFG0, 0x52bb},
2633         {0x7800, 0x7818},
2634         {0x7900, 0x790e},
2635         {HDMI_CEC_CTRL, HDMI_CEC_WKUPCTRL},
2636         {HDMI_I2CM_SLAVE, 0x7e31},
2637 };
2638
2639 static int dw_hdmi_ctrl_show(struct seq_file *s, void *v)
2640 {
2641         struct dw_hdmi *hdmi = s->private;
2642         u32 i = 0, j = 0, val = 0;
2643
2644         seq_puts(s, "\n>>>hdmi_ctl reg ");
2645         for (i = 0; i < 16; i++)
2646                 seq_printf(s, " %2x", i);
2647         seq_puts(s, "\n---------------------------------------------------");
2648
2649         for (i = 0; i < ARRAY_SIZE(hdmi_reg_table); i++) {
2650                 for (j = hdmi_reg_table[i].reg_base;
2651                      j <= hdmi_reg_table[i].reg_end; j++) {
2652                         val = hdmi_readb(hdmi, j);
2653                         if ((j - hdmi_reg_table[i].reg_base) % 16 == 0)
2654                                 seq_printf(s, "\n>>>hdmi_ctl %04x:", j);
2655                         seq_printf(s, " %02x", val);
2656                 }
2657         }
2658         seq_puts(s, "\n---------------------------------------------------\n");
2659
2660         return 0;
2661 }
2662
2663 static int dw_hdmi_ctrl_open(struct inode *inode, struct file *file)
2664 {
2665         return single_open(file, dw_hdmi_ctrl_show, inode->i_private);
2666 }
2667
2668 static ssize_t
2669 dw_hdmi_ctrl_write(struct file *file, const char __user *buf,
2670                    size_t count, loff_t *ppos)
2671 {
2672         struct dw_hdmi *hdmi =
2673                 ((struct seq_file *)file->private_data)->private;
2674         u32 reg, val;
2675         char kbuf[25];
2676
2677         if (copy_from_user(kbuf, buf, count))
2678                 return -EFAULT;
2679         if (sscanf(kbuf, "%x%x", &reg, &val) == -1)
2680                 return -EFAULT;
2681         if ((reg < 0) || (reg > HDMI_I2CM_FS_SCL_LCNT_0_ADDR)) {
2682                 dev_err(hdmi->dev, "it is no a hdmi register\n");
2683                 return count;
2684         }
2685         dev_info(hdmi->dev, "/**********hdmi register config******/");
2686         dev_info(hdmi->dev, "\n reg=%x val=%x\n", reg, val);
2687         hdmi_writeb(hdmi, val, reg);
2688         return count;
2689 }
2690
2691 static const struct file_operations dw_hdmi_ctrl_fops = {
2692         .owner = THIS_MODULE,
2693         .open = dw_hdmi_ctrl_open,
2694         .read = seq_read,
2695         .write = dw_hdmi_ctrl_write,
2696         .llseek = seq_lseek,
2697         .release = single_release,
2698 };
2699
2700 static int dw_hdmi_phy_show(struct seq_file *s, void *v)
2701 {
2702         struct dw_hdmi *hdmi = s->private;
2703         u32 i, total, val;
2704
2705         seq_puts(s, "\n>>>hdmi_phy reg\n");
2706         if (hdmi->dev_type != RK3328_HDMI)
2707                 total = 0x28;
2708         else
2709                 total = 0x100;
2710         for (i = 0; i < total; i++) {
2711                 if (hdmi->dev_type != RK3328_HDMI)
2712                         val = hdmi_phy_i2c_read(hdmi, i);
2713                 else
2714                         val = hdmi->phy.ops->read(hdmi, hdmi->phy.data, i);
2715                 seq_printf(s, "regs %02x val %04x\n", i, val);
2716         }
2717         return 0;
2718 }
2719
2720 static int dw_hdmi_phy_open(struct inode *inode, struct file *file)
2721 {
2722         return single_open(file, dw_hdmi_phy_show, inode->i_private);
2723 }
2724
2725 static ssize_t
2726 dw_hdmi_phy_write(struct file *file, const char __user *buf,
2727                   size_t count, loff_t *ppos)
2728 {
2729         struct dw_hdmi *hdmi =
2730                 ((struct seq_file *)file->private_data)->private;
2731         u32 reg, val;
2732         char kbuf[25];
2733
2734         if (copy_from_user(kbuf, buf, count))
2735                 return -EFAULT;
2736         if (sscanf(kbuf, "%x%x", &reg, &val) == -1)
2737                 return -EFAULT;
2738         if ((reg < 0) || (reg > 0x100)) {
2739                 dev_err(hdmi->dev, "it is not a hdmi phy register\n");
2740                 return count;
2741         }
2742         dev_info(hdmi->dev, "/*******hdmi phy register config******/");
2743         dev_info(hdmi->dev, "\n reg=%x val=%x\n", reg, val);
2744         if (hdmi->dev_type != RK3328_HDMI)
2745                 dw_hdmi_phy_i2c_write(hdmi, val, reg);
2746         else
2747                 hdmi->phy.ops->write(hdmi, hdmi->phy.data, val, reg);
2748         return count;
2749 }
2750
2751 static const struct file_operations dw_hdmi_phy_fops = {
2752         .owner = THIS_MODULE,
2753         .open = dw_hdmi_phy_open,
2754         .read = seq_read,
2755         .write = dw_hdmi_phy_write,
2756         .llseek = seq_lseek,
2757         .release = single_release,
2758 };
2759
2760 static void dw_hdmi_register_debugfs(struct device *dev, struct dw_hdmi *hdmi)
2761 {
2762         struct dentry *debugfs_dir;
2763
2764         debugfs_dir = debugfs_create_dir("dw-hdmi", NULL);
2765         if (IS_ERR(debugfs_dir)) {
2766                 dev_err(dev, "failed to create debugfs dir!\n");
2767                 return;
2768         }
2769         debugfs_create_file("ctrl", 0400, debugfs_dir,
2770                             hdmi, &dw_hdmi_ctrl_fops);
2771         debugfs_create_file("phy", 0400, debugfs_dir,
2772                             hdmi, &dw_hdmi_phy_fops);
2773 }
2774
2775 static void dw_hdmi_register_hdcp(struct device *dev, struct dw_hdmi *hdmi,
2776                                   u32 val)
2777 {
2778         struct dw_hdcp hdmi_hdcp = {
2779                 .hdmi = hdmi,
2780                 .write = hdmi_writeb,
2781                 .read = hdmi_readb,
2782                 .regs = hdmi->regs,
2783                 .reg_io_width = val,
2784                 .enable = 0,
2785         };
2786         struct platform_device_info hdcp_device_info = {
2787                 .parent = dev,
2788                 .id = PLATFORM_DEVID_AUTO,
2789                 .res = NULL,
2790                 .num_res = 0,
2791                 .name = DW_HDCP_DRIVER_NAME,
2792                 .data = &hdmi_hdcp,
2793                 .size_data = sizeof(hdmi_hdcp),
2794                 .dma_mask = DMA_BIT_MASK(32),
2795         };
2796
2797         hdmi->hdcp_dev = platform_device_register_full(&hdcp_device_info);
2798         if (IS_ERR(hdmi->hdcp_dev))
2799                 dev_err(dev, "failed to register hdcp!\n");
2800         else
2801                 hdmi->hdcp = hdmi->hdcp_dev->dev.platform_data;
2802 }
2803
2804 int dw_hdmi_bind(struct device *dev, struct device *master,
2805                  void *data, struct drm_encoder *encoder,
2806                  struct resource *iores, int irq,
2807                  const struct dw_hdmi_plat_data *plat_data)
2808 {
2809         struct drm_device *drm = data;
2810         struct device_node *np = dev->of_node;
2811         struct platform_device_info pdevinfo;
2812         struct device_node *ddc_node;
2813         struct dw_hdmi *hdmi;
2814         int ret;
2815         u8 prod_id0;
2816         u8 prod_id1;
2817         u32 val = 1;
2818         u8 config0;
2819         u8 config3;
2820
2821         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2822         if (!hdmi)
2823                 return -ENOMEM;
2824
2825         hdmi->connector.interlace_allowed = 1;
2826         hdmi->connector.stereo_allowed = 1;
2827
2828         hdmi->plat_data = plat_data;
2829         hdmi->dev = dev;
2830         hdmi->dev_type = plat_data->dev_type;
2831         hdmi->sample_rate = 48000;
2832         hdmi->encoder = encoder;
2833         hdmi->disabled = true;
2834         hdmi->rxsense = true;
2835         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2836         hdmi->irq = irq;
2837
2838         mutex_init(&hdmi->mutex);
2839         mutex_init(&hdmi->audio_mutex);
2840         spin_lock_init(&hdmi->audio_lock);
2841
2842         of_property_read_u32(np, "reg-io-width", &val);
2843
2844         switch (val) {
2845         case 4:
2846                 hdmi->write = dw_hdmi_writel;
2847                 hdmi->read = dw_hdmi_readl;
2848                 break;
2849         case 1:
2850                 hdmi->write = dw_hdmi_writeb;
2851                 hdmi->read = dw_hdmi_readb;
2852                 break;
2853         default:
2854                 dev_err(dev, "reg-io-width must be 1 or 4\n");
2855                 return -EINVAL;
2856         }
2857
2858         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2859         if (ddc_node) {
2860                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2861                 of_node_put(ddc_node);
2862                 if (!hdmi->ddc) {
2863                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
2864                         return -EPROBE_DEFER;
2865                 }
2866
2867         } else {
2868                 dev_dbg(hdmi->dev, "no ddc property found\n");
2869         }
2870
2871         /* If DDC bus is not specified, try to register HDMI I2C bus */
2872         if (!hdmi->ddc) {
2873                 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2874                 if (IS_ERR(hdmi->ddc))
2875                         hdmi->ddc = NULL;
2876                 /*
2877                  * Read high and low time from device tree. If not available use
2878                  * the default timing scl clock rate is about 99.6KHz.
2879                  */
2880                 if (of_property_read_u32(np, "ddc-i2c-scl-high-time-ns",
2881                                          &hdmi->i2c->scl_high_ns))
2882                         hdmi->i2c->scl_high_ns = 4708;
2883                 if (of_property_read_u32(np, "ddc-i2c-scl-low-time-ns",
2884                                          &hdmi->i2c->scl_low_ns))
2885                         hdmi->i2c->scl_low_ns = 4916;
2886         }
2887
2888         hdmi->regs = devm_ioremap_resource(dev, iores);
2889         if (IS_ERR(hdmi->regs))
2890                 return PTR_ERR(hdmi->regs);
2891
2892         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2893         if (IS_ERR(hdmi->isfr_clk)) {
2894                 ret = PTR_ERR(hdmi->isfr_clk);
2895                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2896                 return ret;
2897         }
2898
2899         ret = clk_prepare_enable(hdmi->isfr_clk);
2900         if (ret) {
2901                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2902                 return ret;
2903         }
2904
2905         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2906         if (IS_ERR(hdmi->iahb_clk)) {
2907                 ret = PTR_ERR(hdmi->iahb_clk);
2908                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2909                 goto err_isfr;
2910         }
2911
2912         ret = clk_prepare_enable(hdmi->iahb_clk);
2913         if (ret) {
2914                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2915                 goto err_isfr;
2916         }
2917
2918         /* Product and revision IDs */
2919         hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8)
2920                       | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0);
2921         prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0);
2922         prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1);
2923
2924         if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX ||
2925             (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) {
2926                 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n",
2927                         hdmi->version, prod_id0, prod_id1);
2928                 ret = -ENODEV;
2929                 goto err_iahb;
2930         }
2931
2932         ret = dw_hdmi_detect_phy(hdmi);
2933         if (ret < 0)
2934                 goto err_iahb;
2935
2936         dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n",
2937                  hdmi->version >> 12, hdmi->version & 0xfff,
2938                  prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without",
2939                  hdmi->phy.name);
2940
2941         init_hpd_work(hdmi);
2942         initialize_hdmi_ih_mutes(hdmi);
2943
2944         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2945                                         dw_hdmi_irq, IRQF_SHARED,
2946                                         dev_name(dev), hdmi);
2947         if (ret)
2948                 goto err_iahb;
2949
2950         /*
2951          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2952          * N and cts values before enabling phy
2953          */
2954         hdmi_init_clk_regenerator(hdmi);
2955
2956         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2957                     HDMI_PHY_I2CM_INT_ADDR);
2958
2959         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2960                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2961                     HDMI_PHY_I2CM_CTLINT_ADDR);
2962
2963         /* Re-init HPD polarity */
2964         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
2965
2966         /* Unmask HPD, clear transitory interrupts, then unmute */
2967         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
2968
2969         ret = dw_hdmi_register(drm, hdmi);
2970         if (ret)
2971                 goto err_iahb;
2972
2973 #ifdef CONFIG_SWITCH
2974         hdmi->switchdev.name = "hdmi";
2975         switch_dev_register(&hdmi->switchdev);
2976 #endif
2977
2978         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2979                     HDMI_IH_MUTE_PHY_STAT0);
2980
2981         /* Unmute I2CM interrupts and reset HDMI DDC I2C master controller */
2982         if (hdmi->i2c)
2983                 dw_hdmi_i2c_init(hdmi);
2984
2985         memset(&pdevinfo, 0, sizeof(pdevinfo));
2986         pdevinfo.parent = dev;
2987         pdevinfo.id = PLATFORM_DEVID_AUTO;
2988
2989         config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2990         config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID);
2991
2992         if (config3 & HDMI_CONFIG3_AHBAUDDMA) {
2993                 struct dw_hdmi_audio_data audio;
2994
2995                 audio.phys = iores->start;
2996                 audio.base = hdmi->regs;
2997                 audio.irq = irq;
2998                 audio.hdmi = hdmi;
2999                 audio.eld = hdmi->connector.eld;
3000
3001                 pdevinfo.name = "dw-hdmi-ahb-audio";
3002                 pdevinfo.data = &audio;
3003                 pdevinfo.size_data = sizeof(audio);
3004                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
3005                 hdmi->audio = platform_device_register_full(&pdevinfo);
3006         } else if (config0 & HDMI_CONFIG0_I2S) {
3007                 struct dw_hdmi_i2s_audio_data audio;
3008
3009                 audio.hdmi      = hdmi;
3010                 audio.write     = hdmi_writeb;
3011                 audio.read      = hdmi_readb;
3012                 audio.mod       = hdmi_modb;
3013
3014                 pdevinfo.name = "dw-hdmi-i2s-audio";
3015                 pdevinfo.data = &audio;
3016                 pdevinfo.size_data = sizeof(audio);
3017                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
3018                 hdmi->audio = platform_device_register_full(&pdevinfo);
3019         }
3020
3021         dev_set_drvdata(dev, hdmi);
3022
3023         dw_hdmi_register_debugfs(dev, hdmi);
3024         dw_hdmi_register_hdcp(dev, hdmi, val);
3025
3026         return 0;
3027
3028 err_iahb:
3029         if (hdmi->i2c)
3030                 i2c_del_adapter(&hdmi->i2c->adap);
3031
3032         clk_disable_unprepare(hdmi->iahb_clk);
3033 err_isfr:
3034         clk_disable_unprepare(hdmi->isfr_clk);
3035
3036         return ret;
3037 }
3038 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
3039
3040 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
3041 {
3042         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
3043
3044         if (hdmi->irq)
3045                 disable_irq(hdmi->irq);
3046
3047         cancel_delayed_work(&hdmi->work);
3048         flush_workqueue(hdmi->workqueue);
3049         destroy_workqueue(hdmi->workqueue);
3050
3051         if (hdmi->audio && !IS_ERR(hdmi->audio))
3052                 platform_device_unregister(hdmi->audio);
3053
3054         if (hdmi->hdcp_dev && !IS_ERR(hdmi->hdcp_dev))
3055                 platform_device_unregister(hdmi->hdcp_dev);
3056
3057         /* Disable all interrupts */
3058         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
3059
3060 #ifdef CONFIG_SWITCH
3061         switch_dev_unregister(&hdmi->switchdev);
3062 #endif
3063         hdmi->connector.funcs->destroy(&hdmi->connector);
3064         hdmi->encoder->funcs->destroy(hdmi->encoder);
3065
3066         clk_disable_unprepare(hdmi->iahb_clk);
3067         clk_disable_unprepare(hdmi->isfr_clk);
3068
3069         if (hdmi->i2c)
3070                 i2c_del_adapter(&hdmi->i2c->adap);
3071         else
3072                 i2c_put_adapter(hdmi->ddc);
3073 }
3074 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
3075
3076 static void dw_hdmi_reg_initial(struct dw_hdmi *hdmi)
3077 {
3078         if (hdmi_readb(hdmi, HDMI_IH_MUTE)) {
3079                 initialize_hdmi_ih_mutes(hdmi);
3080                 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
3081                             HDMI_PHY_I2CM_INT_ADDR);
3082
3083                 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
3084                             HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
3085                             HDMI_PHY_I2CM_CTLINT_ADDR);
3086
3087                 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE,
3088                             HDMI_PHY_POL0);
3089                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
3090                 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD |
3091                             HDMI_IH_PHY_STAT0_RX_SENSE),
3092                             HDMI_IH_MUTE_PHY_STAT0);
3093         }
3094 }
3095
3096 void dw_hdmi_suspend(struct device *dev)
3097 {
3098         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
3099
3100         mutex_lock(&hdmi->mutex);
3101         if (hdmi->irq)
3102                 disable_irq(hdmi->irq);
3103         mutex_unlock(&hdmi->mutex);
3104 }
3105 EXPORT_SYMBOL_GPL(dw_hdmi_suspend);
3106
3107 void dw_hdmi_resume(struct device *dev)
3108 {
3109         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
3110
3111         mutex_lock(&hdmi->mutex);
3112         dw_hdmi_reg_initial(hdmi);
3113         if (hdmi->i2c)
3114                 dw_hdmi_i2c_init(hdmi);
3115         if (hdmi->irq)
3116                 enable_irq(hdmi->irq);
3117         mutex_unlock(&hdmi->mutex);
3118 }
3119 EXPORT_SYMBOL_GPL(dw_hdmi_resume);
3120
3121 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
3122 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
3123 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
3124 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
3125 MODULE_DESCRIPTION("DW HDMI transmitter driver");
3126 MODULE_LICENSE("GPL");
3127 MODULE_ALIAS("platform:dw-hdmi");