2 * DesignWare High-Definition Multimedia Interface (HDMI) driver
4 * Copyright (C) 2013-2015 Mentor Graphics Inc.
5 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
6 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * Designware High-Definition Multimedia Interface (HDMI) driver
16 #include <linux/module.h>
17 #include <linux/irq.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/hdmi.h>
22 #include <linux/mutex.h>
23 #include <linux/of_device.h>
24 #include <linux/spinlock.h>
26 #include <drm/drm_of.h>
28 #include <drm/drm_atomic_helper.h>
29 #include <drm/drm_crtc_helper.h>
30 #include <drm/drm_edid.h>
31 #include <drm/drm_encoder_slave.h>
32 #include <drm/drm_scdc_helper.h>
33 #include <drm/bridge/dw_hdmi.h>
35 #include <linux/switch.h>
39 #include "dw-hdmi-audio.h"
41 #define HDMI_EDID_LEN 512
42 #define DDC_SEGMENT_ADDR 0x30
46 #define YCBCR422_16BITS 2
47 #define YCBCR422_8BITS 3
66 * Unless otherwise noted, entries in this table are 100% optimization.
67 * Values can be obtained from hdmi_compute_n() but that function is
68 * slow so we pre-compute values we expect to see.
70 * All 32k and 48k values are expected to be the same (due to the way
71 * the math works) for any rate that's an exact kHz.
73 static const struct dw_hdmi_audio_tmds_n common_tmds_n_table[] = {
74 { .tmds = 25175000, .n_32k = 4096, .n_44k1 = 12854, .n_48k = 6144, },
75 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 5656, .n_48k = 6144, },
76 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
77 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, },
78 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, },
79 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
80 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
81 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
82 { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
83 { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
84 { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
85 { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
86 { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
87 { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
88 { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, },
89 { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
90 { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, },
91 { .tmds = 73250000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
92 { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
93 { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, },
94 { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
95 { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
96 { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
97 { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
98 { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
99 { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
100 { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
101 { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
102 { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
103 { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
104 { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, },
105 { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
106 { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
107 { .tmds = 146250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
108 { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
109 { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
110 { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
112 /* For 297 MHz+ HDMI spec have some other rule for setting N */
113 { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, },
114 { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240, },
117 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, },
121 static const u16 csc_coeff_default[3][4] = {
122 { 0x2000, 0x0000, 0x0000, 0x0000 },
123 { 0x0000, 0x2000, 0x0000, 0x0000 },
124 { 0x0000, 0x0000, 0x2000, 0x0000 }
127 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
128 { 0x2000, 0x6926, 0x74fd, 0x010e },
129 { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
130 { 0x2000, 0x0000, 0x38b4, 0x7e3b }
133 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
134 { 0x2000, 0x7106, 0x7a02, 0x00a7 },
135 { 0x2000, 0x3264, 0x0000, 0x7e6d },
136 { 0x2000, 0x0000, 0x3b61, 0x7e25 }
139 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
140 { 0x2591, 0x1322, 0x074b, 0x0000 },
141 { 0x6535, 0x2000, 0x7acc, 0x0200 },
142 { 0x6acd, 0x7534, 0x2000, 0x0200 }
145 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
146 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
147 { 0x62f0, 0x2000, 0x7d11, 0x0200 },
148 { 0x6756, 0x78ab, 0x2000, 0x0200 }
152 bool mdataenablepolarity;
154 unsigned int mpixelclock;
155 unsigned int mpixelrepetitioninput;
156 unsigned int mpixelrepetitionoutput;
159 struct hdmi_data_info {
160 unsigned int enc_in_format;
161 unsigned int enc_out_format;
162 unsigned int enc_color_depth;
163 unsigned int colorimetry;
164 unsigned int pix_repet_factor;
165 unsigned int hdcp_enable;
166 struct hdmi_vmode video_mode;
170 struct i2c_adapter adap;
173 struct completion cmp;
180 unsigned int scl_high_ns;
181 unsigned int scl_low_ns;
185 struct drm_connector connector;
186 struct drm_encoder *encoder;
187 struct drm_bridge *bridge;
189 struct platform_device *audio;
190 enum dw_hdmi_devtype dev_type;
192 struct clk *isfr_clk;
193 struct clk *iahb_clk;
194 struct dw_hdmi_i2c *i2c;
196 struct hdmi_data_info hdmi_data;
197 const struct dw_hdmi_plat_data *plat_data;
201 u8 edid[HDMI_EDID_LEN];
205 struct drm_display_mode previous_mode;
207 struct i2c_adapter *ddc;
212 struct mutex mutex; /* for state below and previous_mode */
213 enum drm_connector_force force; /* mutex-protected force state */
214 bool disabled; /* DRM has disabled our bridge */
215 bool bridge_is_on; /* indicates the bridge is on */
216 bool rxsense; /* rxsense state */
217 u8 phy_mask; /* desired phy int mask settings */
219 spinlock_t audio_lock;
220 struct mutex audio_mutex;
221 unsigned int sample_rate;
222 unsigned int audio_cts;
223 unsigned int audio_n;
227 struct switch_dev switchdev;
231 void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
232 u8 (*read)(struct dw_hdmi *hdmi, int offset);
235 #define HDMI_IH_PHY_STAT0_RX_SENSE \
236 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
237 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
239 #define HDMI_PHY_RX_SENSE \
240 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
241 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
243 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
245 writel(val, hdmi->regs + (offset << 2));
248 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
250 return readl(hdmi->regs + (offset << 2));
253 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
255 writeb(val, hdmi->regs + offset);
258 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
260 return readb(hdmi->regs + offset);
263 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
265 hdmi->write(hdmi, val, offset);
268 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
270 return hdmi->read(hdmi, offset);
273 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
275 u8 val = hdmi_readb(hdmi, reg) & ~mask;
278 hdmi_writeb(hdmi, val, reg);
281 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
284 hdmi_modb(hdmi, data << shift, mask, reg);
287 static void dw_hdmi_i2c_set_divs(struct dw_hdmi *hdmi)
289 unsigned long clk_rate_khz;
290 unsigned long low_ns, high_ns;
291 unsigned long div_low, div_high;
294 if (hdmi->i2c->scl_high_ns < 4000)
297 high_ns = hdmi->i2c->scl_high_ns;
299 if (hdmi->i2c->scl_low_ns < 4700)
302 low_ns = hdmi->i2c->scl_low_ns;
304 /* Adjust to avoid overflow */
305 clk_rate_khz = DIV_ROUND_UP(clk_get_rate(hdmi->isfr_clk), 1000);
307 div_low = (clk_rate_khz * low_ns) / 1000000;
308 if ((clk_rate_khz * low_ns) % 1000000)
311 div_high = (clk_rate_khz * high_ns) / 1000000;
312 if ((clk_rate_khz * high_ns) % 1000000)
315 /* Maximum divider supported by hw is 0xffff */
316 if (div_low > 0xffff)
319 if (div_high > 0xffff)
322 hdmi_writeb(hdmi, div_high & 0xff, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
323 hdmi_writeb(hdmi, (div_high >> 8) & 0xff,
324 HDMI_I2CM_SS_SCL_HCNT_1_ADDR);
325 hdmi_writeb(hdmi, div_low & 0xff, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
326 hdmi_writeb(hdmi, (div_low >> 8) & 0xff,
327 HDMI_I2CM_SS_SCL_LCNT_1_ADDR);
330 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi)
333 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
335 /* Set Standard Mode speed */
336 hdmi_modb(hdmi, HDMI_I2CM_DIV_STD_MODE,
337 HDMI_I2CM_DIV_FAST_STD_MODE, HDMI_I2CM_DIV);
339 /* Set done, not acknowledged and arbitration interrupt polarities */
340 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT);
341 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL,
344 /* Clear DONE and ERROR interrupts */
345 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
348 /* Mute DONE and ERROR interrupts */
349 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
350 HDMI_IH_MUTE_I2CM_STAT0);
352 dw_hdmi_i2c_set_divs(hdmi);
355 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi,
356 unsigned char *buf, unsigned int length)
358 struct dw_hdmi_i2c *i2c = hdmi->i2c;
361 if (!i2c->is_regaddr) {
362 dev_dbg(hdmi->dev, "set read register address to 0\n");
363 i2c->slave_reg = 0x00;
364 i2c->is_regaddr = true;
368 reinit_completion(&i2c->cmp);
370 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
372 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
373 HDMI_I2CM_OPERATION);
375 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
376 HDMI_I2CM_OPERATION);
378 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
382 /* Check for error condition on the bus */
383 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
386 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
388 i2c->is_segment = false;
393 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi,
394 unsigned char *buf, unsigned int length)
396 struct dw_hdmi_i2c *i2c = hdmi->i2c;
399 if (!i2c->is_regaddr) {
400 /* Use the first write byte as register address */
401 i2c->slave_reg = buf[0];
404 i2c->is_regaddr = true;
408 reinit_completion(&i2c->cmp);
410 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO);
411 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
412 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE,
413 HDMI_I2CM_OPERATION);
415 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
419 /* Check for error condition on the bus */
420 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR)
427 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap,
428 struct i2c_msg *msgs, int num)
430 struct dw_hdmi *hdmi = i2c_get_adapdata(adap);
431 struct dw_hdmi_i2c *i2c = hdmi->i2c;
432 u8 addr = msgs[0].addr;
435 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr);
437 for (i = 0; i < num; i++) {
438 if (msgs[i].len == 0) {
440 "unsupported transfer %d/%d, no data\n",
446 mutex_lock(&i2c->lock);
448 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
450 /* Set slave device address taken from the first I2C message */
451 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE);
453 /* Set slave device register address on transfer */
454 i2c->is_regaddr = false;
456 /* Set segment pointer for I2C extended read mode operation */
457 i2c->is_segment = false;
459 for (i = 0; i < num; i++) {
460 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n",
461 i + 1, num, msgs[i].len, msgs[i].flags);
462 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
463 i2c->is_segment = true;
464 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR);
465 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR);
467 if (msgs[i].flags & I2C_M_RD)
468 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf,
471 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf,
481 /* Mute DONE and ERROR interrupts */
482 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE,
483 HDMI_IH_MUTE_I2CM_STAT0);
485 mutex_unlock(&i2c->lock);
490 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter)
492 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
495 static const struct i2c_algorithm dw_hdmi_algorithm = {
496 .master_xfer = dw_hdmi_i2c_xfer,
497 .functionality = dw_hdmi_i2c_func,
500 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi)
502 struct i2c_adapter *adap;
503 struct dw_hdmi_i2c *i2c;
506 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
508 return ERR_PTR(-ENOMEM);
510 mutex_init(&i2c->lock);
511 init_completion(&i2c->cmp);
514 adap->class = I2C_CLASS_DDC;
515 adap->owner = THIS_MODULE;
516 adap->dev.parent = hdmi->dev;
517 adap->dev.of_node = hdmi->dev->of_node;
518 adap->algo = &dw_hdmi_algorithm;
519 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name));
520 i2c_set_adapdata(adap, hdmi);
522 ret = i2c_add_adapter(adap);
524 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
525 devm_kfree(hdmi->dev, i2c);
531 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
536 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
539 /* Must be set/cleared first */
540 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
542 /* nshift factor = 0 */
543 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
545 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
546 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
547 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
548 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
550 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
551 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
552 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
555 static int hdmi_match_tmds_n_table(struct dw_hdmi *hdmi,
556 unsigned long pixel_clk,
559 const struct dw_hdmi_plat_data *plat_data = hdmi->plat_data;
560 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
563 if (plat_data->tmds_n_table) {
564 for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
565 if (pixel_clk == plat_data->tmds_n_table[i].tmds) {
566 tmds_n = &plat_data->tmds_n_table[i];
572 if (tmds_n == NULL) {
573 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
574 if (pixel_clk == common_tmds_n_table[i].tmds) {
575 tmds_n = &common_tmds_n_table[i];
586 return tmds_n->n_32k;
590 return (freq / 44100) * tmds_n->n_44k1;
594 return (freq / 48000) * tmds_n->n_48k;
600 static u64 hdmi_audio_math_diff(unsigned int freq, unsigned int n,
601 unsigned int pixel_clk)
606 final = (u64)pixel_clk * n;
609 do_div(cts, 128 * freq);
611 diff = final - (u64)cts * (128 * freq);
616 static unsigned int hdmi_compute_n(struct dw_hdmi *hdmi,
617 unsigned long pixel_clk,
620 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
621 unsigned int max_n = (128 * freq) / 300;
622 unsigned int ideal_n = (128 * freq) / 1000;
623 unsigned int best_n_distance = ideal_n;
624 unsigned int best_n = 0;
625 u64 best_diff = U64_MAX;
628 /* If the ideal N could satisfy the audio math, then just take it */
629 if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
632 for (n = min_n; n <= max_n; n++) {
633 u64 diff = hdmi_audio_math_diff(freq, n, pixel_clk);
635 if (diff < best_diff || (diff == best_diff &&
636 abs(n - ideal_n) < best_n_distance)) {
639 best_n_distance = abs(best_n - ideal_n);
643 * The best N already satisfy the audio math, and also be
644 * the closest value to ideal N, so just cut the loop.
646 if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance))
653 static unsigned int hdmi_find_n(struct dw_hdmi *hdmi, unsigned long pixel_clk,
654 unsigned long sample_rate)
658 n = hdmi_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
662 dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n",
665 return hdmi_compute_n(hdmi, pixel_clk, sample_rate);
668 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
669 unsigned long pixel_clk, unsigned int sample_rate)
671 unsigned long ftdms = pixel_clk;
675 n = hdmi_find_n(hdmi, pixel_clk, sample_rate);
678 * Compute the CTS value from the N value. Note that CTS and N
679 * can be up to 20 bits in total, so we need 64-bit math. Also
680 * note that our TDMS clock is not fully accurate; it is accurate
681 * to kHz. This can introduce an unnecessary remainder in the
682 * calculation below, so we don't try to warn about that.
684 tmp = (u64)ftdms * n;
685 do_div(tmp, 128 * sample_rate);
688 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
689 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
692 spin_lock_irq(&hdmi->audio_lock);
694 hdmi->audio_cts = cts;
695 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
696 spin_unlock_irq(&hdmi->audio_lock);
699 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
701 mutex_lock(&hdmi->audio_mutex);
702 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
703 mutex_unlock(&hdmi->audio_mutex);
706 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
708 mutex_lock(&hdmi->audio_mutex);
709 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
711 mutex_unlock(&hdmi->audio_mutex);
714 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
716 mutex_lock(&hdmi->audio_mutex);
717 hdmi->sample_rate = rate;
718 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
720 mutex_unlock(&hdmi->audio_mutex);
722 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
724 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
728 spin_lock_irqsave(&hdmi->audio_lock, flags);
729 hdmi->audio_enable = true;
730 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
731 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
733 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
735 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
739 spin_lock_irqsave(&hdmi->audio_lock, flags);
740 hdmi->audio_enable = false;
741 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
742 spin_unlock_irqrestore(&hdmi->audio_lock, flags);
744 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
747 * this submodule is responsible for the video data synchronization.
748 * for example, for RGB 4:4:4 input, the data map is defined as
749 * pin{47~40} <==> R[7:0]
750 * pin{31~24} <==> G[7:0]
751 * pin{15~8} <==> B[7:0]
753 static void hdmi_video_sample(struct dw_hdmi *hdmi)
755 int color_format = 0;
758 if (hdmi->hdmi_data.enc_in_format == RGB) {
759 if (hdmi->hdmi_data.enc_color_depth == 8)
761 else if (hdmi->hdmi_data.enc_color_depth == 10)
763 else if (hdmi->hdmi_data.enc_color_depth == 12)
765 else if (hdmi->hdmi_data.enc_color_depth == 16)
769 } else if (hdmi->hdmi_data.enc_in_format == YCBCR444 ||
770 hdmi->hdmi_data.enc_in_format == YCBCR420) {
771 if (hdmi->hdmi_data.enc_color_depth == 8)
773 else if (hdmi->hdmi_data.enc_color_depth == 10)
775 else if (hdmi->hdmi_data.enc_color_depth == 12)
777 else if (hdmi->hdmi_data.enc_color_depth == 16)
781 } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
782 if (hdmi->hdmi_data.enc_color_depth == 8)
784 else if (hdmi->hdmi_data.enc_color_depth == 10)
786 else if (hdmi->hdmi_data.enc_color_depth == 12)
792 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
793 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
794 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
795 hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
797 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
798 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
799 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
800 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
801 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
802 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
803 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
804 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
805 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
806 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
807 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
810 static int is_color_space_conversion(struct dw_hdmi *hdmi)
812 return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
815 static int is_color_space_decimation(struct dw_hdmi *hdmi)
817 if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
819 if (hdmi->hdmi_data.enc_in_format == RGB ||
820 hdmi->hdmi_data.enc_in_format == YCBCR444)
825 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
827 if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
829 if (hdmi->hdmi_data.enc_out_format == RGB ||
830 hdmi->hdmi_data.enc_out_format == YCBCR444)
835 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
837 const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
841 if (is_color_space_conversion(hdmi)) {
842 if (hdmi->hdmi_data.enc_out_format == RGB) {
843 if (hdmi->hdmi_data.colorimetry ==
844 HDMI_COLORIMETRY_ITU_601)
845 csc_coeff = &csc_coeff_rgb_out_eitu601;
847 csc_coeff = &csc_coeff_rgb_out_eitu709;
848 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
849 if (hdmi->hdmi_data.colorimetry ==
850 HDMI_COLORIMETRY_ITU_601)
851 csc_coeff = &csc_coeff_rgb_in_eitu601;
853 csc_coeff = &csc_coeff_rgb_in_eitu709;
858 /* The CSC registers are sequential, alternating MSB then LSB */
859 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
860 u16 coeff_a = (*csc_coeff)[0][i];
861 u16 coeff_b = (*csc_coeff)[1][i];
862 u16 coeff_c = (*csc_coeff)[2][i];
864 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
865 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
866 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
867 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
868 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
869 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
872 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
876 static void hdmi_video_csc(struct dw_hdmi *hdmi)
879 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
882 /* YCC422 interpolation to 444 mode */
883 if (is_color_space_interpolation(hdmi))
884 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
885 else if (is_color_space_decimation(hdmi))
886 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
888 if (hdmi->hdmi_data.enc_color_depth == 8)
889 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
890 else if (hdmi->hdmi_data.enc_color_depth == 10)
891 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
892 else if (hdmi->hdmi_data.enc_color_depth == 12)
893 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
894 else if (hdmi->hdmi_data.enc_color_depth == 16)
895 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
899 /* Configure the CSC registers */
900 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
901 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
904 dw_hdmi_update_csc_coeffs(hdmi);
908 * HDMI video packetizer is used to packetize the data.
909 * for example, if input is YCC422 mode or repeater is used,
910 * data should be repacked this module can be bypassed.
912 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
914 unsigned int color_depth = 0;
915 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
916 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
917 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
920 if (hdmi_data->enc_out_format == RGB ||
921 hdmi_data->enc_out_format == YCBCR444 ||
922 hdmi_data->enc_out_format == YCBCR420) {
923 if (!hdmi_data->enc_color_depth) {
924 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
925 } else if (hdmi_data->enc_color_depth == 8) {
927 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
928 } else if (hdmi_data->enc_color_depth == 10) {
930 } else if (hdmi_data->enc_color_depth == 12) {
932 } else if (hdmi_data->enc_color_depth == 16) {
937 } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
938 if (!hdmi_data->enc_color_depth ||
939 hdmi_data->enc_color_depth == 8)
940 remap_size = HDMI_VP_REMAP_YCC422_16bit;
941 else if (hdmi_data->enc_color_depth == 10)
942 remap_size = HDMI_VP_REMAP_YCC422_20bit;
943 else if (hdmi_data->enc_color_depth == 12)
944 remap_size = HDMI_VP_REMAP_YCC422_24bit;
947 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
952 /* set the packetizer registers */
953 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
954 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
955 ((hdmi_data->pix_repet_factor <<
956 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
957 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
958 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
960 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
961 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
963 /* Data from pixel repeater block */
964 if (hdmi_data->pix_repet_factor > 0) {
965 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
966 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
967 } else { /* data from packetizer block */
968 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
969 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
972 hdmi_modb(hdmi, vp_conf,
973 HDMI_VP_CONF_PR_EN_MASK |
974 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
976 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
977 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
979 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
981 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
982 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
983 HDMI_VP_CONF_PP_EN_ENABLE |
984 HDMI_VP_CONF_YCC422_EN_DISABLE;
985 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
986 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
987 HDMI_VP_CONF_PP_EN_DISABLE |
988 HDMI_VP_CONF_YCC422_EN_ENABLE;
989 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
990 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
991 HDMI_VP_CONF_PP_EN_DISABLE |
992 HDMI_VP_CONF_YCC422_EN_DISABLE;
997 hdmi_modb(hdmi, vp_conf,
998 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
999 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
1001 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
1002 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
1003 HDMI_VP_STUFF_PP_STUFFING_MASK |
1004 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
1006 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
1010 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
1013 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
1014 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
1017 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
1020 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
1021 HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
1024 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
1027 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
1028 HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
1031 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
1034 hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
1037 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
1040 hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
1043 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
1047 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
1052 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
1057 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1060 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1061 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1062 hdmi_writeb(hdmi, (unsigned char)(data >> 8),
1063 HDMI_PHY_I2CM_DATAO_1_ADDR);
1064 hdmi_writeb(hdmi, (unsigned char)(data >> 0),
1065 HDMI_PHY_I2CM_DATAO_0_ADDR);
1066 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
1067 HDMI_PHY_I2CM_OPERATION_ADDR);
1068 hdmi_phy_wait_i2c_done(hdmi, 1000);
1071 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
1074 __hdmi_phy_i2c_write(hdmi, data, addr);
1078 static int hdmi_phy_i2c_read(struct dw_hdmi *hdmi, unsigned char addr)
1082 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
1083 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
1084 hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_1_ADDR);
1085 hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_0_ADDR);
1086 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_READ,
1087 HDMI_PHY_I2CM_OPERATION_ADDR);
1088 hdmi_phy_wait_i2c_done(hdmi, 1000);
1089 val = hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_1_ADDR);
1090 val = (val & 0xff) << 8;
1091 val += hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_0_ADDR) & 0xff;
1095 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
1097 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
1098 HDMI_PHY_CONF0_PDZ_OFFSET,
1099 HDMI_PHY_CONF0_PDZ_MASK);
1102 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
1104 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1105 HDMI_PHY_CONF0_ENTMDS_OFFSET,
1106 HDMI_PHY_CONF0_ENTMDS_MASK);
1109 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
1111 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1112 HDMI_PHY_CONF0_SPARECTRL_OFFSET,
1113 HDMI_PHY_CONF0_SPARECTRL_MASK);
1116 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
1118 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1119 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
1120 HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
1123 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
1125 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1126 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
1127 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
1130 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
1132 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1133 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
1134 HDMI_PHY_CONF0_SELDATAENPOL_MASK);
1137 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
1139 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
1140 HDMI_PHY_CONF0_SELDIPIF_OFFSET,
1141 HDMI_PHY_CONF0_SELDIPIF_MASK);
1144 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
1145 unsigned char res, int cscon)
1148 u8 val, msec, tmds_cfg;
1149 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
1150 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
1151 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
1152 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
1158 case 0: /* color resolution 0 is 8 bit colour depth */
1160 res_idx = DW_HDMI_RES_8;
1163 res_idx = DW_HDMI_RES_10;
1166 res_idx = DW_HDMI_RES_12;
1172 /* PLL/MPLL Cfg - always match on final entry */
1173 for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
1174 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1175 mpll_config->mpixelclock)
1178 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
1179 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1180 curr_ctrl->mpixelclock)
1183 for (; phy_config->mpixelclock != ~0UL; phy_config++)
1184 if (hdmi->hdmi_data.video_mode.mpixelclock <=
1185 phy_config->mpixelclock)
1188 if (mpll_config->mpixelclock == ~0UL ||
1189 curr_ctrl->mpixelclock == ~0UL ||
1190 phy_config->mpixelclock == ~0UL) {
1191 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
1192 hdmi->hdmi_data.video_mode.mpixelclock);
1196 /* Enable csc path */
1198 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
1200 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
1202 hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
1204 /* gen2 tx power off */
1205 dw_hdmi_phy_gen2_txpwron(hdmi, 0);
1208 dw_hdmi_phy_gen2_pddq(hdmi, 1);
1210 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */
1211 if (hdmi->connector.scdc_present) {
1212 drm_scdc_readb(hdmi->ddc, SCDC_TMDS_CONFIG, &tmds_cfg);
1213 if (mpll_config->mpixelclock > 340000000)
1217 drm_scdc_writeb(hdmi->ddc, SCDC_TMDS_CONFIG, tmds_cfg);
1221 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
1222 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
1224 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
1226 hdmi_phy_test_clear(hdmi, 1);
1227 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
1228 HDMI_PHY_I2CM_SLAVE_ADDR);
1229 hdmi_phy_test_clear(hdmi, 0);
1231 * RK3399 mpll clock source is vpll, also is vop clock source.
1232 * vpll rate is twice of mpixelclock in YCBCR420 mode, we need
1233 * to enable mpll pre-divider.
1235 if (hdmi->hdmi_data.enc_in_format == YCBCR420 &&
1236 hdmi->dev_type == RK3399_HDMI)
1237 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce | 4,
1240 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
1241 hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
1244 hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
1246 hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); /* PLLPHBYCTRL */
1247 hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
1249 hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19); /* TXTERM */
1250 hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
1251 hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
1253 /* REMOVE CLK TERM */
1254 hdmi_phy_i2c_write(hdmi, 0x8000, 0x05); /* CKCALCTRL */
1256 dw_hdmi_phy_enable_powerdown(hdmi, false);
1258 /* toggle TMDS disable */
1259 dw_hdmi_phy_enable_tmds(hdmi, 0);
1261 /* Wait for resuming transmission of TMDS clock and data */
1262 if (mpll_config->mpixelclock > 340000000)
1265 /* toggle TMDS enable */
1266 dw_hdmi_phy_enable_tmds(hdmi, 1);
1268 /* gen2 tx power on */
1269 dw_hdmi_phy_gen2_txpwron(hdmi, 1);
1270 dw_hdmi_phy_gen2_pddq(hdmi, 0);
1272 if (is_rockchip(hdmi->dev_type))
1273 dw_hdmi_phy_enable_spare(hdmi, 1);
1275 /* Wait for PHY PLL lock */
1278 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
1283 dev_err(hdmi->dev, "PHY PLL not locked\n");
1294 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
1299 /*check csc whether needed activated in HDMI mode */
1300 cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
1302 /* HDMI Phy spec says to do the phy initialization sequence twice */
1303 for (i = 0; i < 2; i++) {
1304 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
1305 dw_hdmi_phy_sel_interface_control(hdmi, 0);
1306 dw_hdmi_phy_enable_tmds(hdmi, 0);
1307 dw_hdmi_phy_enable_powerdown(hdmi, true);
1310 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
1315 hdmi->phy_enabled = true;
1319 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
1323 if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
1324 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
1326 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
1328 /* disable rx detect */
1329 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
1330 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
1332 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
1334 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
1335 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
1338 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1340 struct hdmi_avi_infoframe frame;
1342 bool is_hdmi2 = false;
1344 if ((mode->flags & DRM_MODE_FLAG_420_MASK) ||
1345 hdmi->connector.scdc_present)
1347 /* Initialise info frame from DRM mode */
1348 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, is_hdmi2);
1350 if (hdmi->hdmi_data.enc_out_format == YCBCR444)
1351 frame.colorspace = HDMI_COLORSPACE_YUV444;
1352 else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
1353 frame.colorspace = HDMI_COLORSPACE_YUV422;
1354 else if (hdmi->hdmi_data.enc_out_format == YCBCR420)
1355 frame.colorspace = HDMI_COLORSPACE_YUV420;
1357 frame.colorspace = HDMI_COLORSPACE_RGB;
1359 /* Set up colorimetry */
1360 if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
1361 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
1362 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
1363 frame.extended_colorimetry =
1364 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1365 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
1366 frame.extended_colorimetry =
1367 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
1368 } else if (hdmi->hdmi_data.enc_out_format != RGB) {
1369 frame.colorimetry = hdmi->hdmi_data.colorimetry;
1370 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1371 } else { /* Carries no data */
1372 frame.colorimetry = HDMI_COLORIMETRY_NONE;
1373 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
1376 frame.scan_mode = HDMI_SCAN_MODE_NONE;
1379 * The Designware IP uses a different byte format from standard
1380 * AVI info frames, though generally the bits are in the correct
1385 * AVI data byte 1 differences: Colorspace in bits 0,1,7 rather than
1386 * 5,6,7, active aspect present in bit 6 rather than 4.
1388 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 0x3);
1389 if (frame.active_aspect & 15)
1390 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1391 if (frame.top_bar || frame.bottom_bar)
1392 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1393 if (frame.left_bar || frame.right_bar)
1394 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1395 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1397 /* AVI data byte 2 differences: none */
1398 val = ((frame.colorimetry & 0x3) << 6) |
1399 ((frame.picture_aspect & 0x3) << 4) |
1400 (frame.active_aspect & 0xf);
1401 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1403 /* AVI data byte 3 differences: none */
1404 val = ((frame.extended_colorimetry & 0x7) << 4) |
1405 ((frame.quantization_range & 0x3) << 2) |
1408 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1409 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1411 /* AVI data byte 4 differences: none */
1412 val = frame.video_code & 0x7f;
1413 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1415 /* AVI Data Byte 5- set up input and output pixel repetition */
1416 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1417 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1418 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1419 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1420 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1421 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1422 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1425 * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1426 * ycc range in bits 2,3 rather than 6,7
1428 val = ((frame.ycc_quantization_range & 0x3) << 2) |
1429 (frame.content_type & 0x3);
1430 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1432 /* AVI Data Bytes 6-13 */
1433 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1434 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1435 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1436 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1437 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1438 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1439 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1440 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1443 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi,
1444 struct drm_display_mode *mode)
1446 struct hdmi_vendor_infoframe frame;
1450 /* Disable HDMI vendor specific infoframe send */
1451 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1452 HDMI_FC_DATAUTO0_VSD_MASK);
1454 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode);
1457 * Going into that statement does not means vendor infoframe
1458 * fails. It just informed us that vendor infoframe is not
1459 * needed for the selected mode. Only 4k or stereoscopic 3D
1460 * mode requires vendor infoframe. So just simply return.
1464 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1466 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1471 /* Set the length of HDMI vendor specific InfoFrame payload */
1472 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE);
1474 /* Set 24bit IEEE Registration Identifier */
1475 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0);
1476 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1);
1477 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2);
1479 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */
1480 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0);
1481 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1);
1483 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF)
1484 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2);
1486 /* Packet frame interpolation */
1487 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1);
1489 /* Auto packets per frame and line spacing */
1490 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2);
1492 /* Configures the Frame Composer On RDRB mode */
1493 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET,
1494 HDMI_FC_DATAUTO0_VSD_MASK);
1497 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1498 const struct drm_display_mode *mode)
1501 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1502 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1503 unsigned int hdisplay, vdisplay;
1505 vmode->mpixelclock = mode->crtc_clock * 1000;
1506 if (mode->flags & DRM_MODE_FLAG_420_MASK)
1507 vmode->mpixelclock /= 2;
1508 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1510 /* Set up HDMI_FC_INVIDCONF
1511 * fc_invidconf.HDCP_keepout must be set (1'b1)
1512 * when activate the scrambler feature.
1514 inv_val = (hdmi->hdmi_data.hdcp_enable ||
1515 vmode->mpixelclock > 340000000 ||
1516 hdmi->connector.lte_340mcsc_scramble ?
1517 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1518 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1520 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1521 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1522 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1524 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1525 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1526 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1528 inv_val |= (vmode->mdataenablepolarity ?
1529 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1530 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1532 if (hdmi->vic == 39)
1533 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1535 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1536 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1537 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1539 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1540 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1541 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1543 inv_val |= hdmi->sink_is_hdmi ?
1544 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1545 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1547 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1549 hdisplay = mode->hdisplay;
1550 hblank = mode->htotal - mode->hdisplay;
1551 h_de_hs = mode->hsync_start - mode->hdisplay;
1552 hsync_len = mode->hsync_end - mode->hsync_start;
1555 * When we're setting a YCbCr420 mode, we need
1556 * to adjust the horizontal timing to suit.
1558 if (mode->flags & DRM_MODE_FLAG_420_MASK) {
1565 vdisplay = mode->vdisplay;
1566 vblank = mode->vtotal - mode->vdisplay;
1567 v_de_vs = mode->vsync_start - mode->vdisplay;
1568 vsync_len = mode->vsync_end - mode->vsync_start;
1571 * When we're setting an interlaced mode, we need
1572 * to adjust the vertical timing to suit.
1574 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1581 /* Scrambling Control */
1582 if (hdmi->connector.scdc_present) {
1583 if (vmode->mpixelclock > 340000000 ||
1584 hdmi->connector.lte_340mcsc_scramble) {
1585 drm_scdc_readb(&hdmi->i2c->adap, SCDC_SINK_VERSION,
1587 drm_scdc_writeb(&hdmi->i2c->adap, SCDC_SOURCE_VERSION,
1589 drm_scdc_writeb(&hdmi->i2c->adap, SCDC_TMDS_CONFIG, 1);
1590 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1592 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL);
1594 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
1595 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ,
1597 drm_scdc_writeb(&hdmi->i2c->adap, SCDC_TMDS_CONFIG, 0);
1601 /* Set up horizontal active pixel width */
1602 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1);
1603 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0);
1605 /* Set up vertical active lines */
1606 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1607 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1609 /* Set up horizontal blanking pixel region width */
1610 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1611 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1613 /* Set up vertical blanking pixel region width */
1614 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1616 /* Set up HSYNC active edge delay width (in pixel clks) */
1617 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1618 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1620 /* Set up VSYNC active edge delay (in lines) */
1621 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1623 /* Set up HSYNC active pulse width (in pixel clks) */
1624 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1625 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1627 /* Set up VSYNC active edge delay (in lines) */
1628 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1631 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1633 if (!hdmi->phy_enabled)
1636 dw_hdmi_phy_enable_tmds(hdmi, 0);
1637 dw_hdmi_phy_enable_powerdown(hdmi, true);
1639 hdmi->phy_enabled = false;
1642 /* HDMI Initialization Step B.4 */
1643 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1647 /* control period minimum duration */
1648 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1649 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1650 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1652 /* Set to fill TMDS data channels */
1653 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1654 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1655 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1657 /* Enable pixel clock and tmds data path */
1659 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1660 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1662 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1663 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1665 /* Enable csc path */
1666 if (is_color_space_conversion(hdmi)) {
1667 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1668 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1671 /* Enable pixel repetition path */
1672 if (hdmi->hdmi_data.video_mode.mpixelrepetitioninput) {
1673 clkdis &= ~HDMI_MC_CLKDIS_PREPCLK_DISABLE;
1674 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1678 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1680 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1683 /* Workaround to clear the overflow condition */
1684 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1689 /* TMDS software reset */
1690 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1692 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1693 if (hdmi->dev_type == IMX6DL_HDMI) {
1694 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1698 for (count = 0; count < 4; count++)
1699 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1702 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1704 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1705 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1708 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1710 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1711 HDMI_IH_MUTE_FC_STAT2);
1714 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1718 hdmi_disable_overflow_interrupts(hdmi);
1720 hdmi->vic = drm_match_cea_mode(mode);
1723 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1725 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1728 if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1729 (hdmi->vic == 21) || (hdmi->vic == 22) ||
1730 (hdmi->vic == 2) || (hdmi->vic == 3) ||
1731 (hdmi->vic == 17) || (hdmi->vic == 18))
1732 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1734 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1736 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1737 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1738 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 1;
1740 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1741 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1743 /* TODO: Get input format from IPU (via FB driver interface) */
1744 if (mode->flags & DRM_MODE_FLAG_420_MASK) {
1745 hdmi->hdmi_data.enc_in_format = YCBCR420;
1746 hdmi->hdmi_data.enc_out_format = YCBCR420;
1748 hdmi->hdmi_data.enc_in_format = RGB;
1749 hdmi->hdmi_data.enc_out_format = RGB;
1751 hdmi->hdmi_data.enc_color_depth = 8;
1753 * According to the dw-hdmi specification 6.4.2
1755 * 0000b: No pixel repetition (pixel sent only once)
1756 * 0001b: Pixel sent two times (pixel repeated once)
1758 hdmi->hdmi_data.pix_repet_factor =
1759 (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0;
1760 hdmi->hdmi_data.hdcp_enable = 0;
1761 hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1763 /* HDMI Initialization Step B.1 */
1764 hdmi_av_composer(hdmi, mode);
1766 /* HDMI Initializateion Step B.2 */
1767 ret = dw_hdmi_phy_init(hdmi);
1771 /* HDMI Initialization Step B.3 */
1772 dw_hdmi_enable_video_path(hdmi);
1774 if (hdmi->sink_has_audio) {
1775 dev_dbg(hdmi->dev, "sink has audio support\n");
1777 /* HDMI Initialization Step E - Configure audio */
1778 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1779 hdmi_enable_audio_clk(hdmi);
1782 /* not for DVI mode */
1783 if (hdmi->sink_is_hdmi) {
1784 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1786 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1787 hdmi_config_AVI(hdmi, mode);
1788 hdmi_config_vendor_specific_infoframe(hdmi, mode);
1790 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1793 hdmi_video_packetize(hdmi);
1794 hdmi_video_csc(hdmi);
1795 hdmi_video_sample(hdmi);
1796 hdmi_tx_hdcp_config(hdmi);
1798 dw_hdmi_clear_overflow(hdmi);
1799 if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1800 hdmi_enable_overflow_interrupts(hdmi);
1805 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1810 * Boot up defaults are:
1811 * HDMI_IH_MUTE = 0x03 (disabled)
1812 * HDMI_IH_MUTE_* = 0x00 (enabled)
1814 * Disable top level interrupt bits in HDMI block
1816 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1817 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1818 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1820 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1822 /* by default mask all interrupts */
1823 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1824 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1825 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1826 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1827 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1828 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1829 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1830 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1831 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1832 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1833 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1834 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1835 hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1836 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1837 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1839 /* Disable interrupts in the IH_MUTE_* registers */
1840 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1841 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1842 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1843 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1844 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1845 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1846 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1847 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1848 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1849 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1851 /* Enable top level interrupt bits in HDMI block */
1852 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1853 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1854 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1857 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1859 hdmi->bridge_is_on = true;
1860 dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1863 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1865 dw_hdmi_phy_disable(hdmi);
1866 hdmi->bridge_is_on = false;
1869 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1871 int force = hdmi->force;
1873 if (hdmi->disabled) {
1874 force = DRM_FORCE_OFF;
1875 } else if (force == DRM_FORCE_UNSPECIFIED) {
1877 force = DRM_FORCE_ON;
1879 force = DRM_FORCE_OFF;
1882 if (force == DRM_FORCE_OFF) {
1883 if (hdmi->bridge_is_on)
1884 dw_hdmi_poweroff(hdmi);
1886 if (!hdmi->bridge_is_on)
1887 dw_hdmi_poweron(hdmi);
1892 * Adjust the detection of RXSENSE according to whether we have a forced
1893 * connection mode enabled, or whether we have been disabled. There is
1894 * no point processing RXSENSE interrupts if we have a forced connection
1895 * state, or DRM has us disabled.
1897 * We also disable rxsense interrupts when we think we're disconnected
1898 * to avoid floating TDMS signals giving false rxsense interrupts.
1900 * Note: we still need to listen for HPD interrupts even when DRM has us
1901 * disabled so that we can detect a connect event.
1903 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1905 u8 old_mask = hdmi->phy_mask;
1907 if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1908 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1910 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1912 if (old_mask != hdmi->phy_mask)
1913 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1916 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1917 struct drm_display_mode *orig_mode,
1918 struct drm_display_mode *mode)
1920 struct dw_hdmi *hdmi = bridge->driver_private;
1922 mutex_lock(&hdmi->mutex);
1924 /* Store the display mode for plugin/DKMS poweron events */
1925 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1927 mutex_unlock(&hdmi->mutex);
1930 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1932 struct dw_hdmi *hdmi = bridge->driver_private;
1934 mutex_lock(&hdmi->mutex);
1935 hdmi->disabled = true;
1936 dw_hdmi_update_power(hdmi);
1937 dw_hdmi_update_phy_mask(hdmi);
1938 mutex_unlock(&hdmi->mutex);
1941 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1943 struct dw_hdmi *hdmi = bridge->driver_private;
1945 mutex_lock(&hdmi->mutex);
1946 hdmi->disabled = false;
1947 dw_hdmi_update_power(hdmi);
1948 dw_hdmi_update_phy_mask(hdmi);
1949 mutex_unlock(&hdmi->mutex);
1952 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1957 static enum drm_connector_status
1958 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1960 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1963 mutex_lock(&hdmi->mutex);
1964 hdmi->force = DRM_FORCE_UNSPECIFIED;
1965 dw_hdmi_update_power(hdmi);
1966 dw_hdmi_update_phy_mask(hdmi);
1967 mutex_unlock(&hdmi->mutex);
1969 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1970 connector_status_connected : connector_status_disconnected;
1973 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1975 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1983 edid = drm_get_edid(connector, hdmi->ddc);
1985 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1986 edid->width_cm, edid->height_cm);
1988 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1989 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1990 drm_mode_connector_update_edid_property(connector, edid);
1991 ret = drm_add_edid_modes(connector, edid);
1993 drm_edid_to_eld(connector, edid);
1996 dev_dbg(hdmi->dev, "failed to get edid\n");
2002 static enum drm_mode_status
2003 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
2004 struct drm_display_mode *mode)
2006 struct dw_hdmi *hdmi = container_of(connector,
2007 struct dw_hdmi, connector);
2008 enum drm_mode_status mode_status = MODE_OK;
2010 if (hdmi->plat_data->mode_valid)
2011 mode_status = hdmi->plat_data->mode_valid(connector, mode);
2016 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
2019 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2022 return hdmi->encoder;
2025 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
2027 drm_connector_unregister(connector);
2028 drm_connector_cleanup(connector);
2031 static void dw_hdmi_connector_force(struct drm_connector *connector)
2033 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
2036 mutex_lock(&hdmi->mutex);
2037 hdmi->force = connector->force;
2038 dw_hdmi_update_power(hdmi);
2039 dw_hdmi_update_phy_mask(hdmi);
2040 mutex_unlock(&hdmi->mutex);
2043 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
2044 .dpms = drm_helper_connector_dpms,
2045 .fill_modes = drm_helper_probe_single_connector_modes,
2046 .detect = dw_hdmi_connector_detect,
2047 .destroy = dw_hdmi_connector_destroy,
2048 .force = dw_hdmi_connector_force,
2051 static const struct drm_connector_funcs dw_hdmi_atomic_connector_funcs = {
2052 .dpms = drm_atomic_helper_connector_dpms,
2053 .fill_modes = drm_helper_probe_single_connector_modes,
2054 .detect = dw_hdmi_connector_detect,
2055 .destroy = dw_hdmi_connector_destroy,
2056 .force = dw_hdmi_connector_force,
2057 .reset = drm_atomic_helper_connector_reset,
2058 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
2059 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2062 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
2063 .get_modes = dw_hdmi_connector_get_modes,
2064 .mode_valid = dw_hdmi_connector_mode_valid,
2065 .best_encoder = dw_hdmi_connector_best_encoder,
2068 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
2069 .enable = dw_hdmi_bridge_enable,
2070 .disable = dw_hdmi_bridge_disable,
2071 .pre_enable = dw_hdmi_bridge_nop,
2072 .post_disable = dw_hdmi_bridge_nop,
2073 .mode_set = dw_hdmi_bridge_mode_set,
2076 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi)
2078 struct dw_hdmi_i2c *i2c = hdmi->i2c;
2081 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0);
2085 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0);
2089 complete(&i2c->cmp);
2094 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
2096 struct dw_hdmi *hdmi = dev_id;
2098 irqreturn_t ret = IRQ_NONE;
2101 ret = dw_hdmi_i2c_irq(hdmi);
2103 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2105 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2106 return IRQ_WAKE_THREAD;
2112 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
2114 struct dw_hdmi *hdmi = dev_id;
2115 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
2117 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
2118 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
2119 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
2122 if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
2123 phy_pol_mask |= HDMI_PHY_HPD;
2124 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
2125 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
2126 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
2127 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
2128 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
2129 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
2130 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
2131 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
2134 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
2137 * RX sense tells us whether the TDMS transmitters are detecting
2138 * load - in other words, there's something listening on the
2139 * other end of the link. Use this to decide whether we should
2140 * power on the phy as HPD may be toggled by the sink to merely
2141 * ask the source to re-read the EDID.
2144 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
2145 mutex_lock(&hdmi->mutex);
2146 if (!hdmi->bridge_is_on && !hdmi->force) {
2148 * If the RX sense status indicates we're disconnected,
2149 * clear the software rxsense status.
2151 if (!(phy_stat & HDMI_PHY_RX_SENSE))
2152 hdmi->rxsense = false;
2155 * Only set the software rxsense status when both
2156 * rxsense and hpd indicates we're connected.
2157 * This avoids what seems to be bad behaviour in
2158 * at least iMX6S versions of the phy.
2160 if (phy_stat & HDMI_PHY_HPD)
2161 hdmi->rxsense = true;
2163 dw_hdmi_update_power(hdmi);
2164 dw_hdmi_update_phy_mask(hdmi);
2166 mutex_unlock(&hdmi->mutex);
2169 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
2170 dev_dbg(hdmi->dev, "EVENT=%s\n",
2171 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
2172 drm_helper_hpd_irq_event(hdmi->bridge->dev);
2173 #ifdef CONFIG_SWITCH
2174 if (phy_int_pol & HDMI_PHY_HPD)
2175 switch_set_state(&hdmi->switchdev, 1);
2177 switch_set_state(&hdmi->switchdev, 0);
2181 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
2182 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2183 HDMI_IH_MUTE_PHY_STAT0);
2188 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
2190 struct drm_encoder *encoder = hdmi->encoder;
2191 struct drm_bridge *bridge;
2194 bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
2196 DRM_ERROR("Failed to allocate drm bridge\n");
2200 hdmi->bridge = bridge;
2201 bridge->driver_private = hdmi;
2202 bridge->funcs = &dw_hdmi_bridge_funcs;
2203 ret = drm_bridge_attach(drm, bridge);
2205 DRM_ERROR("Failed to initialize bridge with drm\n");
2209 encoder->bridge = bridge;
2210 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
2211 hdmi->connector.port = hdmi->dev->of_node;
2213 drm_connector_helper_add(&hdmi->connector,
2214 &dw_hdmi_connector_helper_funcs);
2216 if (drm_core_check_feature(drm, DRIVER_ATOMIC))
2217 drm_connector_init(drm, &hdmi->connector,
2218 &dw_hdmi_atomic_connector_funcs,
2219 DRM_MODE_CONNECTOR_HDMIA);
2221 drm_connector_init(drm, &hdmi->connector,
2222 &dw_hdmi_connector_funcs,
2223 DRM_MODE_CONNECTOR_HDMIA);
2225 drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
2230 #include <linux/fs.h>
2231 #include <linux/debugfs.h>
2232 #include <linux/seq_file.h>
2234 struct dw_hdmi_reg_table {
2239 static const struct dw_hdmi_reg_table hdmi_reg_table[] = {
2240 {HDMI_DESIGN_ID, HDMI_CONFIG3_ID},
2241 {HDMI_IH_FC_STAT0, HDMI_IH_MUTE},
2242 {HDMI_TX_INVID0, HDMI_TX_BCBDATA1},
2243 {HDMI_VP_STATUS, HDMI_VP_POL},
2244 {HDMI_FC_INVIDCONF, HDMI_FC_DBGTMDS2},
2245 {HDMI_PHY_CONF0, HDMI_PHY_POL0},
2246 {HDMI_PHY_I2CM_SLAVE_ADDR, HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR},
2247 {HDMI_AUD_CONF0, 0x3624},
2248 {HDMI_MC_SFRDIV, HDMI_MC_HEACPHY_RST},
2249 {HDMI_CSC_CFG, HDMI_CSC_COEF_C4_LSB},
2250 {HDMI_A_HDCPCFG0, 0x52bb},
2253 {HDMI_CEC_CTRL, HDMI_CEC_WKUPCTRL},
2254 {HDMI_I2CM_SLAVE, 0x7e31},
2257 static int dw_hdmi_ctrl_show(struct seq_file *s, void *v)
2259 struct dw_hdmi *hdmi = s->private;
2260 u32 i = 0, j = 0, val = 0;
2262 seq_puts(s, "\n>>>hdmi_ctl reg ");
2263 for (i = 0; i < 16; i++)
2264 seq_printf(s, " %2x", i);
2265 seq_puts(s, "\n---------------------------------------------------");
2267 for (i = 0; i < ARRAY_SIZE(hdmi_reg_table); i++) {
2268 for (j = hdmi_reg_table[i].reg_base;
2269 j <= hdmi_reg_table[i].reg_end; j++) {
2270 val = hdmi_readb(hdmi, j);
2271 if ((j - hdmi_reg_table[i].reg_base) % 16 == 0)
2272 seq_printf(s, "\n>>>hdmi_ctl %04x:", j);
2273 seq_printf(s, " %02x", val);
2276 seq_puts(s, "\n---------------------------------------------------\n");
2281 static int dw_hdmi_ctrl_open(struct inode *inode, struct file *file)
2283 return single_open(file, dw_hdmi_ctrl_show, inode->i_private);
2287 dw_hdmi_ctrl_write(struct file *file, const char __user *buf,
2288 size_t count, loff_t *ppos)
2290 struct dw_hdmi *hdmi =
2291 ((struct seq_file *)file->private_data)->private;
2295 if (copy_from_user(kbuf, buf, count))
2297 if (sscanf(kbuf, "%x%x", ®, &val) == -1)
2299 if ((reg < 0) || (reg > HDMI_I2CM_FS_SCL_LCNT_0_ADDR)) {
2300 dev_err(hdmi->dev, "it is no a hdmi register\n");
2303 dev_info(hdmi->dev, "/**********hdmi register config******/");
2304 dev_info(hdmi->dev, "\n reg=%x val=%x\n", reg, val);
2305 hdmi_writeb(hdmi, val, reg);
2309 static const struct file_operations dw_hdmi_ctrl_fops = {
2310 .owner = THIS_MODULE,
2311 .open = dw_hdmi_ctrl_open,
2313 .write = dw_hdmi_ctrl_write,
2314 .llseek = seq_lseek,
2315 .release = single_release,
2318 static int dw_hdmi_phy_show(struct seq_file *s, void *v)
2320 struct dw_hdmi *hdmi = s->private;
2323 seq_puts(s, "\n>>>hdmi_phy reg ");
2324 for (i = 0; i < 0x28; i++)
2325 seq_printf(s, "regs %02x val %04x\n",
2326 i, hdmi_phy_i2c_read(hdmi, i));
2330 static int dw_hdmi_phy_open(struct inode *inode, struct file *file)
2332 return single_open(file, dw_hdmi_phy_show, inode->i_private);
2336 dw_hdmi_phy_write(struct file *file, const char __user *buf,
2337 size_t count, loff_t *ppos)
2339 struct dw_hdmi *hdmi =
2340 ((struct seq_file *)file->private_data)->private;
2344 if (copy_from_user(kbuf, buf, count))
2346 if (sscanf(kbuf, "%x%x", ®, &val) == -1)
2348 if ((reg < 0) || (reg > 0x28)) {
2349 dev_err(hdmi->dev, "it is not a hdmi phy register\n");
2352 dev_info(hdmi->dev, "/*******hdmi phy register config******/");
2353 dev_info(hdmi->dev, "\n reg=%x val=%x\n", reg, val);
2354 hdmi_phy_i2c_write(hdmi, val, reg);
2358 static const struct file_operations dw_hdmi_phy_fops = {
2359 .owner = THIS_MODULE,
2360 .open = dw_hdmi_phy_open,
2362 .write = dw_hdmi_phy_write,
2363 .llseek = seq_lseek,
2364 .release = single_release,
2367 static void dw_hdmi_register_debugfs(struct device *dev, struct dw_hdmi *hdmi)
2369 struct dentry *debugfs_dir;
2371 debugfs_dir = debugfs_create_dir("dw-hdmi", NULL);
2372 if (IS_ERR(debugfs_dir)) {
2373 dev_err(dev, "failed to create debugfs dir!\n");
2376 debugfs_create_file("ctrl", 0400, debugfs_dir,
2377 hdmi, &dw_hdmi_ctrl_fops);
2378 debugfs_create_file("phy", 0400, debugfs_dir,
2379 hdmi, &dw_hdmi_phy_fops);
2382 int dw_hdmi_bind(struct device *dev, struct device *master,
2383 void *data, struct drm_encoder *encoder,
2384 struct resource *iores, int irq,
2385 const struct dw_hdmi_plat_data *plat_data)
2387 struct drm_device *drm = data;
2388 struct device_node *np = dev->of_node;
2389 struct platform_device_info pdevinfo;
2390 struct device_node *ddc_node;
2391 struct dw_hdmi *hdmi;
2397 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
2401 hdmi->connector.interlace_allowed = 1;
2402 hdmi->connector.stereo_allowed = 1;
2404 hdmi->plat_data = plat_data;
2406 hdmi->dev_type = plat_data->dev_type;
2407 hdmi->sample_rate = 48000;
2408 hdmi->encoder = encoder;
2409 hdmi->disabled = true;
2410 hdmi->rxsense = true;
2411 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
2414 mutex_init(&hdmi->mutex);
2415 mutex_init(&hdmi->audio_mutex);
2416 spin_lock_init(&hdmi->audio_lock);
2418 of_property_read_u32(np, "reg-io-width", &val);
2422 hdmi->write = dw_hdmi_writel;
2423 hdmi->read = dw_hdmi_readl;
2426 hdmi->write = dw_hdmi_writeb;
2427 hdmi->read = dw_hdmi_readb;
2430 dev_err(dev, "reg-io-width must be 1 or 4\n");
2434 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
2436 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
2437 of_node_put(ddc_node);
2439 dev_dbg(hdmi->dev, "failed to read ddc node\n");
2440 return -EPROBE_DEFER;
2444 dev_dbg(hdmi->dev, "no ddc property found\n");
2447 /* If DDC bus is not specified, try to register HDMI I2C bus */
2449 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi);
2450 if (IS_ERR(hdmi->ddc))
2453 * Read high and low time from device tree. If not available use
2454 * the default timing scl clock rate is about 99.6KHz.
2456 if (of_property_read_u32(np, "ddc-i2c-scl-high-time-ns",
2457 &hdmi->i2c->scl_high_ns))
2458 hdmi->i2c->scl_high_ns = 4708;
2459 if (of_property_read_u32(np, "ddc-i2c-scl-low-time-ns",
2460 &hdmi->i2c->scl_low_ns))
2461 hdmi->i2c->scl_low_ns = 4916;
2464 hdmi->regs = devm_ioremap_resource(dev, iores);
2465 if (IS_ERR(hdmi->regs))
2466 return PTR_ERR(hdmi->regs);
2468 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
2469 if (IS_ERR(hdmi->isfr_clk)) {
2470 ret = PTR_ERR(hdmi->isfr_clk);
2471 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
2475 ret = clk_prepare_enable(hdmi->isfr_clk);
2477 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
2481 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
2482 if (IS_ERR(hdmi->iahb_clk)) {
2483 ret = PTR_ERR(hdmi->iahb_clk);
2484 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
2488 ret = clk_prepare_enable(hdmi->iahb_clk);
2490 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
2494 /* Product and revision IDs */
2496 "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
2497 hdmi_readb(hdmi, HDMI_DESIGN_ID),
2498 hdmi_readb(hdmi, HDMI_REVISION_ID),
2499 hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
2500 hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
2502 initialize_hdmi_ih_mutes(hdmi);
2504 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
2505 dw_hdmi_irq, IRQF_SHARED,
2506 dev_name(dev), hdmi);
2511 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
2512 * N and cts values before enabling phy
2514 hdmi_init_clk_regenerator(hdmi);
2516 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2517 HDMI_PHY_I2CM_INT_ADDR);
2519 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2520 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2521 HDMI_PHY_I2CM_CTLINT_ADDR);
2523 /* Re-init HPD polarity */
2524 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
2526 /* Unmask HPD, clear transitory interrupts, then unmute */
2527 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
2529 ret = dw_hdmi_register(drm, hdmi);
2533 #ifdef CONFIG_SWITCH
2534 hdmi->switchdev.name = "hdmi";
2535 switch_dev_register(&hdmi->switchdev);
2538 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
2539 HDMI_IH_MUTE_PHY_STAT0);
2541 /* Unmute I2CM interrupts and reset HDMI DDC I2C master controller */
2543 dw_hdmi_i2c_init(hdmi);
2545 memset(&pdevinfo, 0, sizeof(pdevinfo));
2546 pdevinfo.parent = dev;
2547 pdevinfo.id = PLATFORM_DEVID_AUTO;
2549 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID);
2550 config1 = hdmi_readb(hdmi, HDMI_CONFIG1_ID);
2552 if (config1 & HDMI_CONFIG1_AHB) {
2553 struct dw_hdmi_audio_data audio;
2555 audio.phys = iores->start;
2556 audio.base = hdmi->regs;
2559 audio.eld = hdmi->connector.eld;
2561 pdevinfo.name = "dw-hdmi-ahb-audio";
2562 pdevinfo.data = &audio;
2563 pdevinfo.size_data = sizeof(audio);
2564 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2565 hdmi->audio = platform_device_register_full(&pdevinfo);
2566 } else if (config0 & HDMI_CONFIG0_I2S) {
2567 struct dw_hdmi_i2s_audio_data audio;
2570 audio.write = hdmi_writeb;
2571 audio.read = hdmi_readb;
2573 pdevinfo.name = "dw-hdmi-i2s-audio";
2574 pdevinfo.data = &audio;
2575 pdevinfo.size_data = sizeof(audio);
2576 pdevinfo.dma_mask = DMA_BIT_MASK(32);
2577 hdmi->audio = platform_device_register_full(&pdevinfo);
2580 dev_set_drvdata(dev, hdmi);
2582 dw_hdmi_register_debugfs(dev, hdmi);
2588 i2c_del_adapter(&hdmi->i2c->adap);
2590 clk_disable_unprepare(hdmi->iahb_clk);
2592 clk_disable_unprepare(hdmi->isfr_clk);
2596 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
2598 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
2600 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2602 if (hdmi->audio && !IS_ERR(hdmi->audio))
2603 platform_device_unregister(hdmi->audio);
2605 /* Disable all interrupts */
2606 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
2608 #ifdef CONFIG_SWITCH
2609 switch_dev_unregister(&hdmi->switchdev);
2611 hdmi->connector.funcs->destroy(&hdmi->connector);
2612 hdmi->encoder->funcs->destroy(hdmi->encoder);
2614 clk_disable_unprepare(hdmi->iahb_clk);
2615 clk_disable_unprepare(hdmi->isfr_clk);
2618 i2c_del_adapter(&hdmi->i2c->adap);
2620 i2c_put_adapter(hdmi->ddc);
2622 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
2624 static void dw_hdmi_reg_initial(struct dw_hdmi *hdmi)
2626 if (hdmi_readb(hdmi, HDMI_IH_MUTE)) {
2627 initialize_hdmi_ih_mutes(hdmi);
2628 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
2629 HDMI_PHY_I2CM_INT_ADDR);
2631 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
2632 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
2633 HDMI_PHY_I2CM_CTLINT_ADDR);
2635 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE,
2637 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
2638 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD |
2639 HDMI_IH_PHY_STAT0_RX_SENSE),
2640 HDMI_IH_MUTE_PHY_STAT0);
2644 void dw_hdmi_suspend(struct device *dev)
2646 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2648 mutex_lock(&hdmi->mutex);
2650 disable_irq(hdmi->irq);
2651 mutex_unlock(&hdmi->mutex);
2653 EXPORT_SYMBOL_GPL(dw_hdmi_suspend);
2655 void dw_hdmi_resume(struct device *dev)
2657 struct dw_hdmi *hdmi = dev_get_drvdata(dev);
2659 mutex_lock(&hdmi->mutex);
2660 dw_hdmi_reg_initial(hdmi);
2662 enable_irq(hdmi->irq);
2663 mutex_unlock(&hdmi->mutex);
2665 EXPORT_SYMBOL_GPL(dw_hdmi_resume);
2667 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
2668 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
2669 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
2670 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>");
2671 MODULE_DESCRIPTION("DW HDMI transmitter driver");
2672 MODULE_LICENSE("GPL");
2673 MODULE_ALIAS("platform:dw-hdmi");