drivers/gpu/drm/bridge/dw_hdmi.c

   1 /*
   2  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * Designware High-Definition Multimedia Interface (HDMI) driver
  10  *
  11  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  12  */
  13 #include <linux/module.h>
  14 #include <linux/irq.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/hdmi.h>
  19 #include <linux/mutex.h>
  20 #include <linux/of_device.h>
  21
  22 #include <drm/drm_of.h>
  23 #include <drm/drmP.h>
  24 #include <drm/drm_crtc_helper.h>
  25 #include <drm/drm_edid.h>
  26 #include <drm/drm_encoder_slave.h>
  27 #include <drm/bridge/dw_hdmi.h>
  28
  29 #include "dw_hdmi.h"
  30
  31 #define HDMI_EDID_LEN           512
  32
  33 #define RGB                     0
  34 #define YCBCR444                1
  35 #define YCBCR422_16BITS         2
  36 #define YCBCR422_8BITS          3
  37 #define XVYCC444                4
  38
  39 enum hdmi_datamap {
  40         RGB444_8B = 0x01,
  41         RGB444_10B = 0x03,
  42         RGB444_12B = 0x05,
  43         RGB444_16B = 0x07,
  44         YCbCr444_8B = 0x09,
  45         YCbCr444_10B = 0x0B,
  46         YCbCr444_12B = 0x0D,
  47         YCbCr444_16B = 0x0F,
  48         YCbCr422_8B = 0x16,
  49         YCbCr422_10B = 0x14,
  50         YCbCr422_12B = 0x12,
  51 };
  52
  53 static const u16 csc_coeff_default[3][4] = {
  54         { 0x2000, 0x0000, 0x0000, 0x0000 },
  55         { 0x0000, 0x2000, 0x0000, 0x0000 },
  56         { 0x0000, 0x0000, 0x2000, 0x0000 }
  57 };
  58
  59 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
  60         { 0x2000, 0x6926, 0x74fd, 0x010e },
  61         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
  62         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
  63 };
  64
  65 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
  66         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
  67         { 0x2000, 0x3264, 0x0000, 0x7e6d },
  68         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
  69 };
  70
  71 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
  72         { 0x2591, 0x1322, 0x074b, 0x0000 },
  73         { 0x6535, 0x2000, 0x7acc, 0x0200 },
  74         { 0x6acd, 0x7534, 0x2000, 0x0200 }
  75 };
  76
  77 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
  78         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
  79         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
  80         { 0x6756, 0x78ab, 0x2000, 0x0200 }
  81 };
  82
  83 struct hdmi_vmode {
  84         bool mdvi;
  85         bool mhsyncpolarity;
  86         bool mvsyncpolarity;
  87         bool minterlaced;
  88         bool mdataenablepolarity;
  89
  90         unsigned int mpixelclock;
  91         unsigned int mpixelrepetitioninput;
  92         unsigned int mpixelrepetitionoutput;
  93 };
  94
  95 struct hdmi_data_info {
  96         unsigned int enc_in_format;
  97         unsigned int enc_out_format;
  98         unsigned int enc_color_depth;
  99         unsigned int colorimetry;
 100         unsigned int pix_repet_factor;
 101         unsigned int hdcp_enable;
 102         struct hdmi_vmode video_mode;
 103 };
 104
 105 struct dw_hdmi {
 106         struct drm_connector connector;
 107         struct drm_encoder *encoder;
 108         struct drm_bridge *bridge;
 109
 110         enum dw_hdmi_devtype dev_type;
 111         struct device *dev;
 112         struct clk *isfr_clk;
 113         struct clk *iahb_clk;
 114
 115         struct hdmi_data_info hdmi_data;
 116         const struct dw_hdmi_plat_data *plat_data;
 117
 118         int vic;
 119
 120         u8 edid[HDMI_EDID_LEN];
 121         bool cable_plugin;
 122
 123         bool phy_enabled;
 124         struct drm_display_mode previous_mode;
 125
 126         struct regmap *regmap;
 127         struct i2c_adapter *ddc;
 128         void __iomem *regs;
 129
 130         struct mutex audio_mutex;
 131         unsigned int sample_rate;
 132         int ratio;
 133
 134         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
 135         u8 (*read)(struct dw_hdmi *hdmi, int offset);
 136 };
 137
 138 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
 139 {
 140         writel(val, hdmi->regs + (offset << 2));
 141 }
 142
 143 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
 144 {
 145         return readl(hdmi->regs + (offset << 2));
 146 }
 147
 148 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 149 {
 150         writeb(val, hdmi->regs + offset);
 151 }
 152
 153 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
 154 {
 155         return readb(hdmi->regs + offset);
 156 }
 157
 158 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 159 {
 160         hdmi->write(hdmi, val, offset);
 161 }
 162
 163 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 164 {
 165         return hdmi->read(hdmi, offset);
 166 }
 167
 168 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 169 {
 170         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 171
 172         val |= data & mask;
 173         hdmi_writeb(hdmi, val, reg);
 174 }
 175
 176 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 177                              u8 shift, u8 mask)
 178 {
 179         hdmi_modb(hdmi, data << shift, mask, reg);
 180 }
 181
 182 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 183                            unsigned int n)
 184 {
 185         /* Must be set/cleared first */
 186         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 187
 188         /* nshift factor = 0 */
 189         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 190
 191         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 192                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 193         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 194         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 195
 196         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 197         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 198         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 199 }
 200
 201 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
 202                                    unsigned int ratio)
 203 {
 204         unsigned int n = (128 * freq) / 1000;
 205
 206         switch (freq) {
 207         case 32000:
 208                 if (pixel_clk == 25170000)
 209                         n = (ratio == 150) ? 9152 : 4576;
 210                 else if (pixel_clk == 27020000)
 211                         n = (ratio == 150) ? 8192 : 4096;
 212                 else if (pixel_clk == 74170000 || pixel_clk == 148350000)
 213                         n = 11648;
 214                 else
 215                         n = 4096;
 216                 break;
 217
 218         case 44100:
 219                 if (pixel_clk == 25170000)
 220                         n = 7007;
 221                 else if (pixel_clk == 74170000)
 222                         n = 17836;
 223                 else if (pixel_clk == 148350000)
 224                         n = (ratio == 150) ? 17836 : 8918;
 225                 else
 226                         n = 6272;
 227                 break;
 228
 229         case 48000:
 230                 if (pixel_clk == 25170000)
 231                         n = (ratio == 150) ? 9152 : 6864;
 232                 else if (pixel_clk == 27020000)
 233                         n = (ratio == 150) ? 8192 : 6144;
 234                 else if (pixel_clk == 74170000)
 235                         n = 11648;
 236                 else if (pixel_clk == 148350000)
 237                         n = (ratio == 150) ? 11648 : 5824;
 238                 else
 239                         n = 6144;
 240                 break;
 241
 242         case 88200:
 243                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
 244                 break;
 245
 246         case 96000:
 247                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
 248                 break;
 249
 250         case 176400:
 251                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
 252                 break;
 253
 254         case 192000:
 255                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
 256                 break;
 257
 258         default:
 259                 break;
 260         }
 261
 262         return n;
 263 }
 264
 265 static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
 266                                      unsigned int ratio)
 267 {
 268         unsigned int cts = 0;
 269
 270         pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq,
 271                  pixel_clk, ratio);
 272
 273         switch (freq) {
 274         case 32000:
 275                 if (pixel_clk == 297000000) {
 276                         cts = 222750;
 277                         break;
 278                 }
 279         case 48000:
 280         case 96000:
 281         case 192000:
 282                 switch (pixel_clk) {
 283                 case 25200000:
 284                 case 27000000:
 285                 case 54000000:
 286                 case 74250000:
 287                 case 148500000:
 288                         cts = pixel_clk / 1000;
 289                         break;
 290                 case 297000000:
 291                         cts = 247500;
 292                         break;
 293                 /*
 294                  * All other TMDS clocks are not supported by
 295                  * DWC_hdmi_tx. The TMDS clocks divided or
 296                  * multiplied by 1,001 coefficients are not
 297                  * supported.
 298                  */
 299                 default:
 300                         break;
 301                 }
 302                 break;
 303         case 44100:
 304         case 88200:
 305         case 176400:
 306                 switch (pixel_clk) {
 307                 case 25200000:
 308                         cts = 28000;
 309                         break;
 310                 case 27000000:
 311                         cts = 30000;
 312                         break;
 313                 case 54000000:
 314                         cts = 60000;
 315                         break;
 316                 case 74250000:
 317                         cts = 82500;
 318                         break;
 319                 case 148500000:
 320                         cts = 165000;
 321                         break;
 322                 case 297000000:
 323                         cts = 247500;
 324                         break;
 325                 default:
 326                         break;
 327                 }
 328                 break;
 329         default:
 330                 break;
 331         }
 332         if (ratio == 100)
 333                 return cts;
 334         return (cts * ratio) / 100;
 335 }
 336
 337 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 338         unsigned long pixel_clk, unsigned int sample_rate, unsigned int ratio)
 339 {
 340         unsigned int n, cts;
 341
 342         n = hdmi_compute_n(sample_rate, pixel_clk, ratio);
 343         cts = hdmi_compute_cts(sample_rate, pixel_clk, ratio);
 344         if (!cts) {
 345                 dev_err(hdmi->dev,
 346                         "%s: pixel clock/sample rate not supported: %luMHz / %ukHz\n",
 347                         __func__, pixel_clk, sample_rate);
 348         }
 349
 350         dev_dbg(hdmi->dev, "%s: samplerate=%ukHz ratio=%d pixelclk=%luMHz N=%d cts=%d\n",
 351                 __func__, sample_rate, ratio, pixel_clk, n, cts);
 352
 353         hdmi_set_cts_n(hdmi, cts, n);
 354 }
 355
 356 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 357 {
 358         mutex_lock(&hdmi->audio_mutex);
 359         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate,
 360                                  hdmi->ratio);
 361         mutex_unlock(&hdmi->audio_mutex);
 362 }
 363
 364 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 365 {
 366         mutex_lock(&hdmi->audio_mutex);
 367         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 368                                  hdmi->sample_rate, hdmi->ratio);
 369         mutex_unlock(&hdmi->audio_mutex);
 370 }
 371
 372 /*
 373  * this submodule is responsible for the video data synchronization.
 374  * for example, for RGB 4:4:4 input, the data map is defined as
 375  *                      pin{47~40} <==> R[7:0]
 376  *                      pin{31~24} <==> G[7:0]
 377  *                      pin{15~8}  <==> B[7:0]
 378  */
 379 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 380 {
 381         int color_format = 0;
 382         u8 val;
 383
 384         if (hdmi->hdmi_data.enc_in_format == RGB) {
 385                 if (hdmi->hdmi_data.enc_color_depth == 8)
 386                         color_format = 0x01;
 387                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 388                         color_format = 0x03;
 389                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 390                         color_format = 0x05;
 391                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 392                         color_format = 0x07;
 393                 else
 394                         return;
 395         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
 396                 if (hdmi->hdmi_data.enc_color_depth == 8)
 397                         color_format = 0x09;
 398                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 399                         color_format = 0x0B;
 400                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 401                         color_format = 0x0D;
 402                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 403                         color_format = 0x0F;
 404                 else
 405                         return;
 406         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 407                 if (hdmi->hdmi_data.enc_color_depth == 8)
 408                         color_format = 0x16;
 409                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 410                         color_format = 0x14;
 411                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 412                         color_format = 0x12;
 413                 else
 414                         return;
 415         }
 416
 417         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 418                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 419                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 420         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 421
 422         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 423         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 424                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 425                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 426         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 427         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 428         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 429         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 430         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 431         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 432         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 433 }
 434
 435 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 436 {
 437         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
 438 }
 439
 440 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 441 {
 442         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
 443                 return 0;
 444         if (hdmi->hdmi_data.enc_in_format == RGB ||
 445             hdmi->hdmi_data.enc_in_format == YCBCR444)
 446                 return 1;
 447         return 0;
 448 }
 449
 450 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 451 {
 452         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
 453                 return 0;
 454         if (hdmi->hdmi_data.enc_out_format == RGB ||
 455             hdmi->hdmi_data.enc_out_format == YCBCR444)
 456                 return 1;
 457         return 0;
 458 }
 459
 460 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 461 {
 462         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 463         unsigned i;
 464         u32 csc_scale = 1;
 465
 466         if (is_color_space_conversion(hdmi)) {
 467                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 468                         if (hdmi->hdmi_data.colorimetry ==
 469                                         HDMI_COLORIMETRY_ITU_601)
 470                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 471                         else
 472                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 473                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 474                         if (hdmi->hdmi_data.colorimetry ==
 475                                         HDMI_COLORIMETRY_ITU_601)
 476                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 477                         else
 478                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 479                         csc_scale = 0;
 480                 }
 481         }
 482
 483         /* The CSC registers are sequential, alternating MSB then LSB */
 484         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 485                 u16 coeff_a = (*csc_coeff)[0][i];
 486                 u16 coeff_b = (*csc_coeff)[1][i];
 487                 u16 coeff_c = (*csc_coeff)[2][i];
 488
 489                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 490                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 491                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 492                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 493                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 494                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 495         }
 496
 497         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 498                   HDMI_CSC_SCALE);
 499 }
 500
 501 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 502 {
 503         int color_depth = 0;
 504         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 505         int decimation = 0;
 506
 507         /* YCC422 interpolation to 444 mode */
 508         if (is_color_space_interpolation(hdmi))
 509                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 510         else if (is_color_space_decimation(hdmi))
 511                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 512
 513         if (hdmi->hdmi_data.enc_color_depth == 8)
 514                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 515         else if (hdmi->hdmi_data.enc_color_depth == 10)
 516                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 517         else if (hdmi->hdmi_data.enc_color_depth == 12)
 518                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 519         else if (hdmi->hdmi_data.enc_color_depth == 16)
 520                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 521         else
 522                 return;
 523
 524         /* Configure the CSC registers */
 525         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 526         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 527                   HDMI_CSC_SCALE);
 528
 529         dw_hdmi_update_csc_coeffs(hdmi);
 530 }
 531
 532 /*
 533  * HDMI video packetizer is used to packetize the data.
 534  * for example, if input is YCC422 mode or repeater is used,
 535  * data should be repacked this module can be bypassed.
 536  */
 537 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 538 {
 539         unsigned int color_depth = 0;
 540         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 541         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 542         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 543         u8 val, vp_conf;
 544
 545         if (hdmi_data->enc_out_format == RGB ||
 546             hdmi_data->enc_out_format == YCBCR444) {
 547                 if (!hdmi_data->enc_color_depth) {
 548                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 549                 } else if (hdmi_data->enc_color_depth == 8) {
 550                         color_depth = 4;
 551                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 552                 } else if (hdmi_data->enc_color_depth == 10) {
 553                         color_depth = 5;
 554                 } else if (hdmi_data->enc_color_depth == 12) {
 555                         color_depth = 6;
 556                 } else if (hdmi_data->enc_color_depth == 16) {
 557                         color_depth = 7;
 558                 } else {
 559                         return;
 560                 }
 561         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 562                 if (!hdmi_data->enc_color_depth ||
 563                     hdmi_data->enc_color_depth == 8)
 564                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 565                 else if (hdmi_data->enc_color_depth == 10)
 566                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 567                 else if (hdmi_data->enc_color_depth == 12)
 568                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 569                 else
 570                         return;
 571                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 572         } else {
 573                 return;
 574         }
 575
 576         /* set the packetizer registers */
 577         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 578                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 579                 ((hdmi_data->pix_repet_factor <<
 580                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 581                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 582         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 583
 584         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 585                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 586
 587         /* Data from pixel repeater block */
 588         if (hdmi_data->pix_repet_factor > 1) {
 589                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 590                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 591         } else { /* data from packetizer block */
 592                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 593                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 594         }
 595
 596         hdmi_modb(hdmi, vp_conf,
 597                   HDMI_VP_CONF_PR_EN_MASK |
 598                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 599
 600         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 601                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 602
 603         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 604
 605         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 606                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 607                           HDMI_VP_CONF_PP_EN_ENABLE |
 608                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 609         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 610                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 611                           HDMI_VP_CONF_PP_EN_DISABLE |
 612                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 613         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 614                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 615                           HDMI_VP_CONF_PP_EN_DISABLE |
 616                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 617         } else {
 618                 return;
 619         }
 620
 621         hdmi_modb(hdmi, vp_conf,
 622                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 623                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 624
 625         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 626                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 627                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 628                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 629
 630         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 631                   HDMI_VP_CONF);
 632 }
 633
 634 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
 635                                        unsigned char bit)
 636 {
 637         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 638                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 639 }
 640
 641 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
 642                                         unsigned char bit)
 643 {
 644         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
 645                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
 646 }
 647
 648 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
 649                                        unsigned char bit)
 650 {
 651         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
 652                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
 653 }
 654
 655 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
 656                                      unsigned char bit)
 657 {
 658         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
 659 }
 660
 661 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
 662                                       unsigned char bit)
 663 {
 664         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
 665 }
 666
 667 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
 668 {
 669         u32 val;
 670
 671         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
 672                 if (msec-- == 0)
 673                         return false;
 674                 udelay(1000);
 675         }
 676         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
 677
 678         return true;
 679 }
 680
 681 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 682                                  unsigned char addr)
 683 {
 684         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
 685         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
 686         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
 687                     HDMI_PHY_I2CM_DATAO_1_ADDR);
 688         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
 689                     HDMI_PHY_I2CM_DATAO_0_ADDR);
 690         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
 691                     HDMI_PHY_I2CM_OPERATION_ADDR);
 692         hdmi_phy_wait_i2c_done(hdmi, 1000);
 693 }
 694
 695 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 696                               unsigned char addr)
 697 {
 698         __hdmi_phy_i2c_write(hdmi, data, addr);
 699         return 0;
 700 }
 701
 702 static void dw_hdmi_phy_enable_power(struct dw_hdmi *hdmi, u8 enable)
 703 {
 704         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 705                          HDMI_PHY_CONF0_PDZ_OFFSET,
 706                          HDMI_PHY_CONF0_PDZ_MASK);
 707 }
 708
 709 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
 710 {
 711         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 712                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
 713                          HDMI_PHY_CONF0_ENTMDS_MASK);
 714 }
 715
 716 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
 717 {
 718         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 719                          HDMI_PHY_CONF0_SPARECTRL_OFFSET,
 720                          HDMI_PHY_CONF0_SPARECTRL_MASK);
 721 }
 722
 723 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
 724 {
 725         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 726                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
 727                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
 728 }
 729
 730 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
 731 {
 732         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 733                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
 734                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
 735 }
 736
 737 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
 738 {
 739         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 740                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
 741                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
 742 }
 743
 744 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
 745 {
 746         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 747                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
 748                          HDMI_PHY_CONF0_SELDIPIF_MASK);
 749 }
 750
 751 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
 752                               unsigned char res, int cscon)
 753 {
 754         unsigned res_idx;
 755         u8 val, msec;
 756         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
 757         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
 758         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
 759         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
 760
 761         if (prep)
 762                 return -EINVAL;
 763
 764         switch (res) {
 765         case 0: /* color resolution 0 is 8 bit colour depth */
 766         case 8:
 767                 res_idx = DW_HDMI_RES_8;
 768                 break;
 769         case 10:
 770                 res_idx = DW_HDMI_RES_10;
 771                 break;
 772         case 12:
 773                 res_idx = DW_HDMI_RES_12;
 774                 break;
 775         default:
 776                 return -EINVAL;
 777         }
 778
 779         /* PLL/MPLL Cfg - always match on final entry */
 780         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
 781                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 782                     mpll_config->mpixelclock)
 783                         break;
 784
 785         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
 786                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 787                     curr_ctrl->mpixelclock)
 788                         break;
 789
 790         for (; phy_config->mpixelclock != ~0UL; phy_config++)
 791                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 792                     phy_config->mpixelclock)
 793                         break;
 794
 795         if (mpll_config->mpixelclock == ~0UL ||
 796             curr_ctrl->mpixelclock == ~0UL ||
 797             phy_config->mpixelclock == ~0UL) {
 798                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
 799                         hdmi->hdmi_data.video_mode.mpixelclock);
 800                 return -EINVAL;
 801         }
 802
 803         /* Enable csc path */
 804         if (cscon)
 805                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
 806         else
 807                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
 808
 809         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
 810
 811         /* gen2 tx power off */
 812         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
 813
 814         /* gen2 pddq */
 815         dw_hdmi_phy_gen2_pddq(hdmi, 1);
 816
 817         /* PHY reset */
 818         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
 819         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
 820
 821         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
 822
 823         hdmi_phy_test_clear(hdmi, 1);
 824         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
 825                     HDMI_PHY_I2CM_SLAVE_ADDR);
 826         hdmi_phy_test_clear(hdmi, 0);
 827
 828         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
 829         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
 830
 831         /* CURRCTRL */
 832         hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
 833
 834         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
 835         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
 836
 837         hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19);  /* TXTERM */
 838         hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
 839         hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
 840
 841         /* REMOVE CLK TERM */
 842         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
 843
 844         dw_hdmi_phy_enable_power(hdmi, 1);
 845
 846         /* toggle TMDS enable */
 847         dw_hdmi_phy_enable_tmds(hdmi, 0);
 848         dw_hdmi_phy_enable_tmds(hdmi, 1);
 849
 850         /* gen2 tx power on */
 851         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
 852         dw_hdmi_phy_gen2_pddq(hdmi, 0);
 853
 854         if (hdmi->dev_type == RK3288_HDMI)
 855                 dw_hdmi_phy_enable_spare(hdmi, 1);
 856
 857         /*Wait for PHY PLL lock */
 858         msec = 5;
 859         do {
 860                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
 861                 if (!val)
 862                         break;
 863
 864                 if (msec == 0) {
 865                         dev_err(hdmi->dev, "PHY PLL not locked\n");
 866                         return -ETIMEDOUT;
 867                 }
 868
 869                 udelay(1000);
 870                 msec--;
 871         } while (1);
 872
 873         return 0;
 874 }
 875
 876 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
 877 {
 878         int i, ret;
 879         bool cscon = false;
 880
 881         /*check csc whether needed activated in HDMI mode */
 882         cscon = (is_color_space_conversion(hdmi) &&
 883                         !hdmi->hdmi_data.video_mode.mdvi);
 884
 885         /* HDMI Phy spec says to do the phy initialization sequence twice */
 886         for (i = 0; i < 2; i++) {
 887                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
 888                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
 889                 dw_hdmi_phy_enable_tmds(hdmi, 0);
 890                 dw_hdmi_phy_enable_power(hdmi, 0);
 891
 892                 /* Enable CSC */
 893                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
 894                 if (ret)
 895                         return ret;
 896         }
 897
 898         hdmi->phy_enabled = true;
 899         return 0;
 900 }
 901
 902 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
 903 {
 904         u8 de;
 905
 906         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
 907                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
 908         else
 909                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
 910
 911         /* disable rx detect */
 912         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
 913                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
 914
 915         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
 916
 917         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
 918                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
 919 }
 920
 921 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
 922 {
 923         struct hdmi_avi_infoframe frame;
 924         u8 val;
 925
 926         /* Initialise info frame from DRM mode */
 927         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 928
 929         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
 930                 frame.colorspace = HDMI_COLORSPACE_YUV444;
 931         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
 932                 frame.colorspace = HDMI_COLORSPACE_YUV422;
 933         else
 934                 frame.colorspace = HDMI_COLORSPACE_RGB;
 935
 936         /* Set up colorimetry */
 937         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
 938                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
 939                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
 940                         frame.extended_colorimetry =
 941                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 942                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
 943                         frame.extended_colorimetry =
 944                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
 945         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
 946                 frame.colorimetry = hdmi->hdmi_data.colorimetry;
 947                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 948         } else { /* Carries no data */
 949                 frame.colorimetry = HDMI_COLORIMETRY_NONE;
 950                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 951         }
 952
 953         frame.scan_mode = HDMI_SCAN_MODE_NONE;
 954
 955         /*
 956          * The Designware IP uses a different byte format from standard
 957          * AVI info frames, though generally the bits are in the correct
 958          * bytes.
 959          */
 960
 961         /*
 962          * AVI data byte 1 differences: Colorspace in bits 4,5 rather than 5,6,
 963          * active aspect present in bit 6 rather than 4.
 964          */
 965         val = (frame.colorspace & 3) << 4 | (frame.scan_mode & 0x3);
 966         if (frame.active_aspect & 15)
 967                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
 968         if (frame.top_bar || frame.bottom_bar)
 969                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
 970         if (frame.left_bar || frame.right_bar)
 971                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
 972         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
 973
 974         /* AVI data byte 2 differences: none */
 975         val = ((frame.colorimetry & 0x3) << 6) |
 976               ((frame.picture_aspect & 0x3) << 4) |
 977               (frame.active_aspect & 0xf);
 978         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
 979
 980         /* AVI data byte 3 differences: none */
 981         val = ((frame.extended_colorimetry & 0x7) << 4) |
 982               ((frame.quantization_range & 0x3) << 2) |
 983               (frame.nups & 0x3);
 984         if (frame.itc)
 985                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
 986         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
 987
 988         /* AVI data byte 4 differences: none */
 989         val = frame.video_code & 0x7f;
 990         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
 991
 992         /* AVI Data Byte 5- set up input and output pixel repetition */
 993         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
 994                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
 995                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
 996                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
 997                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
 998                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
 999         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1000
1001         /*
1002          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1003          * ycc range in bits 2,3 rather than 6,7
1004          */
1005         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1006               (frame.content_type & 0x3);
1007         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1008
1009         /* AVI Data Bytes 6-13 */
1010         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1011         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1012         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1013         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1014         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1015         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1016         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1017         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1018 }
1019
1020 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1021                              const struct drm_display_mode *mode)
1022 {
1023         u8 inv_val;
1024         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1025         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1026
1027         vmode->mhsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PHSYNC);
1028         vmode->mvsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PVSYNC);
1029         vmode->minterlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1030         vmode->mpixelclock = mode->clock * 1000;
1031
1032         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1033
1034         /* Set up HDMI_FC_INVIDCONF */
1035         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1036                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1037                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1038
1039         inv_val |= (vmode->mvsyncpolarity ?
1040                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1041                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
1042
1043         inv_val |= (vmode->mhsyncpolarity ?
1044                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1045                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
1046
1047         inv_val |= (vmode->mdataenablepolarity ?
1048                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1049                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1050
1051         if (hdmi->vic == 39)
1052                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1053         else
1054                 inv_val |= (vmode->minterlaced ?
1055                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1056                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW);
1057
1058         inv_val |= (vmode->minterlaced ?
1059                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1060                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE);
1061
1062         inv_val |= (vmode->mdvi ?
1063                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE :
1064                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE);
1065
1066         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1067
1068         /* Set up horizontal active pixel width */
1069         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1070         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1071
1072         /* Set up vertical active lines */
1073         hdmi_writeb(hdmi, mode->vdisplay >> 8, HDMI_FC_INVACTV1);
1074         hdmi_writeb(hdmi, mode->vdisplay, HDMI_FC_INVACTV0);
1075
1076         /* Set up horizontal blanking pixel region width */
1077         hblank = mode->htotal - mode->hdisplay;
1078         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1079         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1080
1081         /* Set up vertical blanking pixel region width */
1082         vblank = mode->vtotal - mode->vdisplay;
1083         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1084
1085         /* Set up HSYNC active edge delay width (in pixel clks) */
1086         h_de_hs = mode->hsync_start - mode->hdisplay;
1087         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1088         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1089
1090         /* Set up VSYNC active edge delay (in lines) */
1091         v_de_vs = mode->vsync_start - mode->vdisplay;
1092         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1093
1094         /* Set up HSYNC active pulse width (in pixel clks) */
1095         hsync_len = mode->hsync_end - mode->hsync_start;
1096         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1097         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1098
1099         /* Set up VSYNC active edge delay (in lines) */
1100         vsync_len = mode->vsync_end - mode->vsync_start;
1101         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1102 }
1103
1104 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1105 {
1106         if (!hdmi->phy_enabled)
1107                 return;
1108
1109         dw_hdmi_phy_enable_tmds(hdmi, 0);
1110         dw_hdmi_phy_enable_power(hdmi, 0);
1111
1112         hdmi->phy_enabled = false;
1113 }
1114
1115 /* HDMI Initialization Step B.4 */
1116 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1117 {
1118         u8 clkdis;
1119
1120         /* control period minimum duration */
1121         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1122         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1123         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1124
1125         /* Set to fill TMDS data channels */
1126         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1127         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1128         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1129
1130         /* Enable pixel clock and tmds data path */
1131         clkdis = 0x7F;
1132         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1133         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1134
1135         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1136         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1137
1138         /* Enable csc path */
1139         if (is_color_space_conversion(hdmi)) {
1140                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1141                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1142         }
1143 }
1144
1145 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1146 {
1147         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1148 }
1149
1150 /* Workaround to clear the overflow condition */
1151 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1152 {
1153         int count;
1154         u8 val;
1155
1156         /* TMDS software reset */
1157         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1158
1159         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1160         if (hdmi->dev_type == IMX6DL_HDMI) {
1161                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1162                 return;
1163         }
1164
1165         for (count = 0; count < 4; count++)
1166                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1167 }
1168
1169 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1170 {
1171         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1172         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1173 }
1174
1175 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1176 {
1177         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1178                     HDMI_IH_MUTE_FC_STAT2);
1179 }
1180
1181 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1182 {
1183         int ret;
1184
1185         hdmi_disable_overflow_interrupts(hdmi);
1186
1187         hdmi->vic = drm_match_cea_mode(mode);
1188
1189         if (!hdmi->vic) {
1190                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1191                 hdmi->hdmi_data.video_mode.mdvi = true;
1192         } else {
1193                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1194                 hdmi->hdmi_data.video_mode.mdvi = false;
1195         }
1196
1197         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1198             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1199             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1200             (hdmi->vic == 17) || (hdmi->vic == 18))
1201                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1202         else
1203                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1204
1205         if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
1206             (hdmi->vic == 12) || (hdmi->vic == 13) ||
1207             (hdmi->vic == 14) || (hdmi->vic == 15) ||
1208             (hdmi->vic == 25) || (hdmi->vic == 26) ||
1209             (hdmi->vic == 27) || (hdmi->vic == 28) ||
1210             (hdmi->vic == 29) || (hdmi->vic == 30) ||
1211             (hdmi->vic == 35) || (hdmi->vic == 36) ||
1212             (hdmi->vic == 37) || (hdmi->vic == 38))
1213                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1214         else
1215                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1216
1217         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1218
1219         /* TODO: Get input format from IPU (via FB driver interface) */
1220         hdmi->hdmi_data.enc_in_format = RGB;
1221
1222         hdmi->hdmi_data.enc_out_format = RGB;
1223
1224         hdmi->hdmi_data.enc_color_depth = 8;
1225         hdmi->hdmi_data.pix_repet_factor = 0;
1226         hdmi->hdmi_data.hdcp_enable = 0;
1227         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1228
1229         /* HDMI Initialization Step B.1 */
1230         hdmi_av_composer(hdmi, mode);
1231
1232         /* HDMI Initializateion Step B.2 */
1233         ret = dw_hdmi_phy_init(hdmi);
1234         if (ret)
1235                 return ret;
1236
1237         /* HDMI Initialization Step B.3 */
1238         dw_hdmi_enable_video_path(hdmi);
1239
1240         /* not for DVI mode */
1241         if (hdmi->hdmi_data.video_mode.mdvi) {
1242                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1243         } else {
1244                 dev_dbg(hdmi->dev, "%s CEA mode\n", __func__);
1245
1246                 /* HDMI Initialization Step E - Configure audio */
1247                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1248                 hdmi_enable_audio_clk(hdmi);
1249
1250                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1251                 hdmi_config_AVI(hdmi, mode);
1252         }
1253
1254         hdmi_video_packetize(hdmi);
1255         hdmi_video_csc(hdmi);
1256         hdmi_video_sample(hdmi);
1257         hdmi_tx_hdcp_config(hdmi);
1258
1259         dw_hdmi_clear_overflow(hdmi);
1260         if (hdmi->cable_plugin && !hdmi->hdmi_data.video_mode.mdvi)
1261                 hdmi_enable_overflow_interrupts(hdmi);
1262
1263         return 0;
1264 }
1265
1266 /* Wait until we are registered to enable interrupts */
1267 static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
1268 {
1269         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1270                     HDMI_PHY_I2CM_INT_ADDR);
1271
1272         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1273                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1274                     HDMI_PHY_I2CM_CTLINT_ADDR);
1275
1276         /* enable cable hot plug irq */
1277         hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
1278
1279         /* Clear Hotplug interrupts */
1280         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1281
1282         return 0;
1283 }
1284
1285 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1286 {
1287         u8 ih_mute;
1288
1289         /*
1290          * Boot up defaults are:
1291          * HDMI_IH_MUTE   = 0x03 (disabled)
1292          * HDMI_IH_MUTE_* = 0x00 (enabled)
1293          *
1294          * Disable top level interrupt bits in HDMI block
1295          */
1296         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1297                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1298                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1299
1300         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1301
1302         /* by default mask all interrupts */
1303         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1304         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1305         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1306         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1307         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1308         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1309         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1310         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1311         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1312         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1313         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1314         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1315         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1316         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1317         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1318
1319         /* Disable interrupts in the IH_MUTE_* registers */
1320         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1321         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1322         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1323         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1324         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1325         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1326         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1327         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1328         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1329         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1330
1331         /* Enable top level interrupt bits in HDMI block */
1332         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1333                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1334         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1335 }
1336
1337 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1338 {
1339         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1340 }
1341
1342 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1343 {
1344         dw_hdmi_phy_disable(hdmi);
1345 }
1346
1347 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1348                                     struct drm_display_mode *orig_mode,
1349                                     struct drm_display_mode *mode)
1350 {
1351         struct dw_hdmi *hdmi = bridge->driver_private;
1352
1353         dw_hdmi_setup(hdmi, mode);
1354
1355         /* Store the display mode for plugin/DKMS poweron events */
1356         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1357 }
1358
1359 static bool dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1360                                       const struct drm_display_mode *mode,
1361                                       struct drm_display_mode *adjusted_mode)
1362 {
1363         return true;
1364 }
1365
1366 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1367 {
1368         struct dw_hdmi *hdmi = bridge->driver_private;
1369
1370         dw_hdmi_poweroff(hdmi);
1371 }
1372
1373 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1374 {
1375         struct dw_hdmi *hdmi = bridge->driver_private;
1376
1377         dw_hdmi_poweron(hdmi);
1378 }
1379
1380 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1381 {
1382         /* do nothing */
1383 }
1384
1385 static enum drm_connector_status
1386 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1387 {
1388         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1389                                              connector);
1390
1391         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1392                 connector_status_connected : connector_status_disconnected;
1393 }
1394
1395 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1396 {
1397         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1398                                              connector);
1399         struct edid *edid;
1400         int ret;
1401
1402         if (!hdmi->ddc)
1403                 return 0;
1404
1405         edid = drm_get_edid(connector, hdmi->ddc);
1406         if (edid) {
1407                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1408                         edid->width_cm, edid->height_cm);
1409
1410                 drm_mode_connector_update_edid_property(connector, edid);
1411                 ret = drm_add_edid_modes(connector, edid);
1412                 kfree(edid);
1413         } else {
1414                 dev_dbg(hdmi->dev, "failed to get edid\n");
1415         }
1416
1417         return 0;
1418 }
1419
1420 static enum drm_mode_status
1421 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1422                              struct drm_display_mode *mode)
1423 {
1424         struct dw_hdmi *hdmi = container_of(connector,
1425                                            struct dw_hdmi, connector);
1426         enum drm_mode_status mode_status = MODE_OK;
1427
1428         if (hdmi->plat_data->mode_valid)
1429                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1430
1431         return mode_status;
1432 }
1433
1434 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1435                                                            *connector)
1436 {
1437         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1438                                              connector);
1439
1440         return hdmi->encoder;
1441 }
1442
1443 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1444 {
1445         drm_connector_unregister(connector);
1446         drm_connector_cleanup(connector);
1447 }
1448
1449 static struct drm_connector_funcs dw_hdmi_connector_funcs = {
1450         .dpms = drm_helper_connector_dpms,
1451         .fill_modes = drm_helper_probe_single_connector_modes,
1452         .detect = dw_hdmi_connector_detect,
1453         .destroy = dw_hdmi_connector_destroy,
1454 };
1455
1456 static struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1457         .get_modes = dw_hdmi_connector_get_modes,
1458         .mode_valid = dw_hdmi_connector_mode_valid,
1459         .best_encoder = dw_hdmi_connector_best_encoder,
1460 };
1461
1462 struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1463         .enable = dw_hdmi_bridge_enable,
1464         .disable = dw_hdmi_bridge_disable,
1465         .pre_enable = dw_hdmi_bridge_nop,
1466         .post_disable = dw_hdmi_bridge_nop,
1467         .mode_set = dw_hdmi_bridge_mode_set,
1468         .mode_fixup = dw_hdmi_bridge_mode_fixup,
1469 };
1470
1471 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1472 {
1473         struct dw_hdmi *hdmi = dev_id;
1474         u8 intr_stat;
1475
1476         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1477         if (intr_stat)
1478                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1479
1480         return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
1481 }
1482
1483 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1484 {
1485         struct dw_hdmi *hdmi = dev_id;
1486         u8 intr_stat;
1487         u8 phy_int_pol;
1488
1489         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1490
1491         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1492
1493         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1494                 if (phy_int_pol & HDMI_PHY_HPD) {
1495                         dev_dbg(hdmi->dev, "EVENT=plugin\n");
1496
1497                         hdmi_modb(hdmi, 0, HDMI_PHY_HPD, HDMI_PHY_POL0);
1498
1499                         dw_hdmi_poweron(hdmi);
1500                 } else {
1501                         dev_dbg(hdmi->dev, "EVENT=plugout\n");
1502
1503                         hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD,
1504                                   HDMI_PHY_POL0);
1505
1506                         dw_hdmi_poweroff(hdmi);
1507                 }
1508                 drm_helper_hpd_irq_event(hdmi->connector.dev);
1509         }
1510
1511         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1512         hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1513
1514         return IRQ_HANDLED;
1515 }
1516
1517 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
1518 {
1519         struct drm_encoder *encoder = hdmi->encoder;
1520         struct drm_bridge *bridge;
1521         int ret;
1522
1523         bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1524         if (!bridge) {
1525                 DRM_ERROR("Failed to allocate drm bridge\n");
1526                 return -ENOMEM;
1527         }
1528
1529         hdmi->bridge = bridge;
1530         bridge->driver_private = hdmi;
1531         bridge->funcs = &dw_hdmi_bridge_funcs;
1532         ret = drm_bridge_attach(drm, bridge);
1533         if (ret) {
1534                 DRM_ERROR("Failed to initialize bridge with drm\n");
1535                 return -EINVAL;
1536         }
1537
1538         encoder->bridge = bridge;
1539         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1540
1541         drm_connector_helper_add(&hdmi->connector,
1542                                  &dw_hdmi_connector_helper_funcs);
1543         drm_connector_init(drm, &hdmi->connector, &dw_hdmi_connector_funcs,
1544                            DRM_MODE_CONNECTOR_HDMIA);
1545
1546         hdmi->connector.encoder = encoder;
1547
1548         drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
1549
1550         return 0;
1551 }
1552
1553 int dw_hdmi_bind(struct device *dev, struct device *master,
1554                  void *data, struct drm_encoder *encoder,
1555                  struct resource *iores, int irq,
1556                  const struct dw_hdmi_plat_data *plat_data)
1557 {
1558         struct drm_device *drm = data;
1559         struct device_node *np = dev->of_node;
1560         struct device_node *ddc_node;
1561         struct dw_hdmi *hdmi;
1562         int ret;
1563         u32 val = 1;
1564
1565         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1566         if (!hdmi)
1567                 return -ENOMEM;
1568
1569         hdmi->plat_data = plat_data;
1570         hdmi->dev = dev;
1571         hdmi->dev_type = plat_data->dev_type;
1572         hdmi->sample_rate = 48000;
1573         hdmi->ratio = 100;
1574         hdmi->encoder = encoder;
1575
1576         mutex_init(&hdmi->audio_mutex);
1577
1578         of_property_read_u32(np, "reg-io-width", &val);
1579
1580         switch (val) {
1581         case 4:
1582                 hdmi->write = dw_hdmi_writel;
1583                 hdmi->read = dw_hdmi_readl;
1584                 break;
1585         case 1:
1586                 hdmi->write = dw_hdmi_writeb;
1587                 hdmi->read = dw_hdmi_readb;
1588                 break;
1589         default:
1590                 dev_err(dev, "reg-io-width must be 1 or 4\n");
1591                 return -EINVAL;
1592         }
1593
1594         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
1595         if (ddc_node) {
1596                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1597                 of_node_put(ddc_node);
1598                 if (!hdmi->ddc) {
1599                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
1600                         return -EPROBE_DEFER;
1601                 }
1602
1603         } else {
1604                 dev_dbg(hdmi->dev, "no ddc property found\n");
1605         }
1606
1607         hdmi->regs = devm_ioremap_resource(dev, iores);
1608         if (IS_ERR(hdmi->regs))
1609                 return PTR_ERR(hdmi->regs);
1610
1611         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1612         if (IS_ERR(hdmi->isfr_clk)) {
1613                 ret = PTR_ERR(hdmi->isfr_clk);
1614                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
1615                 return ret;
1616         }
1617
1618         ret = clk_prepare_enable(hdmi->isfr_clk);
1619         if (ret) {
1620                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
1621                 return ret;
1622         }
1623
1624         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1625         if (IS_ERR(hdmi->iahb_clk)) {
1626                 ret = PTR_ERR(hdmi->iahb_clk);
1627                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
1628                 goto err_isfr;
1629         }
1630
1631         ret = clk_prepare_enable(hdmi->iahb_clk);
1632         if (ret) {
1633                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
1634                 goto err_isfr;
1635         }
1636
1637         /* Product and revision IDs */
1638         dev_info(dev,
1639                  "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1640                  hdmi_readb(hdmi, HDMI_DESIGN_ID),
1641                  hdmi_readb(hdmi, HDMI_REVISION_ID),
1642                  hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1643                  hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
1644
1645         initialize_hdmi_ih_mutes(hdmi);
1646
1647         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
1648                                         dw_hdmi_irq, IRQF_SHARED,
1649                                         dev_name(dev), hdmi);
1650         if (ret)
1651                 goto err_iahb;
1652
1653         /*
1654          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1655          * N and cts values before enabling phy
1656          */
1657         hdmi_init_clk_regenerator(hdmi);
1658
1659         /*
1660          * Configure registers related to HDMI interrupt
1661          * generation before registering IRQ.
1662          */
1663         hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0);
1664
1665         /* Clear Hotplug interrupts */
1666         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1667
1668         ret = dw_hdmi_fb_registered(hdmi);
1669         if (ret)
1670                 goto err_iahb;
1671
1672         ret = dw_hdmi_register(drm, hdmi);
1673         if (ret)
1674                 goto err_iahb;
1675
1676         /* Unmute interrupts */
1677         hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1678
1679         dev_set_drvdata(dev, hdmi);
1680
1681         return 0;
1682
1683 err_iahb:
1684         clk_disable_unprepare(hdmi->iahb_clk);
1685 err_isfr:
1686         clk_disable_unprepare(hdmi->isfr_clk);
1687
1688         return ret;
1689 }
1690 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
1691
1692 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
1693 {
1694         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
1695
1696         /* Disable all interrupts */
1697         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1698
1699         hdmi->connector.funcs->destroy(&hdmi->connector);
1700         hdmi->encoder->funcs->destroy(hdmi->encoder);
1701
1702         clk_disable_unprepare(hdmi->iahb_clk);
1703         clk_disable_unprepare(hdmi->isfr_clk);
1704         i2c_put_adapter(hdmi->ddc);
1705 }
1706 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
1707
1708 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1709 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
1710 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
1711 MODULE_DESCRIPTION("DW HDMI transmitter driver");
1712 MODULE_LICENSE("GPL");
1713 MODULE_ALIAS("platform:dw-hdmi");