drivers/gpu/drm/bridge/dw_hdmi.c

   1 /*
   2  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * Designware High-Definition Multimedia Interface (HDMI) driver
  10  *
  11  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  12  */
  13 #include <linux/module.h>
  14 #include <linux/irq.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/hdmi.h>
  19 #include <linux/mutex.h>
  20 #include <linux/of_device.h>
  21 #include <linux/spinlock.h>
  22
  23 #include <drm/drm_of.h>
  24 #include <drm/drmP.h>
  25 #include <drm/drm_crtc_helper.h>
  26 #include <drm/drm_edid.h>
  27 #include <drm/drm_encoder_slave.h>
  28 #include <drm/bridge/dw_hdmi.h>
  29
  30 #include "dw_hdmi.h"
  31
  32 #define HDMI_EDID_LEN           512
  33
  34 #define RGB                     0
  35 #define YCBCR444                1
  36 #define YCBCR422_16BITS         2
  37 #define YCBCR422_8BITS          3
  38 #define XVYCC444                4
  39
  40 enum hdmi_datamap {
  41         RGB444_8B = 0x01,
  42         RGB444_10B = 0x03,
  43         RGB444_12B = 0x05,
  44         RGB444_16B = 0x07,
  45         YCbCr444_8B = 0x09,
  46         YCbCr444_10B = 0x0B,
  47         YCbCr444_12B = 0x0D,
  48         YCbCr444_16B = 0x0F,
  49         YCbCr422_8B = 0x16,
  50         YCbCr422_10B = 0x14,
  51         YCbCr422_12B = 0x12,
  52 };
  53
  54 static const u16 csc_coeff_default[3][4] = {
  55         { 0x2000, 0x0000, 0x0000, 0x0000 },
  56         { 0x0000, 0x2000, 0x0000, 0x0000 },
  57         { 0x0000, 0x0000, 0x2000, 0x0000 }
  58 };
  59
  60 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
  61         { 0x2000, 0x6926, 0x74fd, 0x010e },
  62         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
  63         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
  64 };
  65
  66 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
  67         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
  68         { 0x2000, 0x3264, 0x0000, 0x7e6d },
  69         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
  70 };
  71
  72 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
  73         { 0x2591, 0x1322, 0x074b, 0x0000 },
  74         { 0x6535, 0x2000, 0x7acc, 0x0200 },
  75         { 0x6acd, 0x7534, 0x2000, 0x0200 }
  76 };
  77
  78 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
  79         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
  80         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
  81         { 0x6756, 0x78ab, 0x2000, 0x0200 }
  82 };
  83
  84 struct hdmi_vmode {
  85         bool mdataenablepolarity;
  86
  87         unsigned int mpixelclock;
  88         unsigned int mpixelrepetitioninput;
  89         unsigned int mpixelrepetitionoutput;
  90 };
  91
  92 struct hdmi_data_info {
  93         unsigned int enc_in_format;
  94         unsigned int enc_out_format;
  95         unsigned int enc_color_depth;
  96         unsigned int colorimetry;
  97         unsigned int pix_repet_factor;
  98         unsigned int hdcp_enable;
  99         struct hdmi_vmode video_mode;
 100 };
 101
 102 struct dw_hdmi {
 103         struct drm_connector connector;
 104         struct drm_encoder *encoder;
 105         struct drm_bridge *bridge;
 106
 107         enum dw_hdmi_devtype dev_type;
 108         struct device *dev;
 109         struct clk *isfr_clk;
 110         struct clk *iahb_clk;
 111
 112         struct hdmi_data_info hdmi_data;
 113         const struct dw_hdmi_plat_data *plat_data;
 114
 115         int vic;
 116
 117         u8 edid[HDMI_EDID_LEN];
 118         bool cable_plugin;
 119
 120         bool phy_enabled;
 121         struct drm_display_mode previous_mode;
 122
 123         struct i2c_adapter *ddc;
 124         void __iomem *regs;
 125         bool sink_is_hdmi;
 126         bool sink_has_audio;
 127
 128         spinlock_t audio_lock;
 129         struct mutex audio_mutex;
 130         unsigned int sample_rate;
 131         unsigned int audio_cts;
 132         unsigned int audio_n;
 133         bool audio_enable;
 134         int ratio;
 135
 136         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
 137         u8 (*read)(struct dw_hdmi *hdmi, int offset);
 138 };
 139
 140 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
 141 {
 142         writel(val, hdmi->regs + (offset << 2));
 143 }
 144
 145 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
 146 {
 147         return readl(hdmi->regs + (offset << 2));
 148 }
 149
 150 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 151 {
 152         writeb(val, hdmi->regs + offset);
 153 }
 154
 155 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
 156 {
 157         return readb(hdmi->regs + offset);
 158 }
 159
 160 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 161 {
 162         hdmi->write(hdmi, val, offset);
 163 }
 164
 165 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 166 {
 167         return hdmi->read(hdmi, offset);
 168 }
 169
 170 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 171 {
 172         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 173
 174         val |= data & mask;
 175         hdmi_writeb(hdmi, val, reg);
 176 }
 177
 178 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 179                              u8 shift, u8 mask)
 180 {
 181         hdmi_modb(hdmi, data << shift, mask, reg);
 182 }
 183
 184 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 185                            unsigned int n)
 186 {
 187         /* Must be set/cleared first */
 188         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 189
 190         /* nshift factor = 0 */
 191         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 192
 193         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 194                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 195         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 196         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 197
 198         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 199         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 200         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 201 }
 202
 203 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
 204                                    unsigned int ratio)
 205 {
 206         unsigned int n = (128 * freq) / 1000;
 207
 208         switch (freq) {
 209         case 32000:
 210                 if (pixel_clk == 25170000)
 211                         n = (ratio == 150) ? 9152 : 4576;
 212                 else if (pixel_clk == 27020000)
 213                         n = (ratio == 150) ? 8192 : 4096;
 214                 else if (pixel_clk == 74170000 || pixel_clk == 148350000)
 215                         n = 11648;
 216                 else
 217                         n = 4096;
 218                 break;
 219
 220         case 44100:
 221                 if (pixel_clk == 25170000)
 222                         n = 7007;
 223                 else if (pixel_clk == 74170000)
 224                         n = 17836;
 225                 else if (pixel_clk == 148350000)
 226                         n = (ratio == 150) ? 17836 : 8918;
 227                 else
 228                         n = 6272;
 229                 break;
 230
 231         case 48000:
 232                 if (pixel_clk == 25170000)
 233                         n = (ratio == 150) ? 9152 : 6864;
 234                 else if (pixel_clk == 27020000)
 235                         n = (ratio == 150) ? 8192 : 6144;
 236                 else if (pixel_clk == 74170000)
 237                         n = 11648;
 238                 else if (pixel_clk == 148350000)
 239                         n = (ratio == 150) ? 11648 : 5824;
 240                 else
 241                         n = 6144;
 242                 break;
 243
 244         case 88200:
 245                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
 246                 break;
 247
 248         case 96000:
 249                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
 250                 break;
 251
 252         case 176400:
 253                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
 254                 break;
 255
 256         case 192000:
 257                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
 258                 break;
 259
 260         default:
 261                 break;
 262         }
 263
 264         return n;
 265 }
 266
 267 static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
 268                                      unsigned int ratio)
 269 {
 270         unsigned int cts = 0;
 271
 272         pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq,
 273                  pixel_clk, ratio);
 274
 275         switch (freq) {
 276         case 32000:
 277                 if (pixel_clk == 297000000) {
 278                         cts = 222750;
 279                         break;
 280                 }
 281         case 48000:
 282         case 96000:
 283         case 192000:
 284                 switch (pixel_clk) {
 285                 case 25200000:
 286                 case 27000000:
 287                 case 54000000:
 288                 case 74250000:
 289                 case 148500000:
 290                         cts = pixel_clk / 1000;
 291                         break;
 292                 case 297000000:
 293                         cts = 247500;
 294                         break;
 295                 /*
 296                  * All other TMDS clocks are not supported by
 297                  * DWC_hdmi_tx. The TMDS clocks divided or
 298                  * multiplied by 1,001 coefficients are not
 299                  * supported.
 300                  */
 301                 default:
 302                         break;
 303                 }
 304                 break;
 305         case 44100:
 306         case 88200:
 307         case 176400:
 308                 switch (pixel_clk) {
 309                 case 25200000:
 310                         cts = 28000;
 311                         break;
 312                 case 27000000:
 313                         cts = 30000;
 314                         break;
 315                 case 54000000:
 316                         cts = 60000;
 317                         break;
 318                 case 74250000:
 319                         cts = 82500;
 320                         break;
 321                 case 148500000:
 322                         cts = 165000;
 323                         break;
 324                 case 297000000:
 325                         cts = 247500;
 326                         break;
 327                 default:
 328                         break;
 329                 }
 330                 break;
 331         default:
 332                 break;
 333         }
 334         if (ratio == 100)
 335                 return cts;
 336         return (cts * ratio) / 100;
 337 }
 338
 339 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 340         unsigned long pixel_clk, unsigned int sample_rate, unsigned int ratio)
 341 {
 342         unsigned int n, cts;
 343
 344         n = hdmi_compute_n(sample_rate, pixel_clk, ratio);
 345         cts = hdmi_compute_cts(sample_rate, pixel_clk, ratio);
 346         if (!cts) {
 347                 dev_err(hdmi->dev,
 348                         "%s: pixel clock/sample rate not supported: %luMHz / %ukHz\n",
 349                         __func__, pixel_clk, sample_rate);
 350         }
 351
 352         dev_dbg(hdmi->dev, "%s: samplerate=%ukHz ratio=%d pixelclk=%luMHz N=%d cts=%d\n",
 353                 __func__, sample_rate, ratio, pixel_clk, n, cts);
 354
 355         spin_lock_irq(&hdmi->audio_lock);
 356         hdmi->audio_n = n;
 357         hdmi->audio_cts = cts;
 358         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
 359         spin_unlock_irq(&hdmi->audio_lock);
 360 }
 361
 362 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 363 {
 364         mutex_lock(&hdmi->audio_mutex);
 365         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate,
 366                                  hdmi->ratio);
 367         mutex_unlock(&hdmi->audio_mutex);
 368 }
 369
 370 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 371 {
 372         mutex_lock(&hdmi->audio_mutex);
 373         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 374                                  hdmi->sample_rate, hdmi->ratio);
 375         mutex_unlock(&hdmi->audio_mutex);
 376 }
 377
 378 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 379 {
 380         mutex_lock(&hdmi->audio_mutex);
 381         hdmi->sample_rate = rate;
 382         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 383                                  hdmi->sample_rate, hdmi->ratio);
 384         mutex_unlock(&hdmi->audio_mutex);
 385 }
 386 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
 387
 388 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
 389 {
 390         unsigned long flags;
 391
 392         spin_lock_irqsave(&hdmi->audio_lock, flags);
 393         hdmi->audio_enable = true;
 394         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 395         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 396 }
 397 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
 398
 399 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 400 {
 401         unsigned long flags;
 402
 403         spin_lock_irqsave(&hdmi->audio_lock, flags);
 404         hdmi->audio_enable = false;
 405         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
 406         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 407 }
 408 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 409
 410 /*
 411  * this submodule is responsible for the video data synchronization.
 412  * for example, for RGB 4:4:4 input, the data map is defined as
 413  *                      pin{47~40} <==> R[7:0]
 414  *                      pin{31~24} <==> G[7:0]
 415  *                      pin{15~8}  <==> B[7:0]
 416  */
 417 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 418 {
 419         int color_format = 0;
 420         u8 val;
 421
 422         if (hdmi->hdmi_data.enc_in_format == RGB) {
 423                 if (hdmi->hdmi_data.enc_color_depth == 8)
 424                         color_format = 0x01;
 425                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 426                         color_format = 0x03;
 427                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 428                         color_format = 0x05;
 429                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 430                         color_format = 0x07;
 431                 else
 432                         return;
 433         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
 434                 if (hdmi->hdmi_data.enc_color_depth == 8)
 435                         color_format = 0x09;
 436                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 437                         color_format = 0x0B;
 438                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 439                         color_format = 0x0D;
 440                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 441                         color_format = 0x0F;
 442                 else
 443                         return;
 444         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 445                 if (hdmi->hdmi_data.enc_color_depth == 8)
 446                         color_format = 0x16;
 447                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 448                         color_format = 0x14;
 449                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 450                         color_format = 0x12;
 451                 else
 452                         return;
 453         }
 454
 455         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 456                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 457                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 458         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 459
 460         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 461         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 462                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 463                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 464         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 465         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 466         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 467         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 468         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 469         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 470         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 471 }
 472
 473 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 474 {
 475         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
 476 }
 477
 478 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 479 {
 480         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
 481                 return 0;
 482         if (hdmi->hdmi_data.enc_in_format == RGB ||
 483             hdmi->hdmi_data.enc_in_format == YCBCR444)
 484                 return 1;
 485         return 0;
 486 }
 487
 488 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 489 {
 490         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
 491                 return 0;
 492         if (hdmi->hdmi_data.enc_out_format == RGB ||
 493             hdmi->hdmi_data.enc_out_format == YCBCR444)
 494                 return 1;
 495         return 0;
 496 }
 497
 498 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 499 {
 500         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 501         unsigned i;
 502         u32 csc_scale = 1;
 503
 504         if (is_color_space_conversion(hdmi)) {
 505                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 506                         if (hdmi->hdmi_data.colorimetry ==
 507                                         HDMI_COLORIMETRY_ITU_601)
 508                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 509                         else
 510                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 511                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 512                         if (hdmi->hdmi_data.colorimetry ==
 513                                         HDMI_COLORIMETRY_ITU_601)
 514                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 515                         else
 516                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 517                         csc_scale = 0;
 518                 }
 519         }
 520
 521         /* The CSC registers are sequential, alternating MSB then LSB */
 522         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 523                 u16 coeff_a = (*csc_coeff)[0][i];
 524                 u16 coeff_b = (*csc_coeff)[1][i];
 525                 u16 coeff_c = (*csc_coeff)[2][i];
 526
 527                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 528                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 529                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 530                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 531                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 532                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 533         }
 534
 535         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 536                   HDMI_CSC_SCALE);
 537 }
 538
 539 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 540 {
 541         int color_depth = 0;
 542         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 543         int decimation = 0;
 544
 545         /* YCC422 interpolation to 444 mode */
 546         if (is_color_space_interpolation(hdmi))
 547                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 548         else if (is_color_space_decimation(hdmi))
 549                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 550
 551         if (hdmi->hdmi_data.enc_color_depth == 8)
 552                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 553         else if (hdmi->hdmi_data.enc_color_depth == 10)
 554                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 555         else if (hdmi->hdmi_data.enc_color_depth == 12)
 556                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 557         else if (hdmi->hdmi_data.enc_color_depth == 16)
 558                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 559         else
 560                 return;
 561
 562         /* Configure the CSC registers */
 563         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 564         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 565                   HDMI_CSC_SCALE);
 566
 567         dw_hdmi_update_csc_coeffs(hdmi);
 568 }
 569
 570 /*
 571  * HDMI video packetizer is used to packetize the data.
 572  * for example, if input is YCC422 mode or repeater is used,
 573  * data should be repacked this module can be bypassed.
 574  */
 575 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 576 {
 577         unsigned int color_depth = 0;
 578         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 579         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 580         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 581         u8 val, vp_conf;
 582
 583         if (hdmi_data->enc_out_format == RGB ||
 584             hdmi_data->enc_out_format == YCBCR444) {
 585                 if (!hdmi_data->enc_color_depth) {
 586                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 587                 } else if (hdmi_data->enc_color_depth == 8) {
 588                         color_depth = 4;
 589                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 590                 } else if (hdmi_data->enc_color_depth == 10) {
 591                         color_depth = 5;
 592                 } else if (hdmi_data->enc_color_depth == 12) {
 593                         color_depth = 6;
 594                 } else if (hdmi_data->enc_color_depth == 16) {
 595                         color_depth = 7;
 596                 } else {
 597                         return;
 598                 }
 599         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 600                 if (!hdmi_data->enc_color_depth ||
 601                     hdmi_data->enc_color_depth == 8)
 602                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 603                 else if (hdmi_data->enc_color_depth == 10)
 604                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 605                 else if (hdmi_data->enc_color_depth == 12)
 606                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 607                 else
 608                         return;
 609                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 610         } else {
 611                 return;
 612         }
 613
 614         /* set the packetizer registers */
 615         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 616                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 617                 ((hdmi_data->pix_repet_factor <<
 618                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 619                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 620         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 621
 622         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 623                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 624
 625         /* Data from pixel repeater block */
 626         if (hdmi_data->pix_repet_factor > 1) {
 627                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 628                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 629         } else { /* data from packetizer block */
 630                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 631                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 632         }
 633
 634         hdmi_modb(hdmi, vp_conf,
 635                   HDMI_VP_CONF_PR_EN_MASK |
 636                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 637
 638         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 639                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 640
 641         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 642
 643         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 644                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 645                           HDMI_VP_CONF_PP_EN_ENABLE |
 646                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 647         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 648                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 649                           HDMI_VP_CONF_PP_EN_DISABLE |
 650                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 651         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 652                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 653                           HDMI_VP_CONF_PP_EN_DISABLE |
 654                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 655         } else {
 656                 return;
 657         }
 658
 659         hdmi_modb(hdmi, vp_conf,
 660                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 661                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 662
 663         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 664                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 665                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 666                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 667
 668         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 669                   HDMI_VP_CONF);
 670 }
 671
 672 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
 673                                        unsigned char bit)
 674 {
 675         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 676                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 677 }
 678
 679 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
 680                                         unsigned char bit)
 681 {
 682         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
 683                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
 684 }
 685
 686 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
 687                                        unsigned char bit)
 688 {
 689         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
 690                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
 691 }
 692
 693 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
 694                                      unsigned char bit)
 695 {
 696         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
 697 }
 698
 699 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
 700                                       unsigned char bit)
 701 {
 702         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
 703 }
 704
 705 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
 706 {
 707         u32 val;
 708
 709         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
 710                 if (msec-- == 0)
 711                         return false;
 712                 udelay(1000);
 713         }
 714         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
 715
 716         return true;
 717 }
 718
 719 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 720                                  unsigned char addr)
 721 {
 722         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
 723         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
 724         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
 725                     HDMI_PHY_I2CM_DATAO_1_ADDR);
 726         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
 727                     HDMI_PHY_I2CM_DATAO_0_ADDR);
 728         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
 729                     HDMI_PHY_I2CM_OPERATION_ADDR);
 730         hdmi_phy_wait_i2c_done(hdmi, 1000);
 731 }
 732
 733 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 734                               unsigned char addr)
 735 {
 736         __hdmi_phy_i2c_write(hdmi, data, addr);
 737         return 0;
 738 }
 739
 740 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
 741 {
 742         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
 743                          HDMI_PHY_CONF0_PDZ_OFFSET,
 744                          HDMI_PHY_CONF0_PDZ_MASK);
 745 }
 746
 747 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
 748 {
 749         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 750                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
 751                          HDMI_PHY_CONF0_ENTMDS_MASK);
 752 }
 753
 754 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
 755 {
 756         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 757                          HDMI_PHY_CONF0_SPARECTRL_OFFSET,
 758                          HDMI_PHY_CONF0_SPARECTRL_MASK);
 759 }
 760
 761 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
 762 {
 763         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 764                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
 765                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
 766 }
 767
 768 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
 769 {
 770         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 771                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
 772                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
 773 }
 774
 775 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
 776 {
 777         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 778                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
 779                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
 780 }
 781
 782 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
 783 {
 784         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 785                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
 786                          HDMI_PHY_CONF0_SELDIPIF_MASK);
 787 }
 788
 789 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
 790                               unsigned char res, int cscon)
 791 {
 792         unsigned res_idx;
 793         u8 val, msec;
 794         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
 795         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
 796         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
 797         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
 798
 799         if (prep)
 800                 return -EINVAL;
 801
 802         switch (res) {
 803         case 0: /* color resolution 0 is 8 bit colour depth */
 804         case 8:
 805                 res_idx = DW_HDMI_RES_8;
 806                 break;
 807         case 10:
 808                 res_idx = DW_HDMI_RES_10;
 809                 break;
 810         case 12:
 811                 res_idx = DW_HDMI_RES_12;
 812                 break;
 813         default:
 814                 return -EINVAL;
 815         }
 816
 817         /* PLL/MPLL Cfg - always match on final entry */
 818         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
 819                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 820                     mpll_config->mpixelclock)
 821                         break;
 822
 823         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
 824                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 825                     curr_ctrl->mpixelclock)
 826                         break;
 827
 828         for (; phy_config->mpixelclock != ~0UL; phy_config++)
 829                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 830                     phy_config->mpixelclock)
 831                         break;
 832
 833         if (mpll_config->mpixelclock == ~0UL ||
 834             curr_ctrl->mpixelclock == ~0UL ||
 835             phy_config->mpixelclock == ~0UL) {
 836                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
 837                         hdmi->hdmi_data.video_mode.mpixelclock);
 838                 return -EINVAL;
 839         }
 840
 841         /* Enable csc path */
 842         if (cscon)
 843                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
 844         else
 845                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
 846
 847         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
 848
 849         /* gen2 tx power off */
 850         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
 851
 852         /* gen2 pddq */
 853         dw_hdmi_phy_gen2_pddq(hdmi, 1);
 854
 855         /* PHY reset */
 856         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
 857         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
 858
 859         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
 860
 861         hdmi_phy_test_clear(hdmi, 1);
 862         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
 863                     HDMI_PHY_I2CM_SLAVE_ADDR);
 864         hdmi_phy_test_clear(hdmi, 0);
 865
 866         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
 867         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
 868
 869         /* CURRCTRL */
 870         hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
 871
 872         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
 873         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
 874
 875         hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19);  /* TXTERM */
 876         hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
 877         hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
 878
 879         /* REMOVE CLK TERM */
 880         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
 881
 882         dw_hdmi_phy_enable_powerdown(hdmi, false);
 883
 884         /* toggle TMDS enable */
 885         dw_hdmi_phy_enable_tmds(hdmi, 0);
 886         dw_hdmi_phy_enable_tmds(hdmi, 1);
 887
 888         /* gen2 tx power on */
 889         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
 890         dw_hdmi_phy_gen2_pddq(hdmi, 0);
 891
 892         if (hdmi->dev_type == RK3288_HDMI)
 893                 dw_hdmi_phy_enable_spare(hdmi, 1);
 894
 895         /*Wait for PHY PLL lock */
 896         msec = 5;
 897         do {
 898                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
 899                 if (!val)
 900                         break;
 901
 902                 if (msec == 0) {
 903                         dev_err(hdmi->dev, "PHY PLL not locked\n");
 904                         return -ETIMEDOUT;
 905                 }
 906
 907                 udelay(1000);
 908                 msec--;
 909         } while (1);
 910
 911         return 0;
 912 }
 913
 914 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
 915 {
 916         int i, ret;
 917         bool cscon;
 918
 919         /*check csc whether needed activated in HDMI mode */
 920         cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
 921
 922         /* HDMI Phy spec says to do the phy initialization sequence twice */
 923         for (i = 0; i < 2; i++) {
 924                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
 925                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
 926                 dw_hdmi_phy_enable_tmds(hdmi, 0);
 927                 dw_hdmi_phy_enable_powerdown(hdmi, true);
 928
 929                 /* Enable CSC */
 930                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
 931                 if (ret)
 932                         return ret;
 933         }
 934
 935         hdmi->phy_enabled = true;
 936         return 0;
 937 }
 938
 939 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
 940 {
 941         u8 de;
 942
 943         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
 944                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
 945         else
 946                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
 947
 948         /* disable rx detect */
 949         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
 950                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
 951
 952         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
 953
 954         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
 955                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
 956 }
 957
 958 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
 959 {
 960         struct hdmi_avi_infoframe frame;
 961         u8 val;
 962
 963         /* Initialise info frame from DRM mode */
 964         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 965
 966         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
 967                 frame.colorspace = HDMI_COLORSPACE_YUV444;
 968         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
 969                 frame.colorspace = HDMI_COLORSPACE_YUV422;
 970         else
 971                 frame.colorspace = HDMI_COLORSPACE_RGB;
 972
 973         /* Set up colorimetry */
 974         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
 975                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
 976                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
 977                         frame.extended_colorimetry =
 978                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 979                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
 980                         frame.extended_colorimetry =
 981                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
 982         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
 983                 frame.colorimetry = hdmi->hdmi_data.colorimetry;
 984                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 985         } else { /* Carries no data */
 986                 frame.colorimetry = HDMI_COLORIMETRY_NONE;
 987                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 988         }
 989
 990         frame.scan_mode = HDMI_SCAN_MODE_NONE;
 991
 992         /*
 993          * The Designware IP uses a different byte format from standard
 994          * AVI info frames, though generally the bits are in the correct
 995          * bytes.
 996          */
 997
 998         /*
 999          * AVI data byte 1 differences: Colorspace in bits 4,5 rather than 5,6,
1000          * active aspect present in bit 6 rather than 4.
1001          */
1002         val = (frame.colorspace & 3) << 4 | (frame.scan_mode & 0x3);
1003         if (frame.active_aspect & 15)
1004                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1005         if (frame.top_bar || frame.bottom_bar)
1006                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1007         if (frame.left_bar || frame.right_bar)
1008                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1009         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1010
1011         /* AVI data byte 2 differences: none */
1012         val = ((frame.colorimetry & 0x3) << 6) |
1013               ((frame.picture_aspect & 0x3) << 4) |
1014               (frame.active_aspect & 0xf);
1015         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1016
1017         /* AVI data byte 3 differences: none */
1018         val = ((frame.extended_colorimetry & 0x7) << 4) |
1019               ((frame.quantization_range & 0x3) << 2) |
1020               (frame.nups & 0x3);
1021         if (frame.itc)
1022                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1023         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1024
1025         /* AVI data byte 4 differences: none */
1026         val = frame.video_code & 0x7f;
1027         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1028
1029         /* AVI Data Byte 5- set up input and output pixel repetition */
1030         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1031                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1032                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1033                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1034                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1035                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1036         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1037
1038         /*
1039          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1040          * ycc range in bits 2,3 rather than 6,7
1041          */
1042         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1043               (frame.content_type & 0x3);
1044         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1045
1046         /* AVI Data Bytes 6-13 */
1047         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1048         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1049         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1050         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1051         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1052         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1053         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1054         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1055 }
1056
1057 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1058                              const struct drm_display_mode *mode)
1059 {
1060         u8 inv_val;
1061         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1062         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1063
1064         vmode->mpixelclock = mode->clock * 1000;
1065
1066         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1067
1068         /* Set up HDMI_FC_INVIDCONF */
1069         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1070                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1071                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1072
1073         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1074                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1075                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1076
1077         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1078                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1079                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1080
1081         inv_val |= (vmode->mdataenablepolarity ?
1082                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1083                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1084
1085         if (hdmi->vic == 39)
1086                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1087         else
1088                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1089                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1090                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1091
1092         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1093                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1094                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1095
1096         inv_val |= hdmi->sink_is_hdmi ?
1097                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1098                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1099
1100         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1101
1102         /* Set up horizontal active pixel width */
1103         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1104         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1105
1106         /* Set up vertical active lines */
1107         hdmi_writeb(hdmi, mode->vdisplay >> 8, HDMI_FC_INVACTV1);
1108         hdmi_writeb(hdmi, mode->vdisplay, HDMI_FC_INVACTV0);
1109
1110         /* Set up horizontal blanking pixel region width */
1111         hblank = mode->htotal - mode->hdisplay;
1112         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1113         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1114
1115         /* Set up vertical blanking pixel region width */
1116         vblank = mode->vtotal - mode->vdisplay;
1117         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1118
1119         /* Set up HSYNC active edge delay width (in pixel clks) */
1120         h_de_hs = mode->hsync_start - mode->hdisplay;
1121         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1122         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1123
1124         /* Set up VSYNC active edge delay (in lines) */
1125         v_de_vs = mode->vsync_start - mode->vdisplay;
1126         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1127
1128         /* Set up HSYNC active pulse width (in pixel clks) */
1129         hsync_len = mode->hsync_end - mode->hsync_start;
1130         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1131         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1132
1133         /* Set up VSYNC active edge delay (in lines) */
1134         vsync_len = mode->vsync_end - mode->vsync_start;
1135         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1136 }
1137
1138 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1139 {
1140         if (!hdmi->phy_enabled)
1141                 return;
1142
1143         dw_hdmi_phy_enable_tmds(hdmi, 0);
1144         dw_hdmi_phy_enable_powerdown(hdmi, true);
1145
1146         hdmi->phy_enabled = false;
1147 }
1148
1149 /* HDMI Initialization Step B.4 */
1150 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1151 {
1152         u8 clkdis;
1153
1154         /* control period minimum duration */
1155         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1156         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1157         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1158
1159         /* Set to fill TMDS data channels */
1160         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1161         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1162         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1163
1164         /* Enable pixel clock and tmds data path */
1165         clkdis = 0x7F;
1166         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1167         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1168
1169         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1170         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1171
1172         /* Enable csc path */
1173         if (is_color_space_conversion(hdmi)) {
1174                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1175                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1176         }
1177 }
1178
1179 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1180 {
1181         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1182 }
1183
1184 /* Workaround to clear the overflow condition */
1185 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1186 {
1187         int count;
1188         u8 val;
1189
1190         /* TMDS software reset */
1191         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1192
1193         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1194         if (hdmi->dev_type == IMX6DL_HDMI) {
1195                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1196                 return;
1197         }
1198
1199         for (count = 0; count < 4; count++)
1200                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1201 }
1202
1203 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1204 {
1205         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1206         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1207 }
1208
1209 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1210 {
1211         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1212                     HDMI_IH_MUTE_FC_STAT2);
1213 }
1214
1215 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1216 {
1217         int ret;
1218
1219         hdmi_disable_overflow_interrupts(hdmi);
1220
1221         hdmi->vic = drm_match_cea_mode(mode);
1222
1223         if (!hdmi->vic) {
1224                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1225         } else {
1226                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1227         }
1228
1229         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1230             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1231             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1232             (hdmi->vic == 17) || (hdmi->vic == 18))
1233                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1234         else
1235                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1236
1237         hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1238         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1239
1240         /* TODO: Get input format from IPU (via FB driver interface) */
1241         hdmi->hdmi_data.enc_in_format = RGB;
1242
1243         hdmi->hdmi_data.enc_out_format = RGB;
1244
1245         hdmi->hdmi_data.enc_color_depth = 8;
1246         hdmi->hdmi_data.pix_repet_factor = 0;
1247         hdmi->hdmi_data.hdcp_enable = 0;
1248         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1249
1250         /* HDMI Initialization Step B.1 */
1251         hdmi_av_composer(hdmi, mode);
1252
1253         /* HDMI Initializateion Step B.2 */
1254         ret = dw_hdmi_phy_init(hdmi);
1255         if (ret)
1256                 return ret;
1257
1258         /* HDMI Initialization Step B.3 */
1259         dw_hdmi_enable_video_path(hdmi);
1260
1261         if (hdmi->sink_has_audio) {
1262                 dev_dbg(hdmi->dev, "sink has audio support\n");
1263
1264                 /* HDMI Initialization Step E - Configure audio */
1265                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1266                 hdmi_enable_audio_clk(hdmi);
1267         }
1268
1269         /* not for DVI mode */
1270         if (hdmi->sink_is_hdmi) {
1271                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1272
1273                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1274                 hdmi_config_AVI(hdmi, mode);
1275         } else {
1276                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1277         }
1278
1279         hdmi_video_packetize(hdmi);
1280         hdmi_video_csc(hdmi);
1281         hdmi_video_sample(hdmi);
1282         hdmi_tx_hdcp_config(hdmi);
1283
1284         dw_hdmi_clear_overflow(hdmi);
1285         if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1286                 hdmi_enable_overflow_interrupts(hdmi);
1287
1288         return 0;
1289 }
1290
1291 /* Wait until we are registered to enable interrupts */
1292 static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
1293 {
1294         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1295                     HDMI_PHY_I2CM_INT_ADDR);
1296
1297         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1298                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1299                     HDMI_PHY_I2CM_CTLINT_ADDR);
1300
1301         /* enable cable hot plug irq */
1302         hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
1303
1304         /* Clear Hotplug interrupts */
1305         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1306
1307         return 0;
1308 }
1309
1310 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1311 {
1312         u8 ih_mute;
1313
1314         /*
1315          * Boot up defaults are:
1316          * HDMI_IH_MUTE   = 0x03 (disabled)
1317          * HDMI_IH_MUTE_* = 0x00 (enabled)
1318          *
1319          * Disable top level interrupt bits in HDMI block
1320          */
1321         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1322                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1323                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1324
1325         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1326
1327         /* by default mask all interrupts */
1328         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1329         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1330         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1331         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1332         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1333         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1334         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1335         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1336         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1337         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1338         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1339         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1340         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1341         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1342         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1343
1344         /* Disable interrupts in the IH_MUTE_* registers */
1345         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1346         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1347         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1348         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1349         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1350         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1351         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1352         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1353         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1354         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1355
1356         /* Enable top level interrupt bits in HDMI block */
1357         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1358                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1359         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1360 }
1361
1362 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1363 {
1364         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1365 }
1366
1367 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1368 {
1369         dw_hdmi_phy_disable(hdmi);
1370 }
1371
1372 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1373                                     struct drm_display_mode *orig_mode,
1374                                     struct drm_display_mode *mode)
1375 {
1376         struct dw_hdmi *hdmi = bridge->driver_private;
1377
1378         /* Store the display mode for plugin/DKMS poweron events */
1379         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1380 }
1381
1382 static bool dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1383                                       const struct drm_display_mode *mode,
1384                                       struct drm_display_mode *adjusted_mode)
1385 {
1386         return true;
1387 }
1388
1389 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1390 {
1391         struct dw_hdmi *hdmi = bridge->driver_private;
1392
1393         dw_hdmi_poweroff(hdmi);
1394 }
1395
1396 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1397 {
1398         struct dw_hdmi *hdmi = bridge->driver_private;
1399
1400         dw_hdmi_poweron(hdmi);
1401 }
1402
1403 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1404 {
1405         /* do nothing */
1406 }
1407
1408 static enum drm_connector_status
1409 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1410 {
1411         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1412                                              connector);
1413
1414         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1415                 connector_status_connected : connector_status_disconnected;
1416 }
1417
1418 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1419 {
1420         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1421                                              connector);
1422         struct edid *edid;
1423         int ret;
1424
1425         if (!hdmi->ddc)
1426                 return 0;
1427
1428         edid = drm_get_edid(connector, hdmi->ddc);
1429         if (edid) {
1430                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1431                         edid->width_cm, edid->height_cm);
1432
1433                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1434                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1435                 drm_mode_connector_update_edid_property(connector, edid);
1436                 ret = drm_add_edid_modes(connector, edid);
1437                 kfree(edid);
1438         } else {
1439                 dev_dbg(hdmi->dev, "failed to get edid\n");
1440         }
1441
1442         return 0;
1443 }
1444
1445 static enum drm_mode_status
1446 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1447                              struct drm_display_mode *mode)
1448 {
1449         struct dw_hdmi *hdmi = container_of(connector,
1450                                            struct dw_hdmi, connector);
1451         enum drm_mode_status mode_status = MODE_OK;
1452
1453         /* We don't support double-clocked modes */
1454         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1455                 return MODE_BAD;
1456
1457         if (hdmi->plat_data->mode_valid)
1458                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1459
1460         return mode_status;
1461 }
1462
1463 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1464                                                            *connector)
1465 {
1466         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1467                                              connector);
1468
1469         return hdmi->encoder;
1470 }
1471
1472 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1473 {
1474         drm_connector_unregister(connector);
1475         drm_connector_cleanup(connector);
1476 }
1477
1478 static struct drm_connector_funcs dw_hdmi_connector_funcs = {
1479         .dpms = drm_helper_connector_dpms,
1480         .fill_modes = drm_helper_probe_single_connector_modes,
1481         .detect = dw_hdmi_connector_detect,
1482         .destroy = dw_hdmi_connector_destroy,
1483 };
1484
1485 static struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1486         .get_modes = dw_hdmi_connector_get_modes,
1487         .mode_valid = dw_hdmi_connector_mode_valid,
1488         .best_encoder = dw_hdmi_connector_best_encoder,
1489 };
1490
1491 struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1492         .enable = dw_hdmi_bridge_enable,
1493         .disable = dw_hdmi_bridge_disable,
1494         .pre_enable = dw_hdmi_bridge_nop,
1495         .post_disable = dw_hdmi_bridge_nop,
1496         .mode_set = dw_hdmi_bridge_mode_set,
1497         .mode_fixup = dw_hdmi_bridge_mode_fixup,
1498 };
1499
1500 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1501 {
1502         struct dw_hdmi *hdmi = dev_id;
1503         u8 intr_stat;
1504
1505         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1506         if (intr_stat)
1507                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1508
1509         return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
1510 }
1511
1512 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1513 {
1514         struct dw_hdmi *hdmi = dev_id;
1515         u8 intr_stat;
1516         u8 phy_int_pol;
1517
1518         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1519
1520         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1521
1522         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1523                 if (phy_int_pol & HDMI_PHY_HPD) {
1524                         dev_dbg(hdmi->dev, "EVENT=plugin\n");
1525
1526                         hdmi_modb(hdmi, 0, HDMI_PHY_HPD, HDMI_PHY_POL0);
1527
1528                         dw_hdmi_poweron(hdmi);
1529                 } else {
1530                         dev_dbg(hdmi->dev, "EVENT=plugout\n");
1531
1532                         hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD,
1533                                   HDMI_PHY_POL0);
1534
1535                         dw_hdmi_poweroff(hdmi);
1536                 }
1537                 drm_helper_hpd_irq_event(hdmi->bridge->dev);
1538         }
1539
1540         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1541         hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1542
1543         return IRQ_HANDLED;
1544 }
1545
1546 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
1547 {
1548         struct drm_encoder *encoder = hdmi->encoder;
1549         struct drm_bridge *bridge;
1550         int ret;
1551
1552         bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1553         if (!bridge) {
1554                 DRM_ERROR("Failed to allocate drm bridge\n");
1555                 return -ENOMEM;
1556         }
1557
1558         hdmi->bridge = bridge;
1559         bridge->driver_private = hdmi;
1560         bridge->funcs = &dw_hdmi_bridge_funcs;
1561         ret = drm_bridge_attach(drm, bridge);
1562         if (ret) {
1563                 DRM_ERROR("Failed to initialize bridge with drm\n");
1564                 return -EINVAL;
1565         }
1566
1567         encoder->bridge = bridge;
1568         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1569
1570         drm_connector_helper_add(&hdmi->connector,
1571                                  &dw_hdmi_connector_helper_funcs);
1572         drm_connector_init(drm, &hdmi->connector, &dw_hdmi_connector_funcs,
1573                            DRM_MODE_CONNECTOR_HDMIA);
1574
1575         hdmi->connector.encoder = encoder;
1576
1577         drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
1578
1579         return 0;
1580 }
1581
1582 int dw_hdmi_bind(struct device *dev, struct device *master,
1583                  void *data, struct drm_encoder *encoder,
1584                  struct resource *iores, int irq,
1585                  const struct dw_hdmi_plat_data *plat_data)
1586 {
1587         struct drm_device *drm = data;
1588         struct device_node *np = dev->of_node;
1589         struct device_node *ddc_node;
1590         struct dw_hdmi *hdmi;
1591         int ret;
1592         u32 val = 1;
1593
1594         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1595         if (!hdmi)
1596                 return -ENOMEM;
1597
1598         hdmi->plat_data = plat_data;
1599         hdmi->dev = dev;
1600         hdmi->dev_type = plat_data->dev_type;
1601         hdmi->sample_rate = 48000;
1602         hdmi->ratio = 100;
1603         hdmi->encoder = encoder;
1604
1605         mutex_init(&hdmi->audio_mutex);
1606         spin_lock_init(&hdmi->audio_lock);
1607
1608         of_property_read_u32(np, "reg-io-width", &val);
1609
1610         switch (val) {
1611         case 4:
1612                 hdmi->write = dw_hdmi_writel;
1613                 hdmi->read = dw_hdmi_readl;
1614                 break;
1615         case 1:
1616                 hdmi->write = dw_hdmi_writeb;
1617                 hdmi->read = dw_hdmi_readb;
1618                 break;
1619         default:
1620                 dev_err(dev, "reg-io-width must be 1 or 4\n");
1621                 return -EINVAL;
1622         }
1623
1624         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
1625         if (ddc_node) {
1626                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1627                 of_node_put(ddc_node);
1628                 if (!hdmi->ddc) {
1629                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
1630                         return -EPROBE_DEFER;
1631                 }
1632
1633         } else {
1634                 dev_dbg(hdmi->dev, "no ddc property found\n");
1635         }
1636
1637         hdmi->regs = devm_ioremap_resource(dev, iores);
1638         if (IS_ERR(hdmi->regs))
1639                 return PTR_ERR(hdmi->regs);
1640
1641         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1642         if (IS_ERR(hdmi->isfr_clk)) {
1643                 ret = PTR_ERR(hdmi->isfr_clk);
1644                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
1645                 return ret;
1646         }
1647
1648         ret = clk_prepare_enable(hdmi->isfr_clk);
1649         if (ret) {
1650                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
1651                 return ret;
1652         }
1653
1654         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1655         if (IS_ERR(hdmi->iahb_clk)) {
1656                 ret = PTR_ERR(hdmi->iahb_clk);
1657                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
1658                 goto err_isfr;
1659         }
1660
1661         ret = clk_prepare_enable(hdmi->iahb_clk);
1662         if (ret) {
1663                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
1664                 goto err_isfr;
1665         }
1666
1667         /* Product and revision IDs */
1668         dev_info(dev,
1669                  "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1670                  hdmi_readb(hdmi, HDMI_DESIGN_ID),
1671                  hdmi_readb(hdmi, HDMI_REVISION_ID),
1672                  hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1673                  hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
1674
1675         initialize_hdmi_ih_mutes(hdmi);
1676
1677         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
1678                                         dw_hdmi_irq, IRQF_SHARED,
1679                                         dev_name(dev), hdmi);
1680         if (ret)
1681                 goto err_iahb;
1682
1683         /*
1684          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1685          * N and cts values before enabling phy
1686          */
1687         hdmi_init_clk_regenerator(hdmi);
1688
1689         /*
1690          * Configure registers related to HDMI interrupt
1691          * generation before registering IRQ.
1692          */
1693         hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0);
1694
1695         /* Clear Hotplug interrupts */
1696         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1697
1698         ret = dw_hdmi_fb_registered(hdmi);
1699         if (ret)
1700                 goto err_iahb;
1701
1702         ret = dw_hdmi_register(drm, hdmi);
1703         if (ret)
1704                 goto err_iahb;
1705
1706         /* Unmute interrupts */
1707         hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1708
1709         dev_set_drvdata(dev, hdmi);
1710
1711         return 0;
1712
1713 err_iahb:
1714         clk_disable_unprepare(hdmi->iahb_clk);
1715 err_isfr:
1716         clk_disable_unprepare(hdmi->isfr_clk);
1717
1718         return ret;
1719 }
1720 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
1721
1722 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
1723 {
1724         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
1725
1726         /* Disable all interrupts */
1727         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1728
1729         hdmi->connector.funcs->destroy(&hdmi->connector);
1730         hdmi->encoder->funcs->destroy(hdmi->encoder);
1731
1732         clk_disable_unprepare(hdmi->iahb_clk);
1733         clk_disable_unprepare(hdmi->isfr_clk);
1734         i2c_put_adapter(hdmi->ddc);
1735 }
1736 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
1737
1738 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1739 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
1740 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
1741 MODULE_DESCRIPTION("DW HDMI transmitter driver");
1742 MODULE_LICENSE("GPL");
1743 MODULE_ALIAS("platform:dw-hdmi");