drivers/gpu/drm/bridge/dw_hdmi.c

   1 /*
   2  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * Designware High-Definition Multimedia Interface (HDMI) driver
  10  *
  11  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  12  */
  13 #include <linux/module.h>
  14 #include <linux/irq.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/hdmi.h>
  19 #include <linux/mutex.h>
  20 #include <linux/of_device.h>
  21 #include <linux/spinlock.h>
  22
  23 #include <drm/drm_of.h>
  24 #include <drm/drmP.h>
  25 #include <drm/drm_crtc_helper.h>
  26 #include <drm/drm_edid.h>
  27 #include <drm/drm_encoder_slave.h>
  28 #include <drm/bridge/dw_hdmi.h>
  29
  30 #include "dw_hdmi.h"
  31
  32 #define HDMI_EDID_LEN           512
  33
  34 #define RGB                     0
  35 #define YCBCR444                1
  36 #define YCBCR422_16BITS         2
  37 #define YCBCR422_8BITS          3
  38 #define XVYCC444                4
  39
  40 enum hdmi_datamap {
  41         RGB444_8B = 0x01,
  42         RGB444_10B = 0x03,
  43         RGB444_12B = 0x05,
  44         RGB444_16B = 0x07,
  45         YCbCr444_8B = 0x09,
  46         YCbCr444_10B = 0x0B,
  47         YCbCr444_12B = 0x0D,
  48         YCbCr444_16B = 0x0F,
  49         YCbCr422_8B = 0x16,
  50         YCbCr422_10B = 0x14,
  51         YCbCr422_12B = 0x12,
  52 };
  53
  54 static const u16 csc_coeff_default[3][4] = {
  55         { 0x2000, 0x0000, 0x0000, 0x0000 },
  56         { 0x0000, 0x2000, 0x0000, 0x0000 },
  57         { 0x0000, 0x0000, 0x2000, 0x0000 }
  58 };
  59
  60 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
  61         { 0x2000, 0x6926, 0x74fd, 0x010e },
  62         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
  63         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
  64 };
  65
  66 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
  67         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
  68         { 0x2000, 0x3264, 0x0000, 0x7e6d },
  69         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
  70 };
  71
  72 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
  73         { 0x2591, 0x1322, 0x074b, 0x0000 },
  74         { 0x6535, 0x2000, 0x7acc, 0x0200 },
  75         { 0x6acd, 0x7534, 0x2000, 0x0200 }
  76 };
  77
  78 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
  79         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
  80         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
  81         { 0x6756, 0x78ab, 0x2000, 0x0200 }
  82 };
  83
  84 struct hdmi_vmode {
  85         bool mdvi;
  86         bool mdataenablepolarity;
  87
  88         unsigned int mpixelclock;
  89         unsigned int mpixelrepetitioninput;
  90         unsigned int mpixelrepetitionoutput;
  91 };
  92
  93 struct hdmi_data_info {
  94         unsigned int enc_in_format;
  95         unsigned int enc_out_format;
  96         unsigned int enc_color_depth;
  97         unsigned int colorimetry;
  98         unsigned int pix_repet_factor;
  99         unsigned int hdcp_enable;
 100         struct hdmi_vmode video_mode;
 101 };
 102
 103 struct dw_hdmi {
 104         struct drm_connector connector;
 105         struct drm_encoder *encoder;
 106         struct drm_bridge *bridge;
 107
 108         enum dw_hdmi_devtype dev_type;
 109         struct device *dev;
 110         struct clk *isfr_clk;
 111         struct clk *iahb_clk;
 112
 113         struct hdmi_data_info hdmi_data;
 114         const struct dw_hdmi_plat_data *plat_data;
 115
 116         int vic;
 117
 118         u8 edid[HDMI_EDID_LEN];
 119         bool cable_plugin;
 120
 121         bool phy_enabled;
 122         struct drm_display_mode previous_mode;
 123
 124         struct i2c_adapter *ddc;
 125         void __iomem *regs;
 126
 127         spinlock_t audio_lock;
 128         struct mutex audio_mutex;
 129         unsigned int sample_rate;
 130         unsigned int audio_cts;
 131         unsigned int audio_n;
 132         bool audio_enable;
 133         int ratio;
 134
 135         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
 136         u8 (*read)(struct dw_hdmi *hdmi, int offset);
 137 };
 138
 139 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
 140 {
 141         writel(val, hdmi->regs + (offset << 2));
 142 }
 143
 144 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
 145 {
 146         return readl(hdmi->regs + (offset << 2));
 147 }
 148
 149 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 150 {
 151         writeb(val, hdmi->regs + offset);
 152 }
 153
 154 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
 155 {
 156         return readb(hdmi->regs + offset);
 157 }
 158
 159 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 160 {
 161         hdmi->write(hdmi, val, offset);
 162 }
 163
 164 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 165 {
 166         return hdmi->read(hdmi, offset);
 167 }
 168
 169 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 170 {
 171         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 172
 173         val |= data & mask;
 174         hdmi_writeb(hdmi, val, reg);
 175 }
 176
 177 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 178                              u8 shift, u8 mask)
 179 {
 180         hdmi_modb(hdmi, data << shift, mask, reg);
 181 }
 182
 183 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 184                            unsigned int n)
 185 {
 186         /* Must be set/cleared first */
 187         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 188
 189         /* nshift factor = 0 */
 190         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 191
 192         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 193                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 194         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 195         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 196
 197         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 198         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 199         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 200 }
 201
 202 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
 203                                    unsigned int ratio)
 204 {
 205         unsigned int n = (128 * freq) / 1000;
 206
 207         switch (freq) {
 208         case 32000:
 209                 if (pixel_clk == 25170000)
 210                         n = (ratio == 150) ? 9152 : 4576;
 211                 else if (pixel_clk == 27020000)
 212                         n = (ratio == 150) ? 8192 : 4096;
 213                 else if (pixel_clk == 74170000 || pixel_clk == 148350000)
 214                         n = 11648;
 215                 else
 216                         n = 4096;
 217                 break;
 218
 219         case 44100:
 220                 if (pixel_clk == 25170000)
 221                         n = 7007;
 222                 else if (pixel_clk == 74170000)
 223                         n = 17836;
 224                 else if (pixel_clk == 148350000)
 225                         n = (ratio == 150) ? 17836 : 8918;
 226                 else
 227                         n = 6272;
 228                 break;
 229
 230         case 48000:
 231                 if (pixel_clk == 25170000)
 232                         n = (ratio == 150) ? 9152 : 6864;
 233                 else if (pixel_clk == 27020000)
 234                         n = (ratio == 150) ? 8192 : 6144;
 235                 else if (pixel_clk == 74170000)
 236                         n = 11648;
 237                 else if (pixel_clk == 148350000)
 238                         n = (ratio == 150) ? 11648 : 5824;
 239                 else
 240                         n = 6144;
 241                 break;
 242
 243         case 88200:
 244                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
 245                 break;
 246
 247         case 96000:
 248                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
 249                 break;
 250
 251         case 176400:
 252                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
 253                 break;
 254
 255         case 192000:
 256                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
 257                 break;
 258
 259         default:
 260                 break;
 261         }
 262
 263         return n;
 264 }
 265
 266 static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
 267                                      unsigned int ratio)
 268 {
 269         unsigned int cts = 0;
 270
 271         pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq,
 272                  pixel_clk, ratio);
 273
 274         switch (freq) {
 275         case 32000:
 276                 if (pixel_clk == 297000000) {
 277                         cts = 222750;
 278                         break;
 279                 }
 280         case 48000:
 281         case 96000:
 282         case 192000:
 283                 switch (pixel_clk) {
 284                 case 25200000:
 285                 case 27000000:
 286                 case 54000000:
 287                 case 74250000:
 288                 case 148500000:
 289                         cts = pixel_clk / 1000;
 290                         break;
 291                 case 297000000:
 292                         cts = 247500;
 293                         break;
 294                 /*
 295                  * All other TMDS clocks are not supported by
 296                  * DWC_hdmi_tx. The TMDS clocks divided or
 297                  * multiplied by 1,001 coefficients are not
 298                  * supported.
 299                  */
 300                 default:
 301                         break;
 302                 }
 303                 break;
 304         case 44100:
 305         case 88200:
 306         case 176400:
 307                 switch (pixel_clk) {
 308                 case 25200000:
 309                         cts = 28000;
 310                         break;
 311                 case 27000000:
 312                         cts = 30000;
 313                         break;
 314                 case 54000000:
 315                         cts = 60000;
 316                         break;
 317                 case 74250000:
 318                         cts = 82500;
 319                         break;
 320                 case 148500000:
 321                         cts = 165000;
 322                         break;
 323                 case 297000000:
 324                         cts = 247500;
 325                         break;
 326                 default:
 327                         break;
 328                 }
 329                 break;
 330         default:
 331                 break;
 332         }
 333         if (ratio == 100)
 334                 return cts;
 335         return (cts * ratio) / 100;
 336 }
 337
 338 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 339         unsigned long pixel_clk, unsigned int sample_rate, unsigned int ratio)
 340 {
 341         unsigned int n, cts;
 342
 343         n = hdmi_compute_n(sample_rate, pixel_clk, ratio);
 344         cts = hdmi_compute_cts(sample_rate, pixel_clk, ratio);
 345         if (!cts) {
 346                 dev_err(hdmi->dev,
 347                         "%s: pixel clock/sample rate not supported: %luMHz / %ukHz\n",
 348                         __func__, pixel_clk, sample_rate);
 349         }
 350
 351         dev_dbg(hdmi->dev, "%s: samplerate=%ukHz ratio=%d pixelclk=%luMHz N=%d cts=%d\n",
 352                 __func__, sample_rate, ratio, pixel_clk, n, cts);
 353
 354         spin_lock_irq(&hdmi->audio_lock);
 355         hdmi->audio_n = n;
 356         hdmi->audio_cts = cts;
 357         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
 358         spin_unlock_irq(&hdmi->audio_lock);
 359 }
 360
 361 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 362 {
 363         mutex_lock(&hdmi->audio_mutex);
 364         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate,
 365                                  hdmi->ratio);
 366         mutex_unlock(&hdmi->audio_mutex);
 367 }
 368
 369 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 370 {
 371         mutex_lock(&hdmi->audio_mutex);
 372         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 373                                  hdmi->sample_rate, hdmi->ratio);
 374         mutex_unlock(&hdmi->audio_mutex);
 375 }
 376
 377 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 378 {
 379         mutex_lock(&hdmi->audio_mutex);
 380         hdmi->sample_rate = rate;
 381         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 382                                  hdmi->sample_rate, hdmi->ratio);
 383         mutex_unlock(&hdmi->audio_mutex);
 384 }
 385 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
 386
 387 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
 388 {
 389         unsigned long flags;
 390
 391         spin_lock_irqsave(&hdmi->audio_lock, flags);
 392         hdmi->audio_enable = true;
 393         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 394         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 395 }
 396 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
 397
 398 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 399 {
 400         unsigned long flags;
 401
 402         spin_lock_irqsave(&hdmi->audio_lock, flags);
 403         hdmi->audio_enable = false;
 404         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
 405         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 406 }
 407 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 408
 409 /*
 410  * this submodule is responsible for the video data synchronization.
 411  * for example, for RGB 4:4:4 input, the data map is defined as
 412  *                      pin{47~40} <==> R[7:0]
 413  *                      pin{31~24} <==> G[7:0]
 414  *                      pin{15~8}  <==> B[7:0]
 415  */
 416 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 417 {
 418         int color_format = 0;
 419         u8 val;
 420
 421         if (hdmi->hdmi_data.enc_in_format == RGB) {
 422                 if (hdmi->hdmi_data.enc_color_depth == 8)
 423                         color_format = 0x01;
 424                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 425                         color_format = 0x03;
 426                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 427                         color_format = 0x05;
 428                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 429                         color_format = 0x07;
 430                 else
 431                         return;
 432         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
 433                 if (hdmi->hdmi_data.enc_color_depth == 8)
 434                         color_format = 0x09;
 435                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 436                         color_format = 0x0B;
 437                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 438                         color_format = 0x0D;
 439                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 440                         color_format = 0x0F;
 441                 else
 442                         return;
 443         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 444                 if (hdmi->hdmi_data.enc_color_depth == 8)
 445                         color_format = 0x16;
 446                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 447                         color_format = 0x14;
 448                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 449                         color_format = 0x12;
 450                 else
 451                         return;
 452         }
 453
 454         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 455                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 456                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 457         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 458
 459         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 460         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 461                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 462                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 463         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 464         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 465         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 466         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 467         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 468         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 469         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 470 }
 471
 472 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 473 {
 474         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
 475 }
 476
 477 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 478 {
 479         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
 480                 return 0;
 481         if (hdmi->hdmi_data.enc_in_format == RGB ||
 482             hdmi->hdmi_data.enc_in_format == YCBCR444)
 483                 return 1;
 484         return 0;
 485 }
 486
 487 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 488 {
 489         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
 490                 return 0;
 491         if (hdmi->hdmi_data.enc_out_format == RGB ||
 492             hdmi->hdmi_data.enc_out_format == YCBCR444)
 493                 return 1;
 494         return 0;
 495 }
 496
 497 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 498 {
 499         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 500         unsigned i;
 501         u32 csc_scale = 1;
 502
 503         if (is_color_space_conversion(hdmi)) {
 504                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 505                         if (hdmi->hdmi_data.colorimetry ==
 506                                         HDMI_COLORIMETRY_ITU_601)
 507                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 508                         else
 509                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 510                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 511                         if (hdmi->hdmi_data.colorimetry ==
 512                                         HDMI_COLORIMETRY_ITU_601)
 513                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 514                         else
 515                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 516                         csc_scale = 0;
 517                 }
 518         }
 519
 520         /* The CSC registers are sequential, alternating MSB then LSB */
 521         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 522                 u16 coeff_a = (*csc_coeff)[0][i];
 523                 u16 coeff_b = (*csc_coeff)[1][i];
 524                 u16 coeff_c = (*csc_coeff)[2][i];
 525
 526                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 527                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 528                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 529                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 530                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 531                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 532         }
 533
 534         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 535                   HDMI_CSC_SCALE);
 536 }
 537
 538 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 539 {
 540         int color_depth = 0;
 541         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 542         int decimation = 0;
 543
 544         /* YCC422 interpolation to 444 mode */
 545         if (is_color_space_interpolation(hdmi))
 546                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 547         else if (is_color_space_decimation(hdmi))
 548                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 549
 550         if (hdmi->hdmi_data.enc_color_depth == 8)
 551                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 552         else if (hdmi->hdmi_data.enc_color_depth == 10)
 553                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 554         else if (hdmi->hdmi_data.enc_color_depth == 12)
 555                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 556         else if (hdmi->hdmi_data.enc_color_depth == 16)
 557                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 558         else
 559                 return;
 560
 561         /* Configure the CSC registers */
 562         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 563         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 564                   HDMI_CSC_SCALE);
 565
 566         dw_hdmi_update_csc_coeffs(hdmi);
 567 }
 568
 569 /*
 570  * HDMI video packetizer is used to packetize the data.
 571  * for example, if input is YCC422 mode or repeater is used,
 572  * data should be repacked this module can be bypassed.
 573  */
 574 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 575 {
 576         unsigned int color_depth = 0;
 577         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 578         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 579         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 580         u8 val, vp_conf;
 581
 582         if (hdmi_data->enc_out_format == RGB ||
 583             hdmi_data->enc_out_format == YCBCR444) {
 584                 if (!hdmi_data->enc_color_depth) {
 585                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 586                 } else if (hdmi_data->enc_color_depth == 8) {
 587                         color_depth = 4;
 588                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 589                 } else if (hdmi_data->enc_color_depth == 10) {
 590                         color_depth = 5;
 591                 } else if (hdmi_data->enc_color_depth == 12) {
 592                         color_depth = 6;
 593                 } else if (hdmi_data->enc_color_depth == 16) {
 594                         color_depth = 7;
 595                 } else {
 596                         return;
 597                 }
 598         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 599                 if (!hdmi_data->enc_color_depth ||
 600                     hdmi_data->enc_color_depth == 8)
 601                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 602                 else if (hdmi_data->enc_color_depth == 10)
 603                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 604                 else if (hdmi_data->enc_color_depth == 12)
 605                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 606                 else
 607                         return;
 608                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 609         } else {
 610                 return;
 611         }
 612
 613         /* set the packetizer registers */
 614         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 615                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 616                 ((hdmi_data->pix_repet_factor <<
 617                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 618                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 619         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 620
 621         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 622                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 623
 624         /* Data from pixel repeater block */
 625         if (hdmi_data->pix_repet_factor > 1) {
 626                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 627                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 628         } else { /* data from packetizer block */
 629                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 630                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 631         }
 632
 633         hdmi_modb(hdmi, vp_conf,
 634                   HDMI_VP_CONF_PR_EN_MASK |
 635                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 636
 637         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 638                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 639
 640         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 641
 642         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 643                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 644                           HDMI_VP_CONF_PP_EN_ENABLE |
 645                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 646         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 647                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 648                           HDMI_VP_CONF_PP_EN_DISABLE |
 649                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 650         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 651                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 652                           HDMI_VP_CONF_PP_EN_DISABLE |
 653                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 654         } else {
 655                 return;
 656         }
 657
 658         hdmi_modb(hdmi, vp_conf,
 659                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 660                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 661
 662         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 663                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 664                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 665                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 666
 667         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 668                   HDMI_VP_CONF);
 669 }
 670
 671 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
 672                                        unsigned char bit)
 673 {
 674         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 675                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 676 }
 677
 678 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
 679                                         unsigned char bit)
 680 {
 681         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
 682                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
 683 }
 684
 685 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
 686                                        unsigned char bit)
 687 {
 688         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
 689                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
 690 }
 691
 692 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
 693                                      unsigned char bit)
 694 {
 695         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
 696 }
 697
 698 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
 699                                       unsigned char bit)
 700 {
 701         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
 702 }
 703
 704 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
 705 {
 706         u32 val;
 707
 708         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
 709                 if (msec-- == 0)
 710                         return false;
 711                 udelay(1000);
 712         }
 713         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
 714
 715         return true;
 716 }
 717
 718 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 719                                  unsigned char addr)
 720 {
 721         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
 722         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
 723         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
 724                     HDMI_PHY_I2CM_DATAO_1_ADDR);
 725         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
 726                     HDMI_PHY_I2CM_DATAO_0_ADDR);
 727         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
 728                     HDMI_PHY_I2CM_OPERATION_ADDR);
 729         hdmi_phy_wait_i2c_done(hdmi, 1000);
 730 }
 731
 732 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 733                               unsigned char addr)
 734 {
 735         __hdmi_phy_i2c_write(hdmi, data, addr);
 736         return 0;
 737 }
 738
 739 static void dw_hdmi_phy_enable_power(struct dw_hdmi *hdmi, u8 enable)
 740 {
 741         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 742                          HDMI_PHY_CONF0_PDZ_OFFSET,
 743                          HDMI_PHY_CONF0_PDZ_MASK);
 744 }
 745
 746 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
 747 {
 748         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 749                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
 750                          HDMI_PHY_CONF0_ENTMDS_MASK);
 751 }
 752
 753 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
 754 {
 755         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 756                          HDMI_PHY_CONF0_SPARECTRL_OFFSET,
 757                          HDMI_PHY_CONF0_SPARECTRL_MASK);
 758 }
 759
 760 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
 761 {
 762         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 763                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
 764                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
 765 }
 766
 767 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
 768 {
 769         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 770                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
 771                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
 772 }
 773
 774 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
 775 {
 776         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 777                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
 778                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
 779 }
 780
 781 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
 782 {
 783         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 784                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
 785                          HDMI_PHY_CONF0_SELDIPIF_MASK);
 786 }
 787
 788 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
 789                               unsigned char res, int cscon)
 790 {
 791         unsigned res_idx;
 792         u8 val, msec;
 793         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
 794         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
 795         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
 796         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
 797
 798         if (prep)
 799                 return -EINVAL;
 800
 801         switch (res) {
 802         case 0: /* color resolution 0 is 8 bit colour depth */
 803         case 8:
 804                 res_idx = DW_HDMI_RES_8;
 805                 break;
 806         case 10:
 807                 res_idx = DW_HDMI_RES_10;
 808                 break;
 809         case 12:
 810                 res_idx = DW_HDMI_RES_12;
 811                 break;
 812         default:
 813                 return -EINVAL;
 814         }
 815
 816         /* PLL/MPLL Cfg - always match on final entry */
 817         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
 818                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 819                     mpll_config->mpixelclock)
 820                         break;
 821
 822         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
 823                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 824                     curr_ctrl->mpixelclock)
 825                         break;
 826
 827         for (; phy_config->mpixelclock != ~0UL; phy_config++)
 828                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 829                     phy_config->mpixelclock)
 830                         break;
 831
 832         if (mpll_config->mpixelclock == ~0UL ||
 833             curr_ctrl->mpixelclock == ~0UL ||
 834             phy_config->mpixelclock == ~0UL) {
 835                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
 836                         hdmi->hdmi_data.video_mode.mpixelclock);
 837                 return -EINVAL;
 838         }
 839
 840         /* Enable csc path */
 841         if (cscon)
 842                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
 843         else
 844                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
 845
 846         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
 847
 848         /* gen2 tx power off */
 849         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
 850
 851         /* gen2 pddq */
 852         dw_hdmi_phy_gen2_pddq(hdmi, 1);
 853
 854         /* PHY reset */
 855         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
 856         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
 857
 858         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
 859
 860         hdmi_phy_test_clear(hdmi, 1);
 861         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
 862                     HDMI_PHY_I2CM_SLAVE_ADDR);
 863         hdmi_phy_test_clear(hdmi, 0);
 864
 865         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
 866         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
 867
 868         /* CURRCTRL */
 869         hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
 870
 871         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
 872         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
 873
 874         hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19);  /* TXTERM */
 875         hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
 876         hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
 877
 878         /* REMOVE CLK TERM */
 879         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
 880
 881         dw_hdmi_phy_enable_power(hdmi, 1);
 882
 883         /* toggle TMDS enable */
 884         dw_hdmi_phy_enable_tmds(hdmi, 0);
 885         dw_hdmi_phy_enable_tmds(hdmi, 1);
 886
 887         /* gen2 tx power on */
 888         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
 889         dw_hdmi_phy_gen2_pddq(hdmi, 0);
 890
 891         if (hdmi->dev_type == RK3288_HDMI)
 892                 dw_hdmi_phy_enable_spare(hdmi, 1);
 893
 894         /*Wait for PHY PLL lock */
 895         msec = 5;
 896         do {
 897                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
 898                 if (!val)
 899                         break;
 900
 901                 if (msec == 0) {
 902                         dev_err(hdmi->dev, "PHY PLL not locked\n");
 903                         return -ETIMEDOUT;
 904                 }
 905
 906                 udelay(1000);
 907                 msec--;
 908         } while (1);
 909
 910         return 0;
 911 }
 912
 913 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
 914 {
 915         int i, ret;
 916         bool cscon = false;
 917
 918         /*check csc whether needed activated in HDMI mode */
 919         cscon = (is_color_space_conversion(hdmi) &&
 920                         !hdmi->hdmi_data.video_mode.mdvi);
 921
 922         /* HDMI Phy spec says to do the phy initialization sequence twice */
 923         for (i = 0; i < 2; i++) {
 924                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
 925                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
 926                 dw_hdmi_phy_enable_tmds(hdmi, 0);
 927                 dw_hdmi_phy_enable_power(hdmi, 0);
 928
 929                 /* Enable CSC */
 930                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
 931                 if (ret)
 932                         return ret;
 933         }
 934
 935         hdmi->phy_enabled = true;
 936         return 0;
 937 }
 938
 939 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
 940 {
 941         u8 de;
 942
 943         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
 944                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
 945         else
 946                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
 947
 948         /* disable rx detect */
 949         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
 950                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
 951
 952         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
 953
 954         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
 955                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
 956 }
 957
 958 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
 959 {
 960         struct hdmi_avi_infoframe frame;
 961         u8 val;
 962
 963         /* Initialise info frame from DRM mode */
 964         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 965
 966         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
 967                 frame.colorspace = HDMI_COLORSPACE_YUV444;
 968         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
 969                 frame.colorspace = HDMI_COLORSPACE_YUV422;
 970         else
 971                 frame.colorspace = HDMI_COLORSPACE_RGB;
 972
 973         /* Set up colorimetry */
 974         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
 975                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
 976                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
 977                         frame.extended_colorimetry =
 978                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 979                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
 980                         frame.extended_colorimetry =
 981                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
 982         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
 983                 frame.colorimetry = hdmi->hdmi_data.colorimetry;
 984                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 985         } else { /* Carries no data */
 986                 frame.colorimetry = HDMI_COLORIMETRY_NONE;
 987                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 988         }
 989
 990         frame.scan_mode = HDMI_SCAN_MODE_NONE;
 991
 992         /*
 993          * The Designware IP uses a different byte format from standard
 994          * AVI info frames, though generally the bits are in the correct
 995          * bytes.
 996          */
 997
 998         /*
 999          * AVI data byte 1 differences: Colorspace in bits 4,5 rather than 5,6,
1000          * active aspect present in bit 6 rather than 4.
1001          */
1002         val = (frame.colorspace & 3) << 4 | (frame.scan_mode & 0x3);
1003         if (frame.active_aspect & 15)
1004                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
1005         if (frame.top_bar || frame.bottom_bar)
1006                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
1007         if (frame.left_bar || frame.right_bar)
1008                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
1009         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
1010
1011         /* AVI data byte 2 differences: none */
1012         val = ((frame.colorimetry & 0x3) << 6) |
1013               ((frame.picture_aspect & 0x3) << 4) |
1014               (frame.active_aspect & 0xf);
1015         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
1016
1017         /* AVI data byte 3 differences: none */
1018         val = ((frame.extended_colorimetry & 0x7) << 4) |
1019               ((frame.quantization_range & 0x3) << 2) |
1020               (frame.nups & 0x3);
1021         if (frame.itc)
1022                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
1023         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
1024
1025         /* AVI data byte 4 differences: none */
1026         val = frame.video_code & 0x7f;
1027         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
1028
1029         /* AVI Data Byte 5- set up input and output pixel repetition */
1030         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
1031                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
1032                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
1033                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
1034                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
1035                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
1036         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
1037
1038         /*
1039          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1040          * ycc range in bits 2,3 rather than 6,7
1041          */
1042         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1043               (frame.content_type & 0x3);
1044         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1045
1046         /* AVI Data Bytes 6-13 */
1047         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1048         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1049         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1050         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1051         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1052         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1053         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1054         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1055 }
1056
1057 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1058                              const struct drm_display_mode *mode)
1059 {
1060         u8 inv_val;
1061         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1062         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1063
1064         vmode->mpixelclock = mode->clock * 1000;
1065
1066         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1067
1068         /* Set up HDMI_FC_INVIDCONF */
1069         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1070                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1071                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1072
1073         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1074                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1075                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1076
1077         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1078                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1079                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1080
1081         inv_val |= (vmode->mdataenablepolarity ?
1082                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1083                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1084
1085         if (hdmi->vic == 39)
1086                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1087         else
1088                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1089                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1090                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1091
1092         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1093                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1094                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1095
1096         inv_val |= (vmode->mdvi ?
1097                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE :
1098                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE);
1099
1100         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1101
1102         /* Set up horizontal active pixel width */
1103         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1104         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1105
1106         /* Set up vertical active lines */
1107         hdmi_writeb(hdmi, mode->vdisplay >> 8, HDMI_FC_INVACTV1);
1108         hdmi_writeb(hdmi, mode->vdisplay, HDMI_FC_INVACTV0);
1109
1110         /* Set up horizontal blanking pixel region width */
1111         hblank = mode->htotal - mode->hdisplay;
1112         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1113         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1114
1115         /* Set up vertical blanking pixel region width */
1116         vblank = mode->vtotal - mode->vdisplay;
1117         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1118
1119         /* Set up HSYNC active edge delay width (in pixel clks) */
1120         h_de_hs = mode->hsync_start - mode->hdisplay;
1121         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1122         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1123
1124         /* Set up VSYNC active edge delay (in lines) */
1125         v_de_vs = mode->vsync_start - mode->vdisplay;
1126         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1127
1128         /* Set up HSYNC active pulse width (in pixel clks) */
1129         hsync_len = mode->hsync_end - mode->hsync_start;
1130         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1131         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1132
1133         /* Set up VSYNC active edge delay (in lines) */
1134         vsync_len = mode->vsync_end - mode->vsync_start;
1135         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1136 }
1137
1138 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1139 {
1140         if (!hdmi->phy_enabled)
1141                 return;
1142
1143         dw_hdmi_phy_enable_tmds(hdmi, 0);
1144         dw_hdmi_phy_enable_power(hdmi, 0);
1145
1146         hdmi->phy_enabled = false;
1147 }
1148
1149 /* HDMI Initialization Step B.4 */
1150 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1151 {
1152         u8 clkdis;
1153
1154         /* control period minimum duration */
1155         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1156         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1157         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1158
1159         /* Set to fill TMDS data channels */
1160         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1161         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1162         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1163
1164         /* Enable pixel clock and tmds data path */
1165         clkdis = 0x7F;
1166         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1167         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1168
1169         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1170         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1171
1172         /* Enable csc path */
1173         if (is_color_space_conversion(hdmi)) {
1174                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1175                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1176         }
1177 }
1178
1179 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1180 {
1181         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1182 }
1183
1184 /* Workaround to clear the overflow condition */
1185 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1186 {
1187         int count;
1188         u8 val;
1189
1190         /* TMDS software reset */
1191         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1192
1193         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1194         if (hdmi->dev_type == IMX6DL_HDMI) {
1195                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1196                 return;
1197         }
1198
1199         for (count = 0; count < 4; count++)
1200                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1201 }
1202
1203 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1204 {
1205         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1206         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1207 }
1208
1209 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1210 {
1211         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1212                     HDMI_IH_MUTE_FC_STAT2);
1213 }
1214
1215 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1216 {
1217         int ret;
1218
1219         hdmi_disable_overflow_interrupts(hdmi);
1220
1221         hdmi->vic = drm_match_cea_mode(mode);
1222
1223         if (!hdmi->vic) {
1224                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1225                 hdmi->hdmi_data.video_mode.mdvi = true;
1226         } else {
1227                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1228                 hdmi->hdmi_data.video_mode.mdvi = false;
1229         }
1230
1231         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1232             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1233             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1234             (hdmi->vic == 17) || (hdmi->vic == 18))
1235                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1236         else
1237                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1238
1239         hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1240         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1241
1242         /* TODO: Get input format from IPU (via FB driver interface) */
1243         hdmi->hdmi_data.enc_in_format = RGB;
1244
1245         hdmi->hdmi_data.enc_out_format = RGB;
1246
1247         hdmi->hdmi_data.enc_color_depth = 8;
1248         hdmi->hdmi_data.pix_repet_factor = 0;
1249         hdmi->hdmi_data.hdcp_enable = 0;
1250         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1251
1252         /* HDMI Initialization Step B.1 */
1253         hdmi_av_composer(hdmi, mode);
1254
1255         /* HDMI Initializateion Step B.2 */
1256         ret = dw_hdmi_phy_init(hdmi);
1257         if (ret)
1258                 return ret;
1259
1260         /* HDMI Initialization Step B.3 */
1261         dw_hdmi_enable_video_path(hdmi);
1262
1263         /* not for DVI mode */
1264         if (hdmi->hdmi_data.video_mode.mdvi) {
1265                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1266         } else {
1267                 dev_dbg(hdmi->dev, "%s CEA mode\n", __func__);
1268
1269                 /* HDMI Initialization Step E - Configure audio */
1270                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1271                 hdmi_enable_audio_clk(hdmi);
1272
1273                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1274                 hdmi_config_AVI(hdmi, mode);
1275         }
1276
1277         hdmi_video_packetize(hdmi);
1278         hdmi_video_csc(hdmi);
1279         hdmi_video_sample(hdmi);
1280         hdmi_tx_hdcp_config(hdmi);
1281
1282         dw_hdmi_clear_overflow(hdmi);
1283         if (hdmi->cable_plugin && !hdmi->hdmi_data.video_mode.mdvi)
1284                 hdmi_enable_overflow_interrupts(hdmi);
1285
1286         return 0;
1287 }
1288
1289 /* Wait until we are registered to enable interrupts */
1290 static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
1291 {
1292         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1293                     HDMI_PHY_I2CM_INT_ADDR);
1294
1295         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1296                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1297                     HDMI_PHY_I2CM_CTLINT_ADDR);
1298
1299         /* enable cable hot plug irq */
1300         hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
1301
1302         /* Clear Hotplug interrupts */
1303         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1304
1305         return 0;
1306 }
1307
1308 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1309 {
1310         u8 ih_mute;
1311
1312         /*
1313          * Boot up defaults are:
1314          * HDMI_IH_MUTE   = 0x03 (disabled)
1315          * HDMI_IH_MUTE_* = 0x00 (enabled)
1316          *
1317          * Disable top level interrupt bits in HDMI block
1318          */
1319         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1320                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1321                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1322
1323         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1324
1325         /* by default mask all interrupts */
1326         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1327         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1328         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1329         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1330         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1331         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1332         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1333         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1334         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1335         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1336         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1337         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1338         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1339         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1340         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1341
1342         /* Disable interrupts in the IH_MUTE_* registers */
1343         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1344         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1345         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1346         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1347         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1348         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1349         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1350         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1351         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1352         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1353
1354         /* Enable top level interrupt bits in HDMI block */
1355         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1356                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1357         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1358 }
1359
1360 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1361 {
1362         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1363 }
1364
1365 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1366 {
1367         dw_hdmi_phy_disable(hdmi);
1368 }
1369
1370 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1371                                     struct drm_display_mode *orig_mode,
1372                                     struct drm_display_mode *mode)
1373 {
1374         struct dw_hdmi *hdmi = bridge->driver_private;
1375
1376         dw_hdmi_setup(hdmi, mode);
1377
1378         /* Store the display mode for plugin/DKMS poweron events */
1379         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1380 }
1381
1382 static bool dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1383                                       const struct drm_display_mode *mode,
1384                                       struct drm_display_mode *adjusted_mode)
1385 {
1386         return true;
1387 }
1388
1389 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1390 {
1391         struct dw_hdmi *hdmi = bridge->driver_private;
1392
1393         dw_hdmi_poweroff(hdmi);
1394 }
1395
1396 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1397 {
1398         struct dw_hdmi *hdmi = bridge->driver_private;
1399
1400         dw_hdmi_poweron(hdmi);
1401 }
1402
1403 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1404 {
1405         /* do nothing */
1406 }
1407
1408 static enum drm_connector_status
1409 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1410 {
1411         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1412                                              connector);
1413
1414         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1415                 connector_status_connected : connector_status_disconnected;
1416 }
1417
1418 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1419 {
1420         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1421                                              connector);
1422         struct edid *edid;
1423         int ret;
1424
1425         if (!hdmi->ddc)
1426                 return 0;
1427
1428         edid = drm_get_edid(connector, hdmi->ddc);
1429         if (edid) {
1430                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1431                         edid->width_cm, edid->height_cm);
1432
1433                 drm_mode_connector_update_edid_property(connector, edid);
1434                 ret = drm_add_edid_modes(connector, edid);
1435                 kfree(edid);
1436         } else {
1437                 dev_dbg(hdmi->dev, "failed to get edid\n");
1438         }
1439
1440         return 0;
1441 }
1442
1443 static enum drm_mode_status
1444 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1445                              struct drm_display_mode *mode)
1446 {
1447         struct dw_hdmi *hdmi = container_of(connector,
1448                                            struct dw_hdmi, connector);
1449         enum drm_mode_status mode_status = MODE_OK;
1450
1451         /* We don't support double-clocked modes */
1452         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1453                 return MODE_BAD;
1454
1455         if (hdmi->plat_data->mode_valid)
1456                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1457
1458         return mode_status;
1459 }
1460
1461 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1462                                                            *connector)
1463 {
1464         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1465                                              connector);
1466
1467         return hdmi->encoder;
1468 }
1469
1470 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1471 {
1472         drm_connector_unregister(connector);
1473         drm_connector_cleanup(connector);
1474 }
1475
1476 static struct drm_connector_funcs dw_hdmi_connector_funcs = {
1477         .dpms = drm_helper_connector_dpms,
1478         .fill_modes = drm_helper_probe_single_connector_modes,
1479         .detect = dw_hdmi_connector_detect,
1480         .destroy = dw_hdmi_connector_destroy,
1481 };
1482
1483 static struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1484         .get_modes = dw_hdmi_connector_get_modes,
1485         .mode_valid = dw_hdmi_connector_mode_valid,
1486         .best_encoder = dw_hdmi_connector_best_encoder,
1487 };
1488
1489 struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1490         .enable = dw_hdmi_bridge_enable,
1491         .disable = dw_hdmi_bridge_disable,
1492         .pre_enable = dw_hdmi_bridge_nop,
1493         .post_disable = dw_hdmi_bridge_nop,
1494         .mode_set = dw_hdmi_bridge_mode_set,
1495         .mode_fixup = dw_hdmi_bridge_mode_fixup,
1496 };
1497
1498 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1499 {
1500         struct dw_hdmi *hdmi = dev_id;
1501         u8 intr_stat;
1502
1503         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1504         if (intr_stat)
1505                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1506
1507         return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
1508 }
1509
1510 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1511 {
1512         struct dw_hdmi *hdmi = dev_id;
1513         u8 intr_stat;
1514         u8 phy_int_pol;
1515
1516         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1517
1518         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1519
1520         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1521                 if (phy_int_pol & HDMI_PHY_HPD) {
1522                         dev_dbg(hdmi->dev, "EVENT=plugin\n");
1523
1524                         hdmi_modb(hdmi, 0, HDMI_PHY_HPD, HDMI_PHY_POL0);
1525
1526                         dw_hdmi_poweron(hdmi);
1527                 } else {
1528                         dev_dbg(hdmi->dev, "EVENT=plugout\n");
1529
1530                         hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD,
1531                                   HDMI_PHY_POL0);
1532
1533                         dw_hdmi_poweroff(hdmi);
1534                 }
1535                 drm_helper_hpd_irq_event(hdmi->bridge->dev);
1536         }
1537
1538         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1539         hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1540
1541         return IRQ_HANDLED;
1542 }
1543
1544 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
1545 {
1546         struct drm_encoder *encoder = hdmi->encoder;
1547         struct drm_bridge *bridge;
1548         int ret;
1549
1550         bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1551         if (!bridge) {
1552                 DRM_ERROR("Failed to allocate drm bridge\n");
1553                 return -ENOMEM;
1554         }
1555
1556         hdmi->bridge = bridge;
1557         bridge->driver_private = hdmi;
1558         bridge->funcs = &dw_hdmi_bridge_funcs;
1559         ret = drm_bridge_attach(drm, bridge);
1560         if (ret) {
1561                 DRM_ERROR("Failed to initialize bridge with drm\n");
1562                 return -EINVAL;
1563         }
1564
1565         encoder->bridge = bridge;
1566         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1567
1568         drm_connector_helper_add(&hdmi->connector,
1569                                  &dw_hdmi_connector_helper_funcs);
1570         drm_connector_init(drm, &hdmi->connector, &dw_hdmi_connector_funcs,
1571                            DRM_MODE_CONNECTOR_HDMIA);
1572
1573         hdmi->connector.encoder = encoder;
1574
1575         drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
1576
1577         return 0;
1578 }
1579
1580 int dw_hdmi_bind(struct device *dev, struct device *master,
1581                  void *data, struct drm_encoder *encoder,
1582                  struct resource *iores, int irq,
1583                  const struct dw_hdmi_plat_data *plat_data)
1584 {
1585         struct drm_device *drm = data;
1586         struct device_node *np = dev->of_node;
1587         struct device_node *ddc_node;
1588         struct dw_hdmi *hdmi;
1589         int ret;
1590         u32 val = 1;
1591
1592         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1593         if (!hdmi)
1594                 return -ENOMEM;
1595
1596         hdmi->plat_data = plat_data;
1597         hdmi->dev = dev;
1598         hdmi->dev_type = plat_data->dev_type;
1599         hdmi->sample_rate = 48000;
1600         hdmi->ratio = 100;
1601         hdmi->encoder = encoder;
1602
1603         mutex_init(&hdmi->audio_mutex);
1604         spin_lock_init(&hdmi->audio_lock);
1605
1606         of_property_read_u32(np, "reg-io-width", &val);
1607
1608         switch (val) {
1609         case 4:
1610                 hdmi->write = dw_hdmi_writel;
1611                 hdmi->read = dw_hdmi_readl;
1612                 break;
1613         case 1:
1614                 hdmi->write = dw_hdmi_writeb;
1615                 hdmi->read = dw_hdmi_readb;
1616                 break;
1617         default:
1618                 dev_err(dev, "reg-io-width must be 1 or 4\n");
1619                 return -EINVAL;
1620         }
1621
1622         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
1623         if (ddc_node) {
1624                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1625                 of_node_put(ddc_node);
1626                 if (!hdmi->ddc) {
1627                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
1628                         return -EPROBE_DEFER;
1629                 }
1630
1631         } else {
1632                 dev_dbg(hdmi->dev, "no ddc property found\n");
1633         }
1634
1635         hdmi->regs = devm_ioremap_resource(dev, iores);
1636         if (IS_ERR(hdmi->regs))
1637                 return PTR_ERR(hdmi->regs);
1638
1639         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1640         if (IS_ERR(hdmi->isfr_clk)) {
1641                 ret = PTR_ERR(hdmi->isfr_clk);
1642                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
1643                 return ret;
1644         }
1645
1646         ret = clk_prepare_enable(hdmi->isfr_clk);
1647         if (ret) {
1648                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
1649                 return ret;
1650         }
1651
1652         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1653         if (IS_ERR(hdmi->iahb_clk)) {
1654                 ret = PTR_ERR(hdmi->iahb_clk);
1655                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
1656                 goto err_isfr;
1657         }
1658
1659         ret = clk_prepare_enable(hdmi->iahb_clk);
1660         if (ret) {
1661                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
1662                 goto err_isfr;
1663         }
1664
1665         /* Product and revision IDs */
1666         dev_info(dev,
1667                  "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1668                  hdmi_readb(hdmi, HDMI_DESIGN_ID),
1669                  hdmi_readb(hdmi, HDMI_REVISION_ID),
1670                  hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1671                  hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
1672
1673         initialize_hdmi_ih_mutes(hdmi);
1674
1675         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
1676                                         dw_hdmi_irq, IRQF_SHARED,
1677                                         dev_name(dev), hdmi);
1678         if (ret)
1679                 goto err_iahb;
1680
1681         /*
1682          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1683          * N and cts values before enabling phy
1684          */
1685         hdmi_init_clk_regenerator(hdmi);
1686
1687         /*
1688          * Configure registers related to HDMI interrupt
1689          * generation before registering IRQ.
1690          */
1691         hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0);
1692
1693         /* Clear Hotplug interrupts */
1694         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1695
1696         ret = dw_hdmi_fb_registered(hdmi);
1697         if (ret)
1698                 goto err_iahb;
1699
1700         ret = dw_hdmi_register(drm, hdmi);
1701         if (ret)
1702                 goto err_iahb;
1703
1704         /* Unmute interrupts */
1705         hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1706
1707         dev_set_drvdata(dev, hdmi);
1708
1709         return 0;
1710
1711 err_iahb:
1712         clk_disable_unprepare(hdmi->iahb_clk);
1713 err_isfr:
1714         clk_disable_unprepare(hdmi->isfr_clk);
1715
1716         return ret;
1717 }
1718 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
1719
1720 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
1721 {
1722         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
1723
1724         /* Disable all interrupts */
1725         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1726
1727         hdmi->connector.funcs->destroy(&hdmi->connector);
1728         hdmi->encoder->funcs->destroy(hdmi->encoder);
1729
1730         clk_disable_unprepare(hdmi->iahb_clk);
1731         clk_disable_unprepare(hdmi->isfr_clk);
1732         i2c_put_adapter(hdmi->ddc);
1733 }
1734 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
1735
1736 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1737 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
1738 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
1739 MODULE_DESCRIPTION("DW HDMI transmitter driver");
1740 MODULE_LICENSE("GPL");
1741 MODULE_ALIAS("platform:dw-hdmi");