drivers/gpu/drm/bridge/dw_hdmi.c

   1 /*
   2  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * Designware High-Definition Multimedia Interface (HDMI) driver
  10  *
  11  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  12  */
  13 #include <linux/module.h>
  14 #include <linux/irq.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/hdmi.h>
  19 #include <linux/mutex.h>
  20 #include <linux/of_device.h>
  21
  22 #include <drm/drm_of.h>
  23 #include <drm/drmP.h>
  24 #include <drm/drm_crtc_helper.h>
  25 #include <drm/drm_edid.h>
  26 #include <drm/drm_encoder_slave.h>
  27 #include <drm/bridge/dw_hdmi.h>
  28
  29 #include "dw_hdmi.h"
  30
  31 #define HDMI_EDID_LEN           512
  32
  33 #define RGB                     0
  34 #define YCBCR444                1
  35 #define YCBCR422_16BITS         2
  36 #define YCBCR422_8BITS          3
  37 #define XVYCC444                4
  38
  39 enum hdmi_datamap {
  40         RGB444_8B = 0x01,
  41         RGB444_10B = 0x03,
  42         RGB444_12B = 0x05,
  43         RGB444_16B = 0x07,
  44         YCbCr444_8B = 0x09,
  45         YCbCr444_10B = 0x0B,
  46         YCbCr444_12B = 0x0D,
  47         YCbCr444_16B = 0x0F,
  48         YCbCr422_8B = 0x16,
  49         YCbCr422_10B = 0x14,
  50         YCbCr422_12B = 0x12,
  51 };
  52
  53 static const u16 csc_coeff_default[3][4] = {
  54         { 0x2000, 0x0000, 0x0000, 0x0000 },
  55         { 0x0000, 0x2000, 0x0000, 0x0000 },
  56         { 0x0000, 0x0000, 0x2000, 0x0000 }
  57 };
  58
  59 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
  60         { 0x2000, 0x6926, 0x74fd, 0x010e },
  61         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
  62         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
  63 };
  64
  65 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
  66         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
  67         { 0x2000, 0x3264, 0x0000, 0x7e6d },
  68         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
  69 };
  70
  71 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
  72         { 0x2591, 0x1322, 0x074b, 0x0000 },
  73         { 0x6535, 0x2000, 0x7acc, 0x0200 },
  74         { 0x6acd, 0x7534, 0x2000, 0x0200 }
  75 };
  76
  77 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
  78         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
  79         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
  80         { 0x6756, 0x78ab, 0x2000, 0x0200 }
  81 };
  82
  83 struct hdmi_vmode {
  84         bool mdvi;
  85         bool mhsyncpolarity;
  86         bool mvsyncpolarity;
  87         bool minterlaced;
  88         bool mdataenablepolarity;
  89
  90         unsigned int mpixelclock;
  91         unsigned int mpixelrepetitioninput;
  92         unsigned int mpixelrepetitionoutput;
  93 };
  94
  95 struct hdmi_data_info {
  96         unsigned int enc_in_format;
  97         unsigned int enc_out_format;
  98         unsigned int enc_color_depth;
  99         unsigned int colorimetry;
 100         unsigned int pix_repet_factor;
 101         unsigned int hdcp_enable;
 102         struct hdmi_vmode video_mode;
 103 };
 104
 105 struct dw_hdmi {
 106         struct drm_connector connector;
 107         struct drm_encoder *encoder;
 108         struct drm_bridge *bridge;
 109
 110         enum dw_hdmi_devtype dev_type;
 111         struct device *dev;
 112         struct clk *isfr_clk;
 113         struct clk *iahb_clk;
 114
 115         struct hdmi_data_info hdmi_data;
 116         const struct dw_hdmi_plat_data *plat_data;
 117
 118         int vic;
 119
 120         u8 edid[HDMI_EDID_LEN];
 121         bool cable_plugin;
 122
 123         bool phy_enabled;
 124         struct drm_display_mode previous_mode;
 125
 126         struct i2c_adapter *ddc;
 127         void __iomem *regs;
 128
 129         struct mutex audio_mutex;
 130         unsigned int sample_rate;
 131         int ratio;
 132
 133         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
 134         u8 (*read)(struct dw_hdmi *hdmi, int offset);
 135 };
 136
 137 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
 138 {
 139         writel(val, hdmi->regs + (offset << 2));
 140 }
 141
 142 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
 143 {
 144         return readl(hdmi->regs + (offset << 2));
 145 }
 146
 147 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 148 {
 149         writeb(val, hdmi->regs + offset);
 150 }
 151
 152 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
 153 {
 154         return readb(hdmi->regs + offset);
 155 }
 156
 157 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 158 {
 159         hdmi->write(hdmi, val, offset);
 160 }
 161
 162 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 163 {
 164         return hdmi->read(hdmi, offset);
 165 }
 166
 167 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 168 {
 169         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 170
 171         val |= data & mask;
 172         hdmi_writeb(hdmi, val, reg);
 173 }
 174
 175 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 176                              u8 shift, u8 mask)
 177 {
 178         hdmi_modb(hdmi, data << shift, mask, reg);
 179 }
 180
 181 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 182                            unsigned int n)
 183 {
 184         /* Must be set/cleared first */
 185         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 186
 187         /* nshift factor = 0 */
 188         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 189
 190         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 191                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 192         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 193         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 194
 195         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 196         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 197         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 198 }
 199
 200 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk,
 201                                    unsigned int ratio)
 202 {
 203         unsigned int n = (128 * freq) / 1000;
 204
 205         switch (freq) {
 206         case 32000:
 207                 if (pixel_clk == 25170000)
 208                         n = (ratio == 150) ? 9152 : 4576;
 209                 else if (pixel_clk == 27020000)
 210                         n = (ratio == 150) ? 8192 : 4096;
 211                 else if (pixel_clk == 74170000 || pixel_clk == 148350000)
 212                         n = 11648;
 213                 else
 214                         n = 4096;
 215                 break;
 216
 217         case 44100:
 218                 if (pixel_clk == 25170000)
 219                         n = 7007;
 220                 else if (pixel_clk == 74170000)
 221                         n = 17836;
 222                 else if (pixel_clk == 148350000)
 223                         n = (ratio == 150) ? 17836 : 8918;
 224                 else
 225                         n = 6272;
 226                 break;
 227
 228         case 48000:
 229                 if (pixel_clk == 25170000)
 230                         n = (ratio == 150) ? 9152 : 6864;
 231                 else if (pixel_clk == 27020000)
 232                         n = (ratio == 150) ? 8192 : 6144;
 233                 else if (pixel_clk == 74170000)
 234                         n = 11648;
 235                 else if (pixel_clk == 148350000)
 236                         n = (ratio == 150) ? 11648 : 5824;
 237                 else
 238                         n = 6144;
 239                 break;
 240
 241         case 88200:
 242                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 2;
 243                 break;
 244
 245         case 96000:
 246                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 2;
 247                 break;
 248
 249         case 176400:
 250                 n = hdmi_compute_n(44100, pixel_clk, ratio) * 4;
 251                 break;
 252
 253         case 192000:
 254                 n = hdmi_compute_n(48000, pixel_clk, ratio) * 4;
 255                 break;
 256
 257         default:
 258                 break;
 259         }
 260
 261         return n;
 262 }
 263
 264 static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk,
 265                                      unsigned int ratio)
 266 {
 267         unsigned int cts = 0;
 268
 269         pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq,
 270                  pixel_clk, ratio);
 271
 272         switch (freq) {
 273         case 32000:
 274                 if (pixel_clk == 297000000) {
 275                         cts = 222750;
 276                         break;
 277                 }
 278         case 48000:
 279         case 96000:
 280         case 192000:
 281                 switch (pixel_clk) {
 282                 case 25200000:
 283                 case 27000000:
 284                 case 54000000:
 285                 case 74250000:
 286                 case 148500000:
 287                         cts = pixel_clk / 1000;
 288                         break;
 289                 case 297000000:
 290                         cts = 247500;
 291                         break;
 292                 /*
 293                  * All other TMDS clocks are not supported by
 294                  * DWC_hdmi_tx. The TMDS clocks divided or
 295                  * multiplied by 1,001 coefficients are not
 296                  * supported.
 297                  */
 298                 default:
 299                         break;
 300                 }
 301                 break;
 302         case 44100:
 303         case 88200:
 304         case 176400:
 305                 switch (pixel_clk) {
 306                 case 25200000:
 307                         cts = 28000;
 308                         break;
 309                 case 27000000:
 310                         cts = 30000;
 311                         break;
 312                 case 54000000:
 313                         cts = 60000;
 314                         break;
 315                 case 74250000:
 316                         cts = 82500;
 317                         break;
 318                 case 148500000:
 319                         cts = 165000;
 320                         break;
 321                 case 297000000:
 322                         cts = 247500;
 323                         break;
 324                 default:
 325                         break;
 326                 }
 327                 break;
 328         default:
 329                 break;
 330         }
 331         if (ratio == 100)
 332                 return cts;
 333         return (cts * ratio) / 100;
 334 }
 335
 336 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 337         unsigned long pixel_clk, unsigned int sample_rate, unsigned int ratio)
 338 {
 339         unsigned int n, cts;
 340
 341         n = hdmi_compute_n(sample_rate, pixel_clk, ratio);
 342         cts = hdmi_compute_cts(sample_rate, pixel_clk, ratio);
 343         if (!cts) {
 344                 dev_err(hdmi->dev,
 345                         "%s: pixel clock/sample rate not supported: %luMHz / %ukHz\n",
 346                         __func__, pixel_clk, sample_rate);
 347         }
 348
 349         dev_dbg(hdmi->dev, "%s: samplerate=%ukHz ratio=%d pixelclk=%luMHz N=%d cts=%d\n",
 350                 __func__, sample_rate, ratio, pixel_clk, n, cts);
 351
 352         hdmi_set_cts_n(hdmi, cts, n);
 353 }
 354
 355 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 356 {
 357         mutex_lock(&hdmi->audio_mutex);
 358         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate,
 359                                  hdmi->ratio);
 360         mutex_unlock(&hdmi->audio_mutex);
 361 }
 362
 363 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 364 {
 365         mutex_lock(&hdmi->audio_mutex);
 366         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 367                                  hdmi->sample_rate, hdmi->ratio);
 368         mutex_unlock(&hdmi->audio_mutex);
 369 }
 370
 371 /*
 372  * this submodule is responsible for the video data synchronization.
 373  * for example, for RGB 4:4:4 input, the data map is defined as
 374  *                      pin{47~40} <==> R[7:0]
 375  *                      pin{31~24} <==> G[7:0]
 376  *                      pin{15~8}  <==> B[7:0]
 377  */
 378 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 379 {
 380         int color_format = 0;
 381         u8 val;
 382
 383         if (hdmi->hdmi_data.enc_in_format == RGB) {
 384                 if (hdmi->hdmi_data.enc_color_depth == 8)
 385                         color_format = 0x01;
 386                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 387                         color_format = 0x03;
 388                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 389                         color_format = 0x05;
 390                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 391                         color_format = 0x07;
 392                 else
 393                         return;
 394         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
 395                 if (hdmi->hdmi_data.enc_color_depth == 8)
 396                         color_format = 0x09;
 397                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 398                         color_format = 0x0B;
 399                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 400                         color_format = 0x0D;
 401                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 402                         color_format = 0x0F;
 403                 else
 404                         return;
 405         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 406                 if (hdmi->hdmi_data.enc_color_depth == 8)
 407                         color_format = 0x16;
 408                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 409                         color_format = 0x14;
 410                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 411                         color_format = 0x12;
 412                 else
 413                         return;
 414         }
 415
 416         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 417                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 418                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 419         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 420
 421         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 422         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 423                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 424                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 425         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 426         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 427         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 428         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 429         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 430         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 431         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 432 }
 433
 434 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 435 {
 436         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
 437 }
 438
 439 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 440 {
 441         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
 442                 return 0;
 443         if (hdmi->hdmi_data.enc_in_format == RGB ||
 444             hdmi->hdmi_data.enc_in_format == YCBCR444)
 445                 return 1;
 446         return 0;
 447 }
 448
 449 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 450 {
 451         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
 452                 return 0;
 453         if (hdmi->hdmi_data.enc_out_format == RGB ||
 454             hdmi->hdmi_data.enc_out_format == YCBCR444)
 455                 return 1;
 456         return 0;
 457 }
 458
 459 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 460 {
 461         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 462         unsigned i;
 463         u32 csc_scale = 1;
 464
 465         if (is_color_space_conversion(hdmi)) {
 466                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 467                         if (hdmi->hdmi_data.colorimetry ==
 468                                         HDMI_COLORIMETRY_ITU_601)
 469                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 470                         else
 471                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 472                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 473                         if (hdmi->hdmi_data.colorimetry ==
 474                                         HDMI_COLORIMETRY_ITU_601)
 475                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 476                         else
 477                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 478                         csc_scale = 0;
 479                 }
 480         }
 481
 482         /* The CSC registers are sequential, alternating MSB then LSB */
 483         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 484                 u16 coeff_a = (*csc_coeff)[0][i];
 485                 u16 coeff_b = (*csc_coeff)[1][i];
 486                 u16 coeff_c = (*csc_coeff)[2][i];
 487
 488                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 489                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 490                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 491                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 492                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 493                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 494         }
 495
 496         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 497                   HDMI_CSC_SCALE);
 498 }
 499
 500 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 501 {
 502         int color_depth = 0;
 503         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 504         int decimation = 0;
 505
 506         /* YCC422 interpolation to 444 mode */
 507         if (is_color_space_interpolation(hdmi))
 508                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 509         else if (is_color_space_decimation(hdmi))
 510                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 511
 512         if (hdmi->hdmi_data.enc_color_depth == 8)
 513                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 514         else if (hdmi->hdmi_data.enc_color_depth == 10)
 515                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 516         else if (hdmi->hdmi_data.enc_color_depth == 12)
 517                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 518         else if (hdmi->hdmi_data.enc_color_depth == 16)
 519                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 520         else
 521                 return;
 522
 523         /* Configure the CSC registers */
 524         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 525         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 526                   HDMI_CSC_SCALE);
 527
 528         dw_hdmi_update_csc_coeffs(hdmi);
 529 }
 530
 531 /*
 532  * HDMI video packetizer is used to packetize the data.
 533  * for example, if input is YCC422 mode or repeater is used,
 534  * data should be repacked this module can be bypassed.
 535  */
 536 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 537 {
 538         unsigned int color_depth = 0;
 539         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 540         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 541         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 542         u8 val, vp_conf;
 543
 544         if (hdmi_data->enc_out_format == RGB ||
 545             hdmi_data->enc_out_format == YCBCR444) {
 546                 if (!hdmi_data->enc_color_depth) {
 547                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 548                 } else if (hdmi_data->enc_color_depth == 8) {
 549                         color_depth = 4;
 550                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 551                 } else if (hdmi_data->enc_color_depth == 10) {
 552                         color_depth = 5;
 553                 } else if (hdmi_data->enc_color_depth == 12) {
 554                         color_depth = 6;
 555                 } else if (hdmi_data->enc_color_depth == 16) {
 556                         color_depth = 7;
 557                 } else {
 558                         return;
 559                 }
 560         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 561                 if (!hdmi_data->enc_color_depth ||
 562                     hdmi_data->enc_color_depth == 8)
 563                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 564                 else if (hdmi_data->enc_color_depth == 10)
 565                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 566                 else if (hdmi_data->enc_color_depth == 12)
 567                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 568                 else
 569                         return;
 570                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 571         } else {
 572                 return;
 573         }
 574
 575         /* set the packetizer registers */
 576         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 577                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 578                 ((hdmi_data->pix_repet_factor <<
 579                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 580                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 581         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 582
 583         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 584                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 585
 586         /* Data from pixel repeater block */
 587         if (hdmi_data->pix_repet_factor > 1) {
 588                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 589                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 590         } else { /* data from packetizer block */
 591                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 592                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 593         }
 594
 595         hdmi_modb(hdmi, vp_conf,
 596                   HDMI_VP_CONF_PR_EN_MASK |
 597                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 598
 599         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 600                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 601
 602         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 603
 604         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 605                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 606                           HDMI_VP_CONF_PP_EN_ENABLE |
 607                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 608         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 609                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 610                           HDMI_VP_CONF_PP_EN_DISABLE |
 611                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 612         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 613                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 614                           HDMI_VP_CONF_PP_EN_DISABLE |
 615                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 616         } else {
 617                 return;
 618         }
 619
 620         hdmi_modb(hdmi, vp_conf,
 621                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 622                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 623
 624         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 625                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 626                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 627                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 628
 629         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 630                   HDMI_VP_CONF);
 631 }
 632
 633 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
 634                                        unsigned char bit)
 635 {
 636         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 637                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 638 }
 639
 640 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
 641                                         unsigned char bit)
 642 {
 643         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
 644                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
 645 }
 646
 647 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
 648                                        unsigned char bit)
 649 {
 650         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
 651                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
 652 }
 653
 654 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
 655                                      unsigned char bit)
 656 {
 657         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
 658 }
 659
 660 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
 661                                       unsigned char bit)
 662 {
 663         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
 664 }
 665
 666 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
 667 {
 668         u32 val;
 669
 670         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
 671                 if (msec-- == 0)
 672                         return false;
 673                 udelay(1000);
 674         }
 675         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
 676
 677         return true;
 678 }
 679
 680 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 681                                  unsigned char addr)
 682 {
 683         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
 684         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
 685         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
 686                     HDMI_PHY_I2CM_DATAO_1_ADDR);
 687         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
 688                     HDMI_PHY_I2CM_DATAO_0_ADDR);
 689         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
 690                     HDMI_PHY_I2CM_OPERATION_ADDR);
 691         hdmi_phy_wait_i2c_done(hdmi, 1000);
 692 }
 693
 694 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 695                               unsigned char addr)
 696 {
 697         __hdmi_phy_i2c_write(hdmi, data, addr);
 698         return 0;
 699 }
 700
 701 static void dw_hdmi_phy_enable_power(struct dw_hdmi *hdmi, u8 enable)
 702 {
 703         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 704                          HDMI_PHY_CONF0_PDZ_OFFSET,
 705                          HDMI_PHY_CONF0_PDZ_MASK);
 706 }
 707
 708 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
 709 {
 710         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 711                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
 712                          HDMI_PHY_CONF0_ENTMDS_MASK);
 713 }
 714
 715 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
 716 {
 717         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 718                          HDMI_PHY_CONF0_SPARECTRL_OFFSET,
 719                          HDMI_PHY_CONF0_SPARECTRL_MASK);
 720 }
 721
 722 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
 723 {
 724         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 725                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
 726                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
 727 }
 728
 729 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
 730 {
 731         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 732                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
 733                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
 734 }
 735
 736 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
 737 {
 738         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 739                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
 740                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
 741 }
 742
 743 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
 744 {
 745         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 746                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
 747                          HDMI_PHY_CONF0_SELDIPIF_MASK);
 748 }
 749
 750 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
 751                               unsigned char res, int cscon)
 752 {
 753         unsigned res_idx;
 754         u8 val, msec;
 755         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
 756         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
 757         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
 758         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
 759
 760         if (prep)
 761                 return -EINVAL;
 762
 763         switch (res) {
 764         case 0: /* color resolution 0 is 8 bit colour depth */
 765         case 8:
 766                 res_idx = DW_HDMI_RES_8;
 767                 break;
 768         case 10:
 769                 res_idx = DW_HDMI_RES_10;
 770                 break;
 771         case 12:
 772                 res_idx = DW_HDMI_RES_12;
 773                 break;
 774         default:
 775                 return -EINVAL;
 776         }
 777
 778         /* PLL/MPLL Cfg - always match on final entry */
 779         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
 780                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 781                     mpll_config->mpixelclock)
 782                         break;
 783
 784         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
 785                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 786                     curr_ctrl->mpixelclock)
 787                         break;
 788
 789         for (; phy_config->mpixelclock != ~0UL; phy_config++)
 790                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 791                     phy_config->mpixelclock)
 792                         break;
 793
 794         if (mpll_config->mpixelclock == ~0UL ||
 795             curr_ctrl->mpixelclock == ~0UL ||
 796             phy_config->mpixelclock == ~0UL) {
 797                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
 798                         hdmi->hdmi_data.video_mode.mpixelclock);
 799                 return -EINVAL;
 800         }
 801
 802         /* Enable csc path */
 803         if (cscon)
 804                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
 805         else
 806                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
 807
 808         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
 809
 810         /* gen2 tx power off */
 811         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
 812
 813         /* gen2 pddq */
 814         dw_hdmi_phy_gen2_pddq(hdmi, 1);
 815
 816         /* PHY reset */
 817         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
 818         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
 819
 820         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
 821
 822         hdmi_phy_test_clear(hdmi, 1);
 823         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
 824                     HDMI_PHY_I2CM_SLAVE_ADDR);
 825         hdmi_phy_test_clear(hdmi, 0);
 826
 827         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
 828         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
 829
 830         /* CURRCTRL */
 831         hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
 832
 833         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
 834         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
 835
 836         hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19);  /* TXTERM */
 837         hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
 838         hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
 839
 840         /* REMOVE CLK TERM */
 841         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
 842
 843         dw_hdmi_phy_enable_power(hdmi, 1);
 844
 845         /* toggle TMDS enable */
 846         dw_hdmi_phy_enable_tmds(hdmi, 0);
 847         dw_hdmi_phy_enable_tmds(hdmi, 1);
 848
 849         /* gen2 tx power on */
 850         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
 851         dw_hdmi_phy_gen2_pddq(hdmi, 0);
 852
 853         if (hdmi->dev_type == RK3288_HDMI)
 854                 dw_hdmi_phy_enable_spare(hdmi, 1);
 855
 856         /*Wait for PHY PLL lock */
 857         msec = 5;
 858         do {
 859                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
 860                 if (!val)
 861                         break;
 862
 863                 if (msec == 0) {
 864                         dev_err(hdmi->dev, "PHY PLL not locked\n");
 865                         return -ETIMEDOUT;
 866                 }
 867
 868                 udelay(1000);
 869                 msec--;
 870         } while (1);
 871
 872         return 0;
 873 }
 874
 875 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
 876 {
 877         int i, ret;
 878         bool cscon = false;
 879
 880         /*check csc whether needed activated in HDMI mode */
 881         cscon = (is_color_space_conversion(hdmi) &&
 882                         !hdmi->hdmi_data.video_mode.mdvi);
 883
 884         /* HDMI Phy spec says to do the phy initialization sequence twice */
 885         for (i = 0; i < 2; i++) {
 886                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
 887                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
 888                 dw_hdmi_phy_enable_tmds(hdmi, 0);
 889                 dw_hdmi_phy_enable_power(hdmi, 0);
 890
 891                 /* Enable CSC */
 892                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
 893                 if (ret)
 894                         return ret;
 895         }
 896
 897         hdmi->phy_enabled = true;
 898         return 0;
 899 }
 900
 901 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
 902 {
 903         u8 de;
 904
 905         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
 906                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
 907         else
 908                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
 909
 910         /* disable rx detect */
 911         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
 912                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
 913
 914         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
 915
 916         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
 917                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
 918 }
 919
 920 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
 921 {
 922         struct hdmi_avi_infoframe frame;
 923         u8 val;
 924
 925         /* Initialise info frame from DRM mode */
 926         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 927
 928         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
 929                 frame.colorspace = HDMI_COLORSPACE_YUV444;
 930         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
 931                 frame.colorspace = HDMI_COLORSPACE_YUV422;
 932         else
 933                 frame.colorspace = HDMI_COLORSPACE_RGB;
 934
 935         /* Set up colorimetry */
 936         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
 937                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
 938                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
 939                         frame.extended_colorimetry =
 940                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 941                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
 942                         frame.extended_colorimetry =
 943                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
 944         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
 945                 frame.colorimetry = hdmi->hdmi_data.colorimetry;
 946                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 947         } else { /* Carries no data */
 948                 frame.colorimetry = HDMI_COLORIMETRY_NONE;
 949                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 950         }
 951
 952         frame.scan_mode = HDMI_SCAN_MODE_NONE;
 953
 954         /*
 955          * The Designware IP uses a different byte format from standard
 956          * AVI info frames, though generally the bits are in the correct
 957          * bytes.
 958          */
 959
 960         /*
 961          * AVI data byte 1 differences: Colorspace in bits 4,5 rather than 5,6,
 962          * active aspect present in bit 6 rather than 4.
 963          */
 964         val = (frame.colorspace & 3) << 4 | (frame.scan_mode & 0x3);
 965         if (frame.active_aspect & 15)
 966                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
 967         if (frame.top_bar || frame.bottom_bar)
 968                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
 969         if (frame.left_bar || frame.right_bar)
 970                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
 971         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
 972
 973         /* AVI data byte 2 differences: none */
 974         val = ((frame.colorimetry & 0x3) << 6) |
 975               ((frame.picture_aspect & 0x3) << 4) |
 976               (frame.active_aspect & 0xf);
 977         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
 978
 979         /* AVI data byte 3 differences: none */
 980         val = ((frame.extended_colorimetry & 0x7) << 4) |
 981               ((frame.quantization_range & 0x3) << 2) |
 982               (frame.nups & 0x3);
 983         if (frame.itc)
 984                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
 985         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
 986
 987         /* AVI data byte 4 differences: none */
 988         val = frame.video_code & 0x7f;
 989         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
 990
 991         /* AVI Data Byte 5- set up input and output pixel repetition */
 992         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
 993                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
 994                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
 995                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
 996                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
 997                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
 998         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
 999
1000         /*
1001          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
1002          * ycc range in bits 2,3 rather than 6,7
1003          */
1004         val = ((frame.ycc_quantization_range & 0x3) << 2) |
1005               (frame.content_type & 0x3);
1006         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
1007
1008         /* AVI Data Bytes 6-13 */
1009         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
1010         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
1011         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
1012         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
1013         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
1014         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
1015         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
1016         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1017 }
1018
1019 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1020                              const struct drm_display_mode *mode)
1021 {
1022         u8 inv_val;
1023         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1024         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1025
1026         vmode->mhsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PHSYNC);
1027         vmode->mvsyncpolarity = !!(mode->flags & DRM_MODE_FLAG_PVSYNC);
1028         vmode->minterlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1029         vmode->mpixelclock = mode->clock * 1000;
1030
1031         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1032
1033         /* Set up HDMI_FC_INVIDCONF */
1034         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1035                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1036                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1037
1038         inv_val |= (vmode->mvsyncpolarity ?
1039                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1040                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
1041
1042         inv_val |= (vmode->mhsyncpolarity ?
1043                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1044                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
1045
1046         inv_val |= (vmode->mdataenablepolarity ?
1047                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1048                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1049
1050         if (hdmi->vic == 39)
1051                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1052         else
1053                 inv_val |= (vmode->minterlaced ?
1054                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1055                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW);
1056
1057         inv_val |= (vmode->minterlaced ?
1058                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1059                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE);
1060
1061         inv_val |= (vmode->mdvi ?
1062                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE :
1063                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE);
1064
1065         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1066
1067         /* Set up horizontal active pixel width */
1068         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1069         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1070
1071         /* Set up vertical active lines */
1072         hdmi_writeb(hdmi, mode->vdisplay >> 8, HDMI_FC_INVACTV1);
1073         hdmi_writeb(hdmi, mode->vdisplay, HDMI_FC_INVACTV0);
1074
1075         /* Set up horizontal blanking pixel region width */
1076         hblank = mode->htotal - mode->hdisplay;
1077         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1078         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1079
1080         /* Set up vertical blanking pixel region width */
1081         vblank = mode->vtotal - mode->vdisplay;
1082         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1083
1084         /* Set up HSYNC active edge delay width (in pixel clks) */
1085         h_de_hs = mode->hsync_start - mode->hdisplay;
1086         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1087         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1088
1089         /* Set up VSYNC active edge delay (in lines) */
1090         v_de_vs = mode->vsync_start - mode->vdisplay;
1091         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1092
1093         /* Set up HSYNC active pulse width (in pixel clks) */
1094         hsync_len = mode->hsync_end - mode->hsync_start;
1095         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1096         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1097
1098         /* Set up VSYNC active edge delay (in lines) */
1099         vsync_len = mode->vsync_end - mode->vsync_start;
1100         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1101 }
1102
1103 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1104 {
1105         if (!hdmi->phy_enabled)
1106                 return;
1107
1108         dw_hdmi_phy_enable_tmds(hdmi, 0);
1109         dw_hdmi_phy_enable_power(hdmi, 0);
1110
1111         hdmi->phy_enabled = false;
1112 }
1113
1114 /* HDMI Initialization Step B.4 */
1115 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1116 {
1117         u8 clkdis;
1118
1119         /* control period minimum duration */
1120         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1121         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1122         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1123
1124         /* Set to fill TMDS data channels */
1125         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1126         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1127         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1128
1129         /* Enable pixel clock and tmds data path */
1130         clkdis = 0x7F;
1131         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1132         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1133
1134         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1135         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1136
1137         /* Enable csc path */
1138         if (is_color_space_conversion(hdmi)) {
1139                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1140                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1141         }
1142 }
1143
1144 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1145 {
1146         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1147 }
1148
1149 /* Workaround to clear the overflow condition */
1150 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1151 {
1152         int count;
1153         u8 val;
1154
1155         /* TMDS software reset */
1156         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1157
1158         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1159         if (hdmi->dev_type == IMX6DL_HDMI) {
1160                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1161                 return;
1162         }
1163
1164         for (count = 0; count < 4; count++)
1165                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1166 }
1167
1168 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1169 {
1170         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1171         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1172 }
1173
1174 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1175 {
1176         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1177                     HDMI_IH_MUTE_FC_STAT2);
1178 }
1179
1180 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1181 {
1182         int ret;
1183
1184         hdmi_disable_overflow_interrupts(hdmi);
1185
1186         hdmi->vic = drm_match_cea_mode(mode);
1187
1188         if (!hdmi->vic) {
1189                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1190                 hdmi->hdmi_data.video_mode.mdvi = true;
1191         } else {
1192                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1193                 hdmi->hdmi_data.video_mode.mdvi = false;
1194         }
1195
1196         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1197             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1198             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1199             (hdmi->vic == 17) || (hdmi->vic == 18))
1200                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1201         else
1202                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1203
1204         if ((hdmi->vic == 10) || (hdmi->vic == 11) ||
1205             (hdmi->vic == 12) || (hdmi->vic == 13) ||
1206             (hdmi->vic == 14) || (hdmi->vic == 15) ||
1207             (hdmi->vic == 25) || (hdmi->vic == 26) ||
1208             (hdmi->vic == 27) || (hdmi->vic == 28) ||
1209             (hdmi->vic == 29) || (hdmi->vic == 30) ||
1210             (hdmi->vic == 35) || (hdmi->vic == 36) ||
1211             (hdmi->vic == 37) || (hdmi->vic == 38))
1212                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 1;
1213         else
1214                 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1215
1216         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1217
1218         /* TODO: Get input format from IPU (via FB driver interface) */
1219         hdmi->hdmi_data.enc_in_format = RGB;
1220
1221         hdmi->hdmi_data.enc_out_format = RGB;
1222
1223         hdmi->hdmi_data.enc_color_depth = 8;
1224         hdmi->hdmi_data.pix_repet_factor = 0;
1225         hdmi->hdmi_data.hdcp_enable = 0;
1226         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1227
1228         /* HDMI Initialization Step B.1 */
1229         hdmi_av_composer(hdmi, mode);
1230
1231         /* HDMI Initializateion Step B.2 */
1232         ret = dw_hdmi_phy_init(hdmi);
1233         if (ret)
1234                 return ret;
1235
1236         /* HDMI Initialization Step B.3 */
1237         dw_hdmi_enable_video_path(hdmi);
1238
1239         /* not for DVI mode */
1240         if (hdmi->hdmi_data.video_mode.mdvi) {
1241                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1242         } else {
1243                 dev_dbg(hdmi->dev, "%s CEA mode\n", __func__);
1244
1245                 /* HDMI Initialization Step E - Configure audio */
1246                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1247                 hdmi_enable_audio_clk(hdmi);
1248
1249                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1250                 hdmi_config_AVI(hdmi, mode);
1251         }
1252
1253         hdmi_video_packetize(hdmi);
1254         hdmi_video_csc(hdmi);
1255         hdmi_video_sample(hdmi);
1256         hdmi_tx_hdcp_config(hdmi);
1257
1258         dw_hdmi_clear_overflow(hdmi);
1259         if (hdmi->cable_plugin && !hdmi->hdmi_data.video_mode.mdvi)
1260                 hdmi_enable_overflow_interrupts(hdmi);
1261
1262         return 0;
1263 }
1264
1265 /* Wait until we are registered to enable interrupts */
1266 static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
1267 {
1268         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1269                     HDMI_PHY_I2CM_INT_ADDR);
1270
1271         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1272                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1273                     HDMI_PHY_I2CM_CTLINT_ADDR);
1274
1275         /* enable cable hot plug irq */
1276         hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
1277
1278         /* Clear Hotplug interrupts */
1279         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1280
1281         return 0;
1282 }
1283
1284 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1285 {
1286         u8 ih_mute;
1287
1288         /*
1289          * Boot up defaults are:
1290          * HDMI_IH_MUTE   = 0x03 (disabled)
1291          * HDMI_IH_MUTE_* = 0x00 (enabled)
1292          *
1293          * Disable top level interrupt bits in HDMI block
1294          */
1295         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1296                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1297                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1298
1299         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1300
1301         /* by default mask all interrupts */
1302         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1303         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1304         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1305         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1306         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1307         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1308         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1309         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1310         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1311         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1312         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1313         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1314         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1315         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1316         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1317
1318         /* Disable interrupts in the IH_MUTE_* registers */
1319         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1320         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1321         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1322         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1323         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1324         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1325         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1326         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1327         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1328         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1329
1330         /* Enable top level interrupt bits in HDMI block */
1331         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1332                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1333         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1334 }
1335
1336 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1337 {
1338         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1339 }
1340
1341 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1342 {
1343         dw_hdmi_phy_disable(hdmi);
1344 }
1345
1346 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1347                                     struct drm_display_mode *orig_mode,
1348                                     struct drm_display_mode *mode)
1349 {
1350         struct dw_hdmi *hdmi = bridge->driver_private;
1351
1352         dw_hdmi_setup(hdmi, mode);
1353
1354         /* Store the display mode for plugin/DKMS poweron events */
1355         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1356 }
1357
1358 static bool dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1359                                       const struct drm_display_mode *mode,
1360                                       struct drm_display_mode *adjusted_mode)
1361 {
1362         return true;
1363 }
1364
1365 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1366 {
1367         struct dw_hdmi *hdmi = bridge->driver_private;
1368
1369         dw_hdmi_poweroff(hdmi);
1370 }
1371
1372 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1373 {
1374         struct dw_hdmi *hdmi = bridge->driver_private;
1375
1376         dw_hdmi_poweron(hdmi);
1377 }
1378
1379 static void dw_hdmi_bridge_nop(struct drm_bridge *bridge)
1380 {
1381         /* do nothing */
1382 }
1383
1384 static enum drm_connector_status
1385 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1386 {
1387         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1388                                              connector);
1389
1390         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1391                 connector_status_connected : connector_status_disconnected;
1392 }
1393
1394 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1395 {
1396         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1397                                              connector);
1398         struct edid *edid;
1399         int ret;
1400
1401         if (!hdmi->ddc)
1402                 return 0;
1403
1404         edid = drm_get_edid(connector, hdmi->ddc);
1405         if (edid) {
1406                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1407                         edid->width_cm, edid->height_cm);
1408
1409                 drm_mode_connector_update_edid_property(connector, edid);
1410                 ret = drm_add_edid_modes(connector, edid);
1411                 kfree(edid);
1412         } else {
1413                 dev_dbg(hdmi->dev, "failed to get edid\n");
1414         }
1415
1416         return 0;
1417 }
1418
1419 static enum drm_mode_status
1420 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1421                              struct drm_display_mode *mode)
1422 {
1423         struct dw_hdmi *hdmi = container_of(connector,
1424                                            struct dw_hdmi, connector);
1425         enum drm_mode_status mode_status = MODE_OK;
1426
1427         if (hdmi->plat_data->mode_valid)
1428                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1429
1430         return mode_status;
1431 }
1432
1433 static struct drm_encoder *dw_hdmi_connector_best_encoder(struct drm_connector
1434                                                            *connector)
1435 {
1436         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1437                                              connector);
1438
1439         return hdmi->encoder;
1440 }
1441
1442 static void dw_hdmi_connector_destroy(struct drm_connector *connector)
1443 {
1444         drm_connector_unregister(connector);
1445         drm_connector_cleanup(connector);
1446 }
1447
1448 static struct drm_connector_funcs dw_hdmi_connector_funcs = {
1449         .dpms = drm_helper_connector_dpms,
1450         .fill_modes = drm_helper_probe_single_connector_modes,
1451         .detect = dw_hdmi_connector_detect,
1452         .destroy = dw_hdmi_connector_destroy,
1453 };
1454
1455 static struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1456         .get_modes = dw_hdmi_connector_get_modes,
1457         .mode_valid = dw_hdmi_connector_mode_valid,
1458         .best_encoder = dw_hdmi_connector_best_encoder,
1459 };
1460
1461 struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1462         .enable = dw_hdmi_bridge_enable,
1463         .disable = dw_hdmi_bridge_disable,
1464         .pre_enable = dw_hdmi_bridge_nop,
1465         .post_disable = dw_hdmi_bridge_nop,
1466         .mode_set = dw_hdmi_bridge_mode_set,
1467         .mode_fixup = dw_hdmi_bridge_mode_fixup,
1468 };
1469
1470 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1471 {
1472         struct dw_hdmi *hdmi = dev_id;
1473         u8 intr_stat;
1474
1475         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1476         if (intr_stat)
1477                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1478
1479         return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
1480 }
1481
1482 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1483 {
1484         struct dw_hdmi *hdmi = dev_id;
1485         u8 intr_stat;
1486         u8 phy_int_pol;
1487
1488         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1489
1490         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1491
1492         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1493                 if (phy_int_pol & HDMI_PHY_HPD) {
1494                         dev_dbg(hdmi->dev, "EVENT=plugin\n");
1495
1496                         hdmi_modb(hdmi, 0, HDMI_PHY_HPD, HDMI_PHY_POL0);
1497
1498                         dw_hdmi_poweron(hdmi);
1499                 } else {
1500                         dev_dbg(hdmi->dev, "EVENT=plugout\n");
1501
1502                         hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD,
1503                                   HDMI_PHY_POL0);
1504
1505                         dw_hdmi_poweroff(hdmi);
1506                 }
1507                 drm_helper_hpd_irq_event(hdmi->connector.dev);
1508         }
1509
1510         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1511         hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1512
1513         return IRQ_HANDLED;
1514 }
1515
1516 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
1517 {
1518         struct drm_encoder *encoder = hdmi->encoder;
1519         struct drm_bridge *bridge;
1520         int ret;
1521
1522         bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1523         if (!bridge) {
1524                 DRM_ERROR("Failed to allocate drm bridge\n");
1525                 return -ENOMEM;
1526         }
1527
1528         hdmi->bridge = bridge;
1529         bridge->driver_private = hdmi;
1530         bridge->funcs = &dw_hdmi_bridge_funcs;
1531         ret = drm_bridge_attach(drm, bridge);
1532         if (ret) {
1533                 DRM_ERROR("Failed to initialize bridge with drm\n");
1534                 return -EINVAL;
1535         }
1536
1537         encoder->bridge = bridge;
1538         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1539
1540         drm_connector_helper_add(&hdmi->connector,
1541                                  &dw_hdmi_connector_helper_funcs);
1542         drm_connector_init(drm, &hdmi->connector, &dw_hdmi_connector_funcs,
1543                            DRM_MODE_CONNECTOR_HDMIA);
1544
1545         hdmi->connector.encoder = encoder;
1546
1547         drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
1548
1549         return 0;
1550 }
1551
1552 int dw_hdmi_bind(struct device *dev, struct device *master,
1553                  void *data, struct drm_encoder *encoder,
1554                  struct resource *iores, int irq,
1555                  const struct dw_hdmi_plat_data *plat_data)
1556 {
1557         struct drm_device *drm = data;
1558         struct device_node *np = dev->of_node;
1559         struct device_node *ddc_node;
1560         struct dw_hdmi *hdmi;
1561         int ret;
1562         u32 val = 1;
1563
1564         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1565         if (!hdmi)
1566                 return -ENOMEM;
1567
1568         hdmi->plat_data = plat_data;
1569         hdmi->dev = dev;
1570         hdmi->dev_type = plat_data->dev_type;
1571         hdmi->sample_rate = 48000;
1572         hdmi->ratio = 100;
1573         hdmi->encoder = encoder;
1574
1575         mutex_init(&hdmi->audio_mutex);
1576
1577         of_property_read_u32(np, "reg-io-width", &val);
1578
1579         switch (val) {
1580         case 4:
1581                 hdmi->write = dw_hdmi_writel;
1582                 hdmi->read = dw_hdmi_readl;
1583                 break;
1584         case 1:
1585                 hdmi->write = dw_hdmi_writeb;
1586                 hdmi->read = dw_hdmi_readb;
1587                 break;
1588         default:
1589                 dev_err(dev, "reg-io-width must be 1 or 4\n");
1590                 return -EINVAL;
1591         }
1592
1593         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
1594         if (ddc_node) {
1595                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1596                 of_node_put(ddc_node);
1597                 if (!hdmi->ddc) {
1598                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
1599                         return -EPROBE_DEFER;
1600                 }
1601
1602         } else {
1603                 dev_dbg(hdmi->dev, "no ddc property found\n");
1604         }
1605
1606         hdmi->regs = devm_ioremap_resource(dev, iores);
1607         if (IS_ERR(hdmi->regs))
1608                 return PTR_ERR(hdmi->regs);
1609
1610         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1611         if (IS_ERR(hdmi->isfr_clk)) {
1612                 ret = PTR_ERR(hdmi->isfr_clk);
1613                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
1614                 return ret;
1615         }
1616
1617         ret = clk_prepare_enable(hdmi->isfr_clk);
1618         if (ret) {
1619                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
1620                 return ret;
1621         }
1622
1623         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1624         if (IS_ERR(hdmi->iahb_clk)) {
1625                 ret = PTR_ERR(hdmi->iahb_clk);
1626                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
1627                 goto err_isfr;
1628         }
1629
1630         ret = clk_prepare_enable(hdmi->iahb_clk);
1631         if (ret) {
1632                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
1633                 goto err_isfr;
1634         }
1635
1636         /* Product and revision IDs */
1637         dev_info(dev,
1638                  "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1639                  hdmi_readb(hdmi, HDMI_DESIGN_ID),
1640                  hdmi_readb(hdmi, HDMI_REVISION_ID),
1641                  hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1642                  hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
1643
1644         initialize_hdmi_ih_mutes(hdmi);
1645
1646         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
1647                                         dw_hdmi_irq, IRQF_SHARED,
1648                                         dev_name(dev), hdmi);
1649         if (ret)
1650                 goto err_iahb;
1651
1652         /*
1653          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1654          * N and cts values before enabling phy
1655          */
1656         hdmi_init_clk_regenerator(hdmi);
1657
1658         /*
1659          * Configure registers related to HDMI interrupt
1660          * generation before registering IRQ.
1661          */
1662         hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0);
1663
1664         /* Clear Hotplug interrupts */
1665         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
1666
1667         ret = dw_hdmi_fb_registered(hdmi);
1668         if (ret)
1669                 goto err_iahb;
1670
1671         ret = dw_hdmi_register(drm, hdmi);
1672         if (ret)
1673                 goto err_iahb;
1674
1675         /* Unmute interrupts */
1676         hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
1677
1678         dev_set_drvdata(dev, hdmi);
1679
1680         return 0;
1681
1682 err_iahb:
1683         clk_disable_unprepare(hdmi->iahb_clk);
1684 err_isfr:
1685         clk_disable_unprepare(hdmi->isfr_clk);
1686
1687         return ret;
1688 }
1689 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
1690
1691 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
1692 {
1693         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
1694
1695         /* Disable all interrupts */
1696         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1697
1698         hdmi->connector.funcs->destroy(&hdmi->connector);
1699         hdmi->encoder->funcs->destroy(hdmi->encoder);
1700
1701         clk_disable_unprepare(hdmi->iahb_clk);
1702         clk_disable_unprepare(hdmi->isfr_clk);
1703         i2c_put_adapter(hdmi->ddc);
1704 }
1705 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
1706
1707 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1708 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
1709 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
1710 MODULE_DESCRIPTION("DW HDMI transmitter driver");
1711 MODULE_LICENSE("GPL");
1712 MODULE_ALIAS("platform:dw-hdmi");