2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_displayid.h>
38 #include <drm/drm_scdc_helper.h>
40 #define version_greater(edid, maj, min) \
41 (((edid)->version > (maj)) || \
42 ((edid)->version == (maj) && (edid)->revision > (min)))
44 #define EDID_EST_TIMINGS 16
45 #define EDID_STD_TIMINGS 8
46 #define EDID_DETAILED_TIMINGS 4
49 * EDID blocks out in the wild have a variety of bugs, try to collect
50 * them here (note that userspace may work around broken monitors first,
51 * but fixes should make their way here so that the kernel "just works"
52 * on as many displays as possible).
55 /* First detailed mode wrong, use largest 60Hz mode */
56 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
57 /* Reported 135MHz pixel clock is too high, needs adjustment */
58 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
59 /* Prefer the largest mode at 75 Hz */
60 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
61 /* Detail timing is in cm not mm */
62 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
63 /* Detailed timing descriptors have bogus size values, so just take the
64 * maximum size and use that.
66 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
67 /* Monitor forgot to set the first detailed is preferred bit. */
68 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
69 /* use +hsync +vsync for detailed mode */
70 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
71 /* Force reduced-blanking timings for detailed modes */
72 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
74 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
76 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
78 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
80 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
82 struct detailed_mode_closure {
83 struct drm_connector *connector;
95 static struct edid_quirk {
99 } edid_quirk_list[] = {
101 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
103 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
105 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
107 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
108 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
110 /* Belinea 10 15 55 */
111 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
112 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
114 /* Envision Peripherals, Inc. EN-7100e */
115 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
116 /* Envision EN2028 */
117 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
119 /* Funai Electronics PM36B */
120 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
121 EDID_QUIRK_DETAILED_IN_CM },
123 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
124 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
126 /* LG Philips LCD LP154W01-A5 */
127 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
128 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
130 /* Philips 107p5 CRT */
131 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
134 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
136 /* Samsung SyncMaster 205BW. Note: irony */
137 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
138 /* Samsung SyncMaster 22[5-6]BW */
139 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
140 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
142 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
143 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
145 /* ViewSonic VA2026w */
146 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
148 /* Medion MD 30217 PG */
149 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
151 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
152 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
154 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
155 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
159 * Autogenerated from the DMT spec.
160 * This table is copied from xfree86/modes/xf86EdidModes.c.
162 static const struct drm_display_mode drm_dmt_modes[] = {
163 /* 0x01 - 640x350@85Hz */
164 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
165 736, 832, 0, 350, 382, 385, 445, 0,
166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
167 /* 0x02 - 640x400@85Hz */
168 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
169 736, 832, 0, 400, 401, 404, 445, 0,
170 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
171 /* 0x03 - 720x400@85Hz */
172 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
173 828, 936, 0, 400, 401, 404, 446, 0,
174 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
175 /* 0x04 - 640x480@60Hz */
176 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
177 752, 800, 0, 480, 490, 492, 525, 0,
178 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
179 /* 0x05 - 640x480@72Hz */
180 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
181 704, 832, 0, 480, 489, 492, 520, 0,
182 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
183 /* 0x06 - 640x480@75Hz */
184 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
185 720, 840, 0, 480, 481, 484, 500, 0,
186 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
187 /* 0x07 - 640x480@85Hz */
188 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
189 752, 832, 0, 480, 481, 484, 509, 0,
190 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
191 /* 0x08 - 800x600@56Hz */
192 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
193 896, 1024, 0, 600, 601, 603, 625, 0,
194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
195 /* 0x09 - 800x600@60Hz */
196 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
197 968, 1056, 0, 600, 601, 605, 628, 0,
198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
199 /* 0x0a - 800x600@72Hz */
200 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
201 976, 1040, 0, 600, 637, 643, 666, 0,
202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
203 /* 0x0b - 800x600@75Hz */
204 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
205 896, 1056, 0, 600, 601, 604, 625, 0,
206 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
207 /* 0x0c - 800x600@85Hz */
208 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
209 896, 1048, 0, 600, 601, 604, 631, 0,
210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
211 /* 0x0d - 800x600@120Hz RB */
212 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
213 880, 960, 0, 600, 603, 607, 636, 0,
214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
215 /* 0x0e - 848x480@60Hz */
216 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
217 976, 1088, 0, 480, 486, 494, 517, 0,
218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
219 /* 0x0f - 1024x768@43Hz, interlace */
220 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
221 1208, 1264, 0, 768, 768, 772, 817, 0,
222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
223 DRM_MODE_FLAG_INTERLACE) },
224 /* 0x10 - 1024x768@60Hz */
225 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
226 1184, 1344, 0, 768, 771, 777, 806, 0,
227 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
228 /* 0x11 - 1024x768@70Hz */
229 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
230 1184, 1328, 0, 768, 771, 777, 806, 0,
231 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
232 /* 0x12 - 1024x768@75Hz */
233 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
234 1136, 1312, 0, 768, 769, 772, 800, 0,
235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
236 /* 0x13 - 1024x768@85Hz */
237 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
238 1168, 1376, 0, 768, 769, 772, 808, 0,
239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
240 /* 0x14 - 1024x768@120Hz RB */
241 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
242 1104, 1184, 0, 768, 771, 775, 813, 0,
243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
244 /* 0x15 - 1152x864@75Hz */
245 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
246 1344, 1600, 0, 864, 865, 868, 900, 0,
247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
248 /* 0x55 - 1280x720@60Hz */
249 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
250 1430, 1650, 0, 720, 725, 730, 750, 0,
251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
252 /* 0x16 - 1280x768@60Hz RB */
253 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
254 1360, 1440, 0, 768, 771, 778, 790, 0,
255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
256 /* 0x17 - 1280x768@60Hz */
257 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
258 1472, 1664, 0, 768, 771, 778, 798, 0,
259 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
260 /* 0x18 - 1280x768@75Hz */
261 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
262 1488, 1696, 0, 768, 771, 778, 805, 0,
263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
264 /* 0x19 - 1280x768@85Hz */
265 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
266 1496, 1712, 0, 768, 771, 778, 809, 0,
267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
268 /* 0x1a - 1280x768@120Hz RB */
269 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
270 1360, 1440, 0, 768, 771, 778, 813, 0,
271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
272 /* 0x1b - 1280x800@60Hz RB */
273 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
274 1360, 1440, 0, 800, 803, 809, 823, 0,
275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
276 /* 0x1c - 1280x800@60Hz */
277 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
278 1480, 1680, 0, 800, 803, 809, 831, 0,
279 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
280 /* 0x1d - 1280x800@75Hz */
281 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
282 1488, 1696, 0, 800, 803, 809, 838, 0,
283 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
284 /* 0x1e - 1280x800@85Hz */
285 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
286 1496, 1712, 0, 800, 803, 809, 843, 0,
287 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
288 /* 0x1f - 1280x800@120Hz RB */
289 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
290 1360, 1440, 0, 800, 803, 809, 847, 0,
291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
292 /* 0x20 - 1280x960@60Hz */
293 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
294 1488, 1800, 0, 960, 961, 964, 1000, 0,
295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
296 /* 0x21 - 1280x960@85Hz */
297 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
298 1504, 1728, 0, 960, 961, 964, 1011, 0,
299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
300 /* 0x22 - 1280x960@120Hz RB */
301 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
302 1360, 1440, 0, 960, 963, 967, 1017, 0,
303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
304 /* 0x23 - 1280x1024@60Hz */
305 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
306 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
308 /* 0x24 - 1280x1024@75Hz */
309 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
310 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
312 /* 0x25 - 1280x1024@85Hz */
313 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
314 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
316 /* 0x26 - 1280x1024@120Hz RB */
317 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
318 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
320 /* 0x27 - 1360x768@60Hz */
321 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
322 1536, 1792, 0, 768, 771, 777, 795, 0,
323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
324 /* 0x28 - 1360x768@120Hz RB */
325 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
326 1440, 1520, 0, 768, 771, 776, 813, 0,
327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
328 /* 0x51 - 1366x768@60Hz */
329 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
330 1579, 1792, 0, 768, 771, 774, 798, 0,
331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
332 /* 0x56 - 1366x768@60Hz */
333 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
334 1436, 1500, 0, 768, 769, 772, 800, 0,
335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
336 /* 0x29 - 1400x1050@60Hz RB */
337 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
338 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
340 /* 0x2a - 1400x1050@60Hz */
341 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
342 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
343 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
344 /* 0x2b - 1400x1050@75Hz */
345 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
346 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
347 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
348 /* 0x2c - 1400x1050@85Hz */
349 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
350 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
351 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
352 /* 0x2d - 1400x1050@120Hz RB */
353 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
354 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
356 /* 0x2e - 1440x900@60Hz RB */
357 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
358 1520, 1600, 0, 900, 903, 909, 926, 0,
359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
360 /* 0x2f - 1440x900@60Hz */
361 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
362 1672, 1904, 0, 900, 903, 909, 934, 0,
363 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
364 /* 0x30 - 1440x900@75Hz */
365 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
366 1688, 1936, 0, 900, 903, 909, 942, 0,
367 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
368 /* 0x31 - 1440x900@85Hz */
369 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
370 1696, 1952, 0, 900, 903, 909, 948, 0,
371 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
372 /* 0x32 - 1440x900@120Hz RB */
373 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
374 1520, 1600, 0, 900, 903, 909, 953, 0,
375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
376 /* 0x53 - 1600x900@60Hz */
377 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
378 1704, 1800, 0, 900, 901, 904, 1000, 0,
379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
380 /* 0x33 - 1600x1200@60Hz */
381 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
382 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
384 /* 0x34 - 1600x1200@65Hz */
385 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
386 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
388 /* 0x35 - 1600x1200@70Hz */
389 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
390 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
392 /* 0x36 - 1600x1200@75Hz */
393 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
394 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
396 /* 0x37 - 1600x1200@85Hz */
397 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
398 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
400 /* 0x38 - 1600x1200@120Hz RB */
401 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
402 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
404 /* 0x39 - 1680x1050@60Hz RB */
405 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
406 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
408 /* 0x3a - 1680x1050@60Hz */
409 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
410 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
411 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
412 /* 0x3b - 1680x1050@75Hz */
413 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
414 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
415 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
416 /* 0x3c - 1680x1050@85Hz */
417 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
418 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
419 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
420 /* 0x3d - 1680x1050@120Hz RB */
421 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
422 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
424 /* 0x3e - 1792x1344@60Hz */
425 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
426 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
427 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
428 /* 0x3f - 1792x1344@75Hz */
429 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
430 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
431 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
432 /* 0x40 - 1792x1344@120Hz RB */
433 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
434 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
436 /* 0x41 - 1856x1392@60Hz */
437 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
438 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
439 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
440 /* 0x42 - 1856x1392@75Hz */
441 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
442 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
443 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
444 /* 0x43 - 1856x1392@120Hz RB */
445 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
446 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
448 /* 0x52 - 1920x1080@60Hz */
449 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
450 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
451 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
452 /* 0x44 - 1920x1200@60Hz RB */
453 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
454 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
456 /* 0x45 - 1920x1200@60Hz */
457 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
458 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
459 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
460 /* 0x46 - 1920x1200@75Hz */
461 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
462 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
463 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
464 /* 0x47 - 1920x1200@85Hz */
465 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
466 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
467 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
468 /* 0x48 - 1920x1200@120Hz RB */
469 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
470 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
472 /* 0x49 - 1920x1440@60Hz */
473 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
474 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
475 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
476 /* 0x4a - 1920x1440@75Hz */
477 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
478 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
479 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
480 /* 0x4b - 1920x1440@120Hz RB */
481 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
482 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
484 /* 0x54 - 2048x1152@60Hz */
485 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
486 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
488 /* 0x4c - 2560x1600@60Hz RB */
489 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
490 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
492 /* 0x4d - 2560x1600@60Hz */
493 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
494 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
495 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
496 /* 0x4e - 2560x1600@75Hz */
497 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
498 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
499 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
500 /* 0x4f - 2560x1600@85Hz */
501 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
502 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
503 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
504 /* 0x50 - 2560x1600@120Hz RB */
505 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
506 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
508 /* 0x57 - 4096x2160@60Hz RB */
509 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
510 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
512 /* 0x58 - 4096x2160@59.94Hz RB */
513 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
514 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
519 * These more or less come from the DMT spec. The 720x400 modes are
520 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
521 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
522 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
525 * The DMT modes have been fact-checked; the rest are mild guesses.
527 static const struct drm_display_mode edid_est_modes[] = {
528 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
529 968, 1056, 0, 600, 601, 605, 628, 0,
530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
531 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
532 896, 1024, 0, 600, 601, 603, 625, 0,
533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
534 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
535 720, 840, 0, 480, 481, 484, 500, 0,
536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
537 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
538 704, 832, 0, 480, 489, 492, 520, 0,
539 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
540 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
541 768, 864, 0, 480, 483, 486, 525, 0,
542 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
543 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
544 752, 800, 0, 480, 490, 492, 525, 0,
545 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
546 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
547 846, 900, 0, 400, 421, 423, 449, 0,
548 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
549 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
550 846, 900, 0, 400, 412, 414, 449, 0,
551 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
552 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
553 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
555 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
556 1136, 1312, 0, 768, 769, 772, 800, 0,
557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
558 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
559 1184, 1328, 0, 768, 771, 777, 806, 0,
560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
561 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
562 1184, 1344, 0, 768, 771, 777, 806, 0,
563 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
564 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
565 1208, 1264, 0, 768, 768, 776, 817, 0,
566 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
567 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
568 928, 1152, 0, 624, 625, 628, 667, 0,
569 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
570 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
571 896, 1056, 0, 600, 601, 604, 625, 0,
572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
573 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
574 976, 1040, 0, 600, 637, 643, 666, 0,
575 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
576 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
577 1344, 1600, 0, 864, 865, 868, 900, 0,
578 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
588 static const struct minimode est3_modes[] = {
596 { 1024, 768, 85, 0 },
597 { 1152, 864, 75, 0 },
599 { 1280, 768, 60, 1 },
600 { 1280, 768, 60, 0 },
601 { 1280, 768, 75, 0 },
602 { 1280, 768, 85, 0 },
603 { 1280, 960, 60, 0 },
604 { 1280, 960, 85, 0 },
605 { 1280, 1024, 60, 0 },
606 { 1280, 1024, 85, 0 },
608 { 1360, 768, 60, 0 },
609 { 1440, 900, 60, 1 },
610 { 1440, 900, 60, 0 },
611 { 1440, 900, 75, 0 },
612 { 1440, 900, 85, 0 },
613 { 1400, 1050, 60, 1 },
614 { 1400, 1050, 60, 0 },
615 { 1400, 1050, 75, 0 },
617 { 1400, 1050, 85, 0 },
618 { 1680, 1050, 60, 1 },
619 { 1680, 1050, 60, 0 },
620 { 1680, 1050, 75, 0 },
621 { 1680, 1050, 85, 0 },
622 { 1600, 1200, 60, 0 },
623 { 1600, 1200, 65, 0 },
624 { 1600, 1200, 70, 0 },
626 { 1600, 1200, 75, 0 },
627 { 1600, 1200, 85, 0 },
628 { 1792, 1344, 60, 0 },
629 { 1792, 1344, 75, 0 },
630 { 1856, 1392, 60, 0 },
631 { 1856, 1392, 75, 0 },
632 { 1920, 1200, 60, 1 },
633 { 1920, 1200, 60, 0 },
635 { 1920, 1200, 75, 0 },
636 { 1920, 1200, 85, 0 },
637 { 1920, 1440, 60, 0 },
638 { 1920, 1440, 75, 0 },
641 static const struct minimode extra_modes[] = {
642 { 1024, 576, 60, 0 },
643 { 1366, 768, 60, 0 },
644 { 1600, 900, 60, 0 },
645 { 1680, 945, 60, 0 },
646 { 1920, 1080, 60, 0 },
647 { 2048, 1152, 60, 0 },
648 { 2048, 1536, 60, 0 },
652 * Probably taken from CEA-861 spec.
653 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
655 * Index using the VIC.
657 static const struct drm_display_mode edid_cea_modes[] = {
658 /* 0 - dummy, VICs start at 1 */
660 /* 1 - 640x480@60Hz */
661 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
662 752, 800, 0, 480, 490, 492, 525, 0,
663 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
664 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
665 /* 2 - 720x480@60Hz */
666 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
667 798, 858, 0, 480, 489, 495, 525, 0,
668 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
669 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
670 /* 3 - 720x480@60Hz */
671 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
672 798, 858, 0, 480, 489, 495, 525, 0,
673 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
674 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
675 /* 4 - 1280x720@60Hz */
676 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
677 1430, 1650, 0, 720, 725, 730, 750, 0,
678 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
679 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
680 /* 5 - 1920x1080i@60Hz */
681 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
682 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
683 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
684 DRM_MODE_FLAG_INTERLACE),
685 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
686 /* 6 - 720(1440)x480i@60Hz */
687 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
688 801, 858, 0, 480, 488, 494, 525, 0,
689 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
690 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
691 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
692 /* 7 - 720(1440)x480i@60Hz */
693 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
694 801, 858, 0, 480, 488, 494, 525, 0,
695 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
696 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
697 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
698 /* 8 - 720(1440)x240@60Hz */
699 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
700 801, 858, 0, 240, 244, 247, 262, 0,
701 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
702 DRM_MODE_FLAG_DBLCLK),
703 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
704 /* 9 - 720(1440)x240@60Hz */
705 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
706 801, 858, 0, 240, 244, 247, 262, 0,
707 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
708 DRM_MODE_FLAG_DBLCLK),
709 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
710 /* 10 - 2880x480i@60Hz */
711 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
712 3204, 3432, 0, 480, 488, 494, 525, 0,
713 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
714 DRM_MODE_FLAG_INTERLACE),
715 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
716 /* 11 - 2880x480i@60Hz */
717 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
718 3204, 3432, 0, 480, 488, 494, 525, 0,
719 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
720 DRM_MODE_FLAG_INTERLACE),
721 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
722 /* 12 - 2880x240@60Hz */
723 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
724 3204, 3432, 0, 240, 244, 247, 262, 0,
725 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
726 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
727 /* 13 - 2880x240@60Hz */
728 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
729 3204, 3432, 0, 240, 244, 247, 262, 0,
730 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
731 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
732 /* 14 - 1440x480@60Hz */
733 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
734 1596, 1716, 0, 480, 489, 495, 525, 0,
735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
736 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
737 /* 15 - 1440x480@60Hz */
738 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
739 1596, 1716, 0, 480, 489, 495, 525, 0,
740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
741 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
742 /* 16 - 1920x1080@60Hz */
743 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
744 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
745 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
746 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
747 /* 17 - 720x576@50Hz */
748 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
749 796, 864, 0, 576, 581, 586, 625, 0,
750 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
751 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
752 /* 18 - 720x576@50Hz */
753 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
754 796, 864, 0, 576, 581, 586, 625, 0,
755 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
756 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
757 /* 19 - 1280x720@50Hz */
758 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
759 1760, 1980, 0, 720, 725, 730, 750, 0,
760 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
761 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
762 /* 20 - 1920x1080i@50Hz */
763 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
764 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
765 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
766 DRM_MODE_FLAG_INTERLACE),
767 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
768 /* 21 - 720(1440)x576i@50Hz */
769 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
770 795, 864, 0, 576, 580, 586, 625, 0,
771 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
772 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
773 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
774 /* 22 - 720(1440)x576i@50Hz */
775 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
776 795, 864, 0, 576, 580, 586, 625, 0,
777 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
778 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
779 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
780 /* 23 - 720(1440)x288@50Hz */
781 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
782 795, 864, 0, 288, 290, 293, 312, 0,
783 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
784 DRM_MODE_FLAG_DBLCLK),
785 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
786 /* 24 - 720(1440)x288@50Hz */
787 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
788 795, 864, 0, 288, 290, 293, 312, 0,
789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
790 DRM_MODE_FLAG_DBLCLK),
791 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
792 /* 25 - 2880x576i@50Hz */
793 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
794 3180, 3456, 0, 576, 580, 586, 625, 0,
795 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
796 DRM_MODE_FLAG_INTERLACE),
797 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
798 /* 26 - 2880x576i@50Hz */
799 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
800 3180, 3456, 0, 576, 580, 586, 625, 0,
801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
802 DRM_MODE_FLAG_INTERLACE),
803 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
804 /* 27 - 2880x288@50Hz */
805 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
806 3180, 3456, 0, 288, 290, 293, 312, 0,
807 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
808 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
809 /* 28 - 2880x288@50Hz */
810 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
811 3180, 3456, 0, 288, 290, 293, 312, 0,
812 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
813 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
814 /* 29 - 1440x576@50Hz */
815 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
816 1592, 1728, 0, 576, 581, 586, 625, 0,
817 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
818 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
819 /* 30 - 1440x576@50Hz */
820 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
821 1592, 1728, 0, 576, 581, 586, 625, 0,
822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
823 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
824 /* 31 - 1920x1080@50Hz */
825 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
826 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
828 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
829 /* 32 - 1920x1080@24Hz */
830 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
831 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
833 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
834 /* 33 - 1920x1080@25Hz */
835 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
836 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
838 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
839 /* 34 - 1920x1080@30Hz */
840 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
841 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
842 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
843 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
844 /* 35 - 2880x480@60Hz */
845 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
846 3192, 3432, 0, 480, 489, 495, 525, 0,
847 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
848 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
849 /* 36 - 2880x480@60Hz */
850 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
851 3192, 3432, 0, 480, 489, 495, 525, 0,
852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
853 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
854 /* 37 - 2880x576@50Hz */
855 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
856 3184, 3456, 0, 576, 581, 586, 625, 0,
857 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
858 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
859 /* 38 - 2880x576@50Hz */
860 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
861 3184, 3456, 0, 576, 581, 586, 625, 0,
862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
863 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
864 /* 39 - 1920x1080i@50Hz */
865 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
866 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
867 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
868 DRM_MODE_FLAG_INTERLACE),
869 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
870 /* 40 - 1920x1080i@100Hz */
871 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
872 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
873 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
874 DRM_MODE_FLAG_INTERLACE),
875 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
876 /* 41 - 1280x720@100Hz */
877 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
878 1760, 1980, 0, 720, 725, 730, 750, 0,
879 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
880 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
881 /* 42 - 720x576@100Hz */
882 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
883 796, 864, 0, 576, 581, 586, 625, 0,
884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
885 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
886 /* 43 - 720x576@100Hz */
887 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
888 796, 864, 0, 576, 581, 586, 625, 0,
889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
890 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
891 /* 44 - 720(1440)x576i@100Hz */
892 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
893 795, 864, 0, 576, 580, 586, 625, 0,
894 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
895 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
896 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
897 /* 45 - 720(1440)x576i@100Hz */
898 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
899 795, 864, 0, 576, 580, 586, 625, 0,
900 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
901 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
902 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
903 /* 46 - 1920x1080i@120Hz */
904 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
905 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
906 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
907 DRM_MODE_FLAG_INTERLACE),
908 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
909 /* 47 - 1280x720@120Hz */
910 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
911 1430, 1650, 0, 720, 725, 730, 750, 0,
912 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
913 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
914 /* 48 - 720x480@120Hz */
915 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
916 798, 858, 0, 480, 489, 495, 525, 0,
917 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
918 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
919 /* 49 - 720x480@120Hz */
920 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
921 798, 858, 0, 480, 489, 495, 525, 0,
922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
923 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
924 /* 50 - 720(1440)x480i@120Hz */
925 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
926 801, 858, 0, 480, 488, 494, 525, 0,
927 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
928 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
929 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
930 /* 51 - 720(1440)x480i@120Hz */
931 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
932 801, 858, 0, 480, 488, 494, 525, 0,
933 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
934 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
935 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
936 /* 52 - 720x576@200Hz */
937 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
938 796, 864, 0, 576, 581, 586, 625, 0,
939 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
940 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
941 /* 53 - 720x576@200Hz */
942 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
943 796, 864, 0, 576, 581, 586, 625, 0,
944 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
945 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
946 /* 54 - 720(1440)x576i@200Hz */
947 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
948 795, 864, 0, 576, 580, 586, 625, 0,
949 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
950 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
951 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
952 /* 55 - 720(1440)x576i@200Hz */
953 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
954 795, 864, 0, 576, 580, 586, 625, 0,
955 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
956 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
957 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
958 /* 56 - 720x480@240Hz */
959 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
960 798, 858, 0, 480, 489, 495, 525, 0,
961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
962 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
963 /* 57 - 720x480@240Hz */
964 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
965 798, 858, 0, 480, 489, 495, 525, 0,
966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
967 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
968 /* 58 - 720(1440)x480i@240 */
969 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
970 801, 858, 0, 480, 488, 494, 525, 0,
971 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
972 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
973 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
974 /* 59 - 720(1440)x480i@240 */
975 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
976 801, 858, 0, 480, 488, 494, 525, 0,
977 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
978 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
979 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
980 /* 60 - 1280x720@24Hz */
981 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
982 3080, 3300, 0, 720, 725, 730, 750, 0,
983 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
984 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
985 /* 61 - 1280x720@25Hz */
986 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
987 3740, 3960, 0, 720, 725, 730, 750, 0,
988 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
989 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
990 /* 62 - 1280x720@30Hz */
991 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
992 3080, 3300, 0, 720, 725, 730, 750, 0,
993 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
994 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
995 /* 63 - 1920x1080@120Hz */
996 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
997 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
998 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
999 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1000 /* 64 - 1920x1080@100Hz */
1001 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1002 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1003 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1004 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1005 /* 65 - 1280x720@24Hz */
1006 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1007 3080, 3300, 0, 720, 725, 730, 750, 0,
1008 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1009 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1010 /* 66 - 1280x720@25Hz */
1011 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1012 3740, 3960, 0, 720, 725, 730, 750, 0,
1013 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1014 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1015 /* 67 - 1280x720@30Hz */
1016 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1017 3080, 3300, 0, 720, 725, 730, 750, 0,
1018 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1019 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1020 /* 68 - 1280x720@50Hz */
1021 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1022 1760, 1980, 0, 720, 725, 730, 750, 0,
1023 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1024 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1025 /* 69 - 1280x720@60Hz */
1026 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1027 1430, 1650, 0, 720, 725, 730, 750, 0,
1028 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1029 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1030 /* 70 - 1280x720@100Hz */
1031 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1032 1760, 1980, 0, 720, 725, 730, 750, 0,
1033 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1034 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1035 /* 71 - 1280x720@120Hz */
1036 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1037 1430, 1650, 0, 720, 725, 730, 750, 0,
1038 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1039 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1040 /* 72 - 1920x1080@24Hz */
1041 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1042 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1043 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1044 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1045 /* 73 - 1920x1080@25Hz */
1046 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1047 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1048 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1049 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1050 /* 74 - 1920x1080@30Hz */
1051 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1052 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1053 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1054 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1055 /* 75 - 1920x1080@50Hz */
1056 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1057 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1058 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1059 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1060 /* 76 - 1920x1080@60Hz */
1061 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1062 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1063 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1064 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1065 /* 77 - 1920x1080@100Hz */
1066 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1067 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
1068 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1069 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1070 /* 78 - 1920x1080@120Hz */
1071 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1072 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1074 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1075 /* 79 - 1680x720@24Hz */
1076 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1077 3080, 3300, 0, 720, 725, 730, 750, 0,
1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1079 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1080 /* 80 - 1680x720@25Hz */
1081 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1082 2948, 3168, 0, 720, 725, 730, 750, 0,
1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1084 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1085 /* 81 - 1680x720@30Hz */
1086 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1087 2420, 2640, 0, 720, 725, 730, 750, 0,
1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1089 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1090 /* 82 - 1680x720@50Hz */
1091 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1092 1980, 2200, 0, 720, 725, 730, 750, 0,
1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1094 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1095 /* 83 - 1680x720@60Hz */
1096 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1097 1980, 2200, 0, 720, 725, 730, 750, 0,
1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1099 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1100 /* 84 - 1680x720@100Hz */
1101 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1102 1780, 2000, 0, 720, 725, 730, 825, 0,
1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1104 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1105 /* 85 - 1680x720@120Hz */
1106 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1107 1780, 2000, 0, 720, 725, 730, 825, 0,
1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1109 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1110 /* 86 - 2560x1080@24Hz */
1111 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1112 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1114 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1115 /* 87 - 2560x1080@25Hz */
1116 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1117 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1119 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1120 /* 88 - 2560x1080@30Hz */
1121 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1122 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1124 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1125 /* 89 - 2560x1080@50Hz */
1126 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1127 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1129 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1130 /* 90 - 2560x1080@60Hz */
1131 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1132 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1134 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1135 /* 91 - 2560x1080@100Hz */
1136 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1137 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1139 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1140 /* 92 - 2560x1080@120Hz */
1141 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1142 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1144 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1145 /* 93 - 3840x2160p@24Hz 16:9 */
1146 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1147 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1149 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,},
1150 /* 94 - 3840x2160p@25Hz 16:9 */
1151 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1152 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1154 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9},
1155 /* 95 - 3840x2160p@30Hz 16:9 */
1156 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1157 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1159 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9},
1160 /* 96 - 3840x2160p@50Hz 16:9 */
1161 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1162 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1164 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9},
1165 /* 97 - 3840x2160p@60Hz 16:9 */
1166 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1167 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1169 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9},
1170 /* 98 - 4096x2160p@24Hz 256:135 */
1171 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1172 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1174 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135},
1175 /* 99 - 4096x2160p@25Hz 256:135 */
1176 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1177 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1179 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135},
1180 /* 100 - 4096x2160p@30Hz 256:135 */
1181 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1182 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1184 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135},
1185 /* 101 - 4096x2160p@50Hz 256:135 */
1186 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1187 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1189 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135},
1190 /* 102 - 4096x2160p@60Hz 256:135 */
1191 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1192 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1194 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135},
1195 /* 103 - 3840x2160p@24Hz 64:27 */
1196 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1197 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1199 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27},
1200 /* 104 - 3840x2160p@25Hz 64:27 */
1201 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1202 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1204 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27},
1205 /* 105 - 3840x2160p@30Hz 64:27 */
1206 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1207 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1209 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27},
1210 /* 106 - 3840x2160p@50Hz 64:27 */
1211 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1212 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1214 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27},
1215 /* 107 - 3840x2160p@60Hz 64:27 */
1216 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1217 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1219 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27},
1223 * HDMI 1.4 4k modes. Index using the VIC.
1225 static const struct drm_display_mode edid_4k_modes[] = {
1226 /* 0 - dummy, VICs start at 1 */
1228 /* 1 - 3840x2160@30Hz */
1229 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1230 3840, 4016, 4104, 4400, 0,
1231 2160, 2168, 2178, 2250, 0,
1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1234 /* 2 - 3840x2160@25Hz */
1235 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1236 3840, 4896, 4984, 5280, 0,
1237 2160, 2168, 2178, 2250, 0,
1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1240 /* 3 - 3840x2160@24Hz */
1241 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1242 3840, 5116, 5204, 5500, 0,
1243 2160, 2168, 2178, 2250, 0,
1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1246 /* 4 - 4096x2160@24Hz (SMPTE) */
1247 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1248 4096, 5116, 5204, 5500, 0,
1249 2160, 2168, 2178, 2250, 0,
1250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1254 /*** DDC fetch and block validation ***/
1256 static const u8 edid_header[] = {
1257 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1261 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1262 * @raw_edid: pointer to raw base EDID block
1264 * Sanity check the header of the base EDID block.
1266 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1268 int drm_edid_header_is_valid(const u8 *raw_edid)
1272 for (i = 0; i < sizeof(edid_header); i++)
1273 if (raw_edid[i] == edid_header[i])
1278 EXPORT_SYMBOL(drm_edid_header_is_valid);
1280 static int edid_fixup __read_mostly = 6;
1281 module_param_named(edid_fixup, edid_fixup, int, 0400);
1282 MODULE_PARM_DESC(edid_fixup,
1283 "Minimum number of valid EDID header bytes (0-8, default 6)");
1285 static void drm_get_displayid(struct drm_connector *connector,
1288 static int drm_edid_block_checksum(const u8 *raw_edid)
1292 for (i = 0; i < EDID_LENGTH; i++)
1293 csum += raw_edid[i];
1298 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1300 if (memchr_inv(in_edid, 0, length))
1307 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1308 * @raw_edid: pointer to raw EDID block
1309 * @block: type of block to validate (0 for base, extension otherwise)
1310 * @print_bad_edid: if true, dump bad EDID blocks to the console
1311 * @edid_corrupt: if true, the header or checksum is invalid
1313 * Validate a base or extension EDID block and optionally dump bad blocks to
1316 * Return: True if the block is valid, false otherwise.
1318 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1322 struct edid *edid = (struct edid *)raw_edid;
1324 if (WARN_ON(!raw_edid))
1327 if (edid_fixup > 8 || edid_fixup < 0)
1331 int score = drm_edid_header_is_valid(raw_edid);
1334 *edid_corrupt = false;
1335 } else if (score >= edid_fixup) {
1336 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1337 * The corrupt flag needs to be set here otherwise, the
1338 * fix-up code here will correct the problem, the
1339 * checksum is correct and the test fails
1342 *edid_corrupt = true;
1343 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1344 memcpy(raw_edid, edid_header, sizeof(edid_header));
1347 *edid_corrupt = true;
1352 csum = drm_edid_block_checksum(raw_edid);
1354 if (print_bad_edid) {
1355 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
1359 *edid_corrupt = true;
1361 /* allow CEA to slide through, switches mangle this */
1362 if (raw_edid[0] != 0x02)
1366 /* per-block-type checks */
1367 switch (raw_edid[0]) {
1369 if (edid->version != 1) {
1370 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
1374 if (edid->revision > 4)
1375 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1385 if (print_bad_edid) {
1386 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1387 printk(KERN_ERR "EDID block is all zeroes\n");
1389 printk(KERN_ERR "Raw EDID:\n");
1390 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1,
1391 raw_edid, EDID_LENGTH, false);
1396 EXPORT_SYMBOL(drm_edid_block_valid);
1399 * drm_edid_is_valid - sanity check EDID data
1402 * Sanity-check an entire EDID record (including extensions)
1404 * Return: True if the EDID data is valid, false otherwise.
1406 bool drm_edid_is_valid(struct edid *edid)
1409 u8 *raw = (u8 *)edid;
1414 for (i = 0; i <= edid->extensions; i++)
1415 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1420 EXPORT_SYMBOL(drm_edid_is_valid);
1422 #define DDC_SEGMENT_ADDR 0x30
1424 * drm_do_probe_ddc_edid() - get EDID information via I2C
1425 * @data: I2C device adapter
1426 * @buf: EDID data buffer to be filled
1427 * @block: 128 byte EDID block to start fetching from
1428 * @len: EDID data buffer length to fetch
1430 * Try to fetch EDID information by calling I2C driver functions.
1432 * Return: 0 on success or -1 on failure.
1435 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1437 struct i2c_adapter *adapter = data;
1438 unsigned char start = block * EDID_LENGTH;
1439 unsigned char segment = block >> 1;
1440 unsigned char xfers = segment ? 3 : 2;
1441 int ret, retries = 5;
1444 * The core I2C driver will automatically retry the transfer if the
1445 * adapter reports EAGAIN. However, we find that bit-banging transfers
1446 * are susceptible to errors under a heavily loaded machine and
1447 * generate spurious NAKs and timeouts. Retrying the transfer
1448 * of the individual block a few times seems to overcome this.
1451 struct i2c_msg msgs[] = {
1453 .addr = DDC_SEGMENT_ADDR,
1471 * Avoid sending the segment addr to not upset non-compliant
1474 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1476 if (ret == -ENXIO) {
1477 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1481 } while (ret != xfers && --retries);
1483 return ret == xfers ? 0 : -1;
1487 * drm_do_get_edid - get EDID data using a custom EDID block read function
1488 * @connector: connector we're probing
1489 * @get_edid_block: EDID block read function
1490 * @data: private data passed to the block read function
1492 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1493 * exposes a different interface to read EDID blocks this function can be used
1494 * to get EDID data using a custom block read function.
1496 * As in the general case the DDC bus is accessible by the kernel at the I2C
1497 * level, drivers must make all reasonable efforts to expose it as an I2C
1498 * adapter and use drm_get_edid() instead of abusing this function.
1500 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1502 struct edid *drm_do_get_edid(struct drm_connector *connector,
1503 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1507 int i, j = 0, valid_extensions = 0;
1509 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS);
1511 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1514 /* base block fetch */
1515 for (i = 0; i < 4; i++) {
1516 if (get_edid_block(data, block, 0, EDID_LENGTH))
1518 if (drm_edid_block_valid(block, 0, print_bad_edid,
1519 &connector->edid_corrupt))
1521 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) {
1522 connector->null_edid_counter++;
1529 /* if there's no extensions, we're done */
1530 if (block[0x7e] == 0)
1531 return (struct edid *)block;
1533 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
1538 for (j = 1; j <= block[0x7e]; j++) {
1539 for (i = 0; i < 4; i++) {
1540 if (get_edid_block(data,
1541 block + (valid_extensions + 1) * EDID_LENGTH,
1544 if (drm_edid_block_valid(block + (valid_extensions + 1)
1553 if (i == 4 && print_bad_edid) {
1554 dev_warn(connector->dev->dev,
1555 "%s: Ignoring invalid EDID block %d.\n",
1556 connector->name, j);
1558 connector->bad_edid_counter++;
1562 if (valid_extensions != block[0x7e]) {
1563 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
1564 block[0x7e] = valid_extensions;
1565 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1571 return (struct edid *)block;
1574 if (print_bad_edid) {
1575 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n",
1576 connector->name, j);
1578 connector->bad_edid_counter++;
1584 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1587 * drm_probe_ddc() - probe DDC presence
1588 * @adapter: I2C adapter to probe
1590 * Return: True on success, false on failure.
1593 drm_probe_ddc(struct i2c_adapter *adapter)
1597 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1599 EXPORT_SYMBOL(drm_probe_ddc);
1602 * drm_get_edid - get EDID data, if available
1603 * @connector: connector we're probing
1604 * @adapter: I2C adapter to use for DDC
1606 * Poke the given I2C channel to grab EDID data if possible. If found,
1607 * attach it to the connector.
1609 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1611 struct edid *drm_get_edid(struct drm_connector *connector,
1612 struct i2c_adapter *adapter)
1616 if (connector->force == DRM_FORCE_OFF)
1619 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1622 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1624 drm_get_displayid(connector, edid);
1627 EXPORT_SYMBOL(drm_get_edid);
1630 * drm_edid_duplicate - duplicate an EDID and the extensions
1631 * @edid: EDID to duplicate
1633 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1635 struct edid *drm_edid_duplicate(const struct edid *edid)
1637 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1639 EXPORT_SYMBOL(drm_edid_duplicate);
1641 /*** EDID parsing ***/
1644 * edid_vendor - match a string against EDID's obfuscated vendor field
1645 * @edid: EDID to match
1646 * @vendor: vendor string
1648 * Returns true if @vendor is in @edid, false otherwise
1650 static bool edid_vendor(struct edid *edid, char *vendor)
1652 char edid_vendor[3];
1654 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1655 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1656 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1657 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1659 return !strncmp(edid_vendor, vendor, 3);
1663 * edid_get_quirks - return quirk flags for a given EDID
1664 * @edid: EDID to process
1666 * This tells subsequent routines what fixes they need to apply.
1668 static u32 edid_get_quirks(struct edid *edid)
1670 struct edid_quirk *quirk;
1673 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1674 quirk = &edid_quirk_list[i];
1676 if (edid_vendor(edid, quirk->vendor) &&
1677 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1678 return quirk->quirks;
1684 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1685 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1688 * edid_fixup_preferred - set preferred modes based on quirk list
1689 * @connector: has mode list to fix up
1690 * @quirks: quirks list
1692 * Walk the mode list for @connector, clearing the preferred status
1693 * on existing modes and setting it anew for the right mode ala @quirks.
1695 static void edid_fixup_preferred(struct drm_connector *connector,
1698 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1699 int target_refresh = 0;
1700 int cur_vrefresh, preferred_vrefresh;
1702 if (list_empty(&connector->probed_modes))
1705 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1706 target_refresh = 60;
1707 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1708 target_refresh = 75;
1710 preferred_mode = list_first_entry(&connector->probed_modes,
1711 struct drm_display_mode, head);
1713 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1714 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1716 if (cur_mode == preferred_mode)
1719 /* Largest mode is preferred */
1720 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1721 preferred_mode = cur_mode;
1723 cur_vrefresh = cur_mode->vrefresh ?
1724 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1725 preferred_vrefresh = preferred_mode->vrefresh ?
1726 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1727 /* At a given size, try to get closest to target refresh */
1728 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1729 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1730 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1731 preferred_mode = cur_mode;
1735 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1739 mode_is_rb(const struct drm_display_mode *mode)
1741 return (mode->htotal - mode->hdisplay == 160) &&
1742 (mode->hsync_end - mode->hdisplay == 80) &&
1743 (mode->hsync_end - mode->hsync_start == 32) &&
1744 (mode->vsync_start - mode->vdisplay == 3);
1748 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1749 * @dev: Device to duplicate against
1750 * @hsize: Mode width
1751 * @vsize: Mode height
1752 * @fresh: Mode refresh rate
1753 * @rb: Mode reduced-blanking-ness
1755 * Walk the DMT mode list looking for a match for the given parameters.
1757 * Return: A newly allocated copy of the mode, or NULL if not found.
1759 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1760 int hsize, int vsize, int fresh,
1765 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1766 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1767 if (hsize != ptr->hdisplay)
1769 if (vsize != ptr->vdisplay)
1771 if (fresh != drm_mode_vrefresh(ptr))
1773 if (rb != mode_is_rb(ptr))
1776 return drm_mode_duplicate(dev, ptr);
1781 EXPORT_SYMBOL(drm_mode_find_dmt);
1783 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1786 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1790 u8 *det_base = ext + d;
1793 for (i = 0; i < n; i++)
1794 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1798 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1800 unsigned int i, n = min((int)ext[0x02], 6);
1801 u8 *det_base = ext + 5;
1804 return; /* unknown version */
1806 for (i = 0; i < n; i++)
1807 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1811 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1814 struct edid *edid = (struct edid *)raw_edid;
1819 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1820 cb(&(edid->detailed_timings[i]), closure);
1822 for (i = 1; i <= raw_edid[0x7e]; i++) {
1823 u8 *ext = raw_edid + (i * EDID_LENGTH);
1826 cea_for_each_detailed_block(ext, cb, closure);
1829 vtb_for_each_detailed_block(ext, cb, closure);
1838 is_rb(struct detailed_timing *t, void *data)
1841 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1843 *(bool *)data = true;
1846 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1848 drm_monitor_supports_rb(struct edid *edid)
1850 if (edid->revision >= 4) {
1852 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1856 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1860 find_gtf2(struct detailed_timing *t, void *data)
1863 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1867 /* Secondary GTF curve kicks in above some break frequency */
1869 drm_gtf2_hbreak(struct edid *edid)
1872 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1873 return r ? (r[12] * 2) : 0;
1877 drm_gtf2_2c(struct edid *edid)
1880 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1881 return r ? r[13] : 0;
1885 drm_gtf2_m(struct edid *edid)
1888 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1889 return r ? (r[15] << 8) + r[14] : 0;
1893 drm_gtf2_k(struct edid *edid)
1896 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1897 return r ? r[16] : 0;
1901 drm_gtf2_2j(struct edid *edid)
1904 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1905 return r ? r[17] : 0;
1909 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1910 * @edid: EDID block to scan
1912 static int standard_timing_level(struct edid *edid)
1914 if (edid->revision >= 2) {
1915 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1917 if (drm_gtf2_hbreak(edid))
1925 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
1926 * monitors fill with ascii space (0x20) instead.
1929 bad_std_timing(u8 a, u8 b)
1931 return (a == 0x00 && b == 0x00) ||
1932 (a == 0x01 && b == 0x01) ||
1933 (a == 0x20 && b == 0x20);
1937 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
1938 * @connector: connector of for the EDID block
1939 * @edid: EDID block to scan
1940 * @t: standard timing params
1942 * Take the standard timing params (in this case width, aspect, and refresh)
1943 * and convert them into a real mode using CVT/GTF/DMT.
1945 static struct drm_display_mode *
1946 drm_mode_std(struct drm_connector *connector, struct edid *edid,
1947 struct std_timing *t)
1949 struct drm_device *dev = connector->dev;
1950 struct drm_display_mode *m, *mode = NULL;
1953 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
1954 >> EDID_TIMING_ASPECT_SHIFT;
1955 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
1956 >> EDID_TIMING_VFREQ_SHIFT;
1957 int timing_level = standard_timing_level(edid);
1959 if (bad_std_timing(t->hsize, t->vfreq_aspect))
1962 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
1963 hsize = t->hsize * 8 + 248;
1964 /* vrefresh_rate = vfreq + 60 */
1965 vrefresh_rate = vfreq + 60;
1966 /* the vdisplay is calculated based on the aspect ratio */
1967 if (aspect_ratio == 0) {
1968 if (edid->revision < 3)
1971 vsize = (hsize * 10) / 16;
1972 } else if (aspect_ratio == 1)
1973 vsize = (hsize * 3) / 4;
1974 else if (aspect_ratio == 2)
1975 vsize = (hsize * 4) / 5;
1977 vsize = (hsize * 9) / 16;
1979 /* HDTV hack, part 1 */
1980 if (vrefresh_rate == 60 &&
1981 ((hsize == 1360 && vsize == 765) ||
1982 (hsize == 1368 && vsize == 769))) {
1988 * If this connector already has a mode for this size and refresh
1989 * rate (because it came from detailed or CVT info), use that
1990 * instead. This way we don't have to guess at interlace or
1993 list_for_each_entry(m, &connector->probed_modes, head)
1994 if (m->hdisplay == hsize && m->vdisplay == vsize &&
1995 drm_mode_vrefresh(m) == vrefresh_rate)
1998 /* HDTV hack, part 2 */
1999 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2000 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2002 mode->hdisplay = 1366;
2003 mode->hsync_start = mode->hsync_start - 1;
2004 mode->hsync_end = mode->hsync_end - 1;
2008 /* check whether it can be found in default mode table */
2009 if (drm_monitor_supports_rb(edid)) {
2010 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2015 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2019 /* okay, generate it */
2020 switch (timing_level) {
2024 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2028 * This is potentially wrong if there's ever a monitor with
2029 * more than one ranges section, each claiming a different
2030 * secondary GTF curve. Please don't do that.
2032 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2035 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2036 drm_mode_destroy(dev, mode);
2037 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2038 vrefresh_rate, 0, 0,
2046 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2054 * EDID is delightfully ambiguous about how interlaced modes are to be
2055 * encoded. Our internal representation is of frame height, but some
2056 * HDTV detailed timings are encoded as field height.
2058 * The format list here is from CEA, in frame size. Technically we
2059 * should be checking refresh rate too. Whatever.
2062 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2063 struct detailed_pixel_timing *pt)
2066 static const struct {
2068 } cea_interlaced[] = {
2078 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2081 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2082 if ((mode->hdisplay == cea_interlaced[i].w) &&
2083 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2084 mode->vdisplay *= 2;
2085 mode->vsync_start *= 2;
2086 mode->vsync_end *= 2;
2092 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2096 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2097 * @dev: DRM device (needed to create new mode)
2099 * @timing: EDID detailed timing info
2100 * @quirks: quirks to apply
2102 * An EDID detailed timing block contains enough info for us to create and
2103 * return a new struct drm_display_mode.
2105 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2107 struct detailed_timing *timing,
2110 struct drm_display_mode *mode;
2111 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2112 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2113 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2114 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2115 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2116 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2117 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2118 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2119 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2121 /* ignore tiny modes */
2122 if (hactive < 64 || vactive < 64)
2125 if (pt->misc & DRM_EDID_PT_STEREO) {
2126 DRM_DEBUG_KMS("stereo mode not supported\n");
2129 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2130 DRM_DEBUG_KMS("composite sync not supported\n");
2133 /* it is incorrect if hsync/vsync width is zero */
2134 if (!hsync_pulse_width || !vsync_pulse_width) {
2135 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2136 "Wrong Hsync/Vsync pulse width\n");
2140 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2141 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2148 mode = drm_mode_create(dev);
2152 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2153 timing->pixel_clock = cpu_to_le16(1088);
2155 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2157 mode->hdisplay = hactive;
2158 mode->hsync_start = mode->hdisplay + hsync_offset;
2159 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2160 mode->htotal = mode->hdisplay + hblank;
2162 mode->vdisplay = vactive;
2163 mode->vsync_start = mode->vdisplay + vsync_offset;
2164 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2165 mode->vtotal = mode->vdisplay + vblank;
2167 /* Some EDIDs have bogus h/vtotal values */
2168 if (mode->hsync_end > mode->htotal)
2169 mode->htotal = mode->hsync_end + 1;
2170 if (mode->vsync_end > mode->vtotal)
2171 mode->vtotal = mode->vsync_end + 1;
2173 drm_mode_do_interlace_quirk(mode, pt);
2175 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2176 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2179 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2180 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2181 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2182 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2185 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2186 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2188 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2189 mode->width_mm *= 10;
2190 mode->height_mm *= 10;
2193 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2194 mode->width_mm = edid->width_cm * 10;
2195 mode->height_mm = edid->height_cm * 10;
2198 mode->type = DRM_MODE_TYPE_DRIVER;
2199 mode->vrefresh = drm_mode_vrefresh(mode);
2200 drm_mode_set_name(mode);
2206 mode_in_hsync_range(const struct drm_display_mode *mode,
2207 struct edid *edid, u8 *t)
2209 int hsync, hmin, hmax;
2212 if (edid->revision >= 4)
2213 hmin += ((t[4] & 0x04) ? 255 : 0);
2215 if (edid->revision >= 4)
2216 hmax += ((t[4] & 0x08) ? 255 : 0);
2217 hsync = drm_mode_hsync(mode);
2219 return (hsync <= hmax && hsync >= hmin);
2223 mode_in_vsync_range(const struct drm_display_mode *mode,
2224 struct edid *edid, u8 *t)
2226 int vsync, vmin, vmax;
2229 if (edid->revision >= 4)
2230 vmin += ((t[4] & 0x01) ? 255 : 0);
2232 if (edid->revision >= 4)
2233 vmax += ((t[4] & 0x02) ? 255 : 0);
2234 vsync = drm_mode_vrefresh(mode);
2236 return (vsync <= vmax && vsync >= vmin);
2240 range_pixel_clock(struct edid *edid, u8 *t)
2243 if (t[9] == 0 || t[9] == 255)
2246 /* 1.4 with CVT support gives us real precision, yay */
2247 if (edid->revision >= 4 && t[10] == 0x04)
2248 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2250 /* 1.3 is pathetic, so fuzz up a bit */
2251 return t[9] * 10000 + 5001;
2255 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2256 struct detailed_timing *timing)
2259 u8 *t = (u8 *)timing;
2261 if (!mode_in_hsync_range(mode, edid, t))
2264 if (!mode_in_vsync_range(mode, edid, t))
2267 if ((max_clock = range_pixel_clock(edid, t)))
2268 if (mode->clock > max_clock)
2271 /* 1.4 max horizontal check */
2272 if (edid->revision >= 4 && t[10] == 0x04)
2273 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2276 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2282 static bool valid_inferred_mode(const struct drm_connector *connector,
2283 const struct drm_display_mode *mode)
2285 const struct drm_display_mode *m;
2288 list_for_each_entry(m, &connector->probed_modes, head) {
2289 if (mode->hdisplay == m->hdisplay &&
2290 mode->vdisplay == m->vdisplay &&
2291 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2292 return false; /* duplicated */
2293 if (mode->hdisplay <= m->hdisplay &&
2294 mode->vdisplay <= m->vdisplay)
2301 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2302 struct detailed_timing *timing)
2305 struct drm_display_mode *newmode;
2306 struct drm_device *dev = connector->dev;
2308 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2309 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2310 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2311 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2313 drm_mode_probed_add(connector, newmode);
2322 /* fix up 1366x768 mode from 1368x768;
2323 * GFT/CVT can't express 1366 width which isn't dividable by 8
2325 static void fixup_mode_1366x768(struct drm_display_mode *mode)
2327 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2328 mode->hdisplay = 1366;
2329 mode->hsync_start--;
2331 drm_mode_set_name(mode);
2336 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2337 struct detailed_timing *timing)
2340 struct drm_display_mode *newmode;
2341 struct drm_device *dev = connector->dev;
2343 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2344 const struct minimode *m = &extra_modes[i];
2345 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2349 fixup_mode_1366x768(newmode);
2350 if (!mode_in_range(newmode, edid, timing) ||
2351 !valid_inferred_mode(connector, newmode)) {
2352 drm_mode_destroy(dev, newmode);
2356 drm_mode_probed_add(connector, newmode);
2364 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2365 struct detailed_timing *timing)
2368 struct drm_display_mode *newmode;
2369 struct drm_device *dev = connector->dev;
2370 bool rb = drm_monitor_supports_rb(edid);
2372 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2373 const struct minimode *m = &extra_modes[i];
2374 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2378 fixup_mode_1366x768(newmode);
2379 if (!mode_in_range(newmode, edid, timing) ||
2380 !valid_inferred_mode(connector, newmode)) {
2381 drm_mode_destroy(dev, newmode);
2385 drm_mode_probed_add(connector, newmode);
2393 do_inferred_modes(struct detailed_timing *timing, void *c)
2395 struct detailed_mode_closure *closure = c;
2396 struct detailed_non_pixel *data = &timing->data.other_data;
2397 struct detailed_data_monitor_range *range = &data->data.range;
2399 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2402 closure->modes += drm_dmt_modes_for_range(closure->connector,
2406 if (!version_greater(closure->edid, 1, 1))
2407 return; /* GTF not defined yet */
2409 switch (range->flags) {
2410 case 0x02: /* secondary gtf, XXX could do more */
2411 case 0x00: /* default gtf */
2412 closure->modes += drm_gtf_modes_for_range(closure->connector,
2416 case 0x04: /* cvt, only in 1.4+ */
2417 if (!version_greater(closure->edid, 1, 3))
2420 closure->modes += drm_cvt_modes_for_range(closure->connector,
2424 case 0x01: /* just the ranges, no formula */
2431 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2433 struct detailed_mode_closure closure = {
2434 .connector = connector,
2438 if (version_greater(edid, 1, 0))
2439 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2442 return closure.modes;
2446 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2448 int i, j, m, modes = 0;
2449 struct drm_display_mode *mode;
2450 u8 *est = ((u8 *)timing) + 6;
2452 for (i = 0; i < 6; i++) {
2453 for (j = 7; j >= 0; j--) {
2454 m = (i * 8) + (7 - j);
2455 if (m >= ARRAY_SIZE(est3_modes))
2457 if (est[i] & (1 << j)) {
2458 mode = drm_mode_find_dmt(connector->dev,
2464 drm_mode_probed_add(connector, mode);
2475 do_established_modes(struct detailed_timing *timing, void *c)
2477 struct detailed_mode_closure *closure = c;
2478 struct detailed_non_pixel *data = &timing->data.other_data;
2480 if (data->type == EDID_DETAIL_EST_TIMINGS)
2481 closure->modes += drm_est3_modes(closure->connector, timing);
2485 * add_established_modes - get est. modes from EDID and add them
2486 * @connector: connector to add mode(s) to
2487 * @edid: EDID block to scan
2489 * Each EDID block contains a bitmap of the supported "established modes" list
2490 * (defined above). Tease them out and add them to the global modes list.
2493 add_established_modes(struct drm_connector *connector, struct edid *edid)
2495 struct drm_device *dev = connector->dev;
2496 unsigned long est_bits = edid->established_timings.t1 |
2497 (edid->established_timings.t2 << 8) |
2498 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2500 struct detailed_mode_closure closure = {
2501 .connector = connector,
2505 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2506 if (est_bits & (1<<i)) {
2507 struct drm_display_mode *newmode;
2508 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2510 drm_mode_probed_add(connector, newmode);
2516 if (version_greater(edid, 1, 0))
2517 drm_for_each_detailed_block((u8 *)edid,
2518 do_established_modes, &closure);
2520 return modes + closure.modes;
2524 do_standard_modes(struct detailed_timing *timing, void *c)
2526 struct detailed_mode_closure *closure = c;
2527 struct detailed_non_pixel *data = &timing->data.other_data;
2528 struct drm_connector *connector = closure->connector;
2529 struct edid *edid = closure->edid;
2531 if (data->type == EDID_DETAIL_STD_MODES) {
2533 for (i = 0; i < 6; i++) {
2534 struct std_timing *std;
2535 struct drm_display_mode *newmode;
2537 std = &data->data.timings[i];
2538 newmode = drm_mode_std(connector, edid, std);
2540 drm_mode_probed_add(connector, newmode);
2548 * add_standard_modes - get std. modes from EDID and add them
2549 * @connector: connector to add mode(s) to
2550 * @edid: EDID block to scan
2552 * Standard modes can be calculated using the appropriate standard (DMT,
2553 * GTF or CVT. Grab them from @edid and add them to the list.
2556 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2559 struct detailed_mode_closure closure = {
2560 .connector = connector,
2564 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2565 struct drm_display_mode *newmode;
2567 newmode = drm_mode_std(connector, edid,
2568 &edid->standard_timings[i]);
2570 drm_mode_probed_add(connector, newmode);
2575 if (version_greater(edid, 1, 0))
2576 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2579 /* XXX should also look for standard codes in VTB blocks */
2581 return modes + closure.modes;
2584 static int drm_cvt_modes(struct drm_connector *connector,
2585 struct detailed_timing *timing)
2587 int i, j, modes = 0;
2588 struct drm_display_mode *newmode;
2589 struct drm_device *dev = connector->dev;
2590 struct cvt_timing *cvt;
2591 const int rates[] = { 60, 85, 75, 60, 50 };
2592 const u8 empty[3] = { 0, 0, 0 };
2594 for (i = 0; i < 4; i++) {
2595 int uninitialized_var(width), height;
2596 cvt = &(timing->data.other_data.data.cvt[i]);
2598 if (!memcmp(cvt->code, empty, 3))
2601 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2602 switch (cvt->code[1] & 0x0c) {
2604 width = height * 4 / 3;
2607 width = height * 16 / 9;
2610 width = height * 16 / 10;
2613 width = height * 15 / 9;
2617 for (j = 1; j < 5; j++) {
2618 if (cvt->code[2] & (1 << j)) {
2619 newmode = drm_cvt_mode(dev, width, height,
2623 drm_mode_probed_add(connector, newmode);
2634 do_cvt_mode(struct detailed_timing *timing, void *c)
2636 struct detailed_mode_closure *closure = c;
2637 struct detailed_non_pixel *data = &timing->data.other_data;
2639 if (data->type == EDID_DETAIL_CVT_3BYTE)
2640 closure->modes += drm_cvt_modes(closure->connector, timing);
2644 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2646 struct detailed_mode_closure closure = {
2647 .connector = connector,
2651 if (version_greater(edid, 1, 2))
2652 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2654 /* XXX should also look for CVT codes in VTB blocks */
2656 return closure.modes;
2659 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2662 do_detailed_mode(struct detailed_timing *timing, void *c)
2664 struct detailed_mode_closure *closure = c;
2665 struct drm_display_mode *newmode;
2667 if (timing->pixel_clock) {
2668 newmode = drm_mode_detailed(closure->connector->dev,
2669 closure->edid, timing,
2674 if (closure->preferred)
2675 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2678 * Detailed modes are limited to 10kHz pixel clock resolution,
2679 * so fix up anything that looks like CEA/HDMI mode, but the clock
2680 * is just slightly off.
2682 fixup_detailed_cea_mode_clock(newmode);
2684 drm_mode_probed_add(closure->connector, newmode);
2686 closure->preferred = 0;
2691 * add_detailed_modes - Add modes from detailed timings
2692 * @connector: attached connector
2693 * @edid: EDID block to scan
2694 * @quirks: quirks to apply
2697 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2700 struct detailed_mode_closure closure = {
2701 .connector = connector,
2707 if (closure.preferred && !version_greater(edid, 1, 3))
2709 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2711 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2713 return closure.modes;
2716 #define AUDIO_BLOCK 0x01
2717 #define VIDEO_BLOCK 0x02
2718 #define VENDOR_BLOCK 0x03
2719 #define SPEAKER_BLOCK 0x04
2720 #define VIDEO_CAPABILITY_BLOCK 0x07
2721 #define VIDEO_DATA_BLOCK_420 0x0E
2722 #define VIDEO_CAP_BLOCK_420 0x0F
2723 #define EDID_BASIC_AUDIO (1 << 6)
2724 #define EDID_CEA_YCRCB444 (1 << 5)
2725 #define EDID_CEA_YCRCB422 (1 << 4)
2726 #define EDID_CEA_VCDB_QS (1 << 6)
2729 * Search EDID for CEA extension block.
2731 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id)
2733 u8 *edid_ext = NULL;
2736 /* No EDID or EDID extensions */
2737 if (edid == NULL || edid->extensions == 0)
2740 /* Find CEA extension */
2741 for (i = 0; i < edid->extensions; i++) {
2742 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2743 if (edid_ext[0] == ext_id)
2747 if (i == edid->extensions)
2753 static u8 *drm_find_cea_extension(struct edid *edid)
2755 return drm_find_edid_extension(edid, CEA_EXT);
2758 static u8 *drm_find_displayid_extension(struct edid *edid)
2760 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2764 * Calculate the alternate clock for the CEA mode
2765 * (60Hz vs. 59.94Hz etc.)
2768 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2770 unsigned int clock = cea_mode->clock;
2772 if (cea_mode->vrefresh % 6 != 0)
2776 * edid_cea_modes contains the 59.94Hz
2777 * variant for 240 and 480 line modes,
2778 * and the 60Hz variant otherwise.
2780 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2781 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2783 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2788 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2789 unsigned int clock_tolerance)
2793 if (!to_match->clock)
2796 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2797 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic];
2798 unsigned int clock1, clock2;
2800 /* Check both 60Hz and 59.94Hz */
2801 clock1 = cea_mode->clock;
2802 clock2 = cea_mode_alternate_clock(cea_mode);
2804 if (abs(to_match->clock - clock1) > clock_tolerance &&
2805 abs(to_match->clock - clock2) > clock_tolerance)
2808 if (drm_mode_equal_no_clocks(to_match, cea_mode))
2816 * drm_match_cea_mode - look for a CEA mode matching given mode
2817 * @to_match: display mode
2819 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2822 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2826 if (!to_match->clock)
2829 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2830 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic];
2831 unsigned int clock1, clock2;
2833 /* Check both 60Hz and 59.94Hz */
2834 clock1 = cea_mode->clock;
2835 clock2 = cea_mode_alternate_clock(cea_mode);
2837 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2838 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2839 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode))
2844 EXPORT_SYMBOL(drm_match_cea_mode);
2846 static bool drm_valid_cea_vic(u8 vic)
2848 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2852 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2853 * the input VIC from the CEA mode list
2854 * @video_code: ID given to each of the CEA modes
2856 * Returns picture aspect ratio
2858 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2860 return edid_cea_modes[video_code].picture_aspect_ratio;
2862 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2865 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2868 * It's almost like cea_mode_alternate_clock(), we just need to add an
2869 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2873 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2875 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
2876 return hdmi_mode->clock;
2878 return cea_mode_alternate_clock(hdmi_mode);
2881 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
2882 unsigned int clock_tolerance)
2886 if (!to_match->clock)
2889 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2890 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2891 unsigned int clock1, clock2;
2893 /* Make sure to also match alternate clocks */
2894 clock1 = hdmi_mode->clock;
2895 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2897 if (abs(to_match->clock - clock1) > clock_tolerance &&
2898 abs(to_match->clock - clock2) > clock_tolerance)
2901 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
2909 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
2910 * @to_match: display mode
2912 * An HDMI mode is one defined in the HDMI vendor specific block.
2914 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
2916 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
2920 if (!to_match->clock)
2923 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2924 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2925 unsigned int clock1, clock2;
2927 /* Make sure to also match alternate clocks */
2928 clock1 = hdmi_mode->clock;
2929 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2931 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2932 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2933 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
2939 static bool drm_valid_hdmi_vic(u8 vic)
2941 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
2945 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
2947 struct drm_device *dev = connector->dev;
2948 struct drm_display_mode *mode, *tmp;
2952 /* Don't add CEA modes if the CEA extension block is missing */
2953 if (!drm_find_cea_extension(edid))
2957 * Go through all probed modes and create a new mode
2958 * with the alternate clock for certain CEA modes.
2960 list_for_each_entry(mode, &connector->probed_modes, head) {
2961 const struct drm_display_mode *cea_mode = NULL;
2962 struct drm_display_mode *newmode;
2963 u8 vic = drm_match_cea_mode(mode);
2964 unsigned int clock1, clock2;
2966 if (drm_valid_cea_vic(vic)) {
2967 cea_mode = &edid_cea_modes[vic];
2968 clock2 = cea_mode_alternate_clock(cea_mode);
2970 vic = drm_match_hdmi_mode(mode);
2971 if (drm_valid_hdmi_vic(vic)) {
2972 cea_mode = &edid_4k_modes[vic];
2973 clock2 = hdmi_mode_alternate_clock(cea_mode);
2980 clock1 = cea_mode->clock;
2982 if (clock1 == clock2)
2985 if (mode->clock != clock1 && mode->clock != clock2)
2988 newmode = drm_mode_duplicate(dev, cea_mode);
2992 /* Carry over the stereo flags */
2993 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
2996 * The current mode could be either variant. Make
2997 * sure to pick the "other" clock for the new mode.
2999 if (mode->clock != clock1)
3000 newmode->clock = clock1;
3002 newmode->clock = clock2;
3004 list_add_tail(&newmode->head, &list);
3007 list_for_each_entry_safe(mode, tmp, &list, head) {
3008 list_del(&mode->head);
3009 drm_mode_probed_add(connector, mode);
3016 static struct drm_display_mode *
3017 drm_display_mode_from_vic_index(struct drm_connector *connector,
3018 const u8 *video_db, u8 video_len,
3021 struct drm_device *dev = connector->dev;
3022 struct drm_display_mode *newmode;
3025 if (video_db == NULL || video_index >= video_len)
3028 /* CEA modes are numbered 1..127 */
3029 vic = (video_db[video_index] & 127);
3030 if (!drm_valid_cea_vic(vic))
3033 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3037 newmode->vrefresh = 0;
3043 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3047 for (i = 0; i < len; i++) {
3048 struct drm_display_mode *mode;
3049 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3051 drm_mode_probed_add(connector, mode);
3059 struct stereo_mandatory_mode {
3060 int width, height, vrefresh;
3064 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3065 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3066 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3068 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3070 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3071 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3072 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3073 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3074 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3078 stereo_match_mandatory(const struct drm_display_mode *mode,
3079 const struct stereo_mandatory_mode *stereo_mode)
3081 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3083 return mode->hdisplay == stereo_mode->width &&
3084 mode->vdisplay == stereo_mode->height &&
3085 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3086 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3089 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3091 struct drm_device *dev = connector->dev;
3092 const struct drm_display_mode *mode;
3093 struct list_head stereo_modes;
3096 INIT_LIST_HEAD(&stereo_modes);
3098 list_for_each_entry(mode, &connector->probed_modes, head) {
3099 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3100 const struct stereo_mandatory_mode *mandatory;
3101 struct drm_display_mode *new_mode;
3103 if (!stereo_match_mandatory(mode,
3104 &stereo_mandatory_modes[i]))
3107 mandatory = &stereo_mandatory_modes[i];
3108 new_mode = drm_mode_duplicate(dev, mode);
3112 new_mode->flags |= mandatory->flags;
3113 list_add_tail(&new_mode->head, &stereo_modes);
3118 list_splice_tail(&stereo_modes, &connector->probed_modes);
3123 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3125 struct drm_device *dev = connector->dev;
3126 struct drm_display_mode *newmode;
3128 if (!drm_valid_hdmi_vic(vic)) {
3129 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3133 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3137 drm_mode_probed_add(connector, newmode);
3142 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3143 const u8 *video_db, u8 video_len, u8 video_index)
3145 struct drm_display_mode *newmode;
3148 if (structure & (1 << 0)) {
3149 newmode = drm_display_mode_from_vic_index(connector, video_db,
3153 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3154 drm_mode_probed_add(connector, newmode);
3158 if (structure & (1 << 6)) {
3159 newmode = drm_display_mode_from_vic_index(connector, video_db,
3163 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3164 drm_mode_probed_add(connector, newmode);
3168 if (structure & (1 << 8)) {
3169 newmode = drm_display_mode_from_vic_index(connector, video_db,
3173 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3174 drm_mode_probed_add(connector, newmode);
3182 static int add_420_mode(struct drm_connector *connector, u8 vic)
3184 struct drm_device *dev = connector->dev;
3185 struct drm_display_mode *newmode;
3187 if (!drm_valid_cea_vic(vic))
3190 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3194 newmode->flags |= DRM_MODE_FLAG_420_ONLY;
3195 drm_mode_probed_add(connector, newmode);
3200 static int add_420_vdb_modes(struct drm_connector *connector, const u8 *svds,
3205 for (i = 0; i < svds_len; i++)
3206 modes += add_420_mode(connector, svds[i]);
3211 static int add_420_vcb_modes(struct drm_connector *connector, const u8 *svds,
3212 u8 svds_len, const u8 *video_db, u8 video_len)
3214 struct drm_display_mode *newmode = NULL;
3215 int modes = 0, i, j;
3217 for (i = 0; i < svds_len; i++) {
3220 for (j = 0; j < 8; j++) {
3221 if (mask & (1 << j)) {
3222 newmode = drm_display_mode_from_vic_index(
3223 connector, video_db, video_len,
3226 newmode->flags |= DRM_MODE_FLAG_420;
3227 drm_mode_probed_add(connector, newmode);
3237 static int add_420_vcb_modes_all(struct drm_connector *connector,
3238 const u8 *video_db, u8 video_len)
3240 struct drm_display_mode *newmode = NULL;
3243 for (i = 0; i < video_len; i++) {
3244 newmode = drm_display_mode_from_vic_index(connector, video_db,
3247 newmode->flags |= DRM_MODE_FLAG_420;
3248 drm_mode_probed_add(connector, newmode);
3256 static int do_hdmi_420_modes(struct drm_connector *connector, const u8 *vdb,
3257 u8 vdb_len, const u8 *vcb, u8 vcb_len, const u8 *video_db,
3262 if (vdb && (vdb_len > 1)) /* Add 4:2:0 modes present in EDID */
3263 modes += add_420_vdb_modes(connector, &vdb[2], vdb_len - 1);
3265 if (vcb && (vcb_len > 1)) /* Parse bit mask of supported modes */
3266 modes += add_420_vcb_modes(connector, &vcb[2], vcb_len - 1,
3267 video_db, video_len);
3268 else if (vcb) /* All modes support 4:2:0 mode */
3269 modes += add_420_vcb_modes_all(connector, video_db, video_len);
3271 DRM_DEBUG("added %d 4:2:0 modes\n", modes);
3276 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3277 * @connector: connector corresponding to the HDMI sink
3278 * @db: start of the CEA vendor specific block
3279 * @len: length of the CEA block payload, ie. one can access up to db[len]
3281 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3282 * also adds the stereo 3d modes when applicable.
3285 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3286 const u8 *video_db, u8 video_len)
3288 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3289 u8 vic_len, hdmi_3d_len = 0;
3296 /* no HDMI_Video_Present */
3297 if (!(db[8] & (1 << 5)))
3300 /* Latency_Fields_Present */
3301 if (db[8] & (1 << 7))
3304 /* I_Latency_Fields_Present */
3305 if (db[8] & (1 << 6))
3308 /* the declared length is not long enough for the 2 first bytes
3309 * of additional video format capabilities */
3310 if (len < (8 + offset + 2))
3315 if (db[8 + offset] & (1 << 7)) {
3316 modes += add_hdmi_mandatory_stereo_modes(connector);
3318 /* 3D_Multi_present */
3319 multi_present = (db[8 + offset] & 0x60) >> 5;
3323 vic_len = db[8 + offset] >> 5;
3324 hdmi_3d_len = db[8 + offset] & 0x1f;
3326 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3329 vic = db[9 + offset + i];
3330 modes += add_hdmi_mode(connector, vic);
3332 offset += 1 + vic_len;
3334 if (multi_present == 1)
3336 else if (multi_present == 2)
3341 if (len < (8 + offset + hdmi_3d_len - 1))
3344 if (hdmi_3d_len < multi_len)
3347 if (multi_present == 1 || multi_present == 2) {
3348 /* 3D_Structure_ALL */
3349 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3351 /* check if 3D_MASK is present */
3352 if (multi_present == 2)
3353 mask = (db[10 + offset] << 8) | db[11 + offset];
3357 for (i = 0; i < 16; i++) {
3358 if (mask & (1 << i))
3359 modes += add_3d_struct_modes(connector,
3366 offset += multi_len;
3368 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3370 struct drm_display_mode *newmode = NULL;
3371 unsigned int newflag = 0;
3372 bool detail_present;
3374 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3376 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3379 /* 2D_VIC_order_X */
3380 vic_index = db[8 + offset + i] >> 4;
3382 /* 3D_Structure_X */
3383 switch (db[8 + offset + i] & 0x0f) {
3385 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3388 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3392 if ((db[9 + offset + i] >> 4) == 1)
3393 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3398 newmode = drm_display_mode_from_vic_index(connector,
3404 newmode->flags |= newflag;
3405 drm_mode_probed_add(connector, newmode);
3419 cea_db_payload_len(const u8 *db)
3421 return db[0] & 0x1f;
3425 cea_db_tag(const u8 *db)
3431 cea_db_extended_tag(const u8 *db)
3437 cea_revision(const u8 *cea)
3443 cea_db_offsets(const u8 *cea, int *start, int *end)
3445 /* Data block offset in CEA extension block */
3450 if (*end < 4 || *end > 127)
3455 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3459 if (cea_db_tag(db) != VENDOR_BLOCK)
3462 if (cea_db_payload_len(db) < 5)
3465 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3467 return hdmi_id == HDMI_IEEE_OUI;
3470 static bool cea_db_is_hdmi_vdb420(const u8 *db)
3472 if (cea_db_tag(db) != VIDEO_CAPABILITY_BLOCK)
3475 if (cea_db_extended_tag(db) != VIDEO_DATA_BLOCK_420)
3481 static bool cea_db_is_hdmi_vcb420(const u8 *db)
3483 if (cea_db_tag(db) != VIDEO_CAPABILITY_BLOCK)
3486 if (cea_db_extended_tag(db) != VIDEO_CAP_BLOCK_420)
3492 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3496 if (cea_db_tag(db) != VENDOR_BLOCK)
3499 if (cea_db_payload_len(db) < 7)
3502 oui = db[3] << 16 | db[2] << 8 | db[1];
3504 return oui == HDMI_FORUM_IEEE_OUI;
3507 #define for_each_cea_db(cea, i, start, end) \
3508 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3511 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3513 const u8 *cea = drm_find_cea_extension(edid);
3514 const u8 *db, *hdmi = NULL, *video = NULL, *vdb420 = NULL,
3516 u8 dbl, hdmi_len, video_len = 0, vdb420_len = 0, vcb420_len = 0;
3519 if (cea && cea_revision(cea) >= 3) {
3522 if (cea_db_offsets(cea, &start, &end))
3525 for_each_cea_db(cea, i, start, end) {
3527 dbl = cea_db_payload_len(db);
3529 if (cea_db_tag(db) == VIDEO_BLOCK) {
3532 modes += do_cea_modes(connector, video, dbl);
3534 else if (cea_db_is_hdmi_vsdb(db)) {
3537 } else if (cea_db_is_hdmi_vdb420(db)) {
3540 } else if (cea_db_is_hdmi_vcb420(db)) {
3548 * We parse the HDMI VSDB after having added the cea modes as we will
3549 * be patching their flags when the sink supports stereo 3D.
3552 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3555 if (vdb420 || vcb420)
3556 modes += do_hdmi_420_modes(connector, vdb420, vdb420_len,
3557 vcb420, vcb420_len, video, video_len);
3562 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3564 const struct drm_display_mode *cea_mode;
3565 int clock1, clock2, clock;
3570 * allow 5kHz clock difference either way to account for
3571 * the 10kHz clock resolution limit of detailed timings.
3573 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3574 if (drm_valid_cea_vic(vic)) {
3576 cea_mode = &edid_cea_modes[vic];
3577 clock1 = cea_mode->clock;
3578 clock2 = cea_mode_alternate_clock(cea_mode);
3580 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3581 if (drm_valid_hdmi_vic(vic)) {
3583 cea_mode = &edid_4k_modes[vic];
3584 clock1 = cea_mode->clock;
3585 clock2 = hdmi_mode_alternate_clock(cea_mode);
3591 /* pick whichever is closest */
3592 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3597 if (mode->clock == clock)
3600 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3601 type, vic, mode->clock, clock);
3602 mode->clock = clock;
3606 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3608 u8 len = cea_db_payload_len(db);
3611 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
3613 connector->latency_present[0] = db[8] >> 7;
3614 connector->latency_present[1] = (db[8] >> 6) & 1;
3617 connector->video_latency[0] = db[9];
3619 connector->audio_latency[0] = db[10];
3621 connector->video_latency[1] = db[11];
3623 connector->audio_latency[1] = db[12];
3625 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3626 "video latency %d %d, "
3627 "audio latency %d %d\n",
3628 connector->latency_present[0],
3629 connector->latency_present[1],
3630 connector->video_latency[0],
3631 connector->video_latency[1],
3632 connector->audio_latency[0],
3633 connector->audio_latency[1]);
3637 monitor_name(struct detailed_timing *t, void *data)
3639 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3640 *(u8 **)data = t->data.other_data.data.str.str;
3644 * drm_edid_to_eld - build ELD from EDID
3645 * @connector: connector corresponding to the HDMI/DP sink
3646 * @edid: EDID to parse
3648 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3649 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3652 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3654 uint8_t *eld = connector->eld;
3658 int total_sad_count = 0;
3662 memset(eld, 0, sizeof(connector->eld));
3664 connector->latency_present[0] = false;
3665 connector->latency_present[1] = false;
3666 connector->video_latency[0] = 0;
3667 connector->audio_latency[0] = 0;
3668 connector->video_latency[1] = 0;
3669 connector->audio_latency[1] = 0;
3671 cea = drm_find_cea_extension(edid);
3673 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3678 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name);
3679 /* max: 13 bytes EDID, 16 bytes ELD */
3680 for (mnl = 0; name && mnl < 13; mnl++) {
3681 if (name[mnl] == 0x0a)
3683 eld[20 + mnl] = name[mnl];
3685 eld[4] = (cea[1] << 5) | mnl;
3686 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3688 eld[0] = 2 << 3; /* ELD version: 2 */
3690 eld[16] = edid->mfg_id[0];
3691 eld[17] = edid->mfg_id[1];
3692 eld[18] = edid->prod_code[0];
3693 eld[19] = edid->prod_code[1];
3695 if (cea_revision(cea) >= 3) {
3698 if (cea_db_offsets(cea, &start, &end)) {
3703 for_each_cea_db(cea, i, start, end) {
3705 dbl = cea_db_payload_len(db);
3707 switch (cea_db_tag(db)) {
3711 /* Audio Data Block, contains SADs */
3712 sad_count = min(dbl / 3, 15 - total_sad_count);
3714 memcpy(eld + 20 + mnl + total_sad_count * 3,
3715 &db[1], sad_count * 3);
3716 total_sad_count += sad_count;
3719 /* Speaker Allocation Data Block */
3724 /* HDMI Vendor-Specific Data Block */
3725 if (cea_db_is_hdmi_vsdb(db))
3726 drm_parse_hdmi_vsdb_audio(connector, db);
3733 eld[5] |= total_sad_count << 4;
3735 eld[DRM_ELD_BASELINE_ELD_LEN] =
3736 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3738 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3739 drm_eld_size(eld), total_sad_count);
3741 EXPORT_SYMBOL(drm_edid_to_eld);
3744 * drm_edid_to_sad - extracts SADs from EDID
3745 * @edid: EDID to parse
3746 * @sads: pointer that will be set to the extracted SADs
3748 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3750 * Note: The returned pointer needs to be freed using kfree().
3752 * Return: The number of found SADs or negative number on error.
3754 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3757 int i, start, end, dbl;
3760 cea = drm_find_cea_extension(edid);
3762 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3766 if (cea_revision(cea) < 3) {
3767 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3771 if (cea_db_offsets(cea, &start, &end)) {
3772 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3776 for_each_cea_db(cea, i, start, end) {
3779 if (cea_db_tag(db) == AUDIO_BLOCK) {
3781 dbl = cea_db_payload_len(db);
3783 count = dbl / 3; /* SAD is 3B */
3784 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3787 for (j = 0; j < count; j++) {
3788 u8 *sad = &db[1 + j * 3];
3790 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3791 (*sads)[j].channels = sad[0] & 0x7;
3792 (*sads)[j].freq = sad[1] & 0x7F;
3793 (*sads)[j].byte2 = sad[2];
3801 EXPORT_SYMBOL(drm_edid_to_sad);
3804 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3805 * @edid: EDID to parse
3806 * @sadb: pointer to the speaker block
3808 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
3810 * Note: The returned pointer needs to be freed using kfree().
3812 * Return: The number of found Speaker Allocation Blocks or negative number on
3815 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
3818 int i, start, end, dbl;
3821 cea = drm_find_cea_extension(edid);
3823 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3827 if (cea_revision(cea) < 3) {
3828 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3832 if (cea_db_offsets(cea, &start, &end)) {
3833 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3837 for_each_cea_db(cea, i, start, end) {
3838 const u8 *db = &cea[i];
3840 if (cea_db_tag(db) == SPEAKER_BLOCK) {
3841 dbl = cea_db_payload_len(db);
3843 /* Speaker Allocation Data Block */
3845 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
3856 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
3859 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
3860 * @connector: connector associated with the HDMI/DP sink
3861 * @mode: the display mode
3863 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
3864 * the sink doesn't support audio or video.
3866 int drm_av_sync_delay(struct drm_connector *connector,
3867 const struct drm_display_mode *mode)
3869 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
3872 if (!connector->latency_present[0])
3874 if (!connector->latency_present[1])
3877 a = connector->audio_latency[i];
3878 v = connector->video_latency[i];
3881 * HDMI/DP sink doesn't support audio or video?
3883 if (a == 255 || v == 255)
3887 * Convert raw EDID values to millisecond.
3888 * Treat unknown latency as 0ms.
3891 a = min(2 * (a - 1), 500);
3893 v = min(2 * (v - 1), 500);
3895 return max(v - a, 0);
3897 EXPORT_SYMBOL(drm_av_sync_delay);
3900 * drm_select_eld - select one ELD from multiple HDMI/DP sinks
3901 * @encoder: the encoder just changed display mode
3903 * It's possible for one encoder to be associated with multiple HDMI/DP sinks.
3904 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD.
3906 * Return: The connector associated with the first HDMI/DP sink that has ELD
3909 struct drm_connector *drm_select_eld(struct drm_encoder *encoder)
3911 struct drm_connector *connector;
3912 struct drm_device *dev = encoder->dev;
3914 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
3915 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3917 drm_for_each_connector(connector, dev)
3918 if (connector->encoder == encoder && connector->eld[0])
3923 EXPORT_SYMBOL(drm_select_eld);
3926 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
3927 * @edid: monitor EDID information
3929 * Parse the CEA extension according to CEA-861-B.
3931 * Return: True if the monitor is HDMI, false if not or unknown.
3933 bool drm_detect_hdmi_monitor(struct edid *edid)
3937 int start_offset, end_offset;
3939 edid_ext = drm_find_cea_extension(edid);
3943 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3947 * Because HDMI identifier is in Vendor Specific Block,
3948 * search it from all data blocks of CEA extension.
3950 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3951 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
3957 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
3960 * drm_detect_monitor_audio - check monitor audio capability
3961 * @edid: EDID block to scan
3963 * Monitor should have CEA extension block.
3964 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
3965 * audio' only. If there is any audio extension block and supported
3966 * audio format, assume at least 'basic audio' support, even if 'basic
3967 * audio' is not defined in EDID.
3969 * Return: True if the monitor supports audio, false otherwise.
3971 bool drm_detect_monitor_audio(struct edid *edid)
3975 bool has_audio = false;
3976 int start_offset, end_offset;
3978 edid_ext = drm_find_cea_extension(edid);
3982 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
3985 DRM_DEBUG_KMS("Monitor has basic audio support\n");
3989 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3992 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3993 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
3995 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
3996 DRM_DEBUG_KMS("CEA audio format %d\n",
3997 (edid_ext[i + j] >> 3) & 0xf);
4004 EXPORT_SYMBOL(drm_detect_monitor_audio);
4007 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
4008 * @edid: EDID block to scan
4010 * Check whether the monitor reports the RGB quantization range selection
4011 * as supported. The AVI infoframe can then be used to inform the monitor
4012 * which quantization range (full or limited) is used.
4014 * Return: True if the RGB quantization range is selectable, false otherwise.
4016 bool drm_rgb_quant_range_selectable(struct edid *edid)
4021 edid_ext = drm_find_cea_extension(edid);
4025 if (cea_db_offsets(edid_ext, &start, &end))
4028 for_each_cea_db(edid_ext, i, start, end) {
4029 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
4030 cea_db_payload_len(&edid_ext[i]) == 2) {
4031 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
4032 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
4038 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
4040 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4043 struct drm_display_info *display = &connector->display_info;
4044 struct drm_hdmi_info *hdmi = &display->hdmi;
4046 if (hf_vsdb[6] & 0x80) {
4047 hdmi->scdc.supported = true;
4048 if (hf_vsdb[6] & 0x40)
4049 hdmi->scdc.read_request = true;
4053 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4054 * And as per the spec, three factors confirm this:
4055 * * Availability of a HF-VSDB block in EDID (check)
4056 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4057 * * SCDC support available (let's check)
4058 * Lets check it out.
4062 /* max clock is 5000 KHz times block value */
4063 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4064 struct drm_scdc *scdc = &hdmi->scdc;
4066 if (max_tmds_clock > 340000) {
4067 display->max_tmds_clock = max_tmds_clock;
4068 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4069 display->max_tmds_clock);
4072 if (scdc->supported) {
4073 scdc->scrambling.supported = true;
4075 /* Few sinks support scrambling for cloks < 340M */
4076 if ((hf_vsdb[6] & 0x8))
4077 scdc->scrambling.low_rates = true;
4082 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4085 struct drm_display_info *info = &connector->display_info;
4086 unsigned int dc_bpc = 0;
4088 /* HDMI supports at least 8 bpc */
4091 if (cea_db_payload_len(hdmi) < 6)
4094 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4096 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4097 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4101 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4103 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4104 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4108 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4110 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4111 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4116 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4121 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4122 connector->name, dc_bpc);
4126 * Deep color support mandates RGB444 support for all video
4127 * modes and forbids YCRCB422 support for all video modes per
4130 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4131 /* YCRCB444 is optional according to spec. */
4132 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4133 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4134 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4139 * Spec says that if any deep color mode is supported at all,
4140 * then deep color 36 bit must be supported.
4142 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4143 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4149 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4151 struct drm_display_info *info = &connector->display_info;
4152 u8 len = cea_db_payload_len(db);
4155 info->dvi_dual = db[6] & 1;
4157 info->max_tmds_clock = db[7] * 5000;
4159 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4160 "max TMDS clock %d kHz\n",
4162 info->max_tmds_clock);
4164 drm_parse_hdmi_deep_color_info(connector, db);
4167 static void drm_parse_cea_ext(struct drm_connector *connector,
4170 struct drm_display_info *info = &connector->display_info;
4174 edid_ext = drm_find_cea_extension(edid);
4178 info->cea_rev = edid_ext[1];
4180 /* The existence of a CEA block should imply RGB support */
4181 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4182 if (edid_ext[3] & EDID_CEA_YCRCB444)
4183 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4184 if (edid_ext[3] & EDID_CEA_YCRCB422)
4185 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4187 if (cea_db_offsets(edid_ext, &start, &end))
4190 for_each_cea_db(edid_ext, i, start, end) {
4191 const u8 *db = &edid_ext[i];
4193 if (cea_db_is_hdmi_vsdb(db))
4194 drm_parse_hdmi_vsdb_video(connector, db);
4195 if (cea_db_is_hdmi_forum_vsdb(db))
4196 drm_parse_hdmi_forum_vsdb(connector, db);
4200 static void drm_add_display_info(struct drm_connector *connector,
4203 struct drm_display_info *info = &connector->display_info;
4205 info->width_mm = edid->width_cm * 10;
4206 info->height_mm = edid->height_cm * 10;
4208 /* driver figures it out in this case */
4210 info->color_formats = 0;
4212 info->max_tmds_clock = 0;
4213 info->dvi_dual = false;
4215 if (edid->revision < 3)
4218 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4221 drm_parse_cea_ext(connector, edid);
4224 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4226 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4227 * tells us to assume 8 bpc color depth if the EDID doesn't have
4228 * extensions which tell otherwise.
4230 if ((info->bpc == 0) && (edid->revision < 4) &&
4231 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
4233 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4234 connector->name, info->bpc);
4237 /* Only defined for 1.4 with digital displays */
4238 if (edid->revision < 4)
4241 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4242 case DRM_EDID_DIGITAL_DEPTH_6:
4245 case DRM_EDID_DIGITAL_DEPTH_8:
4248 case DRM_EDID_DIGITAL_DEPTH_10:
4251 case DRM_EDID_DIGITAL_DEPTH_12:
4254 case DRM_EDID_DIGITAL_DEPTH_14:
4257 case DRM_EDID_DIGITAL_DEPTH_16:
4260 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4266 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4267 connector->name, info->bpc);
4269 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4270 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4271 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4272 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4273 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4276 static int validate_displayid(u8 *displayid, int length, int idx)
4280 struct displayid_hdr *base;
4282 base = (struct displayid_hdr *)&displayid[idx];
4284 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4285 base->rev, base->bytes, base->prod_id, base->ext_count);
4287 if (base->bytes + 5 > length - idx)
4289 for (i = idx; i <= base->bytes + 5; i++) {
4290 csum += displayid[i];
4293 DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum);
4299 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4300 struct displayid_detailed_timings_1 *timings)
4302 struct drm_display_mode *mode;
4303 unsigned pixel_clock = (timings->pixel_clock[0] |
4304 (timings->pixel_clock[1] << 8) |
4305 (timings->pixel_clock[2] << 16));
4306 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4307 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4308 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4309 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4310 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4311 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4312 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4313 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4314 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4315 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4316 mode = drm_mode_create(dev);
4320 mode->clock = pixel_clock * 10;
4321 mode->hdisplay = hactive;
4322 mode->hsync_start = mode->hdisplay + hsync;
4323 mode->hsync_end = mode->hsync_start + hsync_width;
4324 mode->htotal = mode->hdisplay + hblank;
4326 mode->vdisplay = vactive;
4327 mode->vsync_start = mode->vdisplay + vsync;
4328 mode->vsync_end = mode->vsync_start + vsync_width;
4329 mode->vtotal = mode->vdisplay + vblank;
4332 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4333 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4334 mode->type = DRM_MODE_TYPE_DRIVER;
4336 if (timings->flags & 0x80)
4337 mode->type |= DRM_MODE_TYPE_PREFERRED;
4338 mode->vrefresh = drm_mode_vrefresh(mode);
4339 drm_mode_set_name(mode);
4344 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4345 struct displayid_block *block)
4347 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4350 struct drm_display_mode *newmode;
4352 /* blocks must be multiple of 20 bytes length */
4353 if (block->num_bytes % 20)
4356 num_timings = block->num_bytes / 20;
4357 for (i = 0; i < num_timings; i++) {
4358 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4360 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4364 drm_mode_probed_add(connector, newmode);
4370 static int add_displayid_detailed_modes(struct drm_connector *connector,
4376 int length = EDID_LENGTH;
4377 struct displayid_block *block;
4380 displayid = drm_find_displayid_extension(edid);
4384 ret = validate_displayid(displayid, length, idx);
4388 idx += sizeof(struct displayid_hdr);
4389 while (block = (struct displayid_block *)&displayid[idx],
4390 idx + sizeof(struct displayid_block) <= length &&
4391 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4392 block->num_bytes > 0) {
4393 idx += block->num_bytes + sizeof(struct displayid_block);
4394 switch (block->tag) {
4395 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4396 num_modes += add_displayid_detailed_1_modes(connector, block);
4404 * drm_add_edid_modes - add modes from EDID data, if available
4405 * @connector: connector we're probing
4408 * Add the specified modes to the connector's mode list.
4410 * Return: The number of modes added or 0 if we couldn't find any.
4412 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4420 if (!drm_edid_is_valid(edid)) {
4421 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4426 quirks = edid_get_quirks(edid);
4429 * EDID spec says modes should be preferred in this order:
4430 * - preferred detailed mode
4431 * - other detailed modes from base block
4432 * - detailed modes from extension blocks
4433 * - CVT 3-byte code modes
4434 * - standard timing codes
4435 * - established timing codes
4436 * - modes inferred from GTF or CVT range information
4438 * We get this pretty much right.
4440 * XXX order for additional mode types in extension blocks?
4442 num_modes += add_detailed_modes(connector, edid, quirks);
4443 num_modes += add_cvt_modes(connector, edid);
4444 num_modes += add_standard_modes(connector, edid);
4445 num_modes += add_established_modes(connector, edid);
4446 num_modes += add_cea_modes(connector, edid);
4447 num_modes += add_alternate_cea_modes(connector, edid);
4448 num_modes += add_displayid_detailed_modes(connector, edid);
4449 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4450 num_modes += add_inferred_modes(connector, edid);
4452 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4453 edid_fixup_preferred(connector, quirks);
4455 drm_add_display_info(connector, edid);
4457 if (quirks & EDID_QUIRK_FORCE_6BPC)
4458 connector->display_info.bpc = 6;
4460 if (quirks & EDID_QUIRK_FORCE_8BPC)
4461 connector->display_info.bpc = 8;
4463 if (quirks & EDID_QUIRK_FORCE_10BPC)
4464 connector->display_info.bpc = 10;
4466 if (quirks & EDID_QUIRK_FORCE_12BPC)
4467 connector->display_info.bpc = 12;
4471 EXPORT_SYMBOL(drm_add_edid_modes);
4474 * drm_add_modes_noedid - add modes for the connectors without EDID
4475 * @connector: connector we're probing
4476 * @hdisplay: the horizontal display limit
4477 * @vdisplay: the vertical display limit
4479 * Add the specified modes to the connector's mode list. Only when the
4480 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4482 * Return: The number of modes added or 0 if we couldn't find any.
4484 int drm_add_modes_noedid(struct drm_connector *connector,
4485 int hdisplay, int vdisplay)
4487 int i, count, num_modes = 0;
4488 struct drm_display_mode *mode;
4489 struct drm_device *dev = connector->dev;
4491 count = ARRAY_SIZE(drm_dmt_modes);
4497 for (i = 0; i < count; i++) {
4498 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4499 if (hdisplay && vdisplay) {
4501 * Only when two are valid, they will be used to check
4502 * whether the mode should be added to the mode list of
4505 if (ptr->hdisplay > hdisplay ||
4506 ptr->vdisplay > vdisplay)
4509 if (drm_mode_vrefresh(ptr) > 61)
4511 mode = drm_mode_duplicate(dev, ptr);
4513 drm_mode_probed_add(connector, mode);
4519 EXPORT_SYMBOL(drm_add_modes_noedid);
4522 * drm_set_preferred_mode - Sets the preferred mode of a connector
4523 * @connector: connector whose mode list should be processed
4524 * @hpref: horizontal resolution of preferred mode
4525 * @vpref: vertical resolution of preferred mode
4527 * Marks a mode as preferred if it matches the resolution specified by @hpref
4530 void drm_set_preferred_mode(struct drm_connector *connector,
4531 int hpref, int vpref)
4533 struct drm_display_mode *mode;
4535 list_for_each_entry(mode, &connector->probed_modes, head) {
4536 if (mode->hdisplay == hpref &&
4537 mode->vdisplay == vpref)
4538 mode->type |= DRM_MODE_TYPE_PREFERRED;
4541 EXPORT_SYMBOL(drm_set_preferred_mode);
4544 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4545 * data from a DRM display mode
4546 * @frame: HDMI AVI infoframe
4547 * @mode: DRM display mode
4548 * @is_hdmi2: Sink is HDMI 2.0 compliant
4550 * Return: 0 on success or a negative error code on failure.
4553 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4554 const struct drm_display_mode *mode,
4559 if (!frame || !mode)
4562 err = hdmi_avi_infoframe_init(frame);
4566 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4567 frame->pixel_repeat = 1;
4569 frame->video_code = drm_match_cea_mode(mode);
4572 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4573 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4574 * have to make sure we dont break HDMI 1.4 sinks.
4576 if (!is_hdmi2 && frame->video_code > 64)
4577 frame->video_code = 0;
4579 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4582 * Populate picture aspect ratio from either
4583 * user input (if specified) or from the CEA mode list.
4585 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4586 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4587 frame->picture_aspect = mode->picture_aspect_ratio;
4588 else if (frame->video_code > 0)
4589 frame->picture_aspect = drm_get_cea_aspect_ratio(
4592 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4593 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4597 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4599 static enum hdmi_3d_structure
4600 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4602 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4605 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4606 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4607 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4608 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4609 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4610 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4611 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4612 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4613 case DRM_MODE_FLAG_3D_L_DEPTH:
4614 return HDMI_3D_STRUCTURE_L_DEPTH;
4615 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4616 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4617 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4618 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4619 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4620 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4622 return HDMI_3D_STRUCTURE_INVALID;
4627 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4628 * data from a DRM display mode
4629 * @frame: HDMI vendor infoframe
4630 * @mode: DRM display mode
4632 * Note that there's is a need to send HDMI vendor infoframes only when using a
4633 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4634 * function will return -EINVAL, error that can be safely ignored.
4636 * Return: 0 on success or a negative error code on failure.
4639 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4640 const struct drm_display_mode *mode)
4646 if (!frame || !mode)
4649 vic = drm_match_hdmi_mode(mode);
4650 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4652 if (!vic && !s3d_flags)
4655 if (vic && s3d_flags)
4658 err = hdmi_vendor_infoframe_init(frame);
4665 frame->s3d_struct = s3d_structure_from_display_mode(mode);
4669 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
4671 static int drm_parse_tiled_block(struct drm_connector *connector,
4672 struct displayid_block *block)
4674 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
4676 u8 tile_v_loc, tile_h_loc;
4677 u8 num_v_tile, num_h_tile;
4678 struct drm_tile_group *tg;
4680 w = tile->tile_size[0] | tile->tile_size[1] << 8;
4681 h = tile->tile_size[2] | tile->tile_size[3] << 8;
4683 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
4684 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
4685 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
4686 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
4688 connector->has_tile = true;
4689 if (tile->tile_cap & 0x80)
4690 connector->tile_is_single_monitor = true;
4692 connector->num_h_tile = num_h_tile + 1;
4693 connector->num_v_tile = num_v_tile + 1;
4694 connector->tile_h_loc = tile_h_loc;
4695 connector->tile_v_loc = tile_v_loc;
4696 connector->tile_h_size = w + 1;
4697 connector->tile_v_size = h + 1;
4699 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
4700 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
4701 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
4702 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
4703 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
4705 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
4707 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
4712 if (connector->tile_group != tg) {
4713 /* if we haven't got a pointer,
4714 take the reference, drop ref to old tile group */
4715 if (connector->tile_group) {
4716 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4718 connector->tile_group = tg;
4720 /* if same tile group, then release the ref we just took. */
4721 drm_mode_put_tile_group(connector->dev, tg);
4725 static int drm_parse_display_id(struct drm_connector *connector,
4726 u8 *displayid, int length,
4727 bool is_edid_extension)
4729 /* if this is an EDID extension the first byte will be 0x70 */
4731 struct displayid_block *block;
4734 if (is_edid_extension)
4737 ret = validate_displayid(displayid, length, idx);
4741 idx += sizeof(struct displayid_hdr);
4742 while (block = (struct displayid_block *)&displayid[idx],
4743 idx + sizeof(struct displayid_block) <= length &&
4744 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4745 block->num_bytes > 0) {
4746 idx += block->num_bytes + sizeof(struct displayid_block);
4747 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
4748 block->tag, block->rev, block->num_bytes);
4750 switch (block->tag) {
4751 case DATA_BLOCK_TILED_DISPLAY:
4752 ret = drm_parse_tiled_block(connector, block);
4756 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4757 /* handled in mode gathering code. */
4760 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
4767 static void drm_get_displayid(struct drm_connector *connector,
4770 void *displayid = NULL;
4772 connector->has_tile = false;
4773 displayid = drm_find_displayid_extension(edid);
4775 /* drop reference to any tile group we had */
4779 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
4782 if (!connector->has_tile)
4786 if (connector->tile_group) {
4787 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4788 connector->tile_group = NULL;
projects / firefly-linux-kernel-4.4.55.git / blob