2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_displayid.h>
39 #define version_greater(edid, maj, min) \
40 (((edid)->version > (maj)) || \
41 ((edid)->version == (maj) && (edid)->revision > (min)))
43 #define EDID_EST_TIMINGS 16
44 #define EDID_STD_TIMINGS 8
45 #define EDID_DETAILED_TIMINGS 4
48 * EDID blocks out in the wild have a variety of bugs, try to collect
49 * them here (note that userspace may work around broken monitors first,
50 * but fixes should make their way here so that the kernel "just works"
51 * on as many displays as possible).
54 /* First detailed mode wrong, use largest 60Hz mode */
55 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
56 /* Reported 135MHz pixel clock is too high, needs adjustment */
57 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
58 /* Prefer the largest mode at 75 Hz */
59 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
60 /* Detail timing is in cm not mm */
61 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
62 /* Detailed timing descriptors have bogus size values, so just take the
63 * maximum size and use that.
65 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
66 /* Monitor forgot to set the first detailed is preferred bit. */
67 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
68 /* use +hsync +vsync for detailed mode */
69 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
70 /* Force reduced-blanking timings for detailed modes */
71 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
73 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
75 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
77 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
79 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
81 struct detailed_mode_closure {
82 struct drm_connector *connector;
94 static struct edid_quirk {
98 } edid_quirk_list[] = {
100 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
102 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
104 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
106 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
107 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
109 /* Belinea 10 15 55 */
110 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
111 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
113 /* Envision Peripherals, Inc. EN-7100e */
114 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
115 /* Envision EN2028 */
116 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
118 /* Funai Electronics PM36B */
119 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
120 EDID_QUIRK_DETAILED_IN_CM },
122 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
123 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
125 /* LG Philips LCD LP154W01-A5 */
126 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
127 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
129 /* Philips 107p5 CRT */
130 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
133 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
135 /* Samsung SyncMaster 205BW. Note: irony */
136 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
137 /* Samsung SyncMaster 22[5-6]BW */
138 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
139 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
141 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
142 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
144 /* ViewSonic VA2026w */
145 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
147 /* Medion MD 30217 PG */
148 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
150 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
151 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
153 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
154 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
158 * Autogenerated from the DMT spec.
159 * This table is copied from xfree86/modes/xf86EdidModes.c.
161 static const struct drm_display_mode drm_dmt_modes[] = {
162 /* 0x01 - 640x350@85Hz */
163 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
164 736, 832, 0, 350, 382, 385, 445, 0,
165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
166 /* 0x02 - 640x400@85Hz */
167 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
168 736, 832, 0, 400, 401, 404, 445, 0,
169 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
170 /* 0x03 - 720x400@85Hz */
171 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
172 828, 936, 0, 400, 401, 404, 446, 0,
173 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
174 /* 0x04 - 640x480@60Hz */
175 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
176 752, 800, 0, 480, 490, 492, 525, 0,
177 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
178 /* 0x05 - 640x480@72Hz */
179 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
180 704, 832, 0, 480, 489, 492, 520, 0,
181 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
182 /* 0x06 - 640x480@75Hz */
183 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
184 720, 840, 0, 480, 481, 484, 500, 0,
185 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
186 /* 0x07 - 640x480@85Hz */
187 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
188 752, 832, 0, 480, 481, 484, 509, 0,
189 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
190 /* 0x08 - 800x600@56Hz */
191 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
192 896, 1024, 0, 600, 601, 603, 625, 0,
193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
194 /* 0x09 - 800x600@60Hz */
195 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
196 968, 1056, 0, 600, 601, 605, 628, 0,
197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
198 /* 0x0a - 800x600@72Hz */
199 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
200 976, 1040, 0, 600, 637, 643, 666, 0,
201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
202 /* 0x0b - 800x600@75Hz */
203 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
204 896, 1056, 0, 600, 601, 604, 625, 0,
205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
206 /* 0x0c - 800x600@85Hz */
207 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
208 896, 1048, 0, 600, 601, 604, 631, 0,
209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
210 /* 0x0d - 800x600@120Hz RB */
211 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
212 880, 960, 0, 600, 603, 607, 636, 0,
213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
214 /* 0x0e - 848x480@60Hz */
215 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
216 976, 1088, 0, 480, 486, 494, 517, 0,
217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
218 /* 0x0f - 1024x768@43Hz, interlace */
219 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
220 1208, 1264, 0, 768, 768, 772, 817, 0,
221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
222 DRM_MODE_FLAG_INTERLACE) },
223 /* 0x10 - 1024x768@60Hz */
224 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
225 1184, 1344, 0, 768, 771, 777, 806, 0,
226 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
227 /* 0x11 - 1024x768@70Hz */
228 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
229 1184, 1328, 0, 768, 771, 777, 806, 0,
230 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
231 /* 0x12 - 1024x768@75Hz */
232 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
233 1136, 1312, 0, 768, 769, 772, 800, 0,
234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
235 /* 0x13 - 1024x768@85Hz */
236 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
237 1168, 1376, 0, 768, 769, 772, 808, 0,
238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
239 /* 0x14 - 1024x768@120Hz RB */
240 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
241 1104, 1184, 0, 768, 771, 775, 813, 0,
242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
243 /* 0x15 - 1152x864@75Hz */
244 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
245 1344, 1600, 0, 864, 865, 868, 900, 0,
246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
247 /* 0x55 - 1280x720@60Hz */
248 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
249 1430, 1650, 0, 720, 725, 730, 750, 0,
250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
251 /* 0x16 - 1280x768@60Hz RB */
252 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
253 1360, 1440, 0, 768, 771, 778, 790, 0,
254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
255 /* 0x17 - 1280x768@60Hz */
256 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
257 1472, 1664, 0, 768, 771, 778, 798, 0,
258 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
259 /* 0x18 - 1280x768@75Hz */
260 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
261 1488, 1696, 0, 768, 771, 778, 805, 0,
262 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
263 /* 0x19 - 1280x768@85Hz */
264 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
265 1496, 1712, 0, 768, 771, 778, 809, 0,
266 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
267 /* 0x1a - 1280x768@120Hz RB */
268 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
269 1360, 1440, 0, 768, 771, 778, 813, 0,
270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
271 /* 0x1b - 1280x800@60Hz RB */
272 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
273 1360, 1440, 0, 800, 803, 809, 823, 0,
274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
275 /* 0x1c - 1280x800@60Hz */
276 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
277 1480, 1680, 0, 800, 803, 809, 831, 0,
278 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
279 /* 0x1d - 1280x800@75Hz */
280 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
281 1488, 1696, 0, 800, 803, 809, 838, 0,
282 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
283 /* 0x1e - 1280x800@85Hz */
284 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
285 1496, 1712, 0, 800, 803, 809, 843, 0,
286 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
287 /* 0x1f - 1280x800@120Hz RB */
288 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
289 1360, 1440, 0, 800, 803, 809, 847, 0,
290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
291 /* 0x20 - 1280x960@60Hz */
292 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
293 1488, 1800, 0, 960, 961, 964, 1000, 0,
294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
295 /* 0x21 - 1280x960@85Hz */
296 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
297 1504, 1728, 0, 960, 961, 964, 1011, 0,
298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
299 /* 0x22 - 1280x960@120Hz RB */
300 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
301 1360, 1440, 0, 960, 963, 967, 1017, 0,
302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
303 /* 0x23 - 1280x1024@60Hz */
304 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
305 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
307 /* 0x24 - 1280x1024@75Hz */
308 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
309 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
311 /* 0x25 - 1280x1024@85Hz */
312 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
313 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
315 /* 0x26 - 1280x1024@120Hz RB */
316 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
317 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
319 /* 0x27 - 1360x768@60Hz */
320 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
321 1536, 1792, 0, 768, 771, 777, 795, 0,
322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
323 /* 0x28 - 1360x768@120Hz RB */
324 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
325 1440, 1520, 0, 768, 771, 776, 813, 0,
326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
327 /* 0x51 - 1366x768@60Hz */
328 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
329 1579, 1792, 0, 768, 771, 774, 798, 0,
330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
331 /* 0x56 - 1366x768@60Hz */
332 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
333 1436, 1500, 0, 768, 769, 772, 800, 0,
334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
335 /* 0x29 - 1400x1050@60Hz RB */
336 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
337 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
339 /* 0x2a - 1400x1050@60Hz */
340 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
341 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
342 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
343 /* 0x2b - 1400x1050@75Hz */
344 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
345 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
346 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
347 /* 0x2c - 1400x1050@85Hz */
348 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
349 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
350 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
351 /* 0x2d - 1400x1050@120Hz RB */
352 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
353 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
355 /* 0x2e - 1440x900@60Hz RB */
356 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
357 1520, 1600, 0, 900, 903, 909, 926, 0,
358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
359 /* 0x2f - 1440x900@60Hz */
360 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
361 1672, 1904, 0, 900, 903, 909, 934, 0,
362 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
363 /* 0x30 - 1440x900@75Hz */
364 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
365 1688, 1936, 0, 900, 903, 909, 942, 0,
366 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
367 /* 0x31 - 1440x900@85Hz */
368 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
369 1696, 1952, 0, 900, 903, 909, 948, 0,
370 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
371 /* 0x32 - 1440x900@120Hz RB */
372 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
373 1520, 1600, 0, 900, 903, 909, 953, 0,
374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
375 /* 0x53 - 1600x900@60Hz */
376 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
377 1704, 1800, 0, 900, 901, 904, 1000, 0,
378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
379 /* 0x33 - 1600x1200@60Hz */
380 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
381 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
382 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
383 /* 0x34 - 1600x1200@65Hz */
384 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
385 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
386 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
387 /* 0x35 - 1600x1200@70Hz */
388 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
389 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
391 /* 0x36 - 1600x1200@75Hz */
392 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
393 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
395 /* 0x37 - 1600x1200@85Hz */
396 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
397 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
399 /* 0x38 - 1600x1200@120Hz RB */
400 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
401 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
403 /* 0x39 - 1680x1050@60Hz RB */
404 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
405 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
407 /* 0x3a - 1680x1050@60Hz */
408 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
409 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
410 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
411 /* 0x3b - 1680x1050@75Hz */
412 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
413 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
414 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
415 /* 0x3c - 1680x1050@85Hz */
416 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
417 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
418 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
419 /* 0x3d - 1680x1050@120Hz RB */
420 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
421 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
423 /* 0x3e - 1792x1344@60Hz */
424 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
425 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
427 /* 0x3f - 1792x1344@75Hz */
428 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
429 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
430 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
431 /* 0x40 - 1792x1344@120Hz RB */
432 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
433 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
434 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
435 /* 0x41 - 1856x1392@60Hz */
436 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
437 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
439 /* 0x42 - 1856x1392@75Hz */
440 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
441 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
442 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
443 /* 0x43 - 1856x1392@120Hz RB */
444 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
445 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
447 /* 0x52 - 1920x1080@60Hz */
448 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
449 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
450 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
451 /* 0x44 - 1920x1200@60Hz RB */
452 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
453 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
455 /* 0x45 - 1920x1200@60Hz */
456 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
457 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
458 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
459 /* 0x46 - 1920x1200@75Hz */
460 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
461 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
462 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
463 /* 0x47 - 1920x1200@85Hz */
464 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
465 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
466 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
467 /* 0x48 - 1920x1200@120Hz RB */
468 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
469 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
471 /* 0x49 - 1920x1440@60Hz */
472 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
473 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
474 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
475 /* 0x4a - 1920x1440@75Hz */
476 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
477 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
478 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
479 /* 0x4b - 1920x1440@120Hz RB */
480 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
481 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
483 /* 0x54 - 2048x1152@60Hz */
484 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
485 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
487 /* 0x4c - 2560x1600@60Hz RB */
488 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
489 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
491 /* 0x4d - 2560x1600@60Hz */
492 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
493 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
495 /* 0x4e - 2560x1600@75Hz */
496 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
497 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
498 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
499 /* 0x4f - 2560x1600@85Hz */
500 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
501 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
502 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
503 /* 0x50 - 2560x1600@120Hz RB */
504 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
505 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
507 /* 0x57 - 4096x2160@60Hz RB */
508 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
509 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
511 /* 0x58 - 4096x2160@59.94Hz RB */
512 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
513 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
518 * These more or less come from the DMT spec. The 720x400 modes are
519 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
520 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
521 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
524 * The DMT modes have been fact-checked; the rest are mild guesses.
526 static const struct drm_display_mode edid_est_modes[] = {
527 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
528 968, 1056, 0, 600, 601, 605, 628, 0,
529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
530 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
531 896, 1024, 0, 600, 601, 603, 625, 0,
532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
533 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
534 720, 840, 0, 480, 481, 484, 500, 0,
535 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
536 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
537 704, 832, 0, 480, 489, 491, 520, 0,
538 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
539 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
540 768, 864, 0, 480, 483, 486, 525, 0,
541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
542 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656,
543 752, 800, 0, 480, 490, 492, 525, 0,
544 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
545 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
546 846, 900, 0, 400, 421, 423, 449, 0,
547 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
548 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
549 846, 900, 0, 400, 412, 414, 449, 0,
550 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
551 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
552 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
554 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040,
555 1136, 1312, 0, 768, 769, 772, 800, 0,
556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
557 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
558 1184, 1328, 0, 768, 771, 777, 806, 0,
559 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
560 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
561 1184, 1344, 0, 768, 771, 777, 806, 0,
562 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
563 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
564 1208, 1264, 0, 768, 768, 776, 817, 0,
565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
566 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
567 928, 1152, 0, 624, 625, 628, 667, 0,
568 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
569 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
570 896, 1056, 0, 600, 601, 604, 625, 0,
571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
572 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
573 976, 1040, 0, 600, 637, 643, 666, 0,
574 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
575 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
576 1344, 1600, 0, 864, 865, 868, 900, 0,
577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
587 static const struct minimode est3_modes[] = {
595 { 1024, 768, 85, 0 },
596 { 1152, 864, 75, 0 },
598 { 1280, 768, 60, 1 },
599 { 1280, 768, 60, 0 },
600 { 1280, 768, 75, 0 },
601 { 1280, 768, 85, 0 },
602 { 1280, 960, 60, 0 },
603 { 1280, 960, 85, 0 },
604 { 1280, 1024, 60, 0 },
605 { 1280, 1024, 85, 0 },
607 { 1360, 768, 60, 0 },
608 { 1440, 900, 60, 1 },
609 { 1440, 900, 60, 0 },
610 { 1440, 900, 75, 0 },
611 { 1440, 900, 85, 0 },
612 { 1400, 1050, 60, 1 },
613 { 1400, 1050, 60, 0 },
614 { 1400, 1050, 75, 0 },
616 { 1400, 1050, 85, 0 },
617 { 1680, 1050, 60, 1 },
618 { 1680, 1050, 60, 0 },
619 { 1680, 1050, 75, 0 },
620 { 1680, 1050, 85, 0 },
621 { 1600, 1200, 60, 0 },
622 { 1600, 1200, 65, 0 },
623 { 1600, 1200, 70, 0 },
625 { 1600, 1200, 75, 0 },
626 { 1600, 1200, 85, 0 },
627 { 1792, 1344, 60, 0 },
628 { 1792, 1344, 75, 0 },
629 { 1856, 1392, 60, 0 },
630 { 1856, 1392, 75, 0 },
631 { 1920, 1200, 60, 1 },
632 { 1920, 1200, 60, 0 },
634 { 1920, 1200, 75, 0 },
635 { 1920, 1200, 85, 0 },
636 { 1920, 1440, 60, 0 },
637 { 1920, 1440, 75, 0 },
640 static const struct minimode extra_modes[] = {
641 { 1024, 576, 60, 0 },
642 { 1366, 768, 60, 0 },
643 { 1600, 900, 60, 0 },
644 { 1680, 945, 60, 0 },
645 { 1920, 1080, 60, 0 },
646 { 2048, 1152, 60, 0 },
647 { 2048, 1536, 60, 0 },
651 * Probably taken from CEA-861 spec.
652 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
654 * Index using the VIC.
656 static const struct drm_display_mode edid_cea_modes[] = {
657 /* 0 - dummy, VICs start at 1 */
659 /* 1 - 640x480@60Hz */
660 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
661 752, 800, 0, 480, 490, 492, 525, 0,
662 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
663 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
664 /* 2 - 720x480@60Hz */
665 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
666 798, 858, 0, 480, 489, 495, 525, 0,
667 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
668 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
669 /* 3 - 720x480@60Hz */
670 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
671 798, 858, 0, 480, 489, 495, 525, 0,
672 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
673 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
674 /* 4 - 1280x720@60Hz */
675 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
676 1430, 1650, 0, 720, 725, 730, 750, 0,
677 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
678 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
679 /* 5 - 1920x1080i@60Hz */
680 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
681 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
682 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
683 DRM_MODE_FLAG_INTERLACE),
684 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
685 /* 6 - 720(1440)x480i@60Hz */
686 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
687 801, 858, 0, 480, 488, 494, 525, 0,
688 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
689 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
690 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
691 /* 7 - 720(1440)x480i@60Hz */
692 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
693 801, 858, 0, 480, 488, 494, 525, 0,
694 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
695 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
696 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
697 /* 8 - 720(1440)x240@60Hz */
698 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
699 801, 858, 0, 240, 244, 247, 262, 0,
700 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
701 DRM_MODE_FLAG_DBLCLK),
702 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
703 /* 9 - 720(1440)x240@60Hz */
704 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
705 801, 858, 0, 240, 244, 247, 262, 0,
706 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
707 DRM_MODE_FLAG_DBLCLK),
708 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
709 /* 10 - 2880x480i@60Hz */
710 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
711 3204, 3432, 0, 480, 488, 494, 525, 0,
712 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
713 DRM_MODE_FLAG_INTERLACE),
714 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
715 /* 11 - 2880x480i@60Hz */
716 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
717 3204, 3432, 0, 480, 488, 494, 525, 0,
718 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
719 DRM_MODE_FLAG_INTERLACE),
720 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
721 /* 12 - 2880x240@60Hz */
722 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
723 3204, 3432, 0, 240, 244, 247, 262, 0,
724 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
725 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
726 /* 13 - 2880x240@60Hz */
727 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
728 3204, 3432, 0, 240, 244, 247, 262, 0,
729 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
730 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
731 /* 14 - 1440x480@60Hz */
732 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
733 1596, 1716, 0, 480, 489, 495, 525, 0,
734 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
735 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
736 /* 15 - 1440x480@60Hz */
737 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
738 1596, 1716, 0, 480, 489, 495, 525, 0,
739 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
740 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
741 /* 16 - 1920x1080@60Hz */
742 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
743 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
744 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
745 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
746 /* 17 - 720x576@50Hz */
747 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
748 796, 864, 0, 576, 581, 586, 625, 0,
749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
750 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
751 /* 18 - 720x576@50Hz */
752 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
753 796, 864, 0, 576, 581, 586, 625, 0,
754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
755 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
756 /* 19 - 1280x720@50Hz */
757 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
758 1760, 1980, 0, 720, 725, 730, 750, 0,
759 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
760 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
761 /* 20 - 1920x1080i@50Hz */
762 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
763 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
764 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
765 DRM_MODE_FLAG_INTERLACE),
766 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
767 /* 21 - 720(1440)x576i@50Hz */
768 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
769 795, 864, 0, 576, 580, 586, 625, 0,
770 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
771 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
772 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
773 /* 22 - 720(1440)x576i@50Hz */
774 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
775 795, 864, 0, 576, 580, 586, 625, 0,
776 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
777 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
778 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
779 /* 23 - 720(1440)x288@50Hz */
780 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
781 795, 864, 0, 288, 290, 293, 312, 0,
782 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
783 DRM_MODE_FLAG_DBLCLK),
784 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
785 /* 24 - 720(1440)x288@50Hz */
786 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
787 795, 864, 0, 288, 290, 293, 312, 0,
788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
789 DRM_MODE_FLAG_DBLCLK),
790 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
791 /* 25 - 2880x576i@50Hz */
792 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
793 3180, 3456, 0, 576, 580, 586, 625, 0,
794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
795 DRM_MODE_FLAG_INTERLACE),
796 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
797 /* 26 - 2880x576i@50Hz */
798 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
799 3180, 3456, 0, 576, 580, 586, 625, 0,
800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
801 DRM_MODE_FLAG_INTERLACE),
802 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
803 /* 27 - 2880x288@50Hz */
804 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
805 3180, 3456, 0, 288, 290, 293, 312, 0,
806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
807 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
808 /* 28 - 2880x288@50Hz */
809 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
810 3180, 3456, 0, 288, 290, 293, 312, 0,
811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
812 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
813 /* 29 - 1440x576@50Hz */
814 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
815 1592, 1728, 0, 576, 581, 586, 625, 0,
816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
817 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
818 /* 30 - 1440x576@50Hz */
819 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
820 1592, 1728, 0, 576, 581, 586, 625, 0,
821 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
822 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
823 /* 31 - 1920x1080@50Hz */
824 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
825 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
826 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
827 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
828 /* 32 - 1920x1080@24Hz */
829 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
830 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
831 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
832 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
833 /* 33 - 1920x1080@25Hz */
834 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
835 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
837 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
838 /* 34 - 1920x1080@30Hz */
839 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
840 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
841 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
842 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
843 /* 35 - 2880x480@60Hz */
844 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
845 3192, 3432, 0, 480, 489, 495, 525, 0,
846 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
847 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
848 /* 36 - 2880x480@60Hz */
849 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
850 3192, 3432, 0, 480, 489, 495, 525, 0,
851 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
852 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
853 /* 37 - 2880x576@50Hz */
854 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
855 3184, 3456, 0, 576, 581, 586, 625, 0,
856 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
857 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
858 /* 38 - 2880x576@50Hz */
859 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
860 3184, 3456, 0, 576, 581, 586, 625, 0,
861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
862 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
863 /* 39 - 1920x1080i@50Hz */
864 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
865 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
866 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
867 DRM_MODE_FLAG_INTERLACE),
868 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
869 /* 40 - 1920x1080i@100Hz */
870 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
871 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
872 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
873 DRM_MODE_FLAG_INTERLACE),
874 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
875 /* 41 - 1280x720@100Hz */
876 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
877 1760, 1980, 0, 720, 725, 730, 750, 0,
878 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
879 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
880 /* 42 - 720x576@100Hz */
881 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
882 796, 864, 0, 576, 581, 586, 625, 0,
883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
884 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
885 /* 43 - 720x576@100Hz */
886 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
887 796, 864, 0, 576, 581, 586, 625, 0,
888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
889 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
890 /* 44 - 720(1440)x576i@100Hz */
891 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
892 795, 864, 0, 576, 580, 586, 625, 0,
893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
894 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
895 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
896 /* 45 - 720(1440)x576i@100Hz */
897 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
898 795, 864, 0, 576, 580, 586, 625, 0,
899 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
900 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
901 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
902 /* 46 - 1920x1080i@120Hz */
903 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
904 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
905 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
906 DRM_MODE_FLAG_INTERLACE),
907 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
908 /* 47 - 1280x720@120Hz */
909 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
910 1430, 1650, 0, 720, 725, 730, 750, 0,
911 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
912 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
913 /* 48 - 720x480@120Hz */
914 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
915 798, 858, 0, 480, 489, 495, 525, 0,
916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
917 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
918 /* 49 - 720x480@120Hz */
919 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
920 798, 858, 0, 480, 489, 495, 525, 0,
921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
922 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
923 /* 50 - 720(1440)x480i@120Hz */
924 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
925 801, 858, 0, 480, 488, 494, 525, 0,
926 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
927 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
928 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
929 /* 51 - 720(1440)x480i@120Hz */
930 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
931 801, 858, 0, 480, 488, 494, 525, 0,
932 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
933 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
934 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
935 /* 52 - 720x576@200Hz */
936 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
937 796, 864, 0, 576, 581, 586, 625, 0,
938 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
939 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
940 /* 53 - 720x576@200Hz */
941 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
942 796, 864, 0, 576, 581, 586, 625, 0,
943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
944 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
945 /* 54 - 720(1440)x576i@200Hz */
946 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
947 795, 864, 0, 576, 580, 586, 625, 0,
948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
949 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
950 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
951 /* 55 - 720(1440)x576i@200Hz */
952 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
953 795, 864, 0, 576, 580, 586, 625, 0,
954 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
955 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
956 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
957 /* 56 - 720x480@240Hz */
958 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
959 798, 858, 0, 480, 489, 495, 525, 0,
960 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
961 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
962 /* 57 - 720x480@240Hz */
963 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
964 798, 858, 0, 480, 489, 495, 525, 0,
965 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
966 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
967 /* 58 - 720(1440)x480i@240 */
968 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
969 801, 858, 0, 480, 488, 494, 525, 0,
970 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
971 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
972 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
973 /* 59 - 720(1440)x480i@240 */
974 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
975 801, 858, 0, 480, 488, 494, 525, 0,
976 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
977 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
978 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
979 /* 60 - 1280x720@24Hz */
980 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
981 3080, 3300, 0, 720, 725, 730, 750, 0,
982 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
983 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
984 /* 61 - 1280x720@25Hz */
985 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
986 3740, 3960, 0, 720, 725, 730, 750, 0,
987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
988 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
989 /* 62 - 1280x720@30Hz */
990 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
991 3080, 3300, 0, 720, 725, 730, 750, 0,
992 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
993 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
994 /* 63 - 1920x1080@120Hz */
995 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
996 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
997 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
998 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
999 /* 64 - 1920x1080@100Hz */
1000 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1001 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
1002 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1003 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1004 /* 65 - 1280x720@24Hz */
1005 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1006 3080, 3300, 0, 720, 725, 730, 750, 0,
1007 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1008 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1009 /* 66 - 1280x720@25Hz */
1010 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1011 3740, 3960, 0, 720, 725, 730, 750, 0,
1012 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1013 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1014 /* 67 - 1280x720@30Hz */
1015 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1016 3080, 3300, 0, 720, 725, 730, 750, 0,
1017 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1018 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1019 /* 68 - 1280x720@50Hz */
1020 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1021 1760, 1980, 0, 720, 725, 730, 750, 0,
1022 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1023 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1024 /* 69 - 1280x720@60Hz */
1025 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1026 1430, 1650, 0, 720, 725, 730, 750, 0,
1027 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1028 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1029 /* 70 - 1280x720@100Hz */
1030 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1031 1760, 1980, 0, 720, 725, 730, 750, 0,
1032 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1033 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1034 /* 71 - 1280x720@120Hz */
1035 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1036 1430, 1650, 0, 720, 725, 730, 750, 0,
1037 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1038 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1039 /* 72 - 1920x1080@24Hz */
1040 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1041 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1043 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1044 /* 73 - 1920x1080@25Hz */
1045 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1046 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1048 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1049 /* 74 - 1920x1080@30Hz */
1050 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1051 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1053 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1054 /* 75 - 1920x1080@50Hz */
1055 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1056 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1058 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1059 /* 76 - 1920x1080@60Hz */
1060 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1061 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1063 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1064 /* 77 - 1920x1080@100Hz */
1065 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1066 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1068 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1069 /* 78 - 1920x1080@120Hz */
1070 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1071 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1073 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1074 /* 79 - 1680x720@24Hz */
1075 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1076 3080, 3300, 0, 720, 725, 730, 750, 0,
1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1078 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1079 /* 80 - 1680x720@25Hz */
1080 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1081 2948, 3168, 0, 720, 725, 730, 750, 0,
1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1083 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1084 /* 81 - 1680x720@30Hz */
1085 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1086 2420, 2640, 0, 720, 725, 730, 750, 0,
1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1088 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1089 /* 82 - 1680x720@50Hz */
1090 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1091 1980, 2200, 0, 720, 725, 730, 750, 0,
1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1093 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1094 /* 83 - 1680x720@60Hz */
1095 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1096 1980, 2200, 0, 720, 725, 730, 750, 0,
1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1098 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1099 /* 84 - 1680x720@100Hz */
1100 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1101 1780, 2000, 0, 720, 725, 730, 825, 0,
1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1103 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1104 /* 85 - 1680x720@120Hz */
1105 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1106 1780, 2000, 0, 720, 725, 730, 825, 0,
1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1108 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1109 /* 86 - 2560x1080@24Hz */
1110 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1111 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1113 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1114 /* 87 - 2560x1080@25Hz */
1115 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1116 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1118 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1119 /* 88 - 2560x1080@30Hz */
1120 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1121 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1123 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1124 /* 89 - 2560x1080@50Hz */
1125 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1126 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1128 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1129 /* 90 - 2560x1080@60Hz */
1130 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1131 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1133 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1134 /* 91 - 2560x1080@100Hz */
1135 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1136 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1138 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1139 /* 92 - 2560x1080@120Hz */
1140 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1141 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1143 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1144 /* 93 - 3840x2160p@24Hz 16:9 */
1145 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1146 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1148 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9,},
1149 /* 94 - 3840x2160p@25Hz 16:9 */
1150 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1151 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1153 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9},
1154 /* 95 - 3840x2160p@30Hz 16:9 */
1155 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1156 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1158 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9},
1159 /* 96 - 3840x2160p@50Hz 16:9 */
1160 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1161 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1163 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9},
1164 /* 97 - 3840x2160p@60Hz 16:9 */
1165 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1166 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1168 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9},
1169 /* 98 - 4096x2160p@24Hz 256:135 */
1170 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1171 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1173 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135},
1174 /* 99 - 4096x2160p@25Hz 256:135 */
1175 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1176 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1178 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135},
1179 /* 100 - 4096x2160p@30Hz 256:135 */
1180 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1181 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1183 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135},
1184 /* 101 - 4096x2160p@50Hz 256:135 */
1185 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1186 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1188 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135},
1189 /* 102 - 4096x2160p@60Hz 256:135 */
1190 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1191 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1193 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135},
1194 /* 103 - 3840x2160p@24Hz 64:27 */
1195 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1196 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1198 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27},
1199 /* 104 - 3840x2160p@25Hz 64:27 */
1200 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1201 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1203 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27},
1204 /* 105 - 3840x2160p@30Hz 64:27 */
1205 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1206 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1208 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27},
1209 /* 106 - 3840x2160p@50Hz 64:27 */
1210 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1211 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1213 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27},
1214 /* 107 - 3840x2160p@60Hz 64:27 */
1215 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1216 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1218 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27},
1222 * HDMI 1.4 4k modes. Index using the VIC.
1224 static const struct drm_display_mode edid_4k_modes[] = {
1225 /* 0 - dummy, VICs start at 1 */
1227 /* 1 - 3840x2160@30Hz */
1228 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1229 3840, 4016, 4104, 4400, 0,
1230 2160, 2168, 2178, 2250, 0,
1231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1233 /* 2 - 3840x2160@25Hz */
1234 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1235 3840, 4896, 4984, 5280, 0,
1236 2160, 2168, 2178, 2250, 0,
1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1239 /* 3 - 3840x2160@24Hz */
1240 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1241 3840, 5116, 5204, 5500, 0,
1242 2160, 2168, 2178, 2250, 0,
1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1245 /* 4 - 4096x2160@24Hz (SMPTE) */
1246 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1247 4096, 5116, 5204, 5500, 0,
1248 2160, 2168, 2178, 2250, 0,
1249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1253 /*** DDC fetch and block validation ***/
1255 static const u8 edid_header[] = {
1256 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1260 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1261 * @raw_edid: pointer to raw base EDID block
1263 * Sanity check the header of the base EDID block.
1265 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1267 int drm_edid_header_is_valid(const u8 *raw_edid)
1271 for (i = 0; i < sizeof(edid_header); i++)
1272 if (raw_edid[i] == edid_header[i])
1277 EXPORT_SYMBOL(drm_edid_header_is_valid);
1279 static int edid_fixup __read_mostly = 6;
1280 module_param_named(edid_fixup, edid_fixup, int, 0400);
1281 MODULE_PARM_DESC(edid_fixup,
1282 "Minimum number of valid EDID header bytes (0-8, default 6)");
1284 static void drm_get_displayid(struct drm_connector *connector,
1287 static int drm_edid_block_checksum(const u8 *raw_edid)
1291 for (i = 0; i < EDID_LENGTH; i++)
1292 csum += raw_edid[i];
1297 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1299 if (memchr_inv(in_edid, 0, length))
1306 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1307 * @raw_edid: pointer to raw EDID block
1308 * @block: type of block to validate (0 for base, extension otherwise)
1309 * @print_bad_edid: if true, dump bad EDID blocks to the console
1310 * @edid_corrupt: if true, the header or checksum is invalid
1312 * Validate a base or extension EDID block and optionally dump bad blocks to
1315 * Return: True if the block is valid, false otherwise.
1317 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1321 struct edid *edid = (struct edid *)raw_edid;
1323 if (WARN_ON(!raw_edid))
1326 if (edid_fixup > 8 || edid_fixup < 0)
1330 int score = drm_edid_header_is_valid(raw_edid);
1333 *edid_corrupt = false;
1334 } else if (score >= edid_fixup) {
1335 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1336 * The corrupt flag needs to be set here otherwise, the
1337 * fix-up code here will correct the problem, the
1338 * checksum is correct and the test fails
1341 *edid_corrupt = true;
1342 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1343 memcpy(raw_edid, edid_header, sizeof(edid_header));
1346 *edid_corrupt = true;
1351 csum = drm_edid_block_checksum(raw_edid);
1353 if (print_bad_edid) {
1354 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
1358 *edid_corrupt = true;
1360 /* allow CEA to slide through, switches mangle this */
1361 if (raw_edid[0] != 0x02)
1365 /* per-block-type checks */
1366 switch (raw_edid[0]) {
1368 if (edid->version != 1) {
1369 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
1373 if (edid->revision > 4)
1374 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1384 if (print_bad_edid) {
1385 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1386 printk(KERN_ERR "EDID block is all zeroes\n");
1388 printk(KERN_ERR "Raw EDID:\n");
1389 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1,
1390 raw_edid, EDID_LENGTH, false);
1395 EXPORT_SYMBOL(drm_edid_block_valid);
1398 * drm_edid_is_valid - sanity check EDID data
1401 * Sanity-check an entire EDID record (including extensions)
1403 * Return: True if the EDID data is valid, false otherwise.
1405 bool drm_edid_is_valid(struct edid *edid)
1408 u8 *raw = (u8 *)edid;
1413 for (i = 0; i <= edid->extensions; i++)
1414 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1419 EXPORT_SYMBOL(drm_edid_is_valid);
1421 #define DDC_SEGMENT_ADDR 0x30
1423 * drm_do_probe_ddc_edid() - get EDID information via I2C
1424 * @data: I2C device adapter
1425 * @buf: EDID data buffer to be filled
1426 * @block: 128 byte EDID block to start fetching from
1427 * @len: EDID data buffer length to fetch
1429 * Try to fetch EDID information by calling I2C driver functions.
1431 * Return: 0 on success or -1 on failure.
1434 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1436 struct i2c_adapter *adapter = data;
1437 unsigned char start = block * EDID_LENGTH;
1438 unsigned char segment = block >> 1;
1439 unsigned char xfers = segment ? 3 : 2;
1440 int ret, retries = 5;
1443 * The core I2C driver will automatically retry the transfer if the
1444 * adapter reports EAGAIN. However, we find that bit-banging transfers
1445 * are susceptible to errors under a heavily loaded machine and
1446 * generate spurious NAKs and timeouts. Retrying the transfer
1447 * of the individual block a few times seems to overcome this.
1450 struct i2c_msg msgs[] = {
1452 .addr = DDC_SEGMENT_ADDR,
1470 * Avoid sending the segment addr to not upset non-compliant
1473 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1475 if (ret == -ENXIO) {
1476 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1480 } while (ret != xfers && --retries);
1482 return ret == xfers ? 0 : -1;
1486 * drm_do_get_edid - get EDID data using a custom EDID block read function
1487 * @connector: connector we're probing
1488 * @get_edid_block: EDID block read function
1489 * @data: private data passed to the block read function
1491 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1492 * exposes a different interface to read EDID blocks this function can be used
1493 * to get EDID data using a custom block read function.
1495 * As in the general case the DDC bus is accessible by the kernel at the I2C
1496 * level, drivers must make all reasonable efforts to expose it as an I2C
1497 * adapter and use drm_get_edid() instead of abusing this function.
1499 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1501 struct edid *drm_do_get_edid(struct drm_connector *connector,
1502 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1506 int i, j = 0, valid_extensions = 0;
1508 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS);
1510 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1513 /* base block fetch */
1514 for (i = 0; i < 4; i++) {
1515 if (get_edid_block(data, block, 0, EDID_LENGTH))
1517 if (drm_edid_block_valid(block, 0, print_bad_edid,
1518 &connector->edid_corrupt))
1520 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) {
1521 connector->null_edid_counter++;
1528 /* if there's no extensions, we're done */
1529 if (block[0x7e] == 0)
1530 return (struct edid *)block;
1532 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL);
1537 for (j = 1; j <= block[0x7e]; j++) {
1538 for (i = 0; i < 4; i++) {
1539 if (get_edid_block(data,
1540 block + (valid_extensions + 1) * EDID_LENGTH,
1543 if (drm_edid_block_valid(block + (valid_extensions + 1)
1552 if (i == 4 && print_bad_edid) {
1553 dev_warn(connector->dev->dev,
1554 "%s: Ignoring invalid EDID block %d.\n",
1555 connector->name, j);
1557 connector->bad_edid_counter++;
1561 if (valid_extensions != block[0x7e]) {
1562 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
1563 block[0x7e] = valid_extensions;
1564 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1570 return (struct edid *)block;
1573 if (print_bad_edid) {
1574 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n",
1575 connector->name, j);
1577 connector->bad_edid_counter++;
1583 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1586 * drm_probe_ddc() - probe DDC presence
1587 * @adapter: I2C adapter to probe
1589 * Return: True on success, false on failure.
1592 drm_probe_ddc(struct i2c_adapter *adapter)
1596 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1598 EXPORT_SYMBOL(drm_probe_ddc);
1601 * drm_get_edid - get EDID data, if available
1602 * @connector: connector we're probing
1603 * @adapter: I2C adapter to use for DDC
1605 * Poke the given I2C channel to grab EDID data if possible. If found,
1606 * attach it to the connector.
1608 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1610 struct edid *drm_get_edid(struct drm_connector *connector,
1611 struct i2c_adapter *adapter)
1615 if (!drm_probe_ddc(adapter))
1618 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1620 drm_get_displayid(connector, edid);
1623 EXPORT_SYMBOL(drm_get_edid);
1626 * drm_edid_duplicate - duplicate an EDID and the extensions
1627 * @edid: EDID to duplicate
1629 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1631 struct edid *drm_edid_duplicate(const struct edid *edid)
1633 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1635 EXPORT_SYMBOL(drm_edid_duplicate);
1637 /*** EDID parsing ***/
1640 * edid_vendor - match a string against EDID's obfuscated vendor field
1641 * @edid: EDID to match
1642 * @vendor: vendor string
1644 * Returns true if @vendor is in @edid, false otherwise
1646 static bool edid_vendor(struct edid *edid, char *vendor)
1648 char edid_vendor[3];
1650 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1651 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1652 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1653 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1655 return !strncmp(edid_vendor, vendor, 3);
1659 * edid_get_quirks - return quirk flags for a given EDID
1660 * @edid: EDID to process
1662 * This tells subsequent routines what fixes they need to apply.
1664 static u32 edid_get_quirks(struct edid *edid)
1666 struct edid_quirk *quirk;
1669 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1670 quirk = &edid_quirk_list[i];
1672 if (edid_vendor(edid, quirk->vendor) &&
1673 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1674 return quirk->quirks;
1680 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1681 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1684 * edid_fixup_preferred - set preferred modes based on quirk list
1685 * @connector: has mode list to fix up
1686 * @quirks: quirks list
1688 * Walk the mode list for @connector, clearing the preferred status
1689 * on existing modes and setting it anew for the right mode ala @quirks.
1691 static void edid_fixup_preferred(struct drm_connector *connector,
1694 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1695 int target_refresh = 0;
1696 int cur_vrefresh, preferred_vrefresh;
1698 if (list_empty(&connector->probed_modes))
1701 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1702 target_refresh = 60;
1703 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1704 target_refresh = 75;
1706 preferred_mode = list_first_entry(&connector->probed_modes,
1707 struct drm_display_mode, head);
1709 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1710 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1712 if (cur_mode == preferred_mode)
1715 /* Largest mode is preferred */
1716 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1717 preferred_mode = cur_mode;
1719 cur_vrefresh = cur_mode->vrefresh ?
1720 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1721 preferred_vrefresh = preferred_mode->vrefresh ?
1722 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1723 /* At a given size, try to get closest to target refresh */
1724 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1725 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1726 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1727 preferred_mode = cur_mode;
1731 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1735 mode_is_rb(const struct drm_display_mode *mode)
1737 return (mode->htotal - mode->hdisplay == 160) &&
1738 (mode->hsync_end - mode->hdisplay == 80) &&
1739 (mode->hsync_end - mode->hsync_start == 32) &&
1740 (mode->vsync_start - mode->vdisplay == 3);
1744 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1745 * @dev: Device to duplicate against
1746 * @hsize: Mode width
1747 * @vsize: Mode height
1748 * @fresh: Mode refresh rate
1749 * @rb: Mode reduced-blanking-ness
1751 * Walk the DMT mode list looking for a match for the given parameters.
1753 * Return: A newly allocated copy of the mode, or NULL if not found.
1755 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1756 int hsize, int vsize, int fresh,
1761 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1762 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1763 if (hsize != ptr->hdisplay)
1765 if (vsize != ptr->vdisplay)
1767 if (fresh != drm_mode_vrefresh(ptr))
1769 if (rb != mode_is_rb(ptr))
1772 return drm_mode_duplicate(dev, ptr);
1777 EXPORT_SYMBOL(drm_mode_find_dmt);
1779 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1782 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1786 u8 *det_base = ext + d;
1789 for (i = 0; i < n; i++)
1790 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1794 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1796 unsigned int i, n = min((int)ext[0x02], 6);
1797 u8 *det_base = ext + 5;
1800 return; /* unknown version */
1802 for (i = 0; i < n; i++)
1803 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1807 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1810 struct edid *edid = (struct edid *)raw_edid;
1815 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1816 cb(&(edid->detailed_timings[i]), closure);
1818 for (i = 1; i <= raw_edid[0x7e]; i++) {
1819 u8 *ext = raw_edid + (i * EDID_LENGTH);
1822 cea_for_each_detailed_block(ext, cb, closure);
1825 vtb_for_each_detailed_block(ext, cb, closure);
1834 is_rb(struct detailed_timing *t, void *data)
1837 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1839 *(bool *)data = true;
1842 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1844 drm_monitor_supports_rb(struct edid *edid)
1846 if (edid->revision >= 4) {
1848 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1852 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1856 find_gtf2(struct detailed_timing *t, void *data)
1859 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1863 /* Secondary GTF curve kicks in above some break frequency */
1865 drm_gtf2_hbreak(struct edid *edid)
1868 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1869 return r ? (r[12] * 2) : 0;
1873 drm_gtf2_2c(struct edid *edid)
1876 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1877 return r ? r[13] : 0;
1881 drm_gtf2_m(struct edid *edid)
1884 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1885 return r ? (r[15] << 8) + r[14] : 0;
1889 drm_gtf2_k(struct edid *edid)
1892 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1893 return r ? r[16] : 0;
1897 drm_gtf2_2j(struct edid *edid)
1900 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1901 return r ? r[17] : 0;
1905 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1906 * @edid: EDID block to scan
1908 static int standard_timing_level(struct edid *edid)
1910 if (edid->revision >= 2) {
1911 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1913 if (drm_gtf2_hbreak(edid))
1921 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
1922 * monitors fill with ascii space (0x20) instead.
1925 bad_std_timing(u8 a, u8 b)
1927 return (a == 0x00 && b == 0x00) ||
1928 (a == 0x01 && b == 0x01) ||
1929 (a == 0x20 && b == 0x20);
1933 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
1934 * @connector: connector of for the EDID block
1935 * @edid: EDID block to scan
1936 * @t: standard timing params
1938 * Take the standard timing params (in this case width, aspect, and refresh)
1939 * and convert them into a real mode using CVT/GTF/DMT.
1941 static struct drm_display_mode *
1942 drm_mode_std(struct drm_connector *connector, struct edid *edid,
1943 struct std_timing *t)
1945 struct drm_device *dev = connector->dev;
1946 struct drm_display_mode *m, *mode = NULL;
1949 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
1950 >> EDID_TIMING_ASPECT_SHIFT;
1951 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
1952 >> EDID_TIMING_VFREQ_SHIFT;
1953 int timing_level = standard_timing_level(edid);
1955 if (bad_std_timing(t->hsize, t->vfreq_aspect))
1958 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
1959 hsize = t->hsize * 8 + 248;
1960 /* vrefresh_rate = vfreq + 60 */
1961 vrefresh_rate = vfreq + 60;
1962 /* the vdisplay is calculated based on the aspect ratio */
1963 if (aspect_ratio == 0) {
1964 if (edid->revision < 3)
1967 vsize = (hsize * 10) / 16;
1968 } else if (aspect_ratio == 1)
1969 vsize = (hsize * 3) / 4;
1970 else if (aspect_ratio == 2)
1971 vsize = (hsize * 4) / 5;
1973 vsize = (hsize * 9) / 16;
1975 /* HDTV hack, part 1 */
1976 if (vrefresh_rate == 60 &&
1977 ((hsize == 1360 && vsize == 765) ||
1978 (hsize == 1368 && vsize == 769))) {
1984 * If this connector already has a mode for this size and refresh
1985 * rate (because it came from detailed or CVT info), use that
1986 * instead. This way we don't have to guess at interlace or
1989 list_for_each_entry(m, &connector->probed_modes, head)
1990 if (m->hdisplay == hsize && m->vdisplay == vsize &&
1991 drm_mode_vrefresh(m) == vrefresh_rate)
1994 /* HDTV hack, part 2 */
1995 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
1996 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
1998 mode->hdisplay = 1366;
1999 mode->hsync_start = mode->hsync_start - 1;
2000 mode->hsync_end = mode->hsync_end - 1;
2004 /* check whether it can be found in default mode table */
2005 if (drm_monitor_supports_rb(edid)) {
2006 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2011 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2015 /* okay, generate it */
2016 switch (timing_level) {
2020 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2024 * This is potentially wrong if there's ever a monitor with
2025 * more than one ranges section, each claiming a different
2026 * secondary GTF curve. Please don't do that.
2028 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2031 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2032 drm_mode_destroy(dev, mode);
2033 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2034 vrefresh_rate, 0, 0,
2042 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2050 * EDID is delightfully ambiguous about how interlaced modes are to be
2051 * encoded. Our internal representation is of frame height, but some
2052 * HDTV detailed timings are encoded as field height.
2054 * The format list here is from CEA, in frame size. Technically we
2055 * should be checking refresh rate too. Whatever.
2058 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2059 struct detailed_pixel_timing *pt)
2062 static const struct {
2064 } cea_interlaced[] = {
2074 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2077 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2078 if ((mode->hdisplay == cea_interlaced[i].w) &&
2079 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2080 mode->vdisplay *= 2;
2081 mode->vsync_start *= 2;
2082 mode->vsync_end *= 2;
2088 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2092 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2093 * @dev: DRM device (needed to create new mode)
2095 * @timing: EDID detailed timing info
2096 * @quirks: quirks to apply
2098 * An EDID detailed timing block contains enough info for us to create and
2099 * return a new struct drm_display_mode.
2101 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2103 struct detailed_timing *timing,
2106 struct drm_display_mode *mode;
2107 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2108 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2109 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2110 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2111 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2112 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2113 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2114 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2115 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2117 /* ignore tiny modes */
2118 if (hactive < 64 || vactive < 64)
2121 if (pt->misc & DRM_EDID_PT_STEREO) {
2122 DRM_DEBUG_KMS("stereo mode not supported\n");
2125 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2126 DRM_DEBUG_KMS("composite sync not supported\n");
2129 /* it is incorrect if hsync/vsync width is zero */
2130 if (!hsync_pulse_width || !vsync_pulse_width) {
2131 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2132 "Wrong Hsync/Vsync pulse width\n");
2136 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2137 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2144 mode = drm_mode_create(dev);
2148 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2149 timing->pixel_clock = cpu_to_le16(1088);
2151 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2153 mode->hdisplay = hactive;
2154 mode->hsync_start = mode->hdisplay + hsync_offset;
2155 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2156 mode->htotal = mode->hdisplay + hblank;
2158 mode->vdisplay = vactive;
2159 mode->vsync_start = mode->vdisplay + vsync_offset;
2160 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2161 mode->vtotal = mode->vdisplay + vblank;
2163 /* Some EDIDs have bogus h/vtotal values */
2164 if (mode->hsync_end > mode->htotal)
2165 mode->htotal = mode->hsync_end + 1;
2166 if (mode->vsync_end > mode->vtotal)
2167 mode->vtotal = mode->vsync_end + 1;
2169 drm_mode_do_interlace_quirk(mode, pt);
2171 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2172 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2175 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2176 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2177 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2178 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2181 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2182 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2184 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2185 mode->width_mm *= 10;
2186 mode->height_mm *= 10;
2189 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2190 mode->width_mm = edid->width_cm * 10;
2191 mode->height_mm = edid->height_cm * 10;
2194 mode->type = DRM_MODE_TYPE_DRIVER;
2195 mode->vrefresh = drm_mode_vrefresh(mode);
2196 drm_mode_set_name(mode);
2202 mode_in_hsync_range(const struct drm_display_mode *mode,
2203 struct edid *edid, u8 *t)
2205 int hsync, hmin, hmax;
2208 if (edid->revision >= 4)
2209 hmin += ((t[4] & 0x04) ? 255 : 0);
2211 if (edid->revision >= 4)
2212 hmax += ((t[4] & 0x08) ? 255 : 0);
2213 hsync = drm_mode_hsync(mode);
2215 return (hsync <= hmax && hsync >= hmin);
2219 mode_in_vsync_range(const struct drm_display_mode *mode,
2220 struct edid *edid, u8 *t)
2222 int vsync, vmin, vmax;
2225 if (edid->revision >= 4)
2226 vmin += ((t[4] & 0x01) ? 255 : 0);
2228 if (edid->revision >= 4)
2229 vmax += ((t[4] & 0x02) ? 255 : 0);
2230 vsync = drm_mode_vrefresh(mode);
2232 return (vsync <= vmax && vsync >= vmin);
2236 range_pixel_clock(struct edid *edid, u8 *t)
2239 if (t[9] == 0 || t[9] == 255)
2242 /* 1.4 with CVT support gives us real precision, yay */
2243 if (edid->revision >= 4 && t[10] == 0x04)
2244 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2246 /* 1.3 is pathetic, so fuzz up a bit */
2247 return t[9] * 10000 + 5001;
2251 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2252 struct detailed_timing *timing)
2255 u8 *t = (u8 *)timing;
2257 if (!mode_in_hsync_range(mode, edid, t))
2260 if (!mode_in_vsync_range(mode, edid, t))
2263 if ((max_clock = range_pixel_clock(edid, t)))
2264 if (mode->clock > max_clock)
2267 /* 1.4 max horizontal check */
2268 if (edid->revision >= 4 && t[10] == 0x04)
2269 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2272 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2278 static bool valid_inferred_mode(const struct drm_connector *connector,
2279 const struct drm_display_mode *mode)
2281 const struct drm_display_mode *m;
2284 list_for_each_entry(m, &connector->probed_modes, head) {
2285 if (mode->hdisplay == m->hdisplay &&
2286 mode->vdisplay == m->vdisplay &&
2287 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2288 return false; /* duplicated */
2289 if (mode->hdisplay <= m->hdisplay &&
2290 mode->vdisplay <= m->vdisplay)
2297 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2298 struct detailed_timing *timing)
2301 struct drm_display_mode *newmode;
2302 struct drm_device *dev = connector->dev;
2304 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2305 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2306 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2307 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2309 drm_mode_probed_add(connector, newmode);
2318 /* fix up 1366x768 mode from 1368x768;
2319 * GFT/CVT can't express 1366 width which isn't dividable by 8
2321 static void fixup_mode_1366x768(struct drm_display_mode *mode)
2323 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2324 mode->hdisplay = 1366;
2325 mode->hsync_start--;
2327 drm_mode_set_name(mode);
2332 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2333 struct detailed_timing *timing)
2336 struct drm_display_mode *newmode;
2337 struct drm_device *dev = connector->dev;
2339 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2340 const struct minimode *m = &extra_modes[i];
2341 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2345 fixup_mode_1366x768(newmode);
2346 if (!mode_in_range(newmode, edid, timing) ||
2347 !valid_inferred_mode(connector, newmode)) {
2348 drm_mode_destroy(dev, newmode);
2352 drm_mode_probed_add(connector, newmode);
2360 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2361 struct detailed_timing *timing)
2364 struct drm_display_mode *newmode;
2365 struct drm_device *dev = connector->dev;
2366 bool rb = drm_monitor_supports_rb(edid);
2368 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2369 const struct minimode *m = &extra_modes[i];
2370 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2374 fixup_mode_1366x768(newmode);
2375 if (!mode_in_range(newmode, edid, timing) ||
2376 !valid_inferred_mode(connector, newmode)) {
2377 drm_mode_destroy(dev, newmode);
2381 drm_mode_probed_add(connector, newmode);
2389 do_inferred_modes(struct detailed_timing *timing, void *c)
2391 struct detailed_mode_closure *closure = c;
2392 struct detailed_non_pixel *data = &timing->data.other_data;
2393 struct detailed_data_monitor_range *range = &data->data.range;
2395 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2398 closure->modes += drm_dmt_modes_for_range(closure->connector,
2402 if (!version_greater(closure->edid, 1, 1))
2403 return; /* GTF not defined yet */
2405 switch (range->flags) {
2406 case 0x02: /* secondary gtf, XXX could do more */
2407 case 0x00: /* default gtf */
2408 closure->modes += drm_gtf_modes_for_range(closure->connector,
2412 case 0x04: /* cvt, only in 1.4+ */
2413 if (!version_greater(closure->edid, 1, 3))
2416 closure->modes += drm_cvt_modes_for_range(closure->connector,
2420 case 0x01: /* just the ranges, no formula */
2427 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2429 struct detailed_mode_closure closure = {
2430 .connector = connector,
2434 if (version_greater(edid, 1, 0))
2435 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2438 return closure.modes;
2442 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2444 int i, j, m, modes = 0;
2445 struct drm_display_mode *mode;
2446 u8 *est = ((u8 *)timing) + 5;
2448 for (i = 0; i < 6; i++) {
2449 for (j = 7; j >= 0; j--) {
2450 m = (i * 8) + (7 - j);
2451 if (m >= ARRAY_SIZE(est3_modes))
2453 if (est[i] & (1 << j)) {
2454 mode = drm_mode_find_dmt(connector->dev,
2460 drm_mode_probed_add(connector, mode);
2471 do_established_modes(struct detailed_timing *timing, void *c)
2473 struct detailed_mode_closure *closure = c;
2474 struct detailed_non_pixel *data = &timing->data.other_data;
2476 if (data->type == EDID_DETAIL_EST_TIMINGS)
2477 closure->modes += drm_est3_modes(closure->connector, timing);
2481 * add_established_modes - get est. modes from EDID and add them
2482 * @connector: connector to add mode(s) to
2483 * @edid: EDID block to scan
2485 * Each EDID block contains a bitmap of the supported "established modes" list
2486 * (defined above). Tease them out and add them to the global modes list.
2489 add_established_modes(struct drm_connector *connector, struct edid *edid)
2491 struct drm_device *dev = connector->dev;
2492 unsigned long est_bits = edid->established_timings.t1 |
2493 (edid->established_timings.t2 << 8) |
2494 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2496 struct detailed_mode_closure closure = {
2497 .connector = connector,
2501 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2502 if (est_bits & (1<<i)) {
2503 struct drm_display_mode *newmode;
2504 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2506 drm_mode_probed_add(connector, newmode);
2512 if (version_greater(edid, 1, 0))
2513 drm_for_each_detailed_block((u8 *)edid,
2514 do_established_modes, &closure);
2516 return modes + closure.modes;
2520 do_standard_modes(struct detailed_timing *timing, void *c)
2522 struct detailed_mode_closure *closure = c;
2523 struct detailed_non_pixel *data = &timing->data.other_data;
2524 struct drm_connector *connector = closure->connector;
2525 struct edid *edid = closure->edid;
2527 if (data->type == EDID_DETAIL_STD_MODES) {
2529 for (i = 0; i < 6; i++) {
2530 struct std_timing *std;
2531 struct drm_display_mode *newmode;
2533 std = &data->data.timings[i];
2534 newmode = drm_mode_std(connector, edid, std);
2536 drm_mode_probed_add(connector, newmode);
2544 * add_standard_modes - get std. modes from EDID and add them
2545 * @connector: connector to add mode(s) to
2546 * @edid: EDID block to scan
2548 * Standard modes can be calculated using the appropriate standard (DMT,
2549 * GTF or CVT. Grab them from @edid and add them to the list.
2552 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2555 struct detailed_mode_closure closure = {
2556 .connector = connector,
2560 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2561 struct drm_display_mode *newmode;
2563 newmode = drm_mode_std(connector, edid,
2564 &edid->standard_timings[i]);
2566 drm_mode_probed_add(connector, newmode);
2571 if (version_greater(edid, 1, 0))
2572 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2575 /* XXX should also look for standard codes in VTB blocks */
2577 return modes + closure.modes;
2580 static int drm_cvt_modes(struct drm_connector *connector,
2581 struct detailed_timing *timing)
2583 int i, j, modes = 0;
2584 struct drm_display_mode *newmode;
2585 struct drm_device *dev = connector->dev;
2586 struct cvt_timing *cvt;
2587 const int rates[] = { 60, 85, 75, 60, 50 };
2588 const u8 empty[3] = { 0, 0, 0 };
2590 for (i = 0; i < 4; i++) {
2591 int uninitialized_var(width), height;
2592 cvt = &(timing->data.other_data.data.cvt[i]);
2594 if (!memcmp(cvt->code, empty, 3))
2597 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2598 switch (cvt->code[1] & 0x0c) {
2600 width = height * 4 / 3;
2603 width = height * 16 / 9;
2606 width = height * 16 / 10;
2609 width = height * 15 / 9;
2613 for (j = 1; j < 5; j++) {
2614 if (cvt->code[2] & (1 << j)) {
2615 newmode = drm_cvt_mode(dev, width, height,
2619 drm_mode_probed_add(connector, newmode);
2630 do_cvt_mode(struct detailed_timing *timing, void *c)
2632 struct detailed_mode_closure *closure = c;
2633 struct detailed_non_pixel *data = &timing->data.other_data;
2635 if (data->type == EDID_DETAIL_CVT_3BYTE)
2636 closure->modes += drm_cvt_modes(closure->connector, timing);
2640 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2642 struct detailed_mode_closure closure = {
2643 .connector = connector,
2647 if (version_greater(edid, 1, 2))
2648 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2650 /* XXX should also look for CVT codes in VTB blocks */
2652 return closure.modes;
2655 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2658 do_detailed_mode(struct detailed_timing *timing, void *c)
2660 struct detailed_mode_closure *closure = c;
2661 struct drm_display_mode *newmode;
2663 if (timing->pixel_clock) {
2664 newmode = drm_mode_detailed(closure->connector->dev,
2665 closure->edid, timing,
2670 if (closure->preferred)
2671 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2674 * Detailed modes are limited to 10kHz pixel clock resolution,
2675 * so fix up anything that looks like CEA/HDMI mode, but the clock
2676 * is just slightly off.
2678 fixup_detailed_cea_mode_clock(newmode);
2680 drm_mode_probed_add(closure->connector, newmode);
2682 closure->preferred = 0;
2687 * add_detailed_modes - Add modes from detailed timings
2688 * @connector: attached connector
2689 * @edid: EDID block to scan
2690 * @quirks: quirks to apply
2693 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2696 struct detailed_mode_closure closure = {
2697 .connector = connector,
2703 if (closure.preferred && !version_greater(edid, 1, 3))
2705 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2707 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2709 return closure.modes;
2712 #define AUDIO_BLOCK 0x01
2713 #define VIDEO_BLOCK 0x02
2714 #define VENDOR_BLOCK 0x03
2715 #define SPEAKER_BLOCK 0x04
2716 #define VIDEO_CAPABILITY_BLOCK 0x07
2717 #define VIDEO_DATA_BLOCK_420 0x0E
2718 #define VIDEO_CAP_BLOCK_420 0x0F
2719 #define EDID_BASIC_AUDIO (1 << 6)
2720 #define EDID_CEA_YCRCB444 (1 << 5)
2721 #define EDID_CEA_YCRCB422 (1 << 4)
2722 #define EDID_CEA_VCDB_QS (1 << 6)
2725 * Search EDID for CEA extension block.
2727 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id)
2729 u8 *edid_ext = NULL;
2732 /* No EDID or EDID extensions */
2733 if (edid == NULL || edid->extensions == 0)
2736 /* Find CEA extension */
2737 for (i = 0; i < edid->extensions; i++) {
2738 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2739 if (edid_ext[0] == ext_id)
2743 if (i == edid->extensions)
2749 static u8 *drm_find_cea_extension(struct edid *edid)
2751 return drm_find_edid_extension(edid, CEA_EXT);
2754 static u8 *drm_find_displayid_extension(struct edid *edid)
2756 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2760 * Calculate the alternate clock for the CEA mode
2761 * (60Hz vs. 59.94Hz etc.)
2764 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2766 unsigned int clock = cea_mode->clock;
2768 if (cea_mode->vrefresh % 6 != 0)
2772 * edid_cea_modes contains the 59.94Hz
2773 * variant for 240 and 480 line modes,
2774 * and the 60Hz variant otherwise.
2776 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2777 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2779 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2784 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2785 unsigned int clock_tolerance)
2789 if (!to_match->clock)
2792 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2793 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic];
2794 unsigned int clock1, clock2;
2796 /* Check both 60Hz and 59.94Hz */
2797 clock1 = cea_mode->clock;
2798 clock2 = cea_mode_alternate_clock(cea_mode);
2800 if (abs(to_match->clock - clock1) > clock_tolerance &&
2801 abs(to_match->clock - clock2) > clock_tolerance)
2804 if (drm_mode_equal_no_clocks(to_match, cea_mode))
2812 * drm_match_cea_mode - look for a CEA mode matching given mode
2813 * @to_match: display mode
2815 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2818 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2822 if (!to_match->clock)
2825 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2826 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic];
2827 unsigned int clock1, clock2;
2829 /* Check both 60Hz and 59.94Hz */
2830 clock1 = cea_mode->clock;
2831 clock2 = cea_mode_alternate_clock(cea_mode);
2833 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2834 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2835 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode))
2840 EXPORT_SYMBOL(drm_match_cea_mode);
2842 static bool drm_valid_cea_vic(u8 vic)
2844 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2848 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2849 * the input VIC from the CEA mode list
2850 * @video_code: ID given to each of the CEA modes
2852 * Returns picture aspect ratio
2854 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2856 return edid_cea_modes[video_code].picture_aspect_ratio;
2858 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2861 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2864 * It's almost like cea_mode_alternate_clock(), we just need to add an
2865 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2869 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2871 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
2872 return hdmi_mode->clock;
2874 return cea_mode_alternate_clock(hdmi_mode);
2877 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
2878 unsigned int clock_tolerance)
2882 if (!to_match->clock)
2885 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2886 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2887 unsigned int clock1, clock2;
2889 /* Make sure to also match alternate clocks */
2890 clock1 = hdmi_mode->clock;
2891 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2893 if (abs(to_match->clock - clock1) > clock_tolerance &&
2894 abs(to_match->clock - clock2) > clock_tolerance)
2897 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
2905 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
2906 * @to_match: display mode
2908 * An HDMI mode is one defined in the HDMI vendor specific block.
2910 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
2912 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
2916 if (!to_match->clock)
2919 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2920 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2921 unsigned int clock1, clock2;
2923 /* Make sure to also match alternate clocks */
2924 clock1 = hdmi_mode->clock;
2925 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2927 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2928 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2929 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
2935 static bool drm_valid_hdmi_vic(u8 vic)
2937 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
2941 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
2943 struct drm_device *dev = connector->dev;
2944 struct drm_display_mode *mode, *tmp;
2948 /* Don't add CEA modes if the CEA extension block is missing */
2949 if (!drm_find_cea_extension(edid))
2953 * Go through all probed modes and create a new mode
2954 * with the alternate clock for certain CEA modes.
2956 list_for_each_entry(mode, &connector->probed_modes, head) {
2957 const struct drm_display_mode *cea_mode = NULL;
2958 struct drm_display_mode *newmode;
2959 u8 vic = drm_match_cea_mode(mode);
2960 unsigned int clock1, clock2;
2962 if (drm_valid_cea_vic(vic)) {
2963 cea_mode = &edid_cea_modes[vic];
2964 clock2 = cea_mode_alternate_clock(cea_mode);
2966 vic = drm_match_hdmi_mode(mode);
2967 if (drm_valid_hdmi_vic(vic)) {
2968 cea_mode = &edid_4k_modes[vic];
2969 clock2 = hdmi_mode_alternate_clock(cea_mode);
2976 clock1 = cea_mode->clock;
2978 if (clock1 == clock2)
2981 if (mode->clock != clock1 && mode->clock != clock2)
2984 newmode = drm_mode_duplicate(dev, cea_mode);
2988 /* Carry over the stereo flags */
2989 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
2992 * The current mode could be either variant. Make
2993 * sure to pick the "other" clock for the new mode.
2995 if (mode->clock != clock1)
2996 newmode->clock = clock1;
2998 newmode->clock = clock2;
3000 list_add_tail(&newmode->head, &list);
3003 list_for_each_entry_safe(mode, tmp, &list, head) {
3004 list_del(&mode->head);
3005 drm_mode_probed_add(connector, mode);
3012 static struct drm_display_mode *
3013 drm_display_mode_from_vic_index(struct drm_connector *connector,
3014 const u8 *video_db, u8 video_len,
3017 struct drm_device *dev = connector->dev;
3018 struct drm_display_mode *newmode;
3021 if (video_db == NULL || video_index >= video_len)
3024 /* CEA modes are numbered 1..127 */
3025 vic = (video_db[video_index] & 127);
3026 if (!drm_valid_cea_vic(vic))
3029 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3033 newmode->vrefresh = 0;
3039 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3043 for (i = 0; i < len; i++) {
3044 struct drm_display_mode *mode;
3045 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3047 drm_mode_probed_add(connector, mode);
3055 struct stereo_mandatory_mode {
3056 int width, height, vrefresh;
3060 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3061 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3062 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3064 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3066 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3067 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3068 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3069 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3070 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3074 stereo_match_mandatory(const struct drm_display_mode *mode,
3075 const struct stereo_mandatory_mode *stereo_mode)
3077 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3079 return mode->hdisplay == stereo_mode->width &&
3080 mode->vdisplay == stereo_mode->height &&
3081 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3082 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3085 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3087 struct drm_device *dev = connector->dev;
3088 const struct drm_display_mode *mode;
3089 struct list_head stereo_modes;
3092 INIT_LIST_HEAD(&stereo_modes);
3094 list_for_each_entry(mode, &connector->probed_modes, head) {
3095 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3096 const struct stereo_mandatory_mode *mandatory;
3097 struct drm_display_mode *new_mode;
3099 if (!stereo_match_mandatory(mode,
3100 &stereo_mandatory_modes[i]))
3103 mandatory = &stereo_mandatory_modes[i];
3104 new_mode = drm_mode_duplicate(dev, mode);
3108 new_mode->flags |= mandatory->flags;
3109 list_add_tail(&new_mode->head, &stereo_modes);
3114 list_splice_tail(&stereo_modes, &connector->probed_modes);
3119 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3121 struct drm_device *dev = connector->dev;
3122 struct drm_display_mode *newmode;
3124 if (!drm_valid_hdmi_vic(vic)) {
3125 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3129 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3133 drm_mode_probed_add(connector, newmode);
3138 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3139 const u8 *video_db, u8 video_len, u8 video_index)
3141 struct drm_display_mode *newmode;
3144 if (structure & (1 << 0)) {
3145 newmode = drm_display_mode_from_vic_index(connector, video_db,
3149 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3150 drm_mode_probed_add(connector, newmode);
3154 if (structure & (1 << 6)) {
3155 newmode = drm_display_mode_from_vic_index(connector, video_db,
3159 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3160 drm_mode_probed_add(connector, newmode);
3164 if (structure & (1 << 8)) {
3165 newmode = drm_display_mode_from_vic_index(connector, video_db,
3169 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3170 drm_mode_probed_add(connector, newmode);
3178 static int add_420_mode(struct drm_connector *connector, u8 vic)
3180 struct drm_device *dev = connector->dev;
3181 struct drm_display_mode *newmode;
3183 if (!drm_valid_cea_vic(vic))
3186 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3190 newmode->flags |= DRM_MODE_FLAG_420_ONLY;
3191 drm_mode_probed_add(connector, newmode);
3196 static int add_420_vdb_modes(struct drm_connector *connector, const u8 *svds,
3201 for (i = 0; i < svds_len; i++)
3202 modes += add_420_mode(connector, svds[i]);
3207 static int add_420_vcb_modes(struct drm_connector *connector, const u8 *svds,
3208 u8 svds_len, const u8 *video_db, u8 video_len)
3210 struct drm_display_mode *newmode = NULL;
3211 int modes = 0, i, j;
3213 for (i = 0; i < svds_len; i++) {
3216 for (j = 0; j < 8; j++) {
3217 if (mask & (1 << j)) {
3218 newmode = drm_display_mode_from_vic_index(
3219 connector, video_db, video_len,
3222 newmode->flags |= DRM_MODE_FLAG_420;
3223 drm_mode_probed_add(connector, newmode);
3233 static int add_420_vcb_modes_all(struct drm_connector *connector,
3234 const u8 *video_db, u8 video_len)
3236 struct drm_display_mode *newmode = NULL;
3239 for (i = 0; i < video_len; i++) {
3240 newmode = drm_display_mode_from_vic_index(connector, video_db,
3243 newmode->flags |= DRM_MODE_FLAG_420;
3244 drm_mode_probed_add(connector, newmode);
3252 static int do_hdmi_420_modes(struct drm_connector *connector, const u8 *vdb,
3253 u8 vdb_len, const u8 *vcb, u8 vcb_len, const u8 *video_db,
3258 if (vdb && (vdb_len > 1)) /* Add 4:2:0 modes present in EDID */
3259 modes += add_420_vdb_modes(connector, &vdb[2], vdb_len - 1);
3261 if (vcb && (vcb_len > 1)) /* Parse bit mask of supported modes */
3262 modes += add_420_vcb_modes(connector, &vcb[2], vcb_len - 1,
3263 video_db, video_len);
3264 else if (vcb) /* All modes support 4:2:0 mode */
3265 modes += add_420_vcb_modes_all(connector, video_db, video_len);
3267 DRM_DEBUG("added %d 4:2:0 modes\n", modes);
3272 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3273 * @connector: connector corresponding to the HDMI sink
3274 * @db: start of the CEA vendor specific block
3275 * @len: length of the CEA block payload, ie. one can access up to db[len]
3277 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3278 * also adds the stereo 3d modes when applicable.
3281 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3282 const u8 *video_db, u8 video_len)
3284 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3285 u8 vic_len, hdmi_3d_len = 0;
3292 /* no HDMI_Video_Present */
3293 if (!(db[8] & (1 << 5)))
3296 /* Latency_Fields_Present */
3297 if (db[8] & (1 << 7))
3300 /* I_Latency_Fields_Present */
3301 if (db[8] & (1 << 6))
3304 /* the declared length is not long enough for the 2 first bytes
3305 * of additional video format capabilities */
3306 if (len < (8 + offset + 2))
3311 if (db[8 + offset] & (1 << 7)) {
3312 modes += add_hdmi_mandatory_stereo_modes(connector);
3314 /* 3D_Multi_present */
3315 multi_present = (db[8 + offset] & 0x60) >> 5;
3319 vic_len = db[8 + offset] >> 5;
3320 hdmi_3d_len = db[8 + offset] & 0x1f;
3322 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3325 vic = db[9 + offset + i];
3326 modes += add_hdmi_mode(connector, vic);
3328 offset += 1 + vic_len;
3330 if (multi_present == 1)
3332 else if (multi_present == 2)
3337 if (len < (8 + offset + hdmi_3d_len - 1))
3340 if (hdmi_3d_len < multi_len)
3343 if (multi_present == 1 || multi_present == 2) {
3344 /* 3D_Structure_ALL */
3345 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3347 /* check if 3D_MASK is present */
3348 if (multi_present == 2)
3349 mask = (db[10 + offset] << 8) | db[11 + offset];
3353 for (i = 0; i < 16; i++) {
3354 if (mask & (1 << i))
3355 modes += add_3d_struct_modes(connector,
3362 offset += multi_len;
3364 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3366 struct drm_display_mode *newmode = NULL;
3367 unsigned int newflag = 0;
3368 bool detail_present;
3370 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3372 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3375 /* 2D_VIC_order_X */
3376 vic_index = db[8 + offset + i] >> 4;
3378 /* 3D_Structure_X */
3379 switch (db[8 + offset + i] & 0x0f) {
3381 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3384 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3388 if ((db[9 + offset + i] >> 4) == 1)
3389 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3394 newmode = drm_display_mode_from_vic_index(connector,
3400 newmode->flags |= newflag;
3401 drm_mode_probed_add(connector, newmode);
3415 cea_db_payload_len(const u8 *db)
3417 return db[0] & 0x1f;
3421 cea_db_tag(const u8 *db)
3427 cea_db_extended_tag(const u8 *db)
3433 cea_revision(const u8 *cea)
3439 cea_db_offsets(const u8 *cea, int *start, int *end)
3441 /* Data block offset in CEA extension block */
3446 if (*end < 4 || *end > 127)
3451 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3455 if (cea_db_tag(db) != VENDOR_BLOCK)
3458 if (cea_db_payload_len(db) < 5)
3461 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3463 return hdmi_id == HDMI_IEEE_OUI;
3466 static bool cea_db_is_hdmi_hf_vsdb(const u8 *db)
3470 if (cea_db_tag(db) != VENDOR_BLOCK)
3473 if (cea_db_payload_len(db) < 7)
3476 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3478 return hdmi_id == HDMI_IEEE_OUI_HF;
3481 static bool cea_db_is_hdmi_vdb420(const u8 *db)
3483 if (cea_db_tag(db) != VIDEO_CAPABILITY_BLOCK)
3486 if (cea_db_extended_tag(db) != VIDEO_DATA_BLOCK_420)
3492 static bool cea_db_is_hdmi_vcb420(const u8 *db)
3494 if (cea_db_tag(db) != VIDEO_CAPABILITY_BLOCK)
3497 if (cea_db_extended_tag(db) != VIDEO_CAP_BLOCK_420)
3503 #define for_each_cea_db(cea, i, start, end) \
3504 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3507 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3509 const u8 *cea = drm_find_cea_extension(edid);
3510 const u8 *db, *hdmi = NULL, *video = NULL, *vdb420 = NULL,
3512 u8 dbl, hdmi_len, video_len = 0, vdb420_len = 0, vcb420_len = 0;
3515 if (cea && cea_revision(cea) >= 3) {
3518 if (cea_db_offsets(cea, &start, &end))
3521 for_each_cea_db(cea, i, start, end) {
3523 dbl = cea_db_payload_len(db);
3525 if (cea_db_tag(db) == VIDEO_BLOCK) {
3528 modes += do_cea_modes(connector, video, dbl);
3530 else if (cea_db_is_hdmi_vsdb(db)) {
3533 } else if (cea_db_is_hdmi_vdb420(db)) {
3536 } else if (cea_db_is_hdmi_vcb420(db)) {
3544 * We parse the HDMI VSDB after having added the cea modes as we will
3545 * be patching their flags when the sink supports stereo 3D.
3548 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3551 if (vdb420 || vcb420)
3552 modes += do_hdmi_420_modes(connector, vdb420, vdb420_len,
3553 vcb420, vcb420_len, video, video_len);
3558 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3560 const struct drm_display_mode *cea_mode;
3561 int clock1, clock2, clock;
3566 * allow 5kHz clock difference either way to account for
3567 * the 10kHz clock resolution limit of detailed timings.
3569 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3570 if (drm_valid_cea_vic(vic)) {
3572 cea_mode = &edid_cea_modes[vic];
3573 clock1 = cea_mode->clock;
3574 clock2 = cea_mode_alternate_clock(cea_mode);
3576 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3577 if (drm_valid_hdmi_vic(vic)) {
3579 cea_mode = &edid_4k_modes[vic];
3580 clock1 = cea_mode->clock;
3581 clock2 = hdmi_mode_alternate_clock(cea_mode);
3587 /* pick whichever is closest */
3588 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3593 if (mode->clock == clock)
3596 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3597 type, vic, mode->clock, clock);
3598 mode->clock = clock;
3602 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db)
3604 u8 len = cea_db_payload_len(db);
3607 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
3608 connector->dvi_dual = db[6] & 1;
3611 connector->max_tmds_clock = db[7] * 5;
3613 connector->latency_present[0] = db[8] >> 7;
3614 connector->latency_present[1] = (db[8] >> 6) & 1;
3617 connector->video_latency[0] = db[9];
3619 connector->audio_latency[0] = db[10];
3621 connector->video_latency[1] = db[11];
3623 connector->audio_latency[1] = db[12];
3625 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
3626 "max TMDS clock %d, "
3627 "latency present %d %d, "
3628 "video latency %d %d, "
3629 "audio latency %d %d\n",
3630 connector->dvi_dual,
3631 connector->max_tmds_clock,
3632 (int) connector->latency_present[0],
3633 (int) connector->latency_present[1],
3634 connector->video_latency[0],
3635 connector->video_latency[1],
3636 connector->audio_latency[0],
3637 connector->audio_latency[1]);
3641 parse_hdmi_hf_vsdb(struct drm_connector *connector, const u8 *db)
3643 u8 len = cea_db_payload_len(db);
3649 return; /* invalid version */
3651 connector->max_tmds_char = db[5] * 5;
3652 connector->scdc_present = db[6] & (1 << 7);
3653 connector->rr_capable = db[6] & (1 << 6);
3654 connector->flags_3d = db[6] & 0x7;
3655 connector->lte_340mcsc_scramble = db[6] & (1 << 3);
3657 DRM_DEBUG_KMS("HDMI v2: max TMDS clock %d, "
3662 connector->max_tmds_char,
3663 connector->scdc_present ? "available" : "not available",
3664 connector->rr_capable ? "capable" : "not capable",
3665 connector->flags_3d,
3666 connector->lte_340mcsc_scramble ?
3667 "supported" : "not supported");
3671 monitor_name(struct detailed_timing *t, void *data)
3673 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3674 *(u8 **)data = t->data.other_data.data.str.str;
3678 * drm_edid_to_eld - build ELD from EDID
3679 * @connector: connector corresponding to the HDMI/DP sink
3680 * @edid: EDID to parse
3682 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3683 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3686 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3688 uint8_t *eld = connector->eld;
3692 int total_sad_count = 0;
3696 memset(eld, 0, sizeof(connector->eld));
3698 cea = drm_find_cea_extension(edid);
3700 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3705 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name);
3706 /* max: 13 bytes EDID, 16 bytes ELD */
3707 for (mnl = 0; name && mnl < 13; mnl++) {
3708 if (name[mnl] == 0x0a)
3710 eld[20 + mnl] = name[mnl];
3712 eld[4] = (cea[1] << 5) | mnl;
3713 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3715 eld[0] = 2 << 3; /* ELD version: 2 */
3717 eld[16] = edid->mfg_id[0];
3718 eld[17] = edid->mfg_id[1];
3719 eld[18] = edid->prod_code[0];
3720 eld[19] = edid->prod_code[1];
3722 if (cea_revision(cea) >= 3) {
3725 if (cea_db_offsets(cea, &start, &end)) {
3730 for_each_cea_db(cea, i, start, end) {
3732 dbl = cea_db_payload_len(db);
3734 switch (cea_db_tag(db)) {
3738 /* Audio Data Block, contains SADs */
3739 sad_count = min(dbl / 3, 15 - total_sad_count);
3741 memcpy(eld + 20 + mnl + total_sad_count * 3,
3742 &db[1], sad_count * 3);
3743 total_sad_count += sad_count;
3746 /* Speaker Allocation Data Block */
3751 /* HDMI Vendor-Specific Data Block */
3752 if (cea_db_is_hdmi_vsdb(db))
3753 parse_hdmi_vsdb(connector, db);
3754 /* HDMI Forum Vendor-Specific Data Block */
3755 else if (cea_db_is_hdmi_hf_vsdb(db))
3756 parse_hdmi_hf_vsdb(connector, db);
3763 eld[5] |= total_sad_count << 4;
3765 eld[DRM_ELD_BASELINE_ELD_LEN] =
3766 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3768 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3769 drm_eld_size(eld), total_sad_count);
3771 EXPORT_SYMBOL(drm_edid_to_eld);
3774 * drm_edid_to_sad - extracts SADs from EDID
3775 * @edid: EDID to parse
3776 * @sads: pointer that will be set to the extracted SADs
3778 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3780 * Note: The returned pointer needs to be freed using kfree().
3782 * Return: The number of found SADs or negative number on error.
3784 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3787 int i, start, end, dbl;
3790 cea = drm_find_cea_extension(edid);
3792 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3796 if (cea_revision(cea) < 3) {
3797 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3801 if (cea_db_offsets(cea, &start, &end)) {
3802 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3806 for_each_cea_db(cea, i, start, end) {
3809 if (cea_db_tag(db) == AUDIO_BLOCK) {
3811 dbl = cea_db_payload_len(db);
3813 count = dbl / 3; /* SAD is 3B */
3814 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3817 for (j = 0; j < count; j++) {
3818 u8 *sad = &db[1 + j * 3];
3820 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3821 (*sads)[j].channels = sad[0] & 0x7;
3822 (*sads)[j].freq = sad[1] & 0x7F;
3823 (*sads)[j].byte2 = sad[2];
3831 EXPORT_SYMBOL(drm_edid_to_sad);
3834 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3835 * @edid: EDID to parse
3836 * @sadb: pointer to the speaker block
3838 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
3840 * Note: The returned pointer needs to be freed using kfree().
3842 * Return: The number of found Speaker Allocation Blocks or negative number on
3845 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
3848 int i, start, end, dbl;
3851 cea = drm_find_cea_extension(edid);
3853 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3857 if (cea_revision(cea) < 3) {
3858 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3862 if (cea_db_offsets(cea, &start, &end)) {
3863 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3867 for_each_cea_db(cea, i, start, end) {
3868 const u8 *db = &cea[i];
3870 if (cea_db_tag(db) == SPEAKER_BLOCK) {
3871 dbl = cea_db_payload_len(db);
3873 /* Speaker Allocation Data Block */
3875 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
3886 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
3889 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
3890 * @connector: connector associated with the HDMI/DP sink
3891 * @mode: the display mode
3893 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
3894 * the sink doesn't support audio or video.
3896 int drm_av_sync_delay(struct drm_connector *connector,
3897 const struct drm_display_mode *mode)
3899 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
3902 if (!connector->latency_present[0])
3904 if (!connector->latency_present[1])
3907 a = connector->audio_latency[i];
3908 v = connector->video_latency[i];
3911 * HDMI/DP sink doesn't support audio or video?
3913 if (a == 255 || v == 255)
3917 * Convert raw EDID values to millisecond.
3918 * Treat unknown latency as 0ms.
3921 a = min(2 * (a - 1), 500);
3923 v = min(2 * (v - 1), 500);
3925 return max(v - a, 0);
3927 EXPORT_SYMBOL(drm_av_sync_delay);
3930 * drm_select_eld - select one ELD from multiple HDMI/DP sinks
3931 * @encoder: the encoder just changed display mode
3933 * It's possible for one encoder to be associated with multiple HDMI/DP sinks.
3934 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD.
3936 * Return: The connector associated with the first HDMI/DP sink that has ELD
3939 struct drm_connector *drm_select_eld(struct drm_encoder *encoder)
3941 struct drm_connector *connector;
3942 struct drm_device *dev = encoder->dev;
3944 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
3945 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3947 drm_for_each_connector(connector, dev)
3948 if (connector->encoder == encoder && connector->eld[0])
3953 EXPORT_SYMBOL(drm_select_eld);
3956 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
3957 * @edid: monitor EDID information
3959 * Parse the CEA extension according to CEA-861-B.
3961 * Return: True if the monitor is HDMI, false if not or unknown.
3963 bool drm_detect_hdmi_monitor(struct edid *edid)
3967 int start_offset, end_offset;
3969 edid_ext = drm_find_cea_extension(edid);
3973 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3977 * Because HDMI identifier is in Vendor Specific Block,
3978 * search it from all data blocks of CEA extension.
3980 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3981 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
3987 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
3990 * drm_detect_monitor_audio - check monitor audio capability
3991 * @edid: EDID block to scan
3993 * Monitor should have CEA extension block.
3994 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
3995 * audio' only. If there is any audio extension block and supported
3996 * audio format, assume at least 'basic audio' support, even if 'basic
3997 * audio' is not defined in EDID.
3999 * Return: True if the monitor supports audio, false otherwise.
4001 bool drm_detect_monitor_audio(struct edid *edid)
4005 bool has_audio = false;
4006 int start_offset, end_offset;
4008 edid_ext = drm_find_cea_extension(edid);
4012 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4015 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4019 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4022 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4023 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4025 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4026 DRM_DEBUG_KMS("CEA audio format %d\n",
4027 (edid_ext[i + j] >> 3) & 0xf);
4034 EXPORT_SYMBOL(drm_detect_monitor_audio);
4037 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
4038 * @edid: EDID block to scan
4040 * Check whether the monitor reports the RGB quantization range selection
4041 * as supported. The AVI infoframe can then be used to inform the monitor
4042 * which quantization range (full or limited) is used.
4044 * Return: True if the RGB quantization range is selectable, false otherwise.
4046 bool drm_rgb_quant_range_selectable(struct edid *edid)
4051 edid_ext = drm_find_cea_extension(edid);
4055 if (cea_db_offsets(edid_ext, &start, &end))
4058 for_each_cea_db(edid_ext, i, start, end) {
4059 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
4060 cea_db_payload_len(&edid_ext[i]) == 2) {
4061 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
4062 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
4068 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
4071 * drm_assign_hdmi_deep_color_info - detect whether monitor supports
4072 * hdmi deep color modes and update drm_display_info if so.
4073 * @edid: monitor EDID information
4074 * @info: Updated with maximum supported deep color bpc and color format
4075 * if deep color supported.
4076 * @connector: DRM connector, used only for debug output
4078 * Parse the CEA extension according to CEA-861-B.
4079 * Return true if HDMI deep color supported, false if not or unknown.
4081 static bool drm_assign_hdmi_deep_color_info(struct edid *edid,
4082 struct drm_display_info *info,
4083 struct drm_connector *connector)
4085 u8 *edid_ext, *hdmi;
4087 int start_offset, end_offset;
4088 unsigned int dc_bpc = 0;
4090 edid_ext = drm_find_cea_extension(edid);
4094 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4098 * Because HDMI identifier is in Vendor Specific Block,
4099 * search it from all data blocks of CEA extension.
4101 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4102 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) {
4103 /* HDMI supports at least 8 bpc */
4106 hdmi = &edid_ext[i];
4107 if (cea_db_payload_len(hdmi) < 6)
4110 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4112 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4113 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4117 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4119 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4120 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4124 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4126 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4127 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4132 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4133 connector->name, dc_bpc);
4137 * Deep color support mandates RGB444 support for all video
4138 * modes and forbids YCRCB422 support for all video modes per
4141 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4143 /* YCRCB444 is optional according to spec. */
4144 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4145 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4146 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4151 * Spec says that if any deep color mode is supported at all,
4152 * then deep color 36 bit must be supported.
4154 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4155 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4162 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4172 * drm_add_display_info - pull display info out if present
4174 * @info: display info (attached to connector)
4175 * @connector: connector whose edid is used to build display info
4177 * Grab any available display info and stuff it into the drm_display_info
4178 * structure that's part of the connector. Useful for tracking bpp and
4181 static void drm_add_display_info(struct edid *edid,
4182 struct drm_display_info *info,
4183 struct drm_connector *connector)
4187 info->width_mm = edid->width_cm * 10;
4188 info->height_mm = edid->height_cm * 10;
4190 /* driver figures it out in this case */
4192 info->color_formats = 0;
4194 if (edid->revision < 3)
4197 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4200 /* Get data from CEA blocks if present */
4201 edid_ext = drm_find_cea_extension(edid);
4203 info->cea_rev = edid_ext[1];
4205 /* The existence of a CEA block should imply RGB support */
4206 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4207 if (edid_ext[3] & EDID_CEA_YCRCB444)
4208 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4209 if (edid_ext[3] & EDID_CEA_YCRCB422)
4210 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4213 /* HDMI deep color modes supported? Assign to info, if so */
4214 drm_assign_hdmi_deep_color_info(edid, info, connector);
4216 /* Only defined for 1.4 with digital displays */
4217 if (edid->revision < 4)
4220 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4221 case DRM_EDID_DIGITAL_DEPTH_6:
4224 case DRM_EDID_DIGITAL_DEPTH_8:
4227 case DRM_EDID_DIGITAL_DEPTH_10:
4230 case DRM_EDID_DIGITAL_DEPTH_12:
4233 case DRM_EDID_DIGITAL_DEPTH_14:
4236 case DRM_EDID_DIGITAL_DEPTH_16:
4239 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4245 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4246 connector->name, info->bpc);
4248 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4249 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4250 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4251 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4252 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4256 * drm_add_edid_modes - add modes from EDID data, if available
4257 * @connector: connector we're probing
4260 * Add the specified modes to the connector's mode list.
4262 * Return: The number of modes added or 0 if we couldn't find any.
4264 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4272 if (!drm_edid_is_valid(edid)) {
4273 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4278 quirks = edid_get_quirks(edid);
4281 * EDID spec says modes should be preferred in this order:
4282 * - preferred detailed mode
4283 * - other detailed modes from base block
4284 * - detailed modes from extension blocks
4285 * - CVT 3-byte code modes
4286 * - standard timing codes
4287 * - established timing codes
4288 * - modes inferred from GTF or CVT range information
4290 * We get this pretty much right.
4292 * XXX order for additional mode types in extension blocks?
4294 num_modes += add_detailed_modes(connector, edid, quirks);
4295 num_modes += add_cvt_modes(connector, edid);
4296 num_modes += add_standard_modes(connector, edid);
4297 num_modes += add_established_modes(connector, edid);
4298 num_modes += add_cea_modes(connector, edid);
4299 num_modes += add_alternate_cea_modes(connector, edid);
4300 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4301 num_modes += add_inferred_modes(connector, edid);
4303 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4304 edid_fixup_preferred(connector, quirks);
4306 drm_add_display_info(edid, &connector->display_info, connector);
4308 if (quirks & EDID_QUIRK_FORCE_6BPC)
4309 connector->display_info.bpc = 6;
4311 if (quirks & EDID_QUIRK_FORCE_8BPC)
4312 connector->display_info.bpc = 8;
4314 if (quirks & EDID_QUIRK_FORCE_10BPC)
4315 connector->display_info.bpc = 10;
4317 if (quirks & EDID_QUIRK_FORCE_12BPC)
4318 connector->display_info.bpc = 12;
4322 EXPORT_SYMBOL(drm_add_edid_modes);
4325 * drm_add_modes_noedid - add modes for the connectors without EDID
4326 * @connector: connector we're probing
4327 * @hdisplay: the horizontal display limit
4328 * @vdisplay: the vertical display limit
4330 * Add the specified modes to the connector's mode list. Only when the
4331 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4333 * Return: The number of modes added or 0 if we couldn't find any.
4335 int drm_add_modes_noedid(struct drm_connector *connector,
4336 int hdisplay, int vdisplay)
4338 int i, count, num_modes = 0;
4339 struct drm_display_mode *mode;
4340 struct drm_device *dev = connector->dev;
4342 count = ARRAY_SIZE(drm_dmt_modes);
4348 for (i = 0; i < count; i++) {
4349 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4350 if (hdisplay && vdisplay) {
4352 * Only when two are valid, they will be used to check
4353 * whether the mode should be added to the mode list of
4356 if (ptr->hdisplay > hdisplay ||
4357 ptr->vdisplay > vdisplay)
4360 if (drm_mode_vrefresh(ptr) > 61)
4362 mode = drm_mode_duplicate(dev, ptr);
4364 drm_mode_probed_add(connector, mode);
4370 EXPORT_SYMBOL(drm_add_modes_noedid);
4373 * drm_set_preferred_mode - Sets the preferred mode of a connector
4374 * @connector: connector whose mode list should be processed
4375 * @hpref: horizontal resolution of preferred mode
4376 * @vpref: vertical resolution of preferred mode
4378 * Marks a mode as preferred if it matches the resolution specified by @hpref
4381 void drm_set_preferred_mode(struct drm_connector *connector,
4382 int hpref, int vpref)
4384 struct drm_display_mode *mode;
4386 list_for_each_entry(mode, &connector->probed_modes, head) {
4387 if (mode->hdisplay == hpref &&
4388 mode->vdisplay == vpref)
4389 mode->type |= DRM_MODE_TYPE_PREFERRED;
4392 EXPORT_SYMBOL(drm_set_preferred_mode);
4395 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4396 * data from a DRM display mode
4397 * @frame: HDMI AVI infoframe
4398 * @mode: DRM display mode
4399 * @is_hdmi2: Sink is HDMI 2.0 compliant
4401 * Return: 0 on success or a negative error code on failure.
4404 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4405 const struct drm_display_mode *mode,
4410 if (!frame || !mode)
4413 err = hdmi_avi_infoframe_init(frame);
4417 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4418 frame->pixel_repeat = 1;
4420 frame->video_code = drm_match_cea_mode(mode);
4423 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4424 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4425 * have to make sure we dont break HDMI 1.4 sinks.
4427 if (!is_hdmi2 && frame->video_code > 64)
4428 frame->video_code = 0;
4430 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4433 * Populate picture aspect ratio from either
4434 * user input (if specified) or from the CEA mode list.
4436 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4437 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4438 frame->picture_aspect = mode->picture_aspect_ratio;
4439 else if (frame->video_code > 0)
4440 frame->picture_aspect = drm_get_cea_aspect_ratio(
4443 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4444 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4448 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4450 static enum hdmi_3d_structure
4451 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4453 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4456 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4457 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4458 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4459 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4460 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4461 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4462 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4463 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4464 case DRM_MODE_FLAG_3D_L_DEPTH:
4465 return HDMI_3D_STRUCTURE_L_DEPTH;
4466 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4467 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4468 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4469 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4470 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4471 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4473 return HDMI_3D_STRUCTURE_INVALID;
4478 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4479 * data from a DRM display mode
4480 * @frame: HDMI vendor infoframe
4481 * @mode: DRM display mode
4483 * Note that there's is a need to send HDMI vendor infoframes only when using a
4484 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4485 * function will return -EINVAL, error that can be safely ignored.
4487 * Return: 0 on success or a negative error code on failure.
4490 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4491 const struct drm_display_mode *mode)
4497 if (!frame || !mode)
4500 vic = drm_match_hdmi_mode(mode);
4501 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4503 if (!vic && !s3d_flags)
4506 if (vic && s3d_flags)
4509 err = hdmi_vendor_infoframe_init(frame);
4516 frame->s3d_struct = s3d_structure_from_display_mode(mode);
4520 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
4522 static int drm_parse_display_id(struct drm_connector *connector,
4523 u8 *displayid, int length,
4524 bool is_edid_extension)
4526 /* if this is an EDID extension the first byte will be 0x70 */
4528 struct displayid_hdr *base;
4529 struct displayid_block *block;
4533 if (is_edid_extension)
4536 base = (struct displayid_hdr *)&displayid[idx];
4538 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4539 base->rev, base->bytes, base->prod_id, base->ext_count);
4541 if (base->bytes + 5 > length - idx)
4544 for (i = idx; i <= base->bytes + 5; i++) {
4545 csum += displayid[i];
4548 DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum);
4552 block = (struct displayid_block *)&displayid[idx + 4];
4553 DRM_DEBUG_KMS("block id %d, rev %d, len %d\n",
4554 block->tag, block->rev, block->num_bytes);
4556 switch (block->tag) {
4557 case DATA_BLOCK_TILED_DISPLAY: {
4558 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
4561 u8 tile_v_loc, tile_h_loc;
4562 u8 num_v_tile, num_h_tile;
4563 struct drm_tile_group *tg;
4565 w = tile->tile_size[0] | tile->tile_size[1] << 8;
4566 h = tile->tile_size[2] | tile->tile_size[3] << 8;
4568 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
4569 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
4570 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
4571 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
4573 connector->has_tile = true;
4574 if (tile->tile_cap & 0x80)
4575 connector->tile_is_single_monitor = true;
4577 connector->num_h_tile = num_h_tile + 1;
4578 connector->num_v_tile = num_v_tile + 1;
4579 connector->tile_h_loc = tile_h_loc;
4580 connector->tile_v_loc = tile_v_loc;
4581 connector->tile_h_size = w + 1;
4582 connector->tile_v_size = h + 1;
4584 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
4585 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
4586 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
4587 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
4588 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
4590 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
4592 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
4597 if (connector->tile_group != tg) {
4598 /* if we haven't got a pointer,
4599 take the reference, drop ref to old tile group */
4600 if (connector->tile_group) {
4601 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4603 connector->tile_group = tg;
4605 /* if same tile group, then release the ref we just took. */
4606 drm_mode_put_tile_group(connector->dev, tg);
4610 printk("unknown displayid tag %d\n", block->tag);
4616 static void drm_get_displayid(struct drm_connector *connector,
4619 void *displayid = NULL;
4621 connector->has_tile = false;
4622 displayid = drm_find_displayid_extension(edid);
4624 /* drop reference to any tile group we had */
4628 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
4631 if (!connector->has_tile)
4635 if (connector->tile_group) {
4636 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4637 connector->tile_group = NULL;
projects / firefly-linux-kernel-4.4.55.git / blob