1 /* drivers/gpu/drm/exynos/exynos7_drm_decon.c
3 * Copyright (C) 2014 Samsung Electronics Co.Ltd
5 * Akshu Agarwal <akshua@gmail.com>
6 * Ajay Kumar <ajaykumar.rs@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
15 #include <drm/exynos_drm.h>
17 #include <linux/clk.h>
18 #include <linux/component.h>
19 #include <linux/kernel.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/exynos7_decon.h>
30 #include "exynos_drm_crtc.h"
31 #include "exynos_drm_drv.h"
32 #include "exynos_drm_fbdev.h"
33 #include "exynos_drm_iommu.h"
36 * DECON stands for Display and Enhancement controller.
39 #define DECON_DEFAULT_FRAMERATE 60
40 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
44 struct decon_win_data {
47 unsigned int offset_x;
48 unsigned int offset_y;
49 unsigned int ovl_width;
50 unsigned int ovl_height;
51 unsigned int fb_width;
52 unsigned int fb_height;
54 unsigned int pixel_format;
60 struct decon_context {
62 struct drm_device *drm_dev;
63 struct exynos_drm_crtc *crtc;
69 struct decon_win_data win_data[WINDOWS_NR];
70 unsigned int default_win;
71 unsigned long irq_flags;
75 wait_queue_head_t wait_vsync_queue;
76 atomic_t wait_vsync_event;
78 struct exynos_drm_panel_info panel;
79 struct exynos_drm_display *display;
82 static const struct of_device_id decon_driver_dt_match[] = {
83 {.compatible = "samsung,exynos7-decon"},
86 MODULE_DEVICE_TABLE(of, decon_driver_dt_match);
88 static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc)
90 struct decon_context *ctx = crtc->ctx;
95 atomic_set(&ctx->wait_vsync_event, 1);
98 * wait for DECON to signal VSYNC interrupt or return after
99 * timeout which is set to 50ms (refresh rate of 20).
101 if (!wait_event_timeout(ctx->wait_vsync_queue,
102 !atomic_read(&ctx->wait_vsync_event),
104 DRM_DEBUG_KMS("vblank wait timed out.\n");
107 static void decon_clear_channel(struct decon_context *ctx)
109 int win, ch_enabled = 0;
111 DRM_DEBUG_KMS("%s\n", __FILE__);
113 /* Check if any channel is enabled. */
114 for (win = 0; win < WINDOWS_NR; win++) {
115 u32 val = readl(ctx->regs + WINCON(win));
117 if (val & WINCONx_ENWIN) {
118 val &= ~WINCONx_ENWIN;
119 writel(val, ctx->regs + WINCON(win));
124 /* Wait for vsync, as disable channel takes effect at next vsync */
126 unsigned int state = ctx->suspended;
129 decon_wait_for_vblank(ctx->crtc);
130 ctx->suspended = state;
134 static int decon_ctx_initialize(struct decon_context *ctx,
135 struct drm_device *drm_dev)
137 struct exynos_drm_private *priv = drm_dev->dev_private;
139 ctx->drm_dev = drm_dev;
140 ctx->pipe = priv->pipe++;
142 /* attach this sub driver to iommu mapping if supported. */
143 if (is_drm_iommu_supported(ctx->drm_dev)) {
147 * If any channel is already active, iommu will throw
148 * a PAGE FAULT when enabled. So clear any channel if enabled.
150 decon_clear_channel(ctx);
151 ret = drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
153 DRM_ERROR("drm_iommu_attach failed.\n");
161 static void decon_ctx_remove(struct decon_context *ctx)
163 /* detach this sub driver from iommu mapping if supported. */
164 if (is_drm_iommu_supported(ctx->drm_dev))
165 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
168 static u32 decon_calc_clkdiv(struct decon_context *ctx,
169 const struct drm_display_mode *mode)
171 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
174 /* Find the clock divider value that gets us closest to ideal_clk */
175 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk);
177 return (clkdiv < 0x100) ? clkdiv : 0xff;
180 static bool decon_mode_fixup(struct exynos_drm_crtc *crtc,
181 const struct drm_display_mode *mode,
182 struct drm_display_mode *adjusted_mode)
184 if (adjusted_mode->vrefresh == 0)
185 adjusted_mode->vrefresh = DECON_DEFAULT_FRAMERATE;
190 static void decon_commit(struct exynos_drm_crtc *crtc)
192 struct decon_context *ctx = crtc->ctx;
193 struct drm_display_mode *mode = &crtc->base.mode;
199 /* nothing to do if we haven't set the mode yet */
200 if (mode->htotal == 0 || mode->vtotal == 0)
204 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
205 /* setup vertical timing values. */
206 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
207 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
208 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
210 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1);
211 writel(val, ctx->regs + VIDTCON0);
213 val = VIDTCON1_VSPW(vsync_len - 1);
214 writel(val, ctx->regs + VIDTCON1);
216 /* setup horizontal timing values. */
217 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
218 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
219 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
221 /* setup horizontal timing values. */
222 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1);
223 writel(val, ctx->regs + VIDTCON2);
225 val = VIDTCON3_HSPW(hsync_len - 1);
226 writel(val, ctx->regs + VIDTCON3);
229 /* setup horizontal and vertical display size. */
230 val = VIDTCON4_LINEVAL(mode->vdisplay - 1) |
231 VIDTCON4_HOZVAL(mode->hdisplay - 1);
232 writel(val, ctx->regs + VIDTCON4);
234 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD);
237 * fields of register with prefix '_F' would be updated
238 * at vsync(same as dma start)
240 val = VIDCON0_ENVID | VIDCON0_ENVID_F;
241 writel(val, ctx->regs + VIDCON0);
243 clkdiv = decon_calc_clkdiv(ctx, mode);
245 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1);
246 writel(val, ctx->regs + VCLKCON1);
247 writel(val, ctx->regs + VCLKCON2);
250 val = readl(ctx->regs + DECON_UPDATE);
251 val |= DECON_UPDATE_STANDALONE_F;
252 writel(val, ctx->regs + DECON_UPDATE);
255 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
257 struct decon_context *ctx = crtc->ctx;
263 if (!test_and_set_bit(0, &ctx->irq_flags)) {
264 val = readl(ctx->regs + VIDINTCON0);
266 val |= VIDINTCON0_INT_ENABLE;
269 val |= VIDINTCON0_INT_FRAME;
270 val &= ~VIDINTCON0_FRAMESEL0_MASK;
271 val |= VIDINTCON0_FRAMESEL0_VSYNC;
274 writel(val, ctx->regs + VIDINTCON0);
280 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
282 struct decon_context *ctx = crtc->ctx;
288 if (test_and_clear_bit(0, &ctx->irq_flags)) {
289 val = readl(ctx->regs + VIDINTCON0);
291 val &= ~VIDINTCON0_INT_ENABLE;
293 val &= ~VIDINTCON0_INT_FRAME;
295 writel(val, ctx->regs + VIDINTCON0);
299 static void decon_win_mode_set(struct exynos_drm_crtc *crtc,
300 struct exynos_drm_plane *plane)
302 struct decon_context *ctx = crtc->ctx;
303 struct decon_win_data *win_data;
307 DRM_ERROR("plane is NULL\n");
312 if (win == DEFAULT_ZPOS)
313 win = ctx->default_win;
315 if (win < 0 || win >= WINDOWS_NR)
319 win_data = &ctx->win_data[win];
321 padding = (plane->pitch / (plane->bpp >> 3)) - plane->fb_width;
322 win_data->offset_x = plane->fb_x;
323 win_data->offset_y = plane->fb_y;
324 win_data->fb_width = plane->fb_width + padding;
325 win_data->fb_height = plane->fb_height;
326 win_data->ovl_x = plane->crtc_x;
327 win_data->ovl_y = plane->crtc_y;
328 win_data->ovl_width = plane->crtc_width;
329 win_data->ovl_height = plane->crtc_height;
330 win_data->dma_addr = plane->dma_addr[0];
331 win_data->bpp = plane->bpp;
332 win_data->pixel_format = plane->pixel_format;
334 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
335 win_data->offset_x, win_data->offset_y);
336 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
337 win_data->ovl_width, win_data->ovl_height);
338 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
339 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
340 plane->fb_width, plane->crtc_width);
343 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win)
345 struct decon_win_data *win_data = &ctx->win_data[win];
348 val = readl(ctx->regs + WINCON(win));
349 val &= ~WINCONx_BPPMODE_MASK;
351 switch (win_data->pixel_format) {
352 case DRM_FORMAT_RGB565:
353 val |= WINCONx_BPPMODE_16BPP_565;
354 val |= WINCONx_BURSTLEN_16WORD;
356 case DRM_FORMAT_XRGB8888:
357 val |= WINCONx_BPPMODE_24BPP_xRGB;
358 val |= WINCONx_BURSTLEN_16WORD;
360 case DRM_FORMAT_XBGR8888:
361 val |= WINCONx_BPPMODE_24BPP_xBGR;
362 val |= WINCONx_BURSTLEN_16WORD;
364 case DRM_FORMAT_RGBX8888:
365 val |= WINCONx_BPPMODE_24BPP_RGBx;
366 val |= WINCONx_BURSTLEN_16WORD;
368 case DRM_FORMAT_BGRX8888:
369 val |= WINCONx_BPPMODE_24BPP_BGRx;
370 val |= WINCONx_BURSTLEN_16WORD;
372 case DRM_FORMAT_ARGB8888:
373 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX |
375 val |= WINCONx_BURSTLEN_16WORD;
377 case DRM_FORMAT_ABGR8888:
378 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX |
380 val |= WINCONx_BURSTLEN_16WORD;
382 case DRM_FORMAT_RGBA8888:
383 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX |
385 val |= WINCONx_BURSTLEN_16WORD;
387 case DRM_FORMAT_BGRA8888:
388 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX |
390 val |= WINCONx_BURSTLEN_16WORD;
393 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
395 val |= WINCONx_BPPMODE_24BPP_xRGB;
396 val |= WINCONx_BURSTLEN_16WORD;
400 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
403 * In case of exynos, setting dma-burst to 16Word causes permanent
404 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
405 * switching which is based on plane size is not recommended as
406 * plane size varies a lot towards the end of the screen and rapid
407 * movement causes unstable DMA which results into iommu crash/tear.
410 if (win_data->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
411 val &= ~WINCONx_BURSTLEN_MASK;
412 val |= WINCONx_BURSTLEN_8WORD;
415 writel(val, ctx->regs + WINCON(win));
418 static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win)
420 unsigned int keycon0 = 0, keycon1 = 0;
422 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
423 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
425 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
427 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
428 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
432 * shadow_protect_win() - disable updating values from shadow registers at vsync
434 * @win: window to protect registers for
435 * @protect: 1 to protect (disable updates)
437 static void decon_shadow_protect_win(struct decon_context *ctx,
438 int win, bool protect)
442 bits = SHADOWCON_WINx_PROTECT(win);
444 val = readl(ctx->regs + SHADOWCON);
449 writel(val, ctx->regs + SHADOWCON);
452 static void decon_win_commit(struct exynos_drm_crtc *crtc, int zpos)
454 struct decon_context *ctx = crtc->ctx;
455 struct drm_display_mode *mode = &crtc->base.mode;
456 struct decon_win_data *win_data;
458 unsigned long val, alpha;
465 if (win == DEFAULT_ZPOS)
466 win = ctx->default_win;
468 if (win < 0 || win >= WINDOWS_NR)
471 win_data = &ctx->win_data[win];
473 /* If suspended, enable this on resume */
474 if (ctx->suspended) {
475 win_data->resume = true;
480 * SHADOWCON/PRTCON register is used for enabling timing.
482 * for example, once only width value of a register is set,
483 * if the dma is started then decon hardware could malfunction so
484 * with protect window setting, the register fields with prefix '_F'
485 * wouldn't be updated at vsync also but updated once unprotect window
489 /* protect windows */
490 decon_shadow_protect_win(ctx, win, true);
492 /* buffer start address */
493 val = (unsigned long)win_data->dma_addr;
494 writel(val, ctx->regs + VIDW_BUF_START(win));
497 writel(win_data->fb_width, ctx->regs + VIDW_WHOLE_X(win));
498 writel(win_data->fb_height, ctx->regs + VIDW_WHOLE_Y(win));
500 /* offset from the start of the buffer to read */
501 writel(win_data->offset_x, ctx->regs + VIDW_OFFSET_X(win));
502 writel(win_data->offset_y, ctx->regs + VIDW_OFFSET_Y(win));
504 DRM_DEBUG_KMS("start addr = 0x%lx\n",
505 (unsigned long)win_data->dma_addr);
506 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
507 win_data->ovl_width, win_data->ovl_height);
511 * In case the window layout goes of LCD layout, DECON fails.
513 if ((win_data->ovl_x + win_data->ovl_width) > mode->hdisplay)
514 win_data->ovl_x = mode->hdisplay - win_data->ovl_width;
515 if ((win_data->ovl_y + win_data->ovl_height) > mode->vdisplay)
516 win_data->ovl_y = mode->vdisplay - win_data->ovl_height;
518 val = VIDOSDxA_TOPLEFT_X(win_data->ovl_x) |
519 VIDOSDxA_TOPLEFT_Y(win_data->ovl_y);
520 writel(val, ctx->regs + VIDOSD_A(win));
522 last_x = win_data->ovl_x + win_data->ovl_width;
525 last_y = win_data->ovl_y + win_data->ovl_height;
529 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y);
531 writel(val, ctx->regs + VIDOSD_B(win));
533 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
534 win_data->ovl_x, win_data->ovl_y, last_x, last_y);
537 alpha = VIDOSDxC_ALPHA0_R_F(0x0) |
538 VIDOSDxC_ALPHA0_G_F(0x0) |
539 VIDOSDxC_ALPHA0_B_F(0x0);
541 writel(alpha, ctx->regs + VIDOSD_C(win));
543 alpha = VIDOSDxD_ALPHA1_R_F(0xff) |
544 VIDOSDxD_ALPHA1_G_F(0xff) |
545 VIDOSDxD_ALPHA1_B_F(0xff);
547 writel(alpha, ctx->regs + VIDOSD_D(win));
549 decon_win_set_pixfmt(ctx, win);
551 /* hardware window 0 doesn't support color key. */
553 decon_win_set_colkey(ctx, win);
556 val = readl(ctx->regs + WINCON(win));
557 val |= WINCONx_TRIPLE_BUF_MODE;
558 val |= WINCONx_ENWIN;
559 writel(val, ctx->regs + WINCON(win));
561 /* Enable DMA channel and unprotect windows */
562 decon_shadow_protect_win(ctx, win, false);
564 val = readl(ctx->regs + DECON_UPDATE);
565 val |= DECON_UPDATE_STANDALONE_F;
566 writel(val, ctx->regs + DECON_UPDATE);
568 win_data->enabled = true;
571 static void decon_win_disable(struct exynos_drm_crtc *crtc, int zpos)
573 struct decon_context *ctx = crtc->ctx;
574 struct decon_win_data *win_data;
578 if (win == DEFAULT_ZPOS)
579 win = ctx->default_win;
581 if (win < 0 || win >= WINDOWS_NR)
584 win_data = &ctx->win_data[win];
586 if (ctx->suspended) {
587 /* do not resume this window*/
588 win_data->resume = false;
592 /* protect windows */
593 decon_shadow_protect_win(ctx, win, true);
596 val = readl(ctx->regs + WINCON(win));
597 val &= ~WINCONx_ENWIN;
598 writel(val, ctx->regs + WINCON(win));
600 /* unprotect windows */
601 decon_shadow_protect_win(ctx, win, false);
603 val = readl(ctx->regs + DECON_UPDATE);
604 val |= DECON_UPDATE_STANDALONE_F;
605 writel(val, ctx->regs + DECON_UPDATE);
607 win_data->enabled = false;
610 static void decon_window_suspend(struct decon_context *ctx)
612 struct decon_win_data *win_data;
615 for (i = 0; i < WINDOWS_NR; i++) {
616 win_data = &ctx->win_data[i];
617 win_data->resume = win_data->enabled;
618 if (win_data->enabled)
619 decon_win_disable(ctx->crtc, i);
623 static void decon_window_resume(struct decon_context *ctx)
625 struct decon_win_data *win_data;
628 for (i = 0; i < WINDOWS_NR; i++) {
629 win_data = &ctx->win_data[i];
630 win_data->enabled = win_data->resume;
631 win_data->resume = false;
635 static void decon_apply(struct decon_context *ctx)
637 struct decon_win_data *win_data;
640 for (i = 0; i < WINDOWS_NR; i++) {
641 win_data = &ctx->win_data[i];
642 if (win_data->enabled)
643 decon_win_commit(ctx->crtc, i);
645 decon_win_disable(ctx->crtc, i);
648 decon_commit(ctx->crtc);
651 static void decon_init(struct decon_context *ctx)
655 writel(VIDCON0_SWRESET, ctx->regs + VIDCON0);
657 val = VIDOUTCON0_DISP_IF_0_ON;
659 val |= VIDOUTCON0_RGBIF;
660 writel(val, ctx->regs + VIDOUTCON0);
662 writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0);
665 writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0));
668 static int decon_poweron(struct decon_context *ctx)
675 ctx->suspended = false;
677 pm_runtime_get_sync(ctx->dev);
679 ret = clk_prepare_enable(ctx->pclk);
681 DRM_ERROR("Failed to prepare_enable the pclk [%d]\n", ret);
685 ret = clk_prepare_enable(ctx->aclk);
687 DRM_ERROR("Failed to prepare_enable the aclk [%d]\n", ret);
691 ret = clk_prepare_enable(ctx->eclk);
693 DRM_ERROR("Failed to prepare_enable the eclk [%d]\n", ret);
697 ret = clk_prepare_enable(ctx->vclk);
699 DRM_ERROR("Failed to prepare_enable the vclk [%d]\n", ret);
705 /* if vblank was enabled status, enable it again. */
706 if (test_and_clear_bit(0, &ctx->irq_flags)) {
707 ret = decon_enable_vblank(ctx->crtc);
709 DRM_ERROR("Failed to re-enable vblank [%d]\n", ret);
714 decon_window_resume(ctx);
721 clk_disable_unprepare(ctx->vclk);
723 clk_disable_unprepare(ctx->eclk);
725 clk_disable_unprepare(ctx->aclk);
727 clk_disable_unprepare(ctx->pclk);
729 ctx->suspended = true;
733 static int decon_poweroff(struct decon_context *ctx)
739 * We need to make sure that all windows are disabled before we
740 * suspend that connector. Otherwise we might try to scan from
741 * a destroyed buffer later.
743 decon_window_suspend(ctx);
745 clk_disable_unprepare(ctx->vclk);
746 clk_disable_unprepare(ctx->eclk);
747 clk_disable_unprepare(ctx->aclk);
748 clk_disable_unprepare(ctx->pclk);
750 pm_runtime_put_sync(ctx->dev);
752 ctx->suspended = true;
756 static void decon_dpms(struct exynos_drm_crtc *crtc, int mode)
758 DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
761 case DRM_MODE_DPMS_ON:
762 decon_poweron(crtc->ctx);
764 case DRM_MODE_DPMS_STANDBY:
765 case DRM_MODE_DPMS_SUSPEND:
766 case DRM_MODE_DPMS_OFF:
767 decon_poweroff(crtc->ctx);
770 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
775 static struct exynos_drm_crtc_ops decon_crtc_ops = {
777 .mode_fixup = decon_mode_fixup,
778 .commit = decon_commit,
779 .enable_vblank = decon_enable_vblank,
780 .disable_vblank = decon_disable_vblank,
781 .wait_for_vblank = decon_wait_for_vblank,
782 .win_mode_set = decon_win_mode_set,
783 .win_commit = decon_win_commit,
784 .win_disable = decon_win_disable,
788 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
790 struct decon_context *ctx = (struct decon_context *)dev_id;
793 val = readl(ctx->regs + VIDINTCON1);
795 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
797 writel(clear_bit, ctx->regs + VIDINTCON1);
799 /* check the crtc is detached already from encoder */
800 if (ctx->pipe < 0 || !ctx->drm_dev)
804 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
805 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
807 /* set wait vsync event to zero and wake up queue. */
808 if (atomic_read(&ctx->wait_vsync_event)) {
809 atomic_set(&ctx->wait_vsync_event, 0);
810 wake_up(&ctx->wait_vsync_queue);
817 static int decon_bind(struct device *dev, struct device *master, void *data)
819 struct decon_context *ctx = dev_get_drvdata(dev);
820 struct drm_device *drm_dev = data;
823 ret = decon_ctx_initialize(ctx, drm_dev);
825 DRM_ERROR("decon_ctx_initialize failed.\n");
829 ctx->crtc = exynos_drm_crtc_create(drm_dev, ctx->pipe,
830 EXYNOS_DISPLAY_TYPE_LCD,
831 &decon_crtc_ops, ctx);
832 if (IS_ERR(ctx->crtc)) {
833 decon_ctx_remove(ctx);
834 return PTR_ERR(ctx->crtc);
838 exynos_drm_create_enc_conn(drm_dev, ctx->display);
844 static void decon_unbind(struct device *dev, struct device *master,
847 struct decon_context *ctx = dev_get_drvdata(dev);
849 decon_dpms(ctx->crtc, DRM_MODE_DPMS_OFF);
852 exynos_dpi_remove(ctx->display);
854 decon_ctx_remove(ctx);
857 static const struct component_ops decon_component_ops = {
859 .unbind = decon_unbind,
862 static int decon_probe(struct platform_device *pdev)
864 struct device *dev = &pdev->dev;
865 struct decon_context *ctx;
866 struct device_node *i80_if_timings;
867 struct resource *res;
873 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
877 ret = exynos_drm_component_add(dev, EXYNOS_DEVICE_TYPE_CRTC,
878 EXYNOS_DISPLAY_TYPE_LCD);
883 ctx->suspended = true;
885 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
888 of_node_put(i80_if_timings);
890 ctx->regs = of_iomap(dev->of_node, 0);
893 goto err_del_component;
896 ctx->pclk = devm_clk_get(dev, "pclk_decon0");
897 if (IS_ERR(ctx->pclk)) {
898 dev_err(dev, "failed to get bus clock pclk\n");
899 ret = PTR_ERR(ctx->pclk);
903 ctx->aclk = devm_clk_get(dev, "aclk_decon0");
904 if (IS_ERR(ctx->aclk)) {
905 dev_err(dev, "failed to get bus clock aclk\n");
906 ret = PTR_ERR(ctx->aclk);
910 ctx->eclk = devm_clk_get(dev, "decon0_eclk");
911 if (IS_ERR(ctx->eclk)) {
912 dev_err(dev, "failed to get eclock\n");
913 ret = PTR_ERR(ctx->eclk);
917 ctx->vclk = devm_clk_get(dev, "decon0_vclk");
918 if (IS_ERR(ctx->vclk)) {
919 dev_err(dev, "failed to get vclock\n");
920 ret = PTR_ERR(ctx->vclk);
924 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
925 ctx->i80_if ? "lcd_sys" : "vsync");
927 dev_err(dev, "irq request failed.\n");
932 ret = devm_request_irq(dev, res->start, decon_irq_handler,
933 0, "drm_decon", ctx);
935 dev_err(dev, "irq request failed.\n");
939 init_waitqueue_head(&ctx->wait_vsync_queue);
940 atomic_set(&ctx->wait_vsync_event, 0);
942 platform_set_drvdata(pdev, ctx);
944 ctx->display = exynos_dpi_probe(dev);
945 if (IS_ERR(ctx->display)) {
946 ret = PTR_ERR(ctx->display);
950 pm_runtime_enable(dev);
952 ret = component_add(dev, &decon_component_ops);
954 goto err_disable_pm_runtime;
958 err_disable_pm_runtime:
959 pm_runtime_disable(dev);
965 exynos_drm_component_del(dev, EXYNOS_DEVICE_TYPE_CRTC);
969 static int decon_remove(struct platform_device *pdev)
971 struct decon_context *ctx = dev_get_drvdata(&pdev->dev);
973 pm_runtime_disable(&pdev->dev);
977 component_del(&pdev->dev, &decon_component_ops);
978 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
983 struct platform_driver decon_driver = {
984 .probe = decon_probe,
985 .remove = decon_remove,
987 .name = "exynos-decon",
988 .of_match_table = decon_driver_dt_match,