drivers/gpu/drm/exynos/exynos_dp_core.c

   1 /*
   2  * Samsung SoC DP (Display Port) interface driver.
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5  * Author: Jingoo Han <jg1.han@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/io.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/of.h>
  20 #include <linux/of_gpio.h>
  21 #include <linux/gpio.h>
  22 #include <linux/component.h>
  23 #include <linux/phy/phy.h>
  24 #include <video/of_display_timing.h>
  25 #include <video/of_videomode.h>
  26
  27 #include <drm/drmP.h>
  28 #include <drm/drm_crtc.h>
  29 #include <drm/drm_crtc_helper.h>
  30 #include <drm/drm_panel.h>
  31 #include <drm/bridge/ptn3460.h>
  32
  33 #include "exynos_dp_core.h"
  34
  35 #define ctx_from_connector(c)   container_of(c, struct exynos_dp_device, \
  36                                         connector)
  37
  38 static inline struct exynos_dp_device *
  39 display_to_dp(struct exynos_drm_display *d)
  40 {
  41         return container_of(d, struct exynos_dp_device, display);
  42 }
  43
  44 struct bridge_init {
  45         struct i2c_client *client;
  46         struct device_node *node;
  47 };
  48
  49 static void exynos_dp_init_dp(struct exynos_dp_device *dp)
  50 {
  51         exynos_dp_reset(dp);
  52
  53         exynos_dp_swreset(dp);
  54
  55         exynos_dp_init_analog_param(dp);
  56         exynos_dp_init_interrupt(dp);
  57
  58         /* SW defined function Normal operation */
  59         exynos_dp_enable_sw_function(dp);
  60
  61         exynos_dp_config_interrupt(dp);
  62         exynos_dp_init_analog_func(dp);
  63
  64         exynos_dp_init_hpd(dp);
  65         exynos_dp_init_aux(dp);
  66 }
  67
  68 static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
  69 {
  70         int timeout_loop = 0;
  71
  72         while (exynos_dp_get_plug_in_status(dp) != 0) {
  73                 timeout_loop++;
  74                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
  75                         dev_err(dp->dev, "failed to get hpd plug status\n");
  76                         return -ETIMEDOUT;
  77                 }
  78                 usleep_range(10, 11);
  79         }
  80
  81         return 0;
  82 }
  83
  84 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
  85 {
  86         int i;
  87         unsigned char sum = 0;
  88
  89         for (i = 0; i < EDID_BLOCK_LENGTH; i++)
  90                 sum = sum + edid_data[i];
  91
  92         return sum;
  93 }
  94
  95 static int exynos_dp_read_edid(struct exynos_dp_device *dp)
  96 {
  97         unsigned char edid[EDID_BLOCK_LENGTH * 2];
  98         unsigned int extend_block = 0;
  99         unsigned char sum;
 100         unsigned char test_vector;
 101         int retval;
 102
 103         /*
 104          * EDID device address is 0x50.
 105          * However, if necessary, you must have set upper address
 106          * into E-EDID in I2C device, 0x30.
 107          */
 108
 109         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
 110         retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 111                                 EDID_EXTENSION_FLAG,
 112                                 &extend_block);
 113         if (retval)
 114                 return retval;
 115
 116         if (extend_block > 0) {
 117                 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
 118
 119                 /* Read EDID data */
 120                 retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 121                                                 EDID_HEADER_PATTERN,
 122                                                 EDID_BLOCK_LENGTH,
 123                                                 &edid[EDID_HEADER_PATTERN]);
 124                 if (retval != 0) {
 125                         dev_err(dp->dev, "EDID Read failed!\n");
 126                         return -EIO;
 127                 }
 128                 sum = exynos_dp_calc_edid_check_sum(edid);
 129                 if (sum != 0) {
 130                         dev_err(dp->dev, "EDID bad checksum!\n");
 131                         return -EIO;
 132                 }
 133
 134                 /* Read additional EDID data */
 135                 retval = exynos_dp_read_bytes_from_i2c(dp,
 136                                 I2C_EDID_DEVICE_ADDR,
 137                                 EDID_BLOCK_LENGTH,
 138                                 EDID_BLOCK_LENGTH,
 139                                 &edid[EDID_BLOCK_LENGTH]);
 140                 if (retval != 0) {
 141                         dev_err(dp->dev, "EDID Read failed!\n");
 142                         return -EIO;
 143                 }
 144                 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
 145                 if (sum != 0) {
 146                         dev_err(dp->dev, "EDID bad checksum!\n");
 147                         return -EIO;
 148                 }
 149
 150                 exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
 151                                         &test_vector);
 152                 if (test_vector & DP_TEST_LINK_EDID_READ) {
 153                         exynos_dp_write_byte_to_dpcd(dp,
 154                                 DP_TEST_EDID_CHECKSUM,
 155                                 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
 156                         exynos_dp_write_byte_to_dpcd(dp,
 157                                 DP_TEST_RESPONSE,
 158                                 DP_TEST_EDID_CHECKSUM_WRITE);
 159                 }
 160         } else {
 161                 dev_info(dp->dev, "EDID data does not include any extensions.\n");
 162
 163                 /* Read EDID data */
 164                 retval = exynos_dp_read_bytes_from_i2c(dp,
 165                                 I2C_EDID_DEVICE_ADDR,
 166                                 EDID_HEADER_PATTERN,
 167                                 EDID_BLOCK_LENGTH,
 168                                 &edid[EDID_HEADER_PATTERN]);
 169                 if (retval != 0) {
 170                         dev_err(dp->dev, "EDID Read failed!\n");
 171                         return -EIO;
 172                 }
 173                 sum = exynos_dp_calc_edid_check_sum(edid);
 174                 if (sum != 0) {
 175                         dev_err(dp->dev, "EDID bad checksum!\n");
 176                         return -EIO;
 177                 }
 178
 179                 exynos_dp_read_byte_from_dpcd(dp,
 180                         DP_TEST_REQUEST,
 181                         &test_vector);
 182                 if (test_vector & DP_TEST_LINK_EDID_READ) {
 183                         exynos_dp_write_byte_to_dpcd(dp,
 184                                 DP_TEST_EDID_CHECKSUM,
 185                                 edid[EDID_CHECKSUM]);
 186                         exynos_dp_write_byte_to_dpcd(dp,
 187                                 DP_TEST_RESPONSE,
 188                                 DP_TEST_EDID_CHECKSUM_WRITE);
 189                 }
 190         }
 191
 192         dev_err(dp->dev, "EDID Read success!\n");
 193         return 0;
 194 }
 195
 196 static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
 197 {
 198         u8 buf[12];
 199         int i;
 200         int retval;
 201
 202         /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 203         retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
 204                                 12, buf);
 205         if (retval)
 206                 return retval;
 207
 208         /* Read EDID */
 209         for (i = 0; i < 3; i++) {
 210                 retval = exynos_dp_read_edid(dp);
 211                 if (!retval)
 212                         break;
 213         }
 214
 215         return retval;
 216 }
 217
 218 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
 219                                                 bool enable)
 220 {
 221         u8 data;
 222
 223         exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
 224
 225         if (enable)
 226                 exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
 227                         DP_LANE_COUNT_ENHANCED_FRAME_EN |
 228                         DPCD_LANE_COUNT_SET(data));
 229         else
 230                 exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
 231                         DPCD_LANE_COUNT_SET(data));
 232 }
 233
 234 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
 235 {
 236         u8 data;
 237         int retval;
 238
 239         exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
 240         retval = DPCD_ENHANCED_FRAME_CAP(data);
 241
 242         return retval;
 243 }
 244
 245 static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
 246 {
 247         u8 data;
 248
 249         data = exynos_dp_is_enhanced_mode_available(dp);
 250         exynos_dp_enable_rx_to_enhanced_mode(dp, data);
 251         exynos_dp_enable_enhanced_mode(dp, data);
 252 }
 253
 254 static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
 255 {
 256         exynos_dp_set_training_pattern(dp, DP_NONE);
 257
 258         exynos_dp_write_byte_to_dpcd(dp,
 259                 DP_TRAINING_PATTERN_SET,
 260                 DP_TRAINING_PATTERN_DISABLE);
 261 }
 262
 263 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
 264                                         int pre_emphasis, int lane)
 265 {
 266         switch (lane) {
 267         case 0:
 268                 exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 269                 break;
 270         case 1:
 271                 exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 272                 break;
 273
 274         case 2:
 275                 exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 276                 break;
 277
 278         case 3:
 279                 exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 280                 break;
 281         }
 282 }
 283
 284 static int exynos_dp_link_start(struct exynos_dp_device *dp)
 285 {
 286         u8 buf[4];
 287         int lane, lane_count, pll_tries, retval;
 288
 289         lane_count = dp->link_train.lane_count;
 290
 291         dp->link_train.lt_state = CLOCK_RECOVERY;
 292         dp->link_train.eq_loop = 0;
 293
 294         for (lane = 0; lane < lane_count; lane++)
 295                 dp->link_train.cr_loop[lane] = 0;
 296
 297         /* Set link rate and count as you want to establish*/
 298         exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 299         exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
 300
 301         /* Setup RX configuration */
 302         buf[0] = dp->link_train.link_rate;
 303         buf[1] = dp->link_train.lane_count;
 304         retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
 305                                 2, buf);
 306         if (retval)
 307                 return retval;
 308
 309         /* Set TX pre-emphasis to minimum */
 310         for (lane = 0; lane < lane_count; lane++)
 311                 exynos_dp_set_lane_lane_pre_emphasis(dp,
 312                         PRE_EMPHASIS_LEVEL_0, lane);
 313
 314         /* Wait for PLL lock */
 315         pll_tries = 0;
 316         while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 317                 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
 318                         dev_err(dp->dev, "Wait for PLL lock timed out\n");
 319                         return -ETIMEDOUT;
 320                 }
 321
 322                 pll_tries++;
 323                 usleep_range(90, 120);
 324         }
 325
 326         /* Set training pattern 1 */
 327         exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
 328
 329         /* Set RX training pattern */
 330         retval = exynos_dp_write_byte_to_dpcd(dp,
 331                         DP_TRAINING_PATTERN_SET,
 332                         DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
 333         if (retval)
 334                 return retval;
 335
 336         for (lane = 0; lane < lane_count; lane++)
 337                 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
 338                             DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 339
 340         retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
 341                         lane_count, buf);
 342
 343         return retval;
 344 }
 345
 346 static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
 347 {
 348         int shift = (lane & 1) * 4;
 349         u8 link_value = link_status[lane>>1];
 350
 351         return (link_value >> shift) & 0xf;
 352 }
 353
 354 static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 355 {
 356         int lane;
 357         u8 lane_status;
 358
 359         for (lane = 0; lane < lane_count; lane++) {
 360                 lane_status = exynos_dp_get_lane_status(link_status, lane);
 361                 if ((lane_status & DP_LANE_CR_DONE) == 0)
 362                         return -EINVAL;
 363         }
 364         return 0;
 365 }
 366
 367 static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 368                                 int lane_count)
 369 {
 370         int lane;
 371         u8 lane_status;
 372
 373         if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
 374                 return -EINVAL;
 375
 376         for (lane = 0; lane < lane_count; lane++) {
 377                 lane_status = exynos_dp_get_lane_status(link_status, lane);
 378                 lane_status &= DP_CHANNEL_EQ_BITS;
 379                 if (lane_status != DP_CHANNEL_EQ_BITS)
 380                         return -EINVAL;
 381         }
 382
 383         return 0;
 384 }
 385
 386 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
 387                                                         int lane)
 388 {
 389         int shift = (lane & 1) * 4;
 390         u8 link_value = adjust_request[lane>>1];
 391
 392         return (link_value >> shift) & 0x3;
 393 }
 394
 395 static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
 396                                         u8 adjust_request[2],
 397                                         int lane)
 398 {
 399         int shift = (lane & 1) * 4;
 400         u8 link_value = adjust_request[lane>>1];
 401
 402         return ((link_value >> shift) & 0xc) >> 2;
 403 }
 404
 405 static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
 406                                         u8 training_lane_set, int lane)
 407 {
 408         switch (lane) {
 409         case 0:
 410                 exynos_dp_set_lane0_link_training(dp, training_lane_set);
 411                 break;
 412         case 1:
 413                 exynos_dp_set_lane1_link_training(dp, training_lane_set);
 414                 break;
 415
 416         case 2:
 417                 exynos_dp_set_lane2_link_training(dp, training_lane_set);
 418                 break;
 419
 420         case 3:
 421                 exynos_dp_set_lane3_link_training(dp, training_lane_set);
 422                 break;
 423         }
 424 }
 425
 426 static unsigned int exynos_dp_get_lane_link_training(
 427                                 struct exynos_dp_device *dp,
 428                                 int lane)
 429 {
 430         u32 reg;
 431
 432         switch (lane) {
 433         case 0:
 434                 reg = exynos_dp_get_lane0_link_training(dp);
 435                 break;
 436         case 1:
 437                 reg = exynos_dp_get_lane1_link_training(dp);
 438                 break;
 439         case 2:
 440                 reg = exynos_dp_get_lane2_link_training(dp);
 441                 break;
 442         case 3:
 443                 reg = exynos_dp_get_lane3_link_training(dp);
 444                 break;
 445         default:
 446                 WARN_ON(1);
 447                 return 0;
 448         }
 449
 450         return reg;
 451 }
 452
 453 static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
 454 {
 455         exynos_dp_training_pattern_dis(dp);
 456         exynos_dp_set_enhanced_mode(dp);
 457
 458         dp->link_train.lt_state = FAILED;
 459 }
 460
 461 static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
 462                                         u8 adjust_request[2])
 463 {
 464         int lane, lane_count;
 465         u8 voltage_swing, pre_emphasis, training_lane;
 466
 467         lane_count = dp->link_train.lane_count;
 468         for (lane = 0; lane < lane_count; lane++) {
 469                 voltage_swing = exynos_dp_get_adjust_request_voltage(
 470                                                 adjust_request, lane);
 471                 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
 472                                                 adjust_request, lane);
 473                 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 474                                 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 475
 476                 if (voltage_swing == VOLTAGE_LEVEL_3)
 477                         training_lane |= DP_TRAIN_MAX_SWING_REACHED;
 478                 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 479                         training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 480
 481                 dp->link_train.training_lane[lane] = training_lane;
 482         }
 483 }
 484
 485 static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 486 {
 487         int lane, lane_count, retval;
 488         u8 voltage_swing, pre_emphasis, training_lane;
 489         u8 link_status[2], adjust_request[2];
 490
 491         usleep_range(100, 101);
 492
 493         lane_count = dp->link_train.lane_count;
 494
 495         retval =  exynos_dp_read_bytes_from_dpcd(dp,
 496                         DP_LANE0_1_STATUS, 2, link_status);
 497         if (retval)
 498                 return retval;
 499
 500         retval =  exynos_dp_read_bytes_from_dpcd(dp,
 501                         DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
 502         if (retval)
 503                 return retval;
 504
 505         if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 506                 /* set training pattern 2 for EQ */
 507                 exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
 508
 509                 retval = exynos_dp_write_byte_to_dpcd(dp,
 510                                 DP_TRAINING_PATTERN_SET,
 511                                 DP_LINK_SCRAMBLING_DISABLE |
 512                                 DP_TRAINING_PATTERN_2);
 513                 if (retval)
 514                         return retval;
 515
 516                 dev_info(dp->dev, "Link Training Clock Recovery success\n");
 517                 dp->link_train.lt_state = EQUALIZER_TRAINING;
 518         } else {
 519                 for (lane = 0; lane < lane_count; lane++) {
 520                         training_lane = exynos_dp_get_lane_link_training(
 521                                                         dp, lane);
 522                         voltage_swing = exynos_dp_get_adjust_request_voltage(
 523                                                         adjust_request, lane);
 524                         pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
 525                                                         adjust_request, lane);
 526
 527                         if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
 528                                         voltage_swing &&
 529                             DPCD_PRE_EMPHASIS_GET(training_lane) ==
 530                                         pre_emphasis)
 531                                 dp->link_train.cr_loop[lane]++;
 532
 533                         if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
 534                             voltage_swing == VOLTAGE_LEVEL_3 ||
 535                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 536                                 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
 537                                         dp->link_train.cr_loop[lane],
 538                                         voltage_swing, pre_emphasis);
 539                                 exynos_dp_reduce_link_rate(dp);
 540                                 return -EIO;
 541                         }
 542                 }
 543         }
 544
 545         exynos_dp_get_adjust_training_lane(dp, adjust_request);
 546
 547         for (lane = 0; lane < lane_count; lane++)
 548                 exynos_dp_set_lane_link_training(dp,
 549                         dp->link_train.training_lane[lane], lane);
 550
 551         retval = exynos_dp_write_bytes_to_dpcd(dp,
 552                         DP_TRAINING_LANE0_SET, lane_count,
 553                         dp->link_train.training_lane);
 554         if (retval)
 555                 return retval;
 556
 557         return retval;
 558 }
 559
 560 static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 561 {
 562         int lane, lane_count, retval;
 563         u32 reg;
 564         u8 link_align, link_status[2], adjust_request[2];
 565
 566         usleep_range(400, 401);
 567
 568         lane_count = dp->link_train.lane_count;
 569
 570         retval = exynos_dp_read_bytes_from_dpcd(dp,
 571                         DP_LANE0_1_STATUS, 2, link_status);
 572         if (retval)
 573                 return retval;
 574
 575         if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
 576                 exynos_dp_reduce_link_rate(dp);
 577                 return -EIO;
 578         }
 579
 580         retval = exynos_dp_read_bytes_from_dpcd(dp,
 581                         DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
 582         if (retval)
 583                 return retval;
 584
 585         retval = exynos_dp_read_byte_from_dpcd(dp,
 586                         DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
 587         if (retval)
 588                 return retval;
 589
 590         exynos_dp_get_adjust_training_lane(dp, adjust_request);
 591
 592         if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) {
 593                 /* traing pattern Set to Normal */
 594                 exynos_dp_training_pattern_dis(dp);
 595
 596                 dev_info(dp->dev, "Link Training success!\n");
 597
 598                 exynos_dp_get_link_bandwidth(dp, &reg);
 599                 dp->link_train.link_rate = reg;
 600                 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 601                         dp->link_train.link_rate);
 602
 603                 exynos_dp_get_lane_count(dp, &reg);
 604                 dp->link_train.lane_count = reg;
 605                 dev_dbg(dp->dev, "final lane count = %.2x\n",
 606                         dp->link_train.lane_count);
 607
 608                 /* set enhanced mode if available */
 609                 exynos_dp_set_enhanced_mode(dp);
 610                 dp->link_train.lt_state = FINISHED;
 611
 612                 return 0;
 613         }
 614
 615         /* not all locked */
 616         dp->link_train.eq_loop++;
 617
 618         if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 619                 dev_err(dp->dev, "EQ Max loop\n");
 620                 exynos_dp_reduce_link_rate(dp);
 621                 return -EIO;
 622         }
 623
 624         for (lane = 0; lane < lane_count; lane++)
 625                 exynos_dp_set_lane_link_training(dp,
 626                         dp->link_train.training_lane[lane], lane);
 627
 628         retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
 629                         lane_count, dp->link_train.training_lane);
 630
 631         return retval;
 632 }
 633
 634 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
 635                                         u8 *bandwidth)
 636 {
 637         u8 data;
 638
 639         /*
 640          * For DP rev.1.1, Maximum link rate of Main Link lanes
 641          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 642          */
 643         exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
 644         *bandwidth = data;
 645 }
 646
 647 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
 648                                         u8 *lane_count)
 649 {
 650         u8 data;
 651
 652         /*
 653          * For DP rev.1.1, Maximum number of Main Link lanes
 654          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 655          */
 656         exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
 657         *lane_count = DPCD_MAX_LANE_COUNT(data);
 658 }
 659
 660 static void exynos_dp_init_training(struct exynos_dp_device *dp,
 661                         enum link_lane_count_type max_lane,
 662                         enum link_rate_type max_rate)
 663 {
 664         /*
 665          * MACRO_RST must be applied after the PLL_LOCK to avoid
 666          * the DP inter pair skew issue for at least 10 us
 667          */
 668         exynos_dp_reset_macro(dp);
 669
 670         /* Initialize by reading RX's DPCD */
 671         exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 672         exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 673
 674         if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 675            (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 676                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 677                         dp->link_train.link_rate);
 678                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 679         }
 680
 681         if (dp->link_train.lane_count == 0) {
 682                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 683                         dp->link_train.lane_count);
 684                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 685         }
 686
 687         /* Setup TX lane count & rate */
 688         if (dp->link_train.lane_count > max_lane)
 689                 dp->link_train.lane_count = max_lane;
 690         if (dp->link_train.link_rate > max_rate)
 691                 dp->link_train.link_rate = max_rate;
 692
 693         /* All DP analog module power up */
 694         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 695 }
 696
 697 static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 698 {
 699         int retval = 0, training_finished = 0;
 700
 701         dp->link_train.lt_state = START;
 702
 703         /* Process here */
 704         while (!retval && !training_finished) {
 705                 switch (dp->link_train.lt_state) {
 706                 case START:
 707                         retval = exynos_dp_link_start(dp);
 708                         if (retval)
 709                                 dev_err(dp->dev, "LT link start failed!\n");
 710                         break;
 711                 case CLOCK_RECOVERY:
 712                         retval = exynos_dp_process_clock_recovery(dp);
 713                         if (retval)
 714                                 dev_err(dp->dev, "LT CR failed!\n");
 715                         break;
 716                 case EQUALIZER_TRAINING:
 717                         retval = exynos_dp_process_equalizer_training(dp);
 718                         if (retval)
 719                                 dev_err(dp->dev, "LT EQ failed!\n");
 720                         break;
 721                 case FINISHED:
 722                         training_finished = 1;
 723                         break;
 724                 case FAILED:
 725                         return -EREMOTEIO;
 726                 }
 727         }
 728         if (retval)
 729                 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
 730
 731         return retval;
 732 }
 733
 734 static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
 735                                 u32 count,
 736                                 u32 bwtype)
 737 {
 738         int i;
 739         int retval;
 740
 741         for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
 742                 exynos_dp_init_training(dp, count, bwtype);
 743                 retval = exynos_dp_sw_link_training(dp);
 744                 if (retval == 0)
 745                         break;
 746
 747                 usleep_range(100, 110);
 748         }
 749
 750         return retval;
 751 }
 752
 753 static int exynos_dp_config_video(struct exynos_dp_device *dp)
 754 {
 755         int retval = 0;
 756         int timeout_loop = 0;
 757         int done_count = 0;
 758
 759         exynos_dp_config_video_slave_mode(dp);
 760
 761         exynos_dp_set_video_color_format(dp);
 762
 763         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 764                 dev_err(dp->dev, "PLL is not locked yet.\n");
 765                 return -EINVAL;
 766         }
 767
 768         for (;;) {
 769                 timeout_loop++;
 770                 if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
 771                         break;
 772                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 773                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
 774                         return -ETIMEDOUT;
 775                 }
 776
 777                 usleep_range(1, 2);
 778         }
 779
 780         /* Set to use the register calculated M/N video */
 781         exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 782
 783         /* For video bist, Video timing must be generated by register */
 784         exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 785
 786         /* Disable video mute */
 787         exynos_dp_enable_video_mute(dp, 0);
 788
 789         /* Configure video slave mode */
 790         exynos_dp_enable_video_master(dp, 0);
 791
 792         /* Enable video */
 793         exynos_dp_start_video(dp);
 794
 795         timeout_loop = 0;
 796
 797         for (;;) {
 798                 timeout_loop++;
 799                 if (exynos_dp_is_video_stream_on(dp) == 0) {
 800                         done_count++;
 801                         if (done_count > 10)
 802                                 break;
 803                 } else if (done_count) {
 804                         done_count = 0;
 805                 }
 806                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 807                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
 808                         return -ETIMEDOUT;
 809                 }
 810
 811                 usleep_range(1000, 1001);
 812         }
 813
 814         if (retval != 0)
 815                 dev_err(dp->dev, "Video stream is not detected!\n");
 816
 817         return retval;
 818 }
 819
 820 static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
 821 {
 822         u8 data;
 823
 824         if (enable) {
 825                 exynos_dp_enable_scrambling(dp);
 826
 827                 exynos_dp_read_byte_from_dpcd(dp,
 828                         DP_TRAINING_PATTERN_SET,
 829                         &data);
 830                 exynos_dp_write_byte_to_dpcd(dp,
 831                         DP_TRAINING_PATTERN_SET,
 832                         (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 833         } else {
 834                 exynos_dp_disable_scrambling(dp);
 835
 836                 exynos_dp_read_byte_from_dpcd(dp,
 837                         DP_TRAINING_PATTERN_SET,
 838                         &data);
 839                 exynos_dp_write_byte_to_dpcd(dp,
 840                         DP_TRAINING_PATTERN_SET,
 841                         (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
 842         }
 843 }
 844
 845 static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 846 {
 847         struct exynos_dp_device *dp = arg;
 848
 849         enum dp_irq_type irq_type;
 850
 851         irq_type = exynos_dp_get_irq_type(dp);
 852         switch (irq_type) {
 853         case DP_IRQ_TYPE_HP_CABLE_IN:
 854                 dev_dbg(dp->dev, "Received irq - cable in\n");
 855                 schedule_work(&dp->hotplug_work);
 856                 exynos_dp_clear_hotplug_interrupts(dp);
 857                 break;
 858         case DP_IRQ_TYPE_HP_CABLE_OUT:
 859                 dev_dbg(dp->dev, "Received irq - cable out\n");
 860                 exynos_dp_clear_hotplug_interrupts(dp);
 861                 break;
 862         case DP_IRQ_TYPE_HP_CHANGE:
 863                 /*
 864                  * We get these change notifications once in a while, but there
 865                  * is nothing we can do with them. Just ignore it for now and
 866                  * only handle cable changes.
 867                  */
 868                 dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
 869                 exynos_dp_clear_hotplug_interrupts(dp);
 870                 break;
 871         default:
 872                 dev_err(dp->dev, "Received irq - unknown type!\n");
 873                 break;
 874         }
 875         return IRQ_HANDLED;
 876 }
 877
 878 static void exynos_dp_hotplug(struct work_struct *work)
 879 {
 880         struct exynos_dp_device *dp;
 881
 882         dp = container_of(work, struct exynos_dp_device, hotplug_work);
 883
 884         if (dp->drm_dev)
 885                 drm_helper_hpd_irq_event(dp->drm_dev);
 886 }
 887
 888 static void exynos_dp_commit(struct exynos_drm_display *display)
 889 {
 890         struct exynos_dp_device *dp = display_to_dp(display);
 891         int ret;
 892
 893         /* Keep the panel disabled while we configure video */
 894         if (dp->panel) {
 895                 if (drm_panel_disable(dp->panel))
 896                         DRM_ERROR("failed to disable the panel\n");
 897         }
 898
 899         ret = exynos_dp_detect_hpd(dp);
 900         if (ret) {
 901                 /* Cable has been disconnected, we're done */
 902                 return;
 903         }
 904
 905         ret = exynos_dp_handle_edid(dp);
 906         if (ret) {
 907                 dev_err(dp->dev, "unable to handle edid\n");
 908                 return;
 909         }
 910
 911         ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
 912                                         dp->video_info->link_rate);
 913         if (ret) {
 914                 dev_err(dp->dev, "unable to do link train\n");
 915                 return;
 916         }
 917
 918         exynos_dp_enable_scramble(dp, 1);
 919         exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
 920         exynos_dp_enable_enhanced_mode(dp, 1);
 921
 922         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
 923         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
 924
 925         exynos_dp_init_video(dp);
 926         ret = exynos_dp_config_video(dp);
 927         if (ret)
 928                 dev_err(dp->dev, "unable to config video\n");
 929
 930         /* Safe to enable the panel now */
 931         if (dp->panel) {
 932                 if (drm_panel_enable(dp->panel))
 933                         DRM_ERROR("failed to enable the panel\n");
 934         }
 935 }
 936
 937 static enum drm_connector_status exynos_dp_detect(
 938                                 struct drm_connector *connector, bool force)
 939 {
 940         return connector_status_connected;
 941 }
 942
 943 static void exynos_dp_connector_destroy(struct drm_connector *connector)
 944 {
 945         drm_connector_unregister(connector);
 946         drm_connector_cleanup(connector);
 947 }
 948
 949 static struct drm_connector_funcs exynos_dp_connector_funcs = {
 950         .dpms = drm_helper_connector_dpms,
 951         .fill_modes = drm_helper_probe_single_connector_modes,
 952         .detect = exynos_dp_detect,
 953         .destroy = exynos_dp_connector_destroy,
 954 };
 955
 956 static int exynos_dp_get_modes(struct drm_connector *connector)
 957 {
 958         struct exynos_dp_device *dp = ctx_from_connector(connector);
 959         struct drm_display_mode *mode;
 960
 961         if (dp->panel)
 962                 return drm_panel_get_modes(dp->panel);
 963
 964         mode = drm_mode_create(connector->dev);
 965         if (!mode) {
 966                 DRM_ERROR("failed to create a new display mode.\n");
 967                 return 0;
 968         }
 969
 970         drm_display_mode_from_videomode(&dp->priv.vm, mode);
 971         mode->width_mm = dp->priv.width_mm;
 972         mode->height_mm = dp->priv.height_mm;
 973         connector->display_info.width_mm = mode->width_mm;
 974         connector->display_info.height_mm = mode->height_mm;
 975
 976         mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
 977         drm_mode_set_name(mode);
 978         drm_mode_probed_add(connector, mode);
 979
 980         return 1;
 981 }
 982
 983 static struct drm_encoder *exynos_dp_best_encoder(
 984                         struct drm_connector *connector)
 985 {
 986         struct exynos_dp_device *dp = ctx_from_connector(connector);
 987
 988         return dp->encoder;
 989 }
 990
 991 static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
 992         .get_modes = exynos_dp_get_modes,
 993         .best_encoder = exynos_dp_best_encoder,
 994 };
 995
 996 static bool find_bridge(const char *compat, struct bridge_init *bridge)
 997 {
 998         bridge->client = NULL;
 999         bridge->node = of_find_compatible_node(NULL, NULL, compat);
1000         if (!bridge->node)
1001                 return false;
1002
1003         bridge->client = of_find_i2c_device_by_node(bridge->node);
1004         if (!bridge->client)
1005                 return false;
1006
1007         return true;
1008 }
1009
1010 /* returns the number of bridges attached */
1011 static int exynos_drm_attach_lcd_bridge(struct drm_device *dev,
1012                 struct drm_encoder *encoder)
1013 {
1014         struct bridge_init bridge;
1015         int ret;
1016
1017         if (find_bridge("nxp,ptn3460", &bridge)) {
1018                 ret = ptn3460_init(dev, encoder, bridge.client, bridge.node);
1019                 if (!ret)
1020                         return 1;
1021         }
1022         return 0;
1023 }
1024
1025 static int exynos_dp_create_connector(struct exynos_drm_display *display,
1026                                 struct drm_encoder *encoder)
1027 {
1028         struct exynos_dp_device *dp = display_to_dp(display);
1029         struct drm_connector *connector = &dp->connector;
1030         int ret;
1031
1032         dp->encoder = encoder;
1033
1034         /* Pre-empt DP connector creation if there's a bridge */
1035         ret = exynos_drm_attach_lcd_bridge(dp->drm_dev, encoder);
1036         if (ret)
1037                 return 0;
1038
1039         connector->polled = DRM_CONNECTOR_POLL_HPD;
1040
1041         ret = drm_connector_init(dp->drm_dev, connector,
1042                         &exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP);
1043         if (ret) {
1044                 DRM_ERROR("Failed to initialize connector with drm\n");
1045                 return ret;
1046         }
1047
1048         drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
1049         drm_connector_register(connector);
1050         drm_mode_connector_attach_encoder(connector, encoder);
1051
1052         if (dp->panel)
1053                 ret = drm_panel_attach(dp->panel, &dp->connector);
1054
1055         return ret;
1056 }
1057
1058 static void exynos_dp_phy_init(struct exynos_dp_device *dp)
1059 {
1060         if (dp->phy)
1061                 phy_power_on(dp->phy);
1062 }
1063
1064 static void exynos_dp_phy_exit(struct exynos_dp_device *dp)
1065 {
1066         if (dp->phy)
1067                 phy_power_off(dp->phy);
1068 }
1069
1070 static void exynos_dp_poweron(struct exynos_drm_display *display)
1071 {
1072         struct exynos_dp_device *dp = display_to_dp(display);
1073
1074         if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1075                 return;
1076
1077         if (dp->panel) {
1078                 if (drm_panel_prepare(dp->panel)) {
1079                         DRM_ERROR("failed to setup the panel\n");
1080                         return;
1081                 }
1082         }
1083
1084         clk_prepare_enable(dp->clock);
1085         exynos_dp_phy_init(dp);
1086         exynos_dp_init_dp(dp);
1087         enable_irq(dp->irq);
1088         exynos_dp_commit(display);
1089 }
1090
1091 static void exynos_dp_poweroff(struct exynos_drm_display *display)
1092 {
1093         struct exynos_dp_device *dp = display_to_dp(display);
1094
1095         if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1096                 return;
1097
1098         if (dp->panel) {
1099                 if (drm_panel_disable(dp->panel)) {
1100                         DRM_ERROR("failed to disable the panel\n");
1101                         return;
1102                 }
1103         }
1104
1105         disable_irq(dp->irq);
1106         flush_work(&dp->hotplug_work);
1107         exynos_dp_phy_exit(dp);
1108         clk_disable_unprepare(dp->clock);
1109
1110         if (dp->panel) {
1111                 if (drm_panel_unprepare(dp->panel))
1112                         DRM_ERROR("failed to turnoff the panel\n");
1113         }
1114 }
1115
1116 static void exynos_dp_dpms(struct exynos_drm_display *display, int mode)
1117 {
1118         struct exynos_dp_device *dp = display_to_dp(display);
1119
1120         switch (mode) {
1121         case DRM_MODE_DPMS_ON:
1122                 exynos_dp_poweron(display);
1123                 break;
1124         case DRM_MODE_DPMS_STANDBY:
1125         case DRM_MODE_DPMS_SUSPEND:
1126         case DRM_MODE_DPMS_OFF:
1127                 exynos_dp_poweroff(display);
1128                 break;
1129         default:
1130                 break;
1131         }
1132         dp->dpms_mode = mode;
1133 }
1134
1135 static struct exynos_drm_display_ops exynos_dp_display_ops = {
1136         .create_connector = exynos_dp_create_connector,
1137         .dpms = exynos_dp_dpms,
1138         .commit = exynos_dp_commit,
1139 };
1140
1141 static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
1142 {
1143         struct device_node *dp_node = dev->of_node;
1144         struct video_info *dp_video_config;
1145
1146         dp_video_config = devm_kzalloc(dev,
1147                                 sizeof(*dp_video_config), GFP_KERNEL);
1148         if (!dp_video_config)
1149                 return ERR_PTR(-ENOMEM);
1150
1151         dp_video_config->h_sync_polarity =
1152                 of_property_read_bool(dp_node, "hsync-active-high");
1153
1154         dp_video_config->v_sync_polarity =
1155                 of_property_read_bool(dp_node, "vsync-active-high");
1156
1157         dp_video_config->interlaced =
1158                 of_property_read_bool(dp_node, "interlaced");
1159
1160         if (of_property_read_u32(dp_node, "samsung,color-space",
1161                                 &dp_video_config->color_space)) {
1162                 dev_err(dev, "failed to get color-space\n");
1163                 return ERR_PTR(-EINVAL);
1164         }
1165
1166         if (of_property_read_u32(dp_node, "samsung,dynamic-range",
1167                                 &dp_video_config->dynamic_range)) {
1168                 dev_err(dev, "failed to get dynamic-range\n");
1169                 return ERR_PTR(-EINVAL);
1170         }
1171
1172         if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1173                                 &dp_video_config->ycbcr_coeff)) {
1174                 dev_err(dev, "failed to get ycbcr-coeff\n");
1175                 return ERR_PTR(-EINVAL);
1176         }
1177
1178         if (of_property_read_u32(dp_node, "samsung,color-depth",
1179                                 &dp_video_config->color_depth)) {
1180                 dev_err(dev, "failed to get color-depth\n");
1181                 return ERR_PTR(-EINVAL);
1182         }
1183
1184         if (of_property_read_u32(dp_node, "samsung,link-rate",
1185                                 &dp_video_config->link_rate)) {
1186                 dev_err(dev, "failed to get link-rate\n");
1187                 return ERR_PTR(-EINVAL);
1188         }
1189
1190         if (of_property_read_u32(dp_node, "samsung,lane-count",
1191                                 &dp_video_config->lane_count)) {
1192                 dev_err(dev, "failed to get lane-count\n");
1193                 return ERR_PTR(-EINVAL);
1194         }
1195
1196         return dp_video_config;
1197 }
1198
1199 static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
1200 {
1201         int ret;
1202
1203         ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
1204                         OF_USE_NATIVE_MODE);
1205         if (ret) {
1206                 DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
1207                 return ret;
1208         }
1209         return 0;
1210 }
1211
1212 static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
1213 {
1214         struct exynos_dp_device *dp = dev_get_drvdata(dev);
1215         struct platform_device *pdev = to_platform_device(dev);
1216         struct drm_device *drm_dev = data;
1217         struct resource *res;
1218         unsigned int irq_flags;
1219         int ret = 0;
1220
1221         dp->dev = &pdev->dev;
1222         dp->dpms_mode = DRM_MODE_DPMS_OFF;
1223
1224         dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev);
1225         if (IS_ERR(dp->video_info))
1226                 return PTR_ERR(dp->video_info);
1227
1228         dp->phy = devm_phy_get(dp->dev, "dp");
1229         if (IS_ERR(dp->phy)) {
1230                 dev_err(dp->dev, "no DP phy configured\n");
1231                 ret = PTR_ERR(dp->phy);
1232                 if (ret) {
1233                         /*
1234                          * phy itself is not enabled, so we can move forward
1235                          * assigning NULL to phy pointer.
1236                          */
1237                         if (ret == -ENOSYS || ret == -ENODEV)
1238                                 dp->phy = NULL;
1239                         else
1240                                 return ret;
1241                 }
1242         }
1243
1244         if (!dp->panel) {
1245                 ret = exynos_dp_dt_parse_panel(dp);
1246                 if (ret)
1247                         return ret;
1248         }
1249
1250         dp->clock = devm_clk_get(&pdev->dev, "dp");
1251         if (IS_ERR(dp->clock)) {
1252                 dev_err(&pdev->dev, "failed to get clock\n");
1253                 return PTR_ERR(dp->clock);
1254         }
1255
1256         clk_prepare_enable(dp->clock);
1257
1258         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1259
1260         dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
1261         if (IS_ERR(dp->reg_base))
1262                 return PTR_ERR(dp->reg_base);
1263
1264         dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
1265
1266         if (gpio_is_valid(dp->hpd_gpio)) {
1267                 /*
1268                  * Set up the hotplug GPIO from the device tree as an interrupt.
1269                  * Simply specifying a different interrupt in the device tree
1270                  * doesn't work since we handle hotplug rather differently when
1271                  * using a GPIO.  We also need the actual GPIO specifier so
1272                  * that we can get the current state of the GPIO.
1273                  */
1274                 ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,
1275                                             "hpd_gpio");
1276                 if (ret) {
1277                         dev_err(&pdev->dev, "failed to get hpd gpio\n");
1278                         return ret;
1279                 }
1280                 dp->irq = gpio_to_irq(dp->hpd_gpio);
1281                 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1282         } else {
1283                 dp->hpd_gpio = -ENODEV;
1284                 dp->irq = platform_get_irq(pdev, 0);
1285                 irq_flags = 0;
1286         }
1287
1288         if (dp->irq == -ENXIO) {
1289                 dev_err(&pdev->dev, "failed to get irq\n");
1290                 return -ENODEV;
1291         }
1292
1293         INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
1294
1295         exynos_dp_phy_init(dp);
1296
1297         exynos_dp_init_dp(dp);
1298
1299         ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
1300                         irq_flags, "exynos-dp", dp);
1301         if (ret) {
1302                 dev_err(&pdev->dev, "failed to request irq\n");
1303                 return ret;
1304         }
1305         disable_irq(dp->irq);
1306
1307         dp->drm_dev = drm_dev;
1308
1309         return exynos_drm_create_enc_conn(drm_dev, &dp->display);
1310 }
1311
1312 static void exynos_dp_unbind(struct device *dev, struct device *master,
1313                                 void *data)
1314 {
1315         struct exynos_dp_device *dp = dev_get_drvdata(dev);
1316
1317         exynos_dp_dpms(&dp->display, DRM_MODE_DPMS_OFF);
1318 }
1319
1320 static const struct component_ops exynos_dp_ops = {
1321         .bind   = exynos_dp_bind,
1322         .unbind = exynos_dp_unbind,
1323 };
1324
1325 static int exynos_dp_probe(struct platform_device *pdev)
1326 {
1327         struct device *dev = &pdev->dev;
1328         struct device_node *panel_node;
1329         struct exynos_dp_device *dp;
1330         int ret;
1331
1332         dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
1333                                 GFP_KERNEL);
1334         if (!dp)
1335                 return -ENOMEM;
1336
1337         dp->display.type = EXYNOS_DISPLAY_TYPE_LCD;
1338         dp->display.ops = &exynos_dp_display_ops;
1339         platform_set_drvdata(pdev, dp);
1340
1341         ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR,
1342                                         dp->display.type);
1343         if (ret)
1344                 return ret;
1345
1346         panel_node = of_parse_phandle(dev->of_node, "panel", 0);
1347         if (panel_node) {
1348                 dp->panel = of_drm_find_panel(panel_node);
1349                 of_node_put(panel_node);
1350                 if (!dp->panel)
1351                         return -EPROBE_DEFER;
1352         }
1353
1354         ret = component_add(&pdev->dev, &exynos_dp_ops);
1355         if (ret)
1356                 exynos_drm_component_del(&pdev->dev,
1357                                                 EXYNOS_DEVICE_TYPE_CONNECTOR);
1358
1359         return ret;
1360 }
1361
1362 static int exynos_dp_remove(struct platform_device *pdev)
1363 {
1364         component_del(&pdev->dev, &exynos_dp_ops);
1365         exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
1366
1367         return 0;
1368 }
1369
1370 #ifdef CONFIG_PM_SLEEP
1371 static int exynos_dp_suspend(struct device *dev)
1372 {
1373         struct exynos_dp_device *dp = dev_get_drvdata(dev);
1374
1375         exynos_dp_dpms(&dp->display, DRM_MODE_DPMS_OFF);
1376         return 0;
1377 }
1378
1379 static int exynos_dp_resume(struct device *dev)
1380 {
1381         struct exynos_dp_device *dp = dev_get_drvdata(dev);
1382
1383         exynos_dp_dpms(&dp->display, DRM_MODE_DPMS_ON);
1384         return 0;
1385 }
1386 #endif
1387
1388 static const struct dev_pm_ops exynos_dp_pm_ops = {
1389         SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
1390 };
1391
1392 static const struct of_device_id exynos_dp_match[] = {
1393         { .compatible = "samsung,exynos5-dp" },
1394         {},
1395 };
1396 MODULE_DEVICE_TABLE(of, exynos_dp_match);
1397
1398 struct platform_driver dp_driver = {
1399         .probe          = exynos_dp_probe,
1400         .remove         = exynos_dp_remove,
1401         .driver         = {
1402                 .name   = "exynos-dp",
1403                 .owner  = THIS_MODULE,
1404                 .pm     = &exynos_dp_pm_ops,
1405                 .of_match_table = exynos_dp_match,
1406         },
1407 };
1408
1409 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1410 MODULE_DESCRIPTION("Samsung SoC DP Driver");
1411 MODULE_LICENSE("GPL v2");