2 * Samsung SoC DP (Display Port) interface driver.
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
18 #include <linux/interrupt.h>
20 #include <linux/of_gpio.h>
21 #include <linux/gpio.h>
22 #include <linux/component.h>
23 #include <linux/phy/phy.h>
24 #include <video/of_display_timing.h>
25 #include <video/of_videomode.h>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_crtc_helper.h>
30 #include <drm/drm_panel.h>
31 #include <drm/bridge/ptn3460.h>
33 #include "exynos_drm_drv.h"
34 #include "exynos_dp_core.h"
36 #define ctx_from_connector(c) container_of(c, struct exynos_dp_device, \
40 struct i2c_client *client;
41 struct device_node *node;
44 static void exynos_dp_init_dp(struct exynos_dp_device *dp)
48 exynos_dp_swreset(dp);
50 exynos_dp_init_analog_param(dp);
51 exynos_dp_init_interrupt(dp);
53 /* SW defined function Normal operation */
54 exynos_dp_enable_sw_function(dp);
56 exynos_dp_config_interrupt(dp);
57 exynos_dp_init_analog_func(dp);
59 exynos_dp_init_hpd(dp);
60 exynos_dp_init_aux(dp);
63 static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
67 while (exynos_dp_get_plug_in_status(dp) != 0) {
69 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
70 dev_err(dp->dev, "failed to get hpd plug status\n");
79 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
82 unsigned char sum = 0;
84 for (i = 0; i < EDID_BLOCK_LENGTH; i++)
85 sum = sum + edid_data[i];
90 static int exynos_dp_read_edid(struct exynos_dp_device *dp)
92 unsigned char edid[EDID_BLOCK_LENGTH * 2];
93 unsigned int extend_block = 0;
95 unsigned char test_vector;
99 * EDID device address is 0x50.
100 * However, if necessary, you must have set upper address
101 * into E-EDID in I2C device, 0x30.
104 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
105 retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
111 if (extend_block > 0) {
112 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
115 retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
118 &edid[EDID_HEADER_PATTERN]);
120 dev_err(dp->dev, "EDID Read failed!\n");
123 sum = exynos_dp_calc_edid_check_sum(edid);
125 dev_err(dp->dev, "EDID bad checksum!\n");
129 /* Read additional EDID data */
130 retval = exynos_dp_read_bytes_from_i2c(dp,
131 I2C_EDID_DEVICE_ADDR,
134 &edid[EDID_BLOCK_LENGTH]);
136 dev_err(dp->dev, "EDID Read failed!\n");
139 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
141 dev_err(dp->dev, "EDID bad checksum!\n");
145 exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
147 if (test_vector & DP_TEST_LINK_EDID_READ) {
148 exynos_dp_write_byte_to_dpcd(dp,
149 DP_TEST_EDID_CHECKSUM,
150 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
151 exynos_dp_write_byte_to_dpcd(dp,
153 DP_TEST_EDID_CHECKSUM_WRITE);
156 dev_info(dp->dev, "EDID data does not include any extensions.\n");
159 retval = exynos_dp_read_bytes_from_i2c(dp,
160 I2C_EDID_DEVICE_ADDR,
163 &edid[EDID_HEADER_PATTERN]);
165 dev_err(dp->dev, "EDID Read failed!\n");
168 sum = exynos_dp_calc_edid_check_sum(edid);
170 dev_err(dp->dev, "EDID bad checksum!\n");
174 exynos_dp_read_byte_from_dpcd(dp,
177 if (test_vector & DP_TEST_LINK_EDID_READ) {
178 exynos_dp_write_byte_to_dpcd(dp,
179 DP_TEST_EDID_CHECKSUM,
180 edid[EDID_CHECKSUM]);
181 exynos_dp_write_byte_to_dpcd(dp,
183 DP_TEST_EDID_CHECKSUM_WRITE);
187 dev_err(dp->dev, "EDID Read success!\n");
191 static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
197 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
198 retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
204 for (i = 0; i < 3; i++) {
205 retval = exynos_dp_read_edid(dp);
213 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
218 exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
221 exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
222 DP_LANE_COUNT_ENHANCED_FRAME_EN |
223 DPCD_LANE_COUNT_SET(data));
225 exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
226 DPCD_LANE_COUNT_SET(data));
229 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
234 exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
235 retval = DPCD_ENHANCED_FRAME_CAP(data);
240 static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
244 data = exynos_dp_is_enhanced_mode_available(dp);
245 exynos_dp_enable_rx_to_enhanced_mode(dp, data);
246 exynos_dp_enable_enhanced_mode(dp, data);
249 static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
251 exynos_dp_set_training_pattern(dp, DP_NONE);
253 exynos_dp_write_byte_to_dpcd(dp,
254 DP_TRAINING_PATTERN_SET,
255 DP_TRAINING_PATTERN_DISABLE);
258 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
259 int pre_emphasis, int lane)
263 exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
266 exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
270 exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
274 exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
279 static int exynos_dp_link_start(struct exynos_dp_device *dp)
282 int lane, lane_count, pll_tries, retval;
284 lane_count = dp->link_train.lane_count;
286 dp->link_train.lt_state = CLOCK_RECOVERY;
287 dp->link_train.eq_loop = 0;
289 for (lane = 0; lane < lane_count; lane++)
290 dp->link_train.cr_loop[lane] = 0;
292 /* Set link rate and count as you want to establish*/
293 exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
294 exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
296 /* Setup RX configuration */
297 buf[0] = dp->link_train.link_rate;
298 buf[1] = dp->link_train.lane_count;
299 retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
304 /* Set TX pre-emphasis to minimum */
305 for (lane = 0; lane < lane_count; lane++)
306 exynos_dp_set_lane_lane_pre_emphasis(dp,
307 PRE_EMPHASIS_LEVEL_0, lane);
309 /* Wait for PLL lock */
311 while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
312 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
313 dev_err(dp->dev, "Wait for PLL lock timed out\n");
318 usleep_range(90, 120);
321 /* Set training pattern 1 */
322 exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
324 /* Set RX training pattern */
325 retval = exynos_dp_write_byte_to_dpcd(dp,
326 DP_TRAINING_PATTERN_SET,
327 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
331 for (lane = 0; lane < lane_count; lane++)
332 buf[lane] = DP_TRAIN_PRE_EMPHASIS_0 |
333 DP_TRAIN_VOLTAGE_SWING_400;
335 retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
341 static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
343 int shift = (lane & 1) * 4;
344 u8 link_value = link_status[lane>>1];
346 return (link_value >> shift) & 0xf;
349 static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
354 for (lane = 0; lane < lane_count; lane++) {
355 lane_status = exynos_dp_get_lane_status(link_status, lane);
356 if ((lane_status & DP_LANE_CR_DONE) == 0)
362 static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
368 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
371 for (lane = 0; lane < lane_count; lane++) {
372 lane_status = exynos_dp_get_lane_status(link_status, lane);
373 lane_status &= DP_CHANNEL_EQ_BITS;
374 if (lane_status != DP_CHANNEL_EQ_BITS)
381 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
384 int shift = (lane & 1) * 4;
385 u8 link_value = adjust_request[lane>>1];
387 return (link_value >> shift) & 0x3;
390 static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
391 u8 adjust_request[2],
394 int shift = (lane & 1) * 4;
395 u8 link_value = adjust_request[lane>>1];
397 return ((link_value >> shift) & 0xc) >> 2;
400 static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
401 u8 training_lane_set, int lane)
405 exynos_dp_set_lane0_link_training(dp, training_lane_set);
408 exynos_dp_set_lane1_link_training(dp, training_lane_set);
412 exynos_dp_set_lane2_link_training(dp, training_lane_set);
416 exynos_dp_set_lane3_link_training(dp, training_lane_set);
421 static unsigned int exynos_dp_get_lane_link_training(
422 struct exynos_dp_device *dp,
429 reg = exynos_dp_get_lane0_link_training(dp);
432 reg = exynos_dp_get_lane1_link_training(dp);
435 reg = exynos_dp_get_lane2_link_training(dp);
438 reg = exynos_dp_get_lane3_link_training(dp);
448 static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
450 exynos_dp_training_pattern_dis(dp);
451 exynos_dp_set_enhanced_mode(dp);
453 dp->link_train.lt_state = FAILED;
456 static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
457 u8 adjust_request[2])
459 int lane, lane_count;
460 u8 voltage_swing, pre_emphasis, training_lane;
462 lane_count = dp->link_train.lane_count;
463 for (lane = 0; lane < lane_count; lane++) {
464 voltage_swing = exynos_dp_get_adjust_request_voltage(
465 adjust_request, lane);
466 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
467 adjust_request, lane);
468 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
469 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
471 if (voltage_swing == VOLTAGE_LEVEL_3)
472 training_lane |= DP_TRAIN_MAX_SWING_REACHED;
473 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
474 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
476 dp->link_train.training_lane[lane] = training_lane;
480 static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
482 int lane, lane_count, retval;
483 u8 voltage_swing, pre_emphasis, training_lane;
484 u8 link_status[2], adjust_request[2];
486 usleep_range(100, 101);
488 lane_count = dp->link_train.lane_count;
490 retval = exynos_dp_read_bytes_from_dpcd(dp,
491 DP_LANE0_1_STATUS, 2, link_status);
495 retval = exynos_dp_read_bytes_from_dpcd(dp,
496 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
500 if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
501 /* set training pattern 2 for EQ */
502 exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
504 retval = exynos_dp_write_byte_to_dpcd(dp,
505 DP_TRAINING_PATTERN_SET,
506 DP_LINK_SCRAMBLING_DISABLE |
507 DP_TRAINING_PATTERN_2);
511 dev_info(dp->dev, "Link Training Clock Recovery success\n");
512 dp->link_train.lt_state = EQUALIZER_TRAINING;
514 for (lane = 0; lane < lane_count; lane++) {
515 training_lane = exynos_dp_get_lane_link_training(
517 voltage_swing = exynos_dp_get_adjust_request_voltage(
518 adjust_request, lane);
519 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
520 adjust_request, lane);
522 if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
524 DPCD_PRE_EMPHASIS_GET(training_lane) ==
526 dp->link_train.cr_loop[lane]++;
528 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
529 voltage_swing == VOLTAGE_LEVEL_3 ||
530 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
531 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
532 dp->link_train.cr_loop[lane],
533 voltage_swing, pre_emphasis);
534 exynos_dp_reduce_link_rate(dp);
540 exynos_dp_get_adjust_training_lane(dp, adjust_request);
542 for (lane = 0; lane < lane_count; lane++)
543 exynos_dp_set_lane_link_training(dp,
544 dp->link_train.training_lane[lane], lane);
546 retval = exynos_dp_write_bytes_to_dpcd(dp,
547 DP_TRAINING_LANE0_SET, lane_count,
548 dp->link_train.training_lane);
555 static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
557 int lane, lane_count, retval;
559 u8 link_align, link_status[2], adjust_request[2];
561 usleep_range(400, 401);
563 lane_count = dp->link_train.lane_count;
565 retval = exynos_dp_read_bytes_from_dpcd(dp,
566 DP_LANE0_1_STATUS, 2, link_status);
570 if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
571 exynos_dp_reduce_link_rate(dp);
575 retval = exynos_dp_read_bytes_from_dpcd(dp,
576 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
580 retval = exynos_dp_read_byte_from_dpcd(dp,
581 DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
585 exynos_dp_get_adjust_training_lane(dp, adjust_request);
587 if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) {
588 /* traing pattern Set to Normal */
589 exynos_dp_training_pattern_dis(dp);
591 dev_info(dp->dev, "Link Training success!\n");
593 exynos_dp_get_link_bandwidth(dp, ®);
594 dp->link_train.link_rate = reg;
595 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
596 dp->link_train.link_rate);
598 exynos_dp_get_lane_count(dp, ®);
599 dp->link_train.lane_count = reg;
600 dev_dbg(dp->dev, "final lane count = %.2x\n",
601 dp->link_train.lane_count);
603 /* set enhanced mode if available */
604 exynos_dp_set_enhanced_mode(dp);
605 dp->link_train.lt_state = FINISHED;
611 dp->link_train.eq_loop++;
613 if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
614 dev_err(dp->dev, "EQ Max loop\n");
615 exynos_dp_reduce_link_rate(dp);
619 for (lane = 0; lane < lane_count; lane++)
620 exynos_dp_set_lane_link_training(dp,
621 dp->link_train.training_lane[lane], lane);
623 retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
624 lane_count, dp->link_train.training_lane);
629 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
635 * For DP rev.1.1, Maximum link rate of Main Link lanes
636 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
638 exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
642 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
648 * For DP rev.1.1, Maximum number of Main Link lanes
649 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
651 exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
652 *lane_count = DPCD_MAX_LANE_COUNT(data);
655 static void exynos_dp_init_training(struct exynos_dp_device *dp,
656 enum link_lane_count_type max_lane,
657 enum link_rate_type max_rate)
660 * MACRO_RST must be applied after the PLL_LOCK to avoid
661 * the DP inter pair skew issue for at least 10 us
663 exynos_dp_reset_macro(dp);
665 /* Initialize by reading RX's DPCD */
666 exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
667 exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
669 if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
670 (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
671 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
672 dp->link_train.link_rate);
673 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
676 if (dp->link_train.lane_count == 0) {
677 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
678 dp->link_train.lane_count);
679 dp->link_train.lane_count = (u8)LANE_COUNT1;
682 /* Setup TX lane count & rate */
683 if (dp->link_train.lane_count > max_lane)
684 dp->link_train.lane_count = max_lane;
685 if (dp->link_train.link_rate > max_rate)
686 dp->link_train.link_rate = max_rate;
688 /* All DP analog module power up */
689 exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
692 static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
694 int retval = 0, training_finished = 0;
696 dp->link_train.lt_state = START;
699 while (!retval && !training_finished) {
700 switch (dp->link_train.lt_state) {
702 retval = exynos_dp_link_start(dp);
704 dev_err(dp->dev, "LT link start failed!\n");
707 retval = exynos_dp_process_clock_recovery(dp);
709 dev_err(dp->dev, "LT CR failed!\n");
711 case EQUALIZER_TRAINING:
712 retval = exynos_dp_process_equalizer_training(dp);
714 dev_err(dp->dev, "LT EQ failed!\n");
717 training_finished = 1;
724 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
729 static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
736 for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
737 exynos_dp_init_training(dp, count, bwtype);
738 retval = exynos_dp_sw_link_training(dp);
742 usleep_range(100, 110);
748 static int exynos_dp_config_video(struct exynos_dp_device *dp)
751 int timeout_loop = 0;
754 exynos_dp_config_video_slave_mode(dp);
756 exynos_dp_set_video_color_format(dp);
758 if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
759 dev_err(dp->dev, "PLL is not locked yet.\n");
765 if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
767 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
768 dev_err(dp->dev, "Timeout of video streamclk ok\n");
775 /* Set to use the register calculated M/N video */
776 exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
778 /* For video bist, Video timing must be generated by register */
779 exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
781 /* Disable video mute */
782 exynos_dp_enable_video_mute(dp, 0);
784 /* Configure video slave mode */
785 exynos_dp_enable_video_master(dp, 0);
788 exynos_dp_start_video(dp);
794 if (exynos_dp_is_video_stream_on(dp) == 0) {
798 } else if (done_count) {
801 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
802 dev_err(dp->dev, "Timeout of video streamclk ok\n");
806 usleep_range(1000, 1001);
810 dev_err(dp->dev, "Video stream is not detected!\n");
815 static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
820 exynos_dp_enable_scrambling(dp);
822 exynos_dp_read_byte_from_dpcd(dp,
823 DP_TRAINING_PATTERN_SET,
825 exynos_dp_write_byte_to_dpcd(dp,
826 DP_TRAINING_PATTERN_SET,
827 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
829 exynos_dp_disable_scrambling(dp);
831 exynos_dp_read_byte_from_dpcd(dp,
832 DP_TRAINING_PATTERN_SET,
834 exynos_dp_write_byte_to_dpcd(dp,
835 DP_TRAINING_PATTERN_SET,
836 (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
840 static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
842 struct exynos_dp_device *dp = arg;
844 enum dp_irq_type irq_type;
846 irq_type = exynos_dp_get_irq_type(dp);
848 case DP_IRQ_TYPE_HP_CABLE_IN:
849 dev_dbg(dp->dev, "Received irq - cable in\n");
850 schedule_work(&dp->hotplug_work);
851 exynos_dp_clear_hotplug_interrupts(dp);
853 case DP_IRQ_TYPE_HP_CABLE_OUT:
854 dev_dbg(dp->dev, "Received irq - cable out\n");
855 exynos_dp_clear_hotplug_interrupts(dp);
857 case DP_IRQ_TYPE_HP_CHANGE:
859 * We get these change notifications once in a while, but there
860 * is nothing we can do with them. Just ignore it for now and
861 * only handle cable changes.
863 dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
864 exynos_dp_clear_hotplug_interrupts(dp);
867 dev_err(dp->dev, "Received irq - unknown type!\n");
873 static void exynos_dp_hotplug(struct work_struct *work)
875 struct exynos_dp_device *dp;
877 dp = container_of(work, struct exynos_dp_device, hotplug_work);
880 drm_helper_hpd_irq_event(dp->drm_dev);
883 static void exynos_dp_commit(struct exynos_drm_display *display)
885 struct exynos_dp_device *dp = display->ctx;
888 /* Keep the panel disabled while we configure video */
890 if (drm_panel_disable(dp->panel))
891 DRM_ERROR("failed to disable the panel\n");
894 ret = exynos_dp_detect_hpd(dp);
896 /* Cable has been disconnected, we're done */
900 ret = exynos_dp_handle_edid(dp);
902 dev_err(dp->dev, "unable to handle edid\n");
906 ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
907 dp->video_info->link_rate);
909 dev_err(dp->dev, "unable to do link train\n");
913 exynos_dp_enable_scramble(dp, 1);
914 exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
915 exynos_dp_enable_enhanced_mode(dp, 1);
917 exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
918 exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
920 exynos_dp_init_video(dp);
921 ret = exynos_dp_config_video(dp);
923 dev_err(dp->dev, "unable to config video\n");
925 /* Safe to enable the panel now */
927 if (drm_panel_enable(dp->panel))
928 DRM_ERROR("failed to enable the panel\n");
932 static enum drm_connector_status exynos_dp_detect(
933 struct drm_connector *connector, bool force)
935 return connector_status_connected;
938 static void exynos_dp_connector_destroy(struct drm_connector *connector)
942 static struct drm_connector_funcs exynos_dp_connector_funcs = {
943 .dpms = drm_helper_connector_dpms,
944 .fill_modes = drm_helper_probe_single_connector_modes,
945 .detect = exynos_dp_detect,
946 .destroy = exynos_dp_connector_destroy,
949 static int exynos_dp_get_modes(struct drm_connector *connector)
951 struct exynos_dp_device *dp = ctx_from_connector(connector);
952 struct drm_display_mode *mode;
955 return drm_panel_get_modes(dp->panel);
957 mode = drm_mode_create(connector->dev);
959 DRM_ERROR("failed to create a new display mode.\n");
963 drm_display_mode_from_videomode(&dp->priv.vm, mode);
964 mode->width_mm = dp->priv.width_mm;
965 mode->height_mm = dp->priv.height_mm;
966 connector->display_info.width_mm = mode->width_mm;
967 connector->display_info.height_mm = mode->height_mm;
969 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
970 drm_mode_set_name(mode);
971 drm_mode_probed_add(connector, mode);
976 static struct drm_encoder *exynos_dp_best_encoder(
977 struct drm_connector *connector)
979 struct exynos_dp_device *dp = ctx_from_connector(connector);
984 static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
985 .get_modes = exynos_dp_get_modes,
986 .best_encoder = exynos_dp_best_encoder,
989 static bool find_bridge(const char *compat, struct bridge_init *bridge)
991 bridge->client = NULL;
992 bridge->node = of_find_compatible_node(NULL, NULL, compat);
996 bridge->client = of_find_i2c_device_by_node(bridge->node);
1003 /* returns the number of bridges attached */
1004 static int exynos_drm_attach_lcd_bridge(struct drm_device *dev,
1005 struct drm_encoder *encoder)
1007 struct bridge_init bridge;
1010 if (find_bridge("nxp,ptn3460", &bridge)) {
1011 ret = ptn3460_init(dev, encoder, bridge.client, bridge.node);
1018 static int exynos_dp_create_connector(struct exynos_drm_display *display,
1019 struct drm_encoder *encoder)
1021 struct exynos_dp_device *dp = display->ctx;
1022 struct drm_connector *connector = &dp->connector;
1025 dp->encoder = encoder;
1027 /* Pre-empt DP connector creation if there's a bridge */
1028 ret = exynos_drm_attach_lcd_bridge(dp->drm_dev, encoder);
1032 connector->polled = DRM_CONNECTOR_POLL_HPD;
1034 ret = drm_connector_init(dp->drm_dev, connector,
1035 &exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP);
1037 DRM_ERROR("Failed to initialize connector with drm\n");
1041 drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
1042 drm_connector_register(connector);
1043 drm_mode_connector_attach_encoder(connector, encoder);
1046 ret = drm_panel_attach(dp->panel, &dp->connector);
1051 static void exynos_dp_phy_init(struct exynos_dp_device *dp)
1054 phy_power_on(dp->phy);
1055 } else if (dp->phy_addr) {
1058 reg = __raw_readl(dp->phy_addr);
1059 reg |= dp->enable_mask;
1060 __raw_writel(reg, dp->phy_addr);
1064 static void exynos_dp_phy_exit(struct exynos_dp_device *dp)
1067 phy_power_off(dp->phy);
1068 } else if (dp->phy_addr) {
1071 reg = __raw_readl(dp->phy_addr);
1072 reg &= ~(dp->enable_mask);
1073 __raw_writel(reg, dp->phy_addr);
1077 static void exynos_dp_poweron(struct exynos_drm_display *display)
1079 struct exynos_dp_device *dp = display->ctx;
1081 if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1085 if (drm_panel_prepare(dp->panel)) {
1086 DRM_ERROR("failed to setup the panel\n");
1091 clk_prepare_enable(dp->clock);
1092 exynos_dp_phy_init(dp);
1093 exynos_dp_init_dp(dp);
1094 enable_irq(dp->irq);
1095 exynos_dp_commit(display);
1098 static void exynos_dp_poweroff(struct exynos_drm_display *display)
1100 struct exynos_dp_device *dp = display->ctx;
1102 if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1106 if (drm_panel_disable(dp->panel)) {
1107 DRM_ERROR("failed to disable the panel\n");
1112 disable_irq(dp->irq);
1113 flush_work(&dp->hotplug_work);
1114 exynos_dp_phy_exit(dp);
1115 clk_disable_unprepare(dp->clock);
1118 if (drm_panel_unprepare(dp->panel))
1119 DRM_ERROR("failed to turnoff the panel\n");
1123 static void exynos_dp_dpms(struct exynos_drm_display *display, int mode)
1125 struct exynos_dp_device *dp = display->ctx;
1128 case DRM_MODE_DPMS_ON:
1129 exynos_dp_poweron(display);
1131 case DRM_MODE_DPMS_STANDBY:
1132 case DRM_MODE_DPMS_SUSPEND:
1133 case DRM_MODE_DPMS_OFF:
1134 exynos_dp_poweroff(display);
1139 dp->dpms_mode = mode;
1142 static struct exynos_drm_display_ops exynos_dp_display_ops = {
1143 .create_connector = exynos_dp_create_connector,
1144 .dpms = exynos_dp_dpms,
1145 .commit = exynos_dp_commit,
1148 static struct exynos_drm_display exynos_dp_display = {
1149 .type = EXYNOS_DISPLAY_TYPE_LCD,
1150 .ops = &exynos_dp_display_ops,
1153 static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
1155 struct device_node *dp_node = dev->of_node;
1156 struct video_info *dp_video_config;
1158 dp_video_config = devm_kzalloc(dev,
1159 sizeof(*dp_video_config), GFP_KERNEL);
1160 if (!dp_video_config)
1161 return ERR_PTR(-ENOMEM);
1163 dp_video_config->h_sync_polarity =
1164 of_property_read_bool(dp_node, "hsync-active-high");
1166 dp_video_config->v_sync_polarity =
1167 of_property_read_bool(dp_node, "vsync-active-high");
1169 dp_video_config->interlaced =
1170 of_property_read_bool(dp_node, "interlaced");
1172 if (of_property_read_u32(dp_node, "samsung,color-space",
1173 &dp_video_config->color_space)) {
1174 dev_err(dev, "failed to get color-space\n");
1175 return ERR_PTR(-EINVAL);
1178 if (of_property_read_u32(dp_node, "samsung,dynamic-range",
1179 &dp_video_config->dynamic_range)) {
1180 dev_err(dev, "failed to get dynamic-range\n");
1181 return ERR_PTR(-EINVAL);
1184 if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1185 &dp_video_config->ycbcr_coeff)) {
1186 dev_err(dev, "failed to get ycbcr-coeff\n");
1187 return ERR_PTR(-EINVAL);
1190 if (of_property_read_u32(dp_node, "samsung,color-depth",
1191 &dp_video_config->color_depth)) {
1192 dev_err(dev, "failed to get color-depth\n");
1193 return ERR_PTR(-EINVAL);
1196 if (of_property_read_u32(dp_node, "samsung,link-rate",
1197 &dp_video_config->link_rate)) {
1198 dev_err(dev, "failed to get link-rate\n");
1199 return ERR_PTR(-EINVAL);
1202 if (of_property_read_u32(dp_node, "samsung,lane-count",
1203 &dp_video_config->lane_count)) {
1204 dev_err(dev, "failed to get lane-count\n");
1205 return ERR_PTR(-EINVAL);
1208 return dp_video_config;
1211 static int exynos_dp_dt_parse_phydata(struct exynos_dp_device *dp)
1213 struct device_node *dp_phy_node = of_node_get(dp->dev->of_node);
1217 dp_phy_node = of_find_node_by_name(dp_phy_node, "dptx-phy");
1219 dp->phy = devm_phy_get(dp->dev, "dp");
1220 return PTR_ERR_OR_ZERO(dp->phy);
1223 if (of_property_read_u32(dp_phy_node, "reg", &phy_base)) {
1224 dev_err(dp->dev, "failed to get reg for dptx-phy\n");
1229 if (of_property_read_u32(dp_phy_node, "samsung,enable-mask",
1230 &dp->enable_mask)) {
1231 dev_err(dp->dev, "failed to get enable-mask for dptx-phy\n");
1236 dp->phy_addr = ioremap(phy_base, SZ_4);
1237 if (!dp->phy_addr) {
1238 dev_err(dp->dev, "failed to ioremap dp-phy\n");
1244 of_node_put(dp_phy_node);
1249 static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
1253 ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
1254 OF_USE_NATIVE_MODE);
1256 DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
1262 static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
1264 struct platform_device *pdev = to_platform_device(dev);
1265 struct drm_device *drm_dev = data;
1266 struct resource *res;
1267 struct exynos_dp_device *dp = exynos_dp_display.ctx;
1268 unsigned int irq_flags;
1271 dp->dev = &pdev->dev;
1272 dp->dpms_mode = DRM_MODE_DPMS_OFF;
1274 dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev);
1275 if (IS_ERR(dp->video_info))
1276 return PTR_ERR(dp->video_info);
1278 ret = exynos_dp_dt_parse_phydata(dp);
1283 ret = exynos_dp_dt_parse_panel(dp);
1288 dp->clock = devm_clk_get(&pdev->dev, "dp");
1289 if (IS_ERR(dp->clock)) {
1290 dev_err(&pdev->dev, "failed to get clock\n");
1291 return PTR_ERR(dp->clock);
1294 clk_prepare_enable(dp->clock);
1296 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1298 dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
1299 if (IS_ERR(dp->reg_base))
1300 return PTR_ERR(dp->reg_base);
1302 dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
1304 if (gpio_is_valid(dp->hpd_gpio)) {
1306 * Set up the hotplug GPIO from the device tree as an interrupt.
1307 * Simply specifying a different interrupt in the device tree
1308 * doesn't work since we handle hotplug rather differently when
1309 * using a GPIO. We also need the actual GPIO specifier so
1310 * that we can get the current state of the GPIO.
1312 ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,
1315 dev_err(&pdev->dev, "failed to get hpd gpio\n");
1318 dp->irq = gpio_to_irq(dp->hpd_gpio);
1319 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1321 dp->hpd_gpio = -ENODEV;
1322 dp->irq = platform_get_irq(pdev, 0);
1326 if (dp->irq == -ENXIO) {
1327 dev_err(&pdev->dev, "failed to get irq\n");
1331 INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
1333 exynos_dp_phy_init(dp);
1335 exynos_dp_init_dp(dp);
1337 ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
1338 irq_flags, "exynos-dp", dp);
1340 dev_err(&pdev->dev, "failed to request irq\n");
1343 disable_irq(dp->irq);
1345 dp->drm_dev = drm_dev;
1347 platform_set_drvdata(pdev, &exynos_dp_display);
1349 return exynos_drm_create_enc_conn(drm_dev, &exynos_dp_display);
1352 static void exynos_dp_unbind(struct device *dev, struct device *master,
1355 struct exynos_drm_display *display = dev_get_drvdata(dev);
1356 struct exynos_dp_device *dp = display->ctx;
1357 struct drm_encoder *encoder = dp->encoder;
1359 exynos_dp_dpms(display, DRM_MODE_DPMS_OFF);
1361 encoder->funcs->destroy(encoder);
1362 drm_connector_cleanup(&dp->connector);
1365 static const struct component_ops exynos_dp_ops = {
1366 .bind = exynos_dp_bind,
1367 .unbind = exynos_dp_unbind,
1370 static int exynos_dp_probe(struct platform_device *pdev)
1372 struct device *dev = &pdev->dev;
1373 struct device_node *panel_node;
1374 struct exynos_dp_device *dp;
1377 ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR,
1378 exynos_dp_display.type);
1382 dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
1387 panel_node = of_parse_phandle(dev->of_node, "panel", 0);
1389 dp->panel = of_drm_find_panel(panel_node);
1390 of_node_put(panel_node);
1392 return -EPROBE_DEFER;
1395 exynos_dp_display.ctx = dp;
1397 ret = component_add(&pdev->dev, &exynos_dp_ops);
1399 exynos_drm_component_del(&pdev->dev,
1400 EXYNOS_DEVICE_TYPE_CONNECTOR);
1405 static int exynos_dp_remove(struct platform_device *pdev)
1407 component_del(&pdev->dev, &exynos_dp_ops);
1408 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
1413 #ifdef CONFIG_PM_SLEEP
1414 static int exynos_dp_suspend(struct device *dev)
1416 struct platform_device *pdev = to_platform_device(dev);
1417 struct exynos_drm_display *display = platform_get_drvdata(pdev);
1419 exynos_dp_dpms(display, DRM_MODE_DPMS_OFF);
1423 static int exynos_dp_resume(struct device *dev)
1425 struct platform_device *pdev = to_platform_device(dev);
1426 struct exynos_drm_display *display = platform_get_drvdata(pdev);
1428 exynos_dp_dpms(display, DRM_MODE_DPMS_ON);
1433 static const struct dev_pm_ops exynos_dp_pm_ops = {
1434 SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
1437 static const struct of_device_id exynos_dp_match[] = {
1438 { .compatible = "samsung,exynos5-dp" },
1441 MODULE_DEVICE_TABLE(of, exynos_dp_match);
1443 struct platform_driver dp_driver = {
1444 .probe = exynos_dp_probe,
1445 .remove = exynos_dp_remove,
1447 .name = "exynos-dp",
1448 .owner = THIS_MODULE,
1449 .pm = &exynos_dp_pm_ops,
1450 .of_match_table = exynos_dp_match,
1454 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1455 MODULE_DESCRIPTION("Samsung SoC DP Driver");
1456 MODULE_LICENSE("GPL v2");