2 * Samsung SoC DP (Display Port) interface driver.
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
18 #include <linux/interrupt.h>
20 #include <linux/of_gpio.h>
21 #include <linux/of_graph.h>
22 #include <linux/gpio.h>
23 #include <linux/component.h>
24 #include <linux/phy/phy.h>
25 #include <video/of_display_timing.h>
26 #include <video/of_videomode.h>
29 #include <drm/drm_crtc.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/drm_panel.h>
32 #include <drm/bridge/ptn3460.h>
34 #include "exynos_dp_core.h"
36 #define ctx_from_connector(c) container_of(c, struct exynos_dp_device, \
39 static inline struct exynos_dp_device *
40 display_to_dp(struct exynos_drm_display *d)
42 return container_of(d, struct exynos_dp_device, display);
46 struct i2c_client *client;
47 struct device_node *node;
50 static void exynos_dp_init_dp(struct exynos_dp_device *dp)
54 exynos_dp_swreset(dp);
56 exynos_dp_init_analog_param(dp);
57 exynos_dp_init_interrupt(dp);
59 /* SW defined function Normal operation */
60 exynos_dp_enable_sw_function(dp);
62 exynos_dp_config_interrupt(dp);
63 exynos_dp_init_analog_func(dp);
65 exynos_dp_init_hpd(dp);
66 exynos_dp_init_aux(dp);
69 static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
73 while (exynos_dp_get_plug_in_status(dp) != 0) {
75 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
76 dev_err(dp->dev, "failed to get hpd plug status\n");
85 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
88 unsigned char sum = 0;
90 for (i = 0; i < EDID_BLOCK_LENGTH; i++)
91 sum = sum + edid_data[i];
96 static int exynos_dp_read_edid(struct exynos_dp_device *dp)
98 unsigned char edid[EDID_BLOCK_LENGTH * 2];
99 unsigned int extend_block = 0;
101 unsigned char test_vector;
105 * EDID device address is 0x50.
106 * However, if necessary, you must have set upper address
107 * into E-EDID in I2C device, 0x30.
110 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
111 retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
117 if (extend_block > 0) {
118 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
121 retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
124 &edid[EDID_HEADER_PATTERN]);
126 dev_err(dp->dev, "EDID Read failed!\n");
129 sum = exynos_dp_calc_edid_check_sum(edid);
131 dev_err(dp->dev, "EDID bad checksum!\n");
135 /* Read additional EDID data */
136 retval = exynos_dp_read_bytes_from_i2c(dp,
137 I2C_EDID_DEVICE_ADDR,
140 &edid[EDID_BLOCK_LENGTH]);
142 dev_err(dp->dev, "EDID Read failed!\n");
145 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
147 dev_err(dp->dev, "EDID bad checksum!\n");
151 exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
153 if (test_vector & DP_TEST_LINK_EDID_READ) {
154 exynos_dp_write_byte_to_dpcd(dp,
155 DP_TEST_EDID_CHECKSUM,
156 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
157 exynos_dp_write_byte_to_dpcd(dp,
159 DP_TEST_EDID_CHECKSUM_WRITE);
162 dev_info(dp->dev, "EDID data does not include any extensions.\n");
165 retval = exynos_dp_read_bytes_from_i2c(dp,
166 I2C_EDID_DEVICE_ADDR,
169 &edid[EDID_HEADER_PATTERN]);
171 dev_err(dp->dev, "EDID Read failed!\n");
174 sum = exynos_dp_calc_edid_check_sum(edid);
176 dev_err(dp->dev, "EDID bad checksum!\n");
180 exynos_dp_read_byte_from_dpcd(dp,
183 if (test_vector & DP_TEST_LINK_EDID_READ) {
184 exynos_dp_write_byte_to_dpcd(dp,
185 DP_TEST_EDID_CHECKSUM,
186 edid[EDID_CHECKSUM]);
187 exynos_dp_write_byte_to_dpcd(dp,
189 DP_TEST_EDID_CHECKSUM_WRITE);
193 dev_err(dp->dev, "EDID Read success!\n");
197 static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
203 /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
204 retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
210 for (i = 0; i < 3; i++) {
211 retval = exynos_dp_read_edid(dp);
219 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
224 exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
227 exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
228 DP_LANE_COUNT_ENHANCED_FRAME_EN |
229 DPCD_LANE_COUNT_SET(data));
231 exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
232 DPCD_LANE_COUNT_SET(data));
235 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
240 exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
241 retval = DPCD_ENHANCED_FRAME_CAP(data);
246 static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
250 data = exynos_dp_is_enhanced_mode_available(dp);
251 exynos_dp_enable_rx_to_enhanced_mode(dp, data);
252 exynos_dp_enable_enhanced_mode(dp, data);
255 static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
257 exynos_dp_set_training_pattern(dp, DP_NONE);
259 exynos_dp_write_byte_to_dpcd(dp,
260 DP_TRAINING_PATTERN_SET,
261 DP_TRAINING_PATTERN_DISABLE);
264 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
265 int pre_emphasis, int lane)
269 exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
272 exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
276 exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
280 exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
285 static int exynos_dp_link_start(struct exynos_dp_device *dp)
288 int lane, lane_count, pll_tries, retval;
290 lane_count = dp->link_train.lane_count;
292 dp->link_train.lt_state = CLOCK_RECOVERY;
293 dp->link_train.eq_loop = 0;
295 for (lane = 0; lane < lane_count; lane++)
296 dp->link_train.cr_loop[lane] = 0;
298 /* Set link rate and count as you want to establish*/
299 exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
300 exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
302 /* Setup RX configuration */
303 buf[0] = dp->link_train.link_rate;
304 buf[1] = dp->link_train.lane_count;
305 retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
310 /* Set TX pre-emphasis to minimum */
311 for (lane = 0; lane < lane_count; lane++)
312 exynos_dp_set_lane_lane_pre_emphasis(dp,
313 PRE_EMPHASIS_LEVEL_0, lane);
315 /* Wait for PLL lock */
317 while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
318 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
319 dev_err(dp->dev, "Wait for PLL lock timed out\n");
324 usleep_range(90, 120);
327 /* Set training pattern 1 */
328 exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
330 /* Set RX training pattern */
331 retval = exynos_dp_write_byte_to_dpcd(dp,
332 DP_TRAINING_PATTERN_SET,
333 DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
337 for (lane = 0; lane < lane_count; lane++)
338 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
339 DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
341 retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
347 static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
349 int shift = (lane & 1) * 4;
350 u8 link_value = link_status[lane>>1];
352 return (link_value >> shift) & 0xf;
355 static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
360 for (lane = 0; lane < lane_count; lane++) {
361 lane_status = exynos_dp_get_lane_status(link_status, lane);
362 if ((lane_status & DP_LANE_CR_DONE) == 0)
368 static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
374 if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
377 for (lane = 0; lane < lane_count; lane++) {
378 lane_status = exynos_dp_get_lane_status(link_status, lane);
379 lane_status &= DP_CHANNEL_EQ_BITS;
380 if (lane_status != DP_CHANNEL_EQ_BITS)
387 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
390 int shift = (lane & 1) * 4;
391 u8 link_value = adjust_request[lane>>1];
393 return (link_value >> shift) & 0x3;
396 static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
397 u8 adjust_request[2],
400 int shift = (lane & 1) * 4;
401 u8 link_value = adjust_request[lane>>1];
403 return ((link_value >> shift) & 0xc) >> 2;
406 static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
407 u8 training_lane_set, int lane)
411 exynos_dp_set_lane0_link_training(dp, training_lane_set);
414 exynos_dp_set_lane1_link_training(dp, training_lane_set);
418 exynos_dp_set_lane2_link_training(dp, training_lane_set);
422 exynos_dp_set_lane3_link_training(dp, training_lane_set);
427 static unsigned int exynos_dp_get_lane_link_training(
428 struct exynos_dp_device *dp,
435 reg = exynos_dp_get_lane0_link_training(dp);
438 reg = exynos_dp_get_lane1_link_training(dp);
441 reg = exynos_dp_get_lane2_link_training(dp);
444 reg = exynos_dp_get_lane3_link_training(dp);
454 static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
456 exynos_dp_training_pattern_dis(dp);
457 exynos_dp_set_enhanced_mode(dp);
459 dp->link_train.lt_state = FAILED;
462 static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
463 u8 adjust_request[2])
465 int lane, lane_count;
466 u8 voltage_swing, pre_emphasis, training_lane;
468 lane_count = dp->link_train.lane_count;
469 for (lane = 0; lane < lane_count; lane++) {
470 voltage_swing = exynos_dp_get_adjust_request_voltage(
471 adjust_request, lane);
472 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
473 adjust_request, lane);
474 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
475 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
477 if (voltage_swing == VOLTAGE_LEVEL_3)
478 training_lane |= DP_TRAIN_MAX_SWING_REACHED;
479 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
480 training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
482 dp->link_train.training_lane[lane] = training_lane;
486 static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
488 int lane, lane_count, retval;
489 u8 voltage_swing, pre_emphasis, training_lane;
490 u8 link_status[2], adjust_request[2];
492 usleep_range(100, 101);
494 lane_count = dp->link_train.lane_count;
496 retval = exynos_dp_read_bytes_from_dpcd(dp,
497 DP_LANE0_1_STATUS, 2, link_status);
501 retval = exynos_dp_read_bytes_from_dpcd(dp,
502 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
506 if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
507 /* set training pattern 2 for EQ */
508 exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
510 retval = exynos_dp_write_byte_to_dpcd(dp,
511 DP_TRAINING_PATTERN_SET,
512 DP_LINK_SCRAMBLING_DISABLE |
513 DP_TRAINING_PATTERN_2);
517 dev_info(dp->dev, "Link Training Clock Recovery success\n");
518 dp->link_train.lt_state = EQUALIZER_TRAINING;
520 for (lane = 0; lane < lane_count; lane++) {
521 training_lane = exynos_dp_get_lane_link_training(
523 voltage_swing = exynos_dp_get_adjust_request_voltage(
524 adjust_request, lane);
525 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
526 adjust_request, lane);
528 if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
530 DPCD_PRE_EMPHASIS_GET(training_lane) ==
532 dp->link_train.cr_loop[lane]++;
534 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
535 voltage_swing == VOLTAGE_LEVEL_3 ||
536 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
537 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
538 dp->link_train.cr_loop[lane],
539 voltage_swing, pre_emphasis);
540 exynos_dp_reduce_link_rate(dp);
546 exynos_dp_get_adjust_training_lane(dp, adjust_request);
548 for (lane = 0; lane < lane_count; lane++)
549 exynos_dp_set_lane_link_training(dp,
550 dp->link_train.training_lane[lane], lane);
552 retval = exynos_dp_write_bytes_to_dpcd(dp,
553 DP_TRAINING_LANE0_SET, lane_count,
554 dp->link_train.training_lane);
561 static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
563 int lane, lane_count, retval;
565 u8 link_align, link_status[2], adjust_request[2];
567 usleep_range(400, 401);
569 lane_count = dp->link_train.lane_count;
571 retval = exynos_dp_read_bytes_from_dpcd(dp,
572 DP_LANE0_1_STATUS, 2, link_status);
576 if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
577 exynos_dp_reduce_link_rate(dp);
581 retval = exynos_dp_read_bytes_from_dpcd(dp,
582 DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
586 retval = exynos_dp_read_byte_from_dpcd(dp,
587 DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
591 exynos_dp_get_adjust_training_lane(dp, adjust_request);
593 if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) {
594 /* traing pattern Set to Normal */
595 exynos_dp_training_pattern_dis(dp);
597 dev_info(dp->dev, "Link Training success!\n");
599 exynos_dp_get_link_bandwidth(dp, ®);
600 dp->link_train.link_rate = reg;
601 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
602 dp->link_train.link_rate);
604 exynos_dp_get_lane_count(dp, ®);
605 dp->link_train.lane_count = reg;
606 dev_dbg(dp->dev, "final lane count = %.2x\n",
607 dp->link_train.lane_count);
609 /* set enhanced mode if available */
610 exynos_dp_set_enhanced_mode(dp);
611 dp->link_train.lt_state = FINISHED;
617 dp->link_train.eq_loop++;
619 if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
620 dev_err(dp->dev, "EQ Max loop\n");
621 exynos_dp_reduce_link_rate(dp);
625 for (lane = 0; lane < lane_count; lane++)
626 exynos_dp_set_lane_link_training(dp,
627 dp->link_train.training_lane[lane], lane);
629 retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
630 lane_count, dp->link_train.training_lane);
635 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
641 * For DP rev.1.1, Maximum link rate of Main Link lanes
642 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
644 exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
648 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
654 * For DP rev.1.1, Maximum number of Main Link lanes
655 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
657 exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
658 *lane_count = DPCD_MAX_LANE_COUNT(data);
661 static void exynos_dp_init_training(struct exynos_dp_device *dp,
662 enum link_lane_count_type max_lane,
663 enum link_rate_type max_rate)
666 * MACRO_RST must be applied after the PLL_LOCK to avoid
667 * the DP inter pair skew issue for at least 10 us
669 exynos_dp_reset_macro(dp);
671 /* Initialize by reading RX's DPCD */
672 exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
673 exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
675 if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
676 (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
677 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
678 dp->link_train.link_rate);
679 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
682 if (dp->link_train.lane_count == 0) {
683 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
684 dp->link_train.lane_count);
685 dp->link_train.lane_count = (u8)LANE_COUNT1;
688 /* Setup TX lane count & rate */
689 if (dp->link_train.lane_count > max_lane)
690 dp->link_train.lane_count = max_lane;
691 if (dp->link_train.link_rate > max_rate)
692 dp->link_train.link_rate = max_rate;
694 /* All DP analog module power up */
695 exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
698 static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
700 int retval = 0, training_finished = 0;
702 dp->link_train.lt_state = START;
705 while (!retval && !training_finished) {
706 switch (dp->link_train.lt_state) {
708 retval = exynos_dp_link_start(dp);
710 dev_err(dp->dev, "LT link start failed!\n");
713 retval = exynos_dp_process_clock_recovery(dp);
715 dev_err(dp->dev, "LT CR failed!\n");
717 case EQUALIZER_TRAINING:
718 retval = exynos_dp_process_equalizer_training(dp);
720 dev_err(dp->dev, "LT EQ failed!\n");
723 training_finished = 1;
730 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
735 static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
742 for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
743 exynos_dp_init_training(dp, count, bwtype);
744 retval = exynos_dp_sw_link_training(dp);
748 usleep_range(100, 110);
754 static int exynos_dp_config_video(struct exynos_dp_device *dp)
757 int timeout_loop = 0;
760 exynos_dp_config_video_slave_mode(dp);
762 exynos_dp_set_video_color_format(dp);
764 if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
765 dev_err(dp->dev, "PLL is not locked yet.\n");
771 if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
773 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
774 dev_err(dp->dev, "Timeout of video streamclk ok\n");
781 /* Set to use the register calculated M/N video */
782 exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
784 /* For video bist, Video timing must be generated by register */
785 exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
787 /* Disable video mute */
788 exynos_dp_enable_video_mute(dp, 0);
790 /* Configure video slave mode */
791 exynos_dp_enable_video_master(dp, 0);
794 exynos_dp_start_video(dp);
800 if (exynos_dp_is_video_stream_on(dp) == 0) {
804 } else if (done_count) {
807 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
808 dev_err(dp->dev, "Timeout of video streamclk ok\n");
812 usleep_range(1000, 1001);
816 dev_err(dp->dev, "Video stream is not detected!\n");
821 static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
826 exynos_dp_enable_scrambling(dp);
828 exynos_dp_read_byte_from_dpcd(dp,
829 DP_TRAINING_PATTERN_SET,
831 exynos_dp_write_byte_to_dpcd(dp,
832 DP_TRAINING_PATTERN_SET,
833 (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
835 exynos_dp_disable_scrambling(dp);
837 exynos_dp_read_byte_from_dpcd(dp,
838 DP_TRAINING_PATTERN_SET,
840 exynos_dp_write_byte_to_dpcd(dp,
841 DP_TRAINING_PATTERN_SET,
842 (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
846 static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
848 struct exynos_dp_device *dp = arg;
850 enum dp_irq_type irq_type;
852 irq_type = exynos_dp_get_irq_type(dp);
854 case DP_IRQ_TYPE_HP_CABLE_IN:
855 dev_dbg(dp->dev, "Received irq - cable in\n");
856 schedule_work(&dp->hotplug_work);
857 exynos_dp_clear_hotplug_interrupts(dp);
859 case DP_IRQ_TYPE_HP_CABLE_OUT:
860 dev_dbg(dp->dev, "Received irq - cable out\n");
861 exynos_dp_clear_hotplug_interrupts(dp);
863 case DP_IRQ_TYPE_HP_CHANGE:
865 * We get these change notifications once in a while, but there
866 * is nothing we can do with them. Just ignore it for now and
867 * only handle cable changes.
869 dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
870 exynos_dp_clear_hotplug_interrupts(dp);
873 dev_err(dp->dev, "Received irq - unknown type!\n");
879 static void exynos_dp_hotplug(struct work_struct *work)
881 struct exynos_dp_device *dp;
883 dp = container_of(work, struct exynos_dp_device, hotplug_work);
886 drm_helper_hpd_irq_event(dp->drm_dev);
889 static void exynos_dp_commit(struct exynos_drm_display *display)
891 struct exynos_dp_device *dp = display_to_dp(display);
894 /* Keep the panel disabled while we configure video */
896 if (drm_panel_disable(dp->panel))
897 DRM_ERROR("failed to disable the panel\n");
900 ret = exynos_dp_detect_hpd(dp);
902 /* Cable has been disconnected, we're done */
906 ret = exynos_dp_handle_edid(dp);
908 dev_err(dp->dev, "unable to handle edid\n");
912 ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
913 dp->video_info->link_rate);
915 dev_err(dp->dev, "unable to do link train\n");
919 exynos_dp_enable_scramble(dp, 1);
920 exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
921 exynos_dp_enable_enhanced_mode(dp, 1);
923 exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
924 exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
926 exynos_dp_init_video(dp);
927 ret = exynos_dp_config_video(dp);
929 dev_err(dp->dev, "unable to config video\n");
931 /* Safe to enable the panel now */
933 if (drm_panel_enable(dp->panel))
934 DRM_ERROR("failed to enable the panel\n");
938 static enum drm_connector_status exynos_dp_detect(
939 struct drm_connector *connector, bool force)
941 return connector_status_connected;
944 static void exynos_dp_connector_destroy(struct drm_connector *connector)
946 drm_connector_unregister(connector);
947 drm_connector_cleanup(connector);
950 static struct drm_connector_funcs exynos_dp_connector_funcs = {
951 .dpms = drm_helper_connector_dpms,
952 .fill_modes = drm_helper_probe_single_connector_modes,
953 .detect = exynos_dp_detect,
954 .destroy = exynos_dp_connector_destroy,
957 static int exynos_dp_get_modes(struct drm_connector *connector)
959 struct exynos_dp_device *dp = ctx_from_connector(connector);
960 struct drm_display_mode *mode;
963 return drm_panel_get_modes(dp->panel);
965 mode = drm_mode_create(connector->dev);
967 DRM_ERROR("failed to create a new display mode.\n");
971 drm_display_mode_from_videomode(&dp->priv.vm, mode);
972 mode->width_mm = dp->priv.width_mm;
973 mode->height_mm = dp->priv.height_mm;
974 connector->display_info.width_mm = mode->width_mm;
975 connector->display_info.height_mm = mode->height_mm;
977 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
978 drm_mode_set_name(mode);
979 drm_mode_probed_add(connector, mode);
984 static struct drm_encoder *exynos_dp_best_encoder(
985 struct drm_connector *connector)
987 struct exynos_dp_device *dp = ctx_from_connector(connector);
992 static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
993 .get_modes = exynos_dp_get_modes,
994 .best_encoder = exynos_dp_best_encoder,
997 /* returns the number of bridges attached */
998 static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
999 struct drm_encoder *encoder)
1003 encoder->bridge = dp->bridge;
1004 dp->bridge->encoder = encoder;
1005 ret = drm_bridge_attach(encoder->dev, dp->bridge);
1007 DRM_ERROR("Failed to attach bridge to drm\n");
1014 static int exynos_dp_create_connector(struct exynos_drm_display *display,
1015 struct drm_encoder *encoder)
1017 struct exynos_dp_device *dp = display_to_dp(display);
1018 struct drm_connector *connector = &dp->connector;
1021 dp->encoder = encoder;
1023 /* Pre-empt DP connector creation if there's a bridge */
1025 ret = exynos_drm_attach_lcd_bridge(dp, encoder);
1030 connector->polled = DRM_CONNECTOR_POLL_HPD;
1032 ret = drm_connector_init(dp->drm_dev, connector,
1033 &exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP);
1035 DRM_ERROR("Failed to initialize connector with drm\n");
1039 drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
1040 drm_connector_register(connector);
1041 drm_mode_connector_attach_encoder(connector, encoder);
1044 ret = drm_panel_attach(dp->panel, &dp->connector);
1049 static void exynos_dp_phy_init(struct exynos_dp_device *dp)
1052 phy_power_on(dp->phy);
1055 static void exynos_dp_phy_exit(struct exynos_dp_device *dp)
1058 phy_power_off(dp->phy);
1061 static void exynos_dp_poweron(struct exynos_dp_device *dp)
1063 if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1067 if (drm_panel_prepare(dp->panel)) {
1068 DRM_ERROR("failed to setup the panel\n");
1073 clk_prepare_enable(dp->clock);
1074 exynos_dp_phy_init(dp);
1075 exynos_dp_init_dp(dp);
1076 enable_irq(dp->irq);
1077 exynos_dp_commit(&dp->display);
1080 static void exynos_dp_poweroff(struct exynos_dp_device *dp)
1082 if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1086 if (drm_panel_disable(dp->panel)) {
1087 DRM_ERROR("failed to disable the panel\n");
1092 disable_irq(dp->irq);
1093 flush_work(&dp->hotplug_work);
1094 exynos_dp_phy_exit(dp);
1095 clk_disable_unprepare(dp->clock);
1098 if (drm_panel_unprepare(dp->panel))
1099 DRM_ERROR("failed to turnoff the panel\n");
1103 static void exynos_dp_dpms(struct exynos_drm_display *display, int mode)
1105 struct exynos_dp_device *dp = display_to_dp(display);
1108 case DRM_MODE_DPMS_ON:
1109 exynos_dp_poweron(dp);
1111 case DRM_MODE_DPMS_STANDBY:
1112 case DRM_MODE_DPMS_SUSPEND:
1113 case DRM_MODE_DPMS_OFF:
1114 exynos_dp_poweroff(dp);
1119 dp->dpms_mode = mode;
1122 static struct exynos_drm_display_ops exynos_dp_display_ops = {
1123 .create_connector = exynos_dp_create_connector,
1124 .dpms = exynos_dp_dpms,
1125 .commit = exynos_dp_commit,
1128 static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
1130 struct device_node *dp_node = dev->of_node;
1131 struct video_info *dp_video_config;
1133 dp_video_config = devm_kzalloc(dev,
1134 sizeof(*dp_video_config), GFP_KERNEL);
1135 if (!dp_video_config)
1136 return ERR_PTR(-ENOMEM);
1138 dp_video_config->h_sync_polarity =
1139 of_property_read_bool(dp_node, "hsync-active-high");
1141 dp_video_config->v_sync_polarity =
1142 of_property_read_bool(dp_node, "vsync-active-high");
1144 dp_video_config->interlaced =
1145 of_property_read_bool(dp_node, "interlaced");
1147 if (of_property_read_u32(dp_node, "samsung,color-space",
1148 &dp_video_config->color_space)) {
1149 dev_err(dev, "failed to get color-space\n");
1150 return ERR_PTR(-EINVAL);
1153 if (of_property_read_u32(dp_node, "samsung,dynamic-range",
1154 &dp_video_config->dynamic_range)) {
1155 dev_err(dev, "failed to get dynamic-range\n");
1156 return ERR_PTR(-EINVAL);
1159 if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1160 &dp_video_config->ycbcr_coeff)) {
1161 dev_err(dev, "failed to get ycbcr-coeff\n");
1162 return ERR_PTR(-EINVAL);
1165 if (of_property_read_u32(dp_node, "samsung,color-depth",
1166 &dp_video_config->color_depth)) {
1167 dev_err(dev, "failed to get color-depth\n");
1168 return ERR_PTR(-EINVAL);
1171 if (of_property_read_u32(dp_node, "samsung,link-rate",
1172 &dp_video_config->link_rate)) {
1173 dev_err(dev, "failed to get link-rate\n");
1174 return ERR_PTR(-EINVAL);
1177 if (of_property_read_u32(dp_node, "samsung,lane-count",
1178 &dp_video_config->lane_count)) {
1179 dev_err(dev, "failed to get lane-count\n");
1180 return ERR_PTR(-EINVAL);
1183 return dp_video_config;
1186 static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
1190 ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
1191 OF_USE_NATIVE_MODE);
1193 DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
1199 static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
1201 struct exynos_dp_device *dp = dev_get_drvdata(dev);
1202 struct platform_device *pdev = to_platform_device(dev);
1203 struct drm_device *drm_dev = data;
1204 struct resource *res;
1205 unsigned int irq_flags;
1208 dp->dev = &pdev->dev;
1209 dp->dpms_mode = DRM_MODE_DPMS_OFF;
1211 dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev);
1212 if (IS_ERR(dp->video_info))
1213 return PTR_ERR(dp->video_info);
1215 dp->phy = devm_phy_get(dp->dev, "dp");
1216 if (IS_ERR(dp->phy)) {
1217 dev_err(dp->dev, "no DP phy configured\n");
1218 ret = PTR_ERR(dp->phy);
1221 * phy itself is not enabled, so we can move forward
1222 * assigning NULL to phy pointer.
1224 if (ret == -ENOSYS || ret == -ENODEV)
1231 if (!dp->panel && !dp->bridge) {
1232 ret = exynos_dp_dt_parse_panel(dp);
1237 dp->clock = devm_clk_get(&pdev->dev, "dp");
1238 if (IS_ERR(dp->clock)) {
1239 dev_err(&pdev->dev, "failed to get clock\n");
1240 return PTR_ERR(dp->clock);
1243 clk_prepare_enable(dp->clock);
1245 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1247 dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
1248 if (IS_ERR(dp->reg_base))
1249 return PTR_ERR(dp->reg_base);
1251 dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
1253 if (gpio_is_valid(dp->hpd_gpio)) {
1255 * Set up the hotplug GPIO from the device tree as an interrupt.
1256 * Simply specifying a different interrupt in the device tree
1257 * doesn't work since we handle hotplug rather differently when
1258 * using a GPIO. We also need the actual GPIO specifier so
1259 * that we can get the current state of the GPIO.
1261 ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,
1264 dev_err(&pdev->dev, "failed to get hpd gpio\n");
1267 dp->irq = gpio_to_irq(dp->hpd_gpio);
1268 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1270 dp->hpd_gpio = -ENODEV;
1271 dp->irq = platform_get_irq(pdev, 0);
1275 if (dp->irq == -ENXIO) {
1276 dev_err(&pdev->dev, "failed to get irq\n");
1280 INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
1282 exynos_dp_phy_init(dp);
1284 exynos_dp_init_dp(dp);
1286 ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
1287 irq_flags, "exynos-dp", dp);
1289 dev_err(&pdev->dev, "failed to request irq\n");
1292 disable_irq(dp->irq);
1294 dp->drm_dev = drm_dev;
1296 return exynos_drm_create_enc_conn(drm_dev, &dp->display);
1299 static void exynos_dp_unbind(struct device *dev, struct device *master,
1302 struct exynos_dp_device *dp = dev_get_drvdata(dev);
1304 exynos_dp_dpms(&dp->display, DRM_MODE_DPMS_OFF);
1307 static const struct component_ops exynos_dp_ops = {
1308 .bind = exynos_dp_bind,
1309 .unbind = exynos_dp_unbind,
1312 static int exynos_dp_probe(struct platform_device *pdev)
1314 struct device *dev = &pdev->dev;
1315 struct device_node *panel_node, *bridge_node, *endpoint;
1316 struct exynos_dp_device *dp;
1319 dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
1324 dp->display.type = EXYNOS_DISPLAY_TYPE_LCD;
1325 dp->display.ops = &exynos_dp_display_ops;
1326 platform_set_drvdata(pdev, dp);
1328 ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR,
1333 panel_node = of_parse_phandle(dev->of_node, "panel", 0);
1335 dp->panel = of_drm_find_panel(panel_node);
1336 of_node_put(panel_node);
1338 return -EPROBE_DEFER;
1341 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1343 bridge_node = of_graph_get_remote_port_parent(endpoint);
1345 dp->bridge = of_drm_find_bridge(bridge_node);
1346 of_node_put(bridge_node);
1348 return -EPROBE_DEFER;
1350 return -EPROBE_DEFER;
1353 ret = component_add(&pdev->dev, &exynos_dp_ops);
1355 exynos_drm_component_del(&pdev->dev,
1356 EXYNOS_DEVICE_TYPE_CONNECTOR);
1361 static int exynos_dp_remove(struct platform_device *pdev)
1363 component_del(&pdev->dev, &exynos_dp_ops);
1364 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
1369 #ifdef CONFIG_PM_SLEEP
1370 static int exynos_dp_suspend(struct device *dev)
1372 struct exynos_dp_device *dp = dev_get_drvdata(dev);
1374 exynos_dp_dpms(&dp->display, DRM_MODE_DPMS_OFF);
1378 static int exynos_dp_resume(struct device *dev)
1380 struct exynos_dp_device *dp = dev_get_drvdata(dev);
1382 exynos_dp_dpms(&dp->display, DRM_MODE_DPMS_ON);
1387 static const struct dev_pm_ops exynos_dp_pm_ops = {
1388 SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
1391 static const struct of_device_id exynos_dp_match[] = {
1392 { .compatible = "samsung,exynos5-dp" },
1395 MODULE_DEVICE_TABLE(of, exynos_dp_match);
1397 struct platform_driver dp_driver = {
1398 .probe = exynos_dp_probe,
1399 .remove = exynos_dp_remove,
1401 .name = "exynos-dp",
1402 .owner = THIS_MODULE,
1403 .pm = &exynos_dp_pm_ops,
1404 .of_match_table = exynos_dp_match,
1408 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1409 MODULE_DESCRIPTION("Samsung SoC DP Driver");
1410 MODULE_LICENSE("GPL v2");