2 * Samsung SoC MIPI DSI Master driver.
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd
6 * Contacts: Tomasz Figa <t.figa@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <drm/drm_crtc_helper.h>
15 #include <drm/drm_mipi_dsi.h>
16 #include <drm/drm_panel.h>
18 #include <linux/clk.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/irq.h>
21 #include <linux/of_device.h>
22 #include <linux/of_gpio.h>
23 #include <linux/phy/phy.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/component.h>
27 #include <video/mipi_display.h>
28 #include <video/videomode.h>
30 #include "exynos_drm_crtc.h"
31 #include "exynos_drm_drv.h"
33 /* returns true iff both arguments logically differs */
34 #define NEQV(a, b) (!(a) ^ !(b))
36 #define DSIM_STATUS_REG 0x0 /* Status register */
37 #define DSIM_SWRST_REG 0x4 /* Software reset register */
38 #define DSIM_CLKCTRL_REG 0x8 /* Clock control register */
39 #define DSIM_TIMEOUT_REG 0xc /* Time out register */
40 #define DSIM_CONFIG_REG 0x10 /* Configuration register */
41 #define DSIM_ESCMODE_REG 0x14 /* Escape mode register */
43 /* Main display image resolution register */
44 #define DSIM_MDRESOL_REG 0x18
45 #define DSIM_MVPORCH_REG 0x1c /* Main display Vporch register */
46 #define DSIM_MHPORCH_REG 0x20 /* Main display Hporch register */
47 #define DSIM_MSYNC_REG 0x24 /* Main display sync area register */
49 /* Sub display image resolution register */
50 #define DSIM_SDRESOL_REG 0x28
51 #define DSIM_INTSRC_REG 0x2c /* Interrupt source register */
52 #define DSIM_INTMSK_REG 0x30 /* Interrupt mask register */
53 #define DSIM_PKTHDR_REG 0x34 /* Packet Header FIFO register */
54 #define DSIM_PAYLOAD_REG 0x38 /* Payload FIFO register */
55 #define DSIM_RXFIFO_REG 0x3c /* Read FIFO register */
56 #define DSIM_FIFOTHLD_REG 0x40 /* FIFO threshold level register */
57 #define DSIM_FIFOCTRL_REG 0x44 /* FIFO status and control register */
59 /* FIFO memory AC characteristic register */
60 #define DSIM_PLLCTRL_REG 0x4c /* PLL control register */
61 #define DSIM_PHYACCHR_REG 0x54 /* D-PHY AC characteristic register */
62 #define DSIM_PHYACCHR1_REG 0x58 /* D-PHY AC characteristic register1 */
63 #define DSIM_PHYCTRL_REG 0x5c
64 #define DSIM_PHYTIMING_REG 0x64
65 #define DSIM_PHYTIMING1_REG 0x68
66 #define DSIM_PHYTIMING2_REG 0x6c
69 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
70 #define DSIM_STOP_STATE_CLK (1 << 8)
71 #define DSIM_TX_READY_HS_CLK (1 << 10)
72 #define DSIM_PLL_STABLE (1 << 31)
75 #define DSIM_FUNCRST (1 << 16)
76 #define DSIM_SWRST (1 << 0)
79 #define DSIM_LPDR_TIMEOUT(x) ((x) << 0)
80 #define DSIM_BTA_TIMEOUT(x) ((x) << 16)
83 #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0)
84 #define DSIM_ESC_PRESCALER_MASK (0xffff << 0)
85 #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19)
86 #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20)
87 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20)
88 #define DSIM_BYTE_CLKEN (1 << 24)
89 #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25)
90 #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25)
91 #define DSIM_PLL_BYPASS (1 << 27)
92 #define DSIM_ESC_CLKEN (1 << 28)
93 #define DSIM_TX_REQUEST_HSCLK (1 << 31)
96 #define DSIM_LANE_EN_CLK (1 << 0)
97 #define DSIM_LANE_EN(x) (((x) & 0xf) << 1)
98 #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5)
99 #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8)
100 #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12)
101 #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12)
102 #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12)
103 #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12)
104 #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12)
105 #define DSIM_SUB_VC (((x) & 0x3) << 16)
106 #define DSIM_MAIN_VC (((x) & 0x3) << 18)
107 #define DSIM_HSA_MODE (1 << 20)
108 #define DSIM_HBP_MODE (1 << 21)
109 #define DSIM_HFP_MODE (1 << 22)
110 #define DSIM_HSE_MODE (1 << 23)
111 #define DSIM_AUTO_MODE (1 << 24)
112 #define DSIM_VIDEO_MODE (1 << 25)
113 #define DSIM_BURST_MODE (1 << 26)
114 #define DSIM_SYNC_INFORM (1 << 27)
115 #define DSIM_EOT_DISABLE (1 << 28)
116 #define DSIM_MFLUSH_VS (1 << 29)
117 /* This flag is valid only for exynos3250/3472/4415/5260/5430 */
118 #define DSIM_CLKLANE_STOP (1 << 30)
121 #define DSIM_TX_TRIGGER_RST (1 << 4)
122 #define DSIM_TX_LPDT_LP (1 << 6)
123 #define DSIM_CMD_LPDT_LP (1 << 7)
124 #define DSIM_FORCE_BTA (1 << 16)
125 #define DSIM_FORCE_STOP_STATE (1 << 20)
126 #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21)
127 #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21)
130 #define DSIM_MAIN_STAND_BY (1 << 31)
131 #define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16)
132 #define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0)
135 #define DSIM_CMD_ALLOW(x) ((x) << 28)
136 #define DSIM_STABLE_VFP(x) ((x) << 16)
137 #define DSIM_MAIN_VBP(x) ((x) << 0)
138 #define DSIM_CMD_ALLOW_MASK (0xf << 28)
139 #define DSIM_STABLE_VFP_MASK (0x7ff << 16)
140 #define DSIM_MAIN_VBP_MASK (0x7ff << 0)
143 #define DSIM_MAIN_HFP(x) ((x) << 16)
144 #define DSIM_MAIN_HBP(x) ((x) << 0)
145 #define DSIM_MAIN_HFP_MASK ((0xffff) << 16)
146 #define DSIM_MAIN_HBP_MASK ((0xffff) << 0)
149 #define DSIM_MAIN_VSA(x) ((x) << 22)
150 #define DSIM_MAIN_HSA(x) ((x) << 0)
151 #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22)
152 #define DSIM_MAIN_HSA_MASK ((0xffff) << 0)
155 #define DSIM_SUB_STANDY(x) ((x) << 31)
156 #define DSIM_SUB_VRESOL(x) ((x) << 16)
157 #define DSIM_SUB_HRESOL(x) ((x) << 0)
158 #define DSIM_SUB_STANDY_MASK ((0x1) << 31)
159 #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16)
160 #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0)
163 #define DSIM_INT_PLL_STABLE (1 << 31)
164 #define DSIM_INT_SW_RST_RELEASE (1 << 30)
165 #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29)
166 #define DSIM_INT_BTA (1 << 25)
167 #define DSIM_INT_FRAME_DONE (1 << 24)
168 #define DSIM_INT_RX_TIMEOUT (1 << 21)
169 #define DSIM_INT_BTA_TIMEOUT (1 << 20)
170 #define DSIM_INT_RX_DONE (1 << 18)
171 #define DSIM_INT_RX_TE (1 << 17)
172 #define DSIM_INT_RX_ACK (1 << 16)
173 #define DSIM_INT_RX_ECC_ERR (1 << 15)
174 #define DSIM_INT_RX_CRC_ERR (1 << 14)
177 #define DSIM_RX_DATA_FULL (1 << 25)
178 #define DSIM_RX_DATA_EMPTY (1 << 24)
179 #define DSIM_SFR_HEADER_FULL (1 << 23)
180 #define DSIM_SFR_HEADER_EMPTY (1 << 22)
181 #define DSIM_SFR_PAYLOAD_FULL (1 << 21)
182 #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20)
183 #define DSIM_I80_HEADER_FULL (1 << 19)
184 #define DSIM_I80_HEADER_EMPTY (1 << 18)
185 #define DSIM_I80_PAYLOAD_FULL (1 << 17)
186 #define DSIM_I80_PAYLOAD_EMPTY (1 << 16)
187 #define DSIM_SD_HEADER_FULL (1 << 15)
188 #define DSIM_SD_HEADER_EMPTY (1 << 14)
189 #define DSIM_SD_PAYLOAD_FULL (1 << 13)
190 #define DSIM_SD_PAYLOAD_EMPTY (1 << 12)
191 #define DSIM_MD_HEADER_FULL (1 << 11)
192 #define DSIM_MD_HEADER_EMPTY (1 << 10)
193 #define DSIM_MD_PAYLOAD_FULL (1 << 9)
194 #define DSIM_MD_PAYLOAD_EMPTY (1 << 8)
195 #define DSIM_RX_FIFO (1 << 4)
196 #define DSIM_SFR_FIFO (1 << 3)
197 #define DSIM_I80_FIFO (1 << 2)
198 #define DSIM_SD_FIFO (1 << 1)
199 #define DSIM_MD_FIFO (1 << 0)
202 #define DSIM_AFC_EN (1 << 14)
203 #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
206 #define DSIM_FREQ_BAND(x) ((x) << 24)
207 #define DSIM_PLL_EN (1 << 23)
208 #define DSIM_PLL_P(x) ((x) << 13)
209 #define DSIM_PLL_M(x) ((x) << 4)
210 #define DSIM_PLL_S(x) ((x) << 1)
213 #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0)
216 #define DSIM_PHYTIMING_LPX(x) ((x) << 8)
217 #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0)
219 /* DSIM_PHYTIMING1 */
220 #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24)
221 #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16)
222 #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8)
223 #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0)
225 /* DSIM_PHYTIMING2 */
226 #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16)
227 #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8)
228 #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0)
230 #define DSI_MAX_BUS_WIDTH 4
231 #define DSI_NUM_VIRTUAL_CHANNELS 4
232 #define DSI_TX_FIFO_SIZE 2048
233 #define DSI_RX_FIFO_SIZE 256
234 #define DSI_XFER_TIMEOUT_MS 100
235 #define DSI_RX_FIFO_EMPTY 0x30800002
237 enum exynos_dsi_transfer_type {
242 struct exynos_dsi_transfer {
243 struct list_head list;
244 struct completion completed;
250 const u8 *tx_payload;
259 #define DSIM_STATE_ENABLED BIT(0)
260 #define DSIM_STATE_INITIALIZED BIT(1)
261 #define DSIM_STATE_CMD_LPM BIT(2)
263 struct exynos_dsi_driver_data {
264 unsigned int plltmr_reg;
266 unsigned int has_freqband:1;
267 unsigned int has_clklane_stop:1;
271 struct exynos_drm_display display;
272 struct mipi_dsi_host dsi_host;
273 struct drm_connector connector;
274 struct device_node *panel_node;
275 struct drm_panel *panel;
278 void __iomem *reg_base;
282 struct regulator_bulk_data supplies[2];
295 struct drm_property *brightness;
296 struct completion completed;
298 spinlock_t transfer_lock; /* protects transfer_list */
299 struct list_head transfer_list;
301 struct exynos_dsi_driver_data *driver_data;
304 #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
305 #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
307 static inline struct exynos_dsi *display_to_dsi(struct exynos_drm_display *d)
309 return container_of(d, struct exynos_dsi, display);
312 static struct exynos_dsi_driver_data exynos3_dsi_driver_data = {
315 .has_clklane_stop = 1,
318 static struct exynos_dsi_driver_data exynos4_dsi_driver_data = {
321 .has_clklane_stop = 1,
324 static struct exynos_dsi_driver_data exynos4415_dsi_driver_data = {
326 .has_clklane_stop = 1,
329 static struct exynos_dsi_driver_data exynos5_dsi_driver_data = {
333 static struct of_device_id exynos_dsi_of_match[] = {
334 { .compatible = "samsung,exynos3250-mipi-dsi",
335 .data = &exynos3_dsi_driver_data },
336 { .compatible = "samsung,exynos4210-mipi-dsi",
337 .data = &exynos4_dsi_driver_data },
338 { .compatible = "samsung,exynos4415-mipi-dsi",
339 .data = &exynos4415_dsi_driver_data },
340 { .compatible = "samsung,exynos5410-mipi-dsi",
341 .data = &exynos5_dsi_driver_data },
345 static inline struct exynos_dsi_driver_data *exynos_dsi_get_driver_data(
346 struct platform_device *pdev)
348 const struct of_device_id *of_id =
349 of_match_device(exynos_dsi_of_match, &pdev->dev);
351 return (struct exynos_dsi_driver_data *)of_id->data;
354 static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
356 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
359 dev_err(dsi->dev, "timeout waiting for reset\n");
362 static void exynos_dsi_reset(struct exynos_dsi *dsi)
364 reinit_completion(&dsi->completed);
365 writel(DSIM_SWRST, dsi->reg_base + DSIM_SWRST_REG);
369 #define MHZ (1000*1000)
372 static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
373 unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s)
375 unsigned long best_freq = 0;
376 u32 min_delta = 0xffffffff;
378 u8 _p, uninitialized_var(best_p);
379 u16 _m, uninitialized_var(best_m);
380 u8 _s, uninitialized_var(best_s);
382 p_min = DIV_ROUND_UP(fin, (12 * MHZ));
383 p_max = fin / (6 * MHZ);
385 for (_p = p_min; _p <= p_max; ++_p) {
386 for (_s = 0; _s <= 5; ++_s) {
390 tmp = (u64)fout * (_p << _s);
393 if (_m < 41 || _m > 125)
398 if (tmp < 500 * MHZ || tmp > 1000 * MHZ)
402 do_div(tmp, _p << _s);
404 delta = abs(fout - tmp);
405 if (delta < min_delta) {
424 static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
427 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
428 unsigned long fin, fout;
434 clk_set_rate(dsi->pll_clk, dsi->pll_clk_rate);
436 fin = clk_get_rate(dsi->pll_clk);
438 dev_err(dsi->dev, "failed to get PLL clock frequency\n");
442 dev_dbg(dsi->dev, "PLL input frequency: %lu\n", fin);
444 fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
447 "failed to find PLL PMS for requested frequency\n");
450 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s);
452 writel(500, dsi->reg_base + driver_data->plltmr_reg);
454 reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
456 if (driver_data->has_freqband) {
457 static const unsigned long freq_bands[] = {
458 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
459 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
460 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
461 770 * MHZ, 870 * MHZ, 950 * MHZ,
465 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
466 if (fout < freq_bands[band])
469 dev_dbg(dsi->dev, "band %d\n", band);
471 reg |= DSIM_FREQ_BAND(band);
474 writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);
478 if (timeout-- == 0) {
479 dev_err(dsi->dev, "PLL failed to stabilize\n");
482 reg = readl(dsi->reg_base + DSIM_STATUS_REG);
483 } while ((reg & DSIM_PLL_STABLE) == 0);
488 static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
490 unsigned long hs_clk, byte_clk, esc_clk;
491 unsigned long esc_div;
494 hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate);
496 dev_err(dsi->dev, "failed to configure DSI PLL\n");
500 byte_clk = hs_clk / 8;
501 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
502 esc_clk = byte_clk / esc_div;
504 if (esc_clk > 20 * MHZ) {
506 esc_clk = byte_clk / esc_div;
509 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
510 hs_clk, byte_clk, esc_clk);
512 reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
513 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
514 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
515 | DSIM_BYTE_CLK_SRC_MASK);
516 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
517 | DSIM_ESC_PRESCALER(esc_div)
518 | DSIM_LANE_ESC_CLK_EN_CLK
519 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
520 | DSIM_BYTE_CLK_SRC(0)
521 | DSIM_TX_REQUEST_HSCLK;
522 writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
527 static void exynos_dsi_set_phy_ctrl(struct exynos_dsi *dsi)
529 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
532 if (driver_data->has_freqband)
535 /* B D-PHY: D-PHY Master & Slave Analog Block control */
536 reg = DSIM_PHYCTRL_ULPS_EXIT(0x0af);
537 writel(reg, dsi->reg_base + DSIM_PHYCTRL_REG);
540 * T LPX: Transmitted length of any Low-Power state period
541 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS
544 reg = DSIM_PHYTIMING_LPX(0x06) | DSIM_PHYTIMING_HS_EXIT(0x0b);
545 writel(reg, dsi->reg_base + DSIM_PHYTIMING_REG);
548 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00
549 * Line state immediately before the HS-0 Line state starting the
551 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to
552 * transmitting the Clock.
553 * T CLK_POST: Time that the transmitter continues to send HS clock
554 * after the last associated Data Lane has transitioned to LP Mode
555 * Interval is defined as the period from the end of T HS-TRAIL to
556 * the beginning of T CLK-TRAIL
557 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after
558 * the last payload clock bit of a HS transmission burst
560 reg = DSIM_PHYTIMING1_CLK_PREPARE(0x07) |
561 DSIM_PHYTIMING1_CLK_ZERO(0x27) |
562 DSIM_PHYTIMING1_CLK_POST(0x0d) |
563 DSIM_PHYTIMING1_CLK_TRAIL(0x08);
564 writel(reg, dsi->reg_base + DSIM_PHYTIMING1_REG);
567 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00
568 * Line state immediately before the HS-0 Line state starting the
570 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to
571 * transmitting the Sync sequence.
572 * T HS-TRAIL: Time that the transmitter drives the flipped differential
573 * state after last payload data bit of a HS transmission burst
575 reg = DSIM_PHYTIMING2_HS_PREPARE(0x09) | DSIM_PHYTIMING2_HS_ZERO(0x0d) |
576 DSIM_PHYTIMING2_HS_TRAIL(0x0b);
577 writel(reg, dsi->reg_base + DSIM_PHYTIMING2_REG);
580 static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
584 reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
585 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
586 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
587 writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
589 reg = readl(dsi->reg_base + DSIM_PLLCTRL_REG);
591 writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);
594 static int exynos_dsi_init_link(struct exynos_dsi *dsi)
596 struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
601 /* Initialize FIFO pointers */
602 reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);
604 writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);
606 usleep_range(9000, 11000);
609 writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);
611 usleep_range(9000, 11000);
613 /* DSI configuration */
617 * The first bit of mode_flags specifies display configuration.
618 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video
619 * mode, otherwise it will support command mode.
621 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
622 reg |= DSIM_VIDEO_MODE;
625 * The user manual describes that following bits are ignored in
628 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
629 reg |= DSIM_MFLUSH_VS;
630 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
631 reg |= DSIM_SYNC_INFORM;
632 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
633 reg |= DSIM_BURST_MODE;
634 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
635 reg |= DSIM_AUTO_MODE;
636 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
637 reg |= DSIM_HSE_MODE;
638 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
639 reg |= DSIM_HFP_MODE;
640 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
641 reg |= DSIM_HBP_MODE;
642 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA))
643 reg |= DSIM_HSA_MODE;
646 if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
647 reg |= DSIM_EOT_DISABLE;
649 switch (dsi->format) {
650 case MIPI_DSI_FMT_RGB888:
651 reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
653 case MIPI_DSI_FMT_RGB666:
654 reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
656 case MIPI_DSI_FMT_RGB666_PACKED:
657 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
659 case MIPI_DSI_FMT_RGB565:
660 reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
663 dev_err(dsi->dev, "invalid pixel format\n");
667 reg |= DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1);
669 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
671 reg |= DSIM_LANE_EN_CLK;
672 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
674 lanes_mask = BIT(dsi->lanes) - 1;
675 reg |= DSIM_LANE_EN(lanes_mask);
676 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
679 * Use non-continuous clock mode if the periparal wants and
680 * host controller supports
682 * In non-continous clock mode, host controller will turn off
683 * the HS clock between high-speed transmissions to reduce
686 if (driver_data->has_clklane_stop &&
687 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
688 reg |= DSIM_CLKLANE_STOP;
689 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
692 /* Check clock and data lane state are stop state */
695 if (timeout-- == 0) {
696 dev_err(dsi->dev, "waiting for bus lanes timed out\n");
700 reg = readl(dsi->reg_base + DSIM_STATUS_REG);
701 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
702 != DSIM_STOP_STATE_DAT(lanes_mask))
704 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
706 reg = readl(dsi->reg_base + DSIM_ESCMODE_REG);
707 reg &= ~DSIM_STOP_STATE_CNT_MASK;
708 reg |= DSIM_STOP_STATE_CNT(0xf);
709 writel(reg, dsi->reg_base + DSIM_ESCMODE_REG);
711 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
712 writel(reg, dsi->reg_base + DSIM_TIMEOUT_REG);
717 static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
719 struct videomode *vm = &dsi->vm;
722 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
723 reg = DSIM_CMD_ALLOW(0xf)
724 | DSIM_STABLE_VFP(vm->vfront_porch)
725 | DSIM_MAIN_VBP(vm->vback_porch);
726 writel(reg, dsi->reg_base + DSIM_MVPORCH_REG);
728 reg = DSIM_MAIN_HFP(vm->hfront_porch)
729 | DSIM_MAIN_HBP(vm->hback_porch);
730 writel(reg, dsi->reg_base + DSIM_MHPORCH_REG);
732 reg = DSIM_MAIN_VSA(vm->vsync_len)
733 | DSIM_MAIN_HSA(vm->hsync_len);
734 writel(reg, dsi->reg_base + DSIM_MSYNC_REG);
737 reg = DSIM_MAIN_HRESOL(vm->hactive) | DSIM_MAIN_VRESOL(vm->vactive);
738 writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);
740 dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive);
743 static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable)
747 reg = readl(dsi->reg_base + DSIM_MDRESOL_REG);
749 reg |= DSIM_MAIN_STAND_BY;
751 reg &= ~DSIM_MAIN_STAND_BY;
752 writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);
755 static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
760 u32 reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);
762 if (!(reg & DSIM_SFR_HEADER_FULL))
766 usleep_range(950, 1050);
772 static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm)
774 u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);
777 v |= DSIM_CMD_LPDT_LP;
779 v &= ~DSIM_CMD_LPDT_LP;
781 writel(v, dsi->reg_base + DSIM_ESCMODE_REG);
784 static void exynos_dsi_force_bta(struct exynos_dsi *dsi)
786 u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);
789 writel(v, dsi->reg_base + DSIM_ESCMODE_REG);
792 static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
793 struct exynos_dsi_transfer *xfer)
795 struct device *dev = dsi->dev;
796 const u8 *payload = xfer->tx_payload + xfer->tx_done;
797 u16 length = xfer->tx_len - xfer->tx_done;
798 bool first = !xfer->tx_done;
801 dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n",
802 xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done);
804 if (length > DSI_TX_FIFO_SIZE)
805 length = DSI_TX_FIFO_SIZE;
807 xfer->tx_done += length;
810 while (length >= 4) {
811 reg = (payload[3] << 24) | (payload[2] << 16)
812 | (payload[1] << 8) | payload[0];
813 writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);
821 reg |= payload[2] << 16;
824 reg |= payload[1] << 8;
828 writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);
835 /* Send packet header */
839 reg = (xfer->data[1] << 16) | (xfer->data[0] << 8) | xfer->data_id;
840 if (exynos_dsi_wait_for_hdr_fifo(dsi)) {
841 dev_err(dev, "waiting for header FIFO timed out\n");
845 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
846 dsi->state & DSIM_STATE_CMD_LPM)) {
847 exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
848 dsi->state ^= DSIM_STATE_CMD_LPM;
851 writel(reg, dsi->reg_base + DSIM_PKTHDR_REG);
853 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
854 exynos_dsi_force_bta(dsi);
857 static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
858 struct exynos_dsi_transfer *xfer)
860 u8 *payload = xfer->rx_payload + xfer->rx_done;
861 bool first = !xfer->rx_done;
862 struct device *dev = dsi->dev;
867 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
869 switch (reg & 0x3f) {
870 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
871 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
872 if (xfer->rx_len >= 2) {
873 payload[1] = reg >> 16;
877 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
878 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
879 payload[0] = reg >> 8;
881 xfer->rx_len = xfer->rx_done;
884 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
885 dev_err(dev, "DSI Error Report: 0x%04x\n",
886 (reg >> 8) & 0xffff);
891 length = (reg >> 8) & 0xffff;
892 if (length > xfer->rx_len) {
894 "response too long (%u > %u bytes), stripping\n",
895 xfer->rx_len, length);
896 length = xfer->rx_len;
897 } else if (length < xfer->rx_len)
898 xfer->rx_len = length;
901 length = xfer->rx_len - xfer->rx_done;
902 xfer->rx_done += length;
904 /* Receive payload */
905 while (length >= 4) {
906 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
907 payload[0] = (reg >> 0) & 0xff;
908 payload[1] = (reg >> 8) & 0xff;
909 payload[2] = (reg >> 16) & 0xff;
910 payload[3] = (reg >> 24) & 0xff;
916 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
919 payload[2] = (reg >> 16) & 0xff;
922 payload[1] = (reg >> 8) & 0xff;
925 payload[0] = reg & 0xff;
929 if (xfer->rx_done == xfer->rx_len)
933 length = DSI_RX_FIFO_SIZE / 4;
935 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
936 if (reg == DSI_RX_FIFO_EMPTY)
941 static void exynos_dsi_transfer_start(struct exynos_dsi *dsi)
944 struct exynos_dsi_transfer *xfer;
948 spin_lock_irqsave(&dsi->transfer_lock, flags);
950 if (list_empty(&dsi->transfer_list)) {
951 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
955 xfer = list_first_entry(&dsi->transfer_list,
956 struct exynos_dsi_transfer, list);
958 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
960 if (xfer->tx_len && xfer->tx_done == xfer->tx_len)
964 exynos_dsi_send_to_fifo(dsi, xfer);
966 if (xfer->tx_len || xfer->rx_len)
970 complete(&xfer->completed);
972 spin_lock_irqsave(&dsi->transfer_lock, flags);
974 list_del_init(&xfer->list);
975 start = !list_empty(&dsi->transfer_list);
977 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
983 static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi)
985 struct exynos_dsi_transfer *xfer;
989 spin_lock_irqsave(&dsi->transfer_lock, flags);
991 if (list_empty(&dsi->transfer_list)) {
992 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
996 xfer = list_first_entry(&dsi->transfer_list,
997 struct exynos_dsi_transfer, list);
999 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1002 "> xfer %p, tx_len %u, tx_done %u, rx_len %u, rx_done %u\n",
1003 xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done);
1005 if (xfer->tx_done != xfer->tx_len)
1008 if (xfer->rx_done != xfer->rx_len)
1009 exynos_dsi_read_from_fifo(dsi, xfer);
1011 if (xfer->rx_done != xfer->rx_len)
1014 spin_lock_irqsave(&dsi->transfer_lock, flags);
1016 list_del_init(&xfer->list);
1017 start = !list_empty(&dsi->transfer_list);
1019 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1023 complete(&xfer->completed);
1028 static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi,
1029 struct exynos_dsi_transfer *xfer)
1031 unsigned long flags;
1034 spin_lock_irqsave(&dsi->transfer_lock, flags);
1036 if (!list_empty(&dsi->transfer_list) &&
1037 xfer == list_first_entry(&dsi->transfer_list,
1038 struct exynos_dsi_transfer, list)) {
1039 list_del_init(&xfer->list);
1040 start = !list_empty(&dsi->transfer_list);
1041 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1043 exynos_dsi_transfer_start(dsi);
1047 list_del_init(&xfer->list);
1049 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1052 static int exynos_dsi_transfer(struct exynos_dsi *dsi,
1053 struct exynos_dsi_transfer *xfer)
1055 unsigned long flags;
1060 xfer->result = -ETIMEDOUT;
1061 init_completion(&xfer->completed);
1063 spin_lock_irqsave(&dsi->transfer_lock, flags);
1065 stopped = list_empty(&dsi->transfer_list);
1066 list_add_tail(&xfer->list, &dsi->transfer_list);
1068 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
1071 exynos_dsi_transfer_start(dsi);
1073 wait_for_completion_timeout(&xfer->completed,
1074 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
1075 if (xfer->result == -ETIMEDOUT) {
1076 exynos_dsi_remove_transfer(dsi, xfer);
1077 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 2, xfer->data,
1078 xfer->tx_len, xfer->tx_payload);
1082 /* Also covers hardware timeout condition */
1083 return xfer->result;
1086 static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
1088 struct exynos_dsi *dsi = dev_id;
1091 status = readl(dsi->reg_base + DSIM_INTSRC_REG);
1093 static unsigned long int j;
1094 if (printk_timed_ratelimit(&j, 500))
1095 dev_warn(dsi->dev, "spurious interrupt\n");
1098 writel(status, dsi->reg_base + DSIM_INTSRC_REG);
1100 if (status & DSIM_INT_SW_RST_RELEASE) {
1101 u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY);
1102 writel(mask, dsi->reg_base + DSIM_INTMSK_REG);
1103 complete(&dsi->completed);
1107 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY)))
1110 if (exynos_dsi_transfer_finish(dsi))
1111 exynos_dsi_transfer_start(dsi);
1116 static irqreturn_t exynos_dsi_te_irq_handler(int irq, void *dev_id)
1118 struct exynos_dsi *dsi = (struct exynos_dsi *)dev_id;
1119 struct drm_encoder *encoder = dsi->display.encoder;
1121 if (dsi->state & DSIM_STATE_ENABLED)
1122 exynos_drm_crtc_te_handler(encoder->crtc);
1127 static void exynos_dsi_enable_irq(struct exynos_dsi *dsi)
1129 enable_irq(dsi->irq);
1131 if (gpio_is_valid(dsi->te_gpio))
1132 enable_irq(gpio_to_irq(dsi->te_gpio));
1135 static void exynos_dsi_disable_irq(struct exynos_dsi *dsi)
1137 if (gpio_is_valid(dsi->te_gpio))
1138 disable_irq(gpio_to_irq(dsi->te_gpio));
1140 disable_irq(dsi->irq);
1143 static int exynos_dsi_init(struct exynos_dsi *dsi)
1145 exynos_dsi_reset(dsi);
1146 exynos_dsi_enable_irq(dsi);
1147 exynos_dsi_enable_clock(dsi);
1148 exynos_dsi_wait_for_reset(dsi);
1149 exynos_dsi_set_phy_ctrl(dsi);
1150 exynos_dsi_init_link(dsi);
1155 static int exynos_dsi_register_te_irq(struct exynos_dsi *dsi)
1160 dsi->te_gpio = of_get_named_gpio(dsi->panel_node, "te-gpios", 0);
1161 if (!gpio_is_valid(dsi->te_gpio)) {
1162 dev_err(dsi->dev, "no te-gpios specified\n");
1167 ret = gpio_request_one(dsi->te_gpio, GPIOF_IN, "te_gpio");
1169 dev_err(dsi->dev, "gpio request failed with %d\n", ret);
1173 te_gpio_irq = gpio_to_irq(dsi->te_gpio);
1175 irq_set_status_flags(te_gpio_irq, IRQ_NOAUTOEN);
1176 ret = request_threaded_irq(te_gpio_irq, exynos_dsi_te_irq_handler, NULL,
1177 IRQF_TRIGGER_RISING, "TE", dsi);
1179 dev_err(dsi->dev, "request interrupt failed with %d\n", ret);
1180 gpio_free(dsi->te_gpio);
1188 static void exynos_dsi_unregister_te_irq(struct exynos_dsi *dsi)
1190 if (gpio_is_valid(dsi->te_gpio)) {
1191 free_irq(gpio_to_irq(dsi->te_gpio), dsi);
1192 gpio_free(dsi->te_gpio);
1193 dsi->te_gpio = -ENOENT;
1197 static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
1198 struct mipi_dsi_device *device)
1200 struct exynos_dsi *dsi = host_to_dsi(host);
1202 dsi->lanes = device->lanes;
1203 dsi->format = device->format;
1204 dsi->mode_flags = device->mode_flags;
1205 dsi->panel_node = device->dev.of_node;
1208 * This is a temporary solution and should be made by more generic way.
1210 * If attached panel device is for command mode one, dsi should register
1211 * TE interrupt handler.
1213 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1214 int ret = exynos_dsi_register_te_irq(dsi);
1220 if (dsi->connector.dev)
1221 drm_helper_hpd_irq_event(dsi->connector.dev);
1226 static int exynos_dsi_host_detach(struct mipi_dsi_host *host,
1227 struct mipi_dsi_device *device)
1229 struct exynos_dsi *dsi = host_to_dsi(host);
1231 exynos_dsi_unregister_te_irq(dsi);
1233 dsi->panel_node = NULL;
1235 if (dsi->connector.dev)
1236 drm_helper_hpd_irq_event(dsi->connector.dev);
1241 /* distinguish between short and long DSI packet types */
1242 static bool exynos_dsi_is_short_dsi_type(u8 type)
1244 return (type & 0x0f) <= 8;
1247 static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host,
1248 const struct mipi_dsi_msg *msg)
1250 struct exynos_dsi *dsi = host_to_dsi(host);
1251 struct exynos_dsi_transfer xfer;
1254 if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
1255 ret = exynos_dsi_init(dsi);
1258 dsi->state |= DSIM_STATE_INITIALIZED;
1261 if (msg->tx_len == 0)
1264 xfer.data_id = msg->type | (msg->channel << 6);
1266 if (exynos_dsi_is_short_dsi_type(msg->type)) {
1267 const char *tx_buf = msg->tx_buf;
1269 if (msg->tx_len > 2)
1272 xfer.data[0] = tx_buf[0];
1273 xfer.data[1] = (msg->tx_len == 2) ? tx_buf[1] : 0;
1275 xfer.tx_len = msg->tx_len;
1276 xfer.data[0] = msg->tx_len & 0xff;
1277 xfer.data[1] = msg->tx_len >> 8;
1278 xfer.tx_payload = msg->tx_buf;
1281 xfer.rx_len = msg->rx_len;
1282 xfer.rx_payload = msg->rx_buf;
1283 xfer.flags = msg->flags;
1285 ret = exynos_dsi_transfer(dsi, &xfer);
1286 return (ret < 0) ? ret : xfer.rx_done;
1289 static const struct mipi_dsi_host_ops exynos_dsi_ops = {
1290 .attach = exynos_dsi_host_attach,
1291 .detach = exynos_dsi_host_detach,
1292 .transfer = exynos_dsi_host_transfer,
1295 static int exynos_dsi_poweron(struct exynos_dsi *dsi)
1299 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1301 dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
1305 ret = clk_prepare_enable(dsi->bus_clk);
1307 dev_err(dsi->dev, "cannot enable bus clock %d\n", ret);
1311 ret = clk_prepare_enable(dsi->pll_clk);
1313 dev_err(dsi->dev, "cannot enable pll clock %d\n", ret);
1317 ret = phy_power_on(dsi->phy);
1319 dev_err(dsi->dev, "cannot enable phy %d\n", ret);
1326 clk_disable_unprepare(dsi->pll_clk);
1328 clk_disable_unprepare(dsi->bus_clk);
1330 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1335 static void exynos_dsi_poweroff(struct exynos_dsi *dsi)
1339 usleep_range(10000, 20000);
1341 if (dsi->state & DSIM_STATE_INITIALIZED) {
1342 dsi->state &= ~DSIM_STATE_INITIALIZED;
1344 exynos_dsi_disable_clock(dsi);
1346 exynos_dsi_disable_irq(dsi);
1349 dsi->state &= ~DSIM_STATE_CMD_LPM;
1351 phy_power_off(dsi->phy);
1353 clk_disable_unprepare(dsi->pll_clk);
1354 clk_disable_unprepare(dsi->bus_clk);
1356 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1358 dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
1361 static int exynos_dsi_enable(struct exynos_dsi *dsi)
1365 if (dsi->state & DSIM_STATE_ENABLED)
1368 ret = exynos_dsi_poweron(dsi);
1372 ret = drm_panel_prepare(dsi->panel);
1374 exynos_dsi_poweroff(dsi);
1378 exynos_dsi_set_display_mode(dsi);
1379 exynos_dsi_set_display_enable(dsi, true);
1381 dsi->state |= DSIM_STATE_ENABLED;
1383 ret = drm_panel_enable(dsi->panel);
1385 dsi->state &= ~DSIM_STATE_ENABLED;
1386 exynos_dsi_set_display_enable(dsi, false);
1387 drm_panel_unprepare(dsi->panel);
1388 exynos_dsi_poweroff(dsi);
1395 static void exynos_dsi_disable(struct exynos_dsi *dsi)
1397 if (!(dsi->state & DSIM_STATE_ENABLED))
1400 drm_panel_disable(dsi->panel);
1401 exynos_dsi_set_display_enable(dsi, false);
1402 drm_panel_unprepare(dsi->panel);
1403 exynos_dsi_poweroff(dsi);
1405 dsi->state &= ~DSIM_STATE_ENABLED;
1408 static void exynos_dsi_dpms(struct exynos_drm_display *display, int mode)
1410 struct exynos_dsi *dsi = display_to_dsi(display);
1414 case DRM_MODE_DPMS_ON:
1415 exynos_dsi_enable(dsi);
1417 case DRM_MODE_DPMS_STANDBY:
1418 case DRM_MODE_DPMS_SUSPEND:
1419 case DRM_MODE_DPMS_OFF:
1420 exynos_dsi_disable(dsi);
1428 static enum drm_connector_status
1429 exynos_dsi_detect(struct drm_connector *connector, bool force)
1431 struct exynos_dsi *dsi = connector_to_dsi(connector);
1434 dsi->panel = of_drm_find_panel(dsi->panel_node);
1436 drm_panel_attach(dsi->panel, &dsi->connector);
1437 } else if (!dsi->panel_node) {
1438 struct exynos_drm_display *display;
1440 display = platform_get_drvdata(to_platform_device(dsi->dev));
1441 exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF);
1442 drm_panel_detach(dsi->panel);
1447 return connector_status_connected;
1449 return connector_status_disconnected;
1452 static void exynos_dsi_connector_destroy(struct drm_connector *connector)
1454 drm_connector_unregister(connector);
1455 drm_connector_cleanup(connector);
1456 connector->dev = NULL;
1459 static struct drm_connector_funcs exynos_dsi_connector_funcs = {
1460 .dpms = drm_helper_connector_dpms,
1461 .detect = exynos_dsi_detect,
1462 .fill_modes = drm_helper_probe_single_connector_modes,
1463 .destroy = exynos_dsi_connector_destroy,
1466 static int exynos_dsi_get_modes(struct drm_connector *connector)
1468 struct exynos_dsi *dsi = connector_to_dsi(connector);
1471 return dsi->panel->funcs->get_modes(dsi->panel);
1476 static int exynos_dsi_mode_valid(struct drm_connector *connector,
1477 struct drm_display_mode *mode)
1482 static struct drm_encoder *
1483 exynos_dsi_best_encoder(struct drm_connector *connector)
1485 struct exynos_dsi *dsi = connector_to_dsi(connector);
1487 return dsi->display.encoder;
1490 static struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = {
1491 .get_modes = exynos_dsi_get_modes,
1492 .mode_valid = exynos_dsi_mode_valid,
1493 .best_encoder = exynos_dsi_best_encoder,
1496 static int exynos_dsi_create_connector(struct exynos_drm_display *display,
1497 struct drm_encoder *encoder)
1499 struct exynos_dsi *dsi = display_to_dsi(display);
1500 struct drm_connector *connector = &dsi->connector;
1503 connector->polled = DRM_CONNECTOR_POLL_HPD;
1505 ret = drm_connector_init(encoder->dev, connector,
1506 &exynos_dsi_connector_funcs,
1507 DRM_MODE_CONNECTOR_DSI);
1509 DRM_ERROR("Failed to initialize connector with drm\n");
1513 drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs);
1514 drm_connector_register(connector);
1515 drm_mode_connector_attach_encoder(connector, encoder);
1520 static void exynos_dsi_mode_set(struct exynos_drm_display *display,
1521 struct drm_display_mode *mode)
1523 struct exynos_dsi *dsi = display_to_dsi(display);
1524 struct videomode *vm = &dsi->vm;
1526 vm->hactive = mode->hdisplay;
1527 vm->vactive = mode->vdisplay;
1528 vm->vfront_porch = mode->vsync_start - mode->vdisplay;
1529 vm->vback_porch = mode->vtotal - mode->vsync_end;
1530 vm->vsync_len = mode->vsync_end - mode->vsync_start;
1531 vm->hfront_porch = mode->hsync_start - mode->hdisplay;
1532 vm->hback_porch = mode->htotal - mode->hsync_end;
1533 vm->hsync_len = mode->hsync_end - mode->hsync_start;
1536 static struct exynos_drm_display_ops exynos_dsi_display_ops = {
1537 .create_connector = exynos_dsi_create_connector,
1538 .mode_set = exynos_dsi_mode_set,
1539 .dpms = exynos_dsi_dpms
1542 MODULE_DEVICE_TABLE(of, exynos_dsi_of_match);
1544 /* of_* functions will be removed after merge of of_graph patches */
1545 static struct device_node *
1546 of_get_child_by_name_reg(struct device_node *parent, const char *name, u32 reg)
1548 struct device_node *np;
1550 for_each_child_of_node(parent, np) {
1553 if (!np->name || of_node_cmp(np->name, name))
1556 if (of_property_read_u32(np, "reg", &r) < 0)
1566 static struct device_node *of_graph_get_port_by_reg(struct device_node *parent,
1569 struct device_node *ports, *port;
1571 ports = of_get_child_by_name(parent, "ports");
1575 port = of_get_child_by_name_reg(parent, "port", reg);
1582 static struct device_node *
1583 of_graph_get_endpoint_by_reg(struct device_node *port, u32 reg)
1585 return of_get_child_by_name_reg(port, "endpoint", reg);
1588 static int exynos_dsi_of_read_u32(const struct device_node *np,
1589 const char *propname, u32 *out_value)
1591 int ret = of_property_read_u32(np, propname, out_value);
1594 pr_err("%s: failed to get '%s' property\n", np->full_name,
1605 static int exynos_dsi_parse_dt(struct exynos_dsi *dsi)
1607 struct device *dev = dsi->dev;
1608 struct device_node *node = dev->of_node;
1609 struct device_node *port, *ep;
1612 ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
1613 &dsi->pll_clk_rate);
1617 port = of_graph_get_port_by_reg(node, DSI_PORT_OUT);
1619 dev_err(dev, "no output port specified\n");
1623 ep = of_graph_get_endpoint_by_reg(port, 0);
1626 dev_err(dev, "no endpoint specified in output port\n");
1630 ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency",
1631 &dsi->burst_clk_rate);
1635 ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency",
1636 &dsi->esc_clk_rate);
1644 static int exynos_dsi_bind(struct device *dev, struct device *master,
1647 struct exynos_drm_display *display = dev_get_drvdata(dev);
1648 struct exynos_dsi *dsi = display_to_dsi(display);
1649 struct drm_device *drm_dev = data;
1652 ret = exynos_drm_create_enc_conn(drm_dev, display);
1654 DRM_ERROR("Encoder create [%d] failed with %d\n",
1655 display->type, ret);
1659 return mipi_dsi_host_register(&dsi->dsi_host);
1662 static void exynos_dsi_unbind(struct device *dev, struct device *master,
1665 struct exynos_drm_display *display = dev_get_drvdata(dev);
1666 struct exynos_dsi *dsi = display_to_dsi(display);
1668 exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF);
1670 mipi_dsi_host_unregister(&dsi->dsi_host);
1673 static const struct component_ops exynos_dsi_component_ops = {
1674 .bind = exynos_dsi_bind,
1675 .unbind = exynos_dsi_unbind,
1678 static int exynos_dsi_probe(struct platform_device *pdev)
1680 struct device *dev = &pdev->dev;
1681 struct resource *res;
1682 struct exynos_dsi *dsi;
1685 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1689 dsi->display.type = EXYNOS_DISPLAY_TYPE_LCD;
1690 dsi->display.ops = &exynos_dsi_display_ops;
1692 ret = exynos_drm_component_add(dev, EXYNOS_DEVICE_TYPE_CONNECTOR,
1697 /* To be checked as invalid one */
1698 dsi->te_gpio = -ENOENT;
1700 init_completion(&dsi->completed);
1701 spin_lock_init(&dsi->transfer_lock);
1702 INIT_LIST_HEAD(&dsi->transfer_list);
1704 dsi->dsi_host.ops = &exynos_dsi_ops;
1705 dsi->dsi_host.dev = dev;
1708 dsi->driver_data = exynos_dsi_get_driver_data(pdev);
1710 ret = exynos_dsi_parse_dt(dsi);
1712 goto err_del_component;
1714 dsi->supplies[0].supply = "vddcore";
1715 dsi->supplies[1].supply = "vddio";
1716 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies),
1719 dev_info(dev, "failed to get regulators: %d\n", ret);
1720 return -EPROBE_DEFER;
1723 dsi->pll_clk = devm_clk_get(dev, "pll_clk");
1724 if (IS_ERR(dsi->pll_clk)) {
1725 dev_info(dev, "failed to get dsi pll input clock\n");
1726 ret = PTR_ERR(dsi->pll_clk);
1727 goto err_del_component;
1730 dsi->bus_clk = devm_clk_get(dev, "bus_clk");
1731 if (IS_ERR(dsi->bus_clk)) {
1732 dev_info(dev, "failed to get dsi bus clock\n");
1733 ret = PTR_ERR(dsi->bus_clk);
1734 goto err_del_component;
1737 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1738 dsi->reg_base = devm_ioremap_resource(dev, res);
1739 if (IS_ERR(dsi->reg_base)) {
1740 dev_err(dev, "failed to remap io region\n");
1741 ret = PTR_ERR(dsi->reg_base);
1742 goto err_del_component;
1745 dsi->phy = devm_phy_get(dev, "dsim");
1746 if (IS_ERR(dsi->phy)) {
1747 dev_info(dev, "failed to get dsim phy\n");
1748 ret = PTR_ERR(dsi->phy);
1749 goto err_del_component;
1752 dsi->irq = platform_get_irq(pdev, 0);
1754 dev_err(dev, "failed to request dsi irq resource\n");
1756 goto err_del_component;
1759 irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN);
1760 ret = devm_request_threaded_irq(dev, dsi->irq, NULL,
1761 exynos_dsi_irq, IRQF_ONESHOT,
1762 dev_name(dev), dsi);
1764 dev_err(dev, "failed to request dsi irq\n");
1765 goto err_del_component;
1768 platform_set_drvdata(pdev, &dsi->display);
1770 ret = component_add(dev, &exynos_dsi_component_ops);
1772 goto err_del_component;
1777 exynos_drm_component_del(dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
1781 static int exynos_dsi_remove(struct platform_device *pdev)
1783 component_del(&pdev->dev, &exynos_dsi_component_ops);
1784 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
1789 struct platform_driver dsi_driver = {
1790 .probe = exynos_dsi_probe,
1791 .remove = exynos_dsi_remove,
1793 .name = "exynos-dsi",
1794 .owner = THIS_MODULE,
1795 .of_match_table = exynos_dsi_of_match,
1799 MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
1800 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
1801 MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master");
1802 MODULE_LICENSE("GPL v2");