2 * Copyright (C) 2012 Samsung Electronics Co.Ltd
4 * Eunchul Kim <chulspro.kim@samsung.com>
5 * Jinyoung Jeon <jy0.jeon@samsung.com>
6 * Sangmin Lee <lsmin.lee@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/regmap.h>
18 #include <linux/clk.h>
19 #include <linux/pm_runtime.h>
21 #include <linux/spinlock.h>
24 #include <drm/exynos_drm.h>
25 #include "regs-fimc.h"
26 #include "exynos_drm_drv.h"
27 #include "exynos_drm_ipp.h"
28 #include "exynos_drm_fimc.h"
31 * FIMC stands for Fully Interactive Mobile Camera and
32 * supports image scaler/rotator and input/output DMA operations.
33 * input DMA reads image data from the memory.
34 * output DMA writes image data to memory.
35 * FIMC supports image rotation and image effect functions.
37 * M2M operation : supports crop/scale/rotation/csc so on.
38 * Memory ----> FIMC H/W ----> Memory.
39 * Writeback operation : supports cloned screen with FIMD.
40 * FIMD ----> FIMC H/W ----> Memory.
41 * Output operation : supports direct display using local path.
42 * Memory ----> FIMC H/W ----> FIMD.
47 * 1. check suspend/resume api if needed.
48 * 2. need to check use case platform_device_id.
49 * 3. check src/dst size with, height.
50 * 4. added check_prepare api for right register.
51 * 5. need to add supported list in prop_list.
52 * 6. check prescaler/scaler optimization.
55 #define FIMC_MAX_DEVS 4
56 #define FIMC_MAX_SRC 2
57 #define FIMC_MAX_DST 32
58 #define FIMC_SHFACTOR 10
59 #define FIMC_BUF_STOP 1
60 #define FIMC_BUF_START 2
61 #define FIMC_WIDTH_ITU_709 1280
62 #define FIMC_REFRESH_MAX 60
63 #define FIMC_REFRESH_MIN 12
64 #define FIMC_CROP_MAX 8192
65 #define FIMC_CROP_MIN 32
66 #define FIMC_SCALE_MAX 4224
67 #define FIMC_SCALE_MIN 32
69 #define get_fimc_context(dev) platform_get_drvdata(to_platform_device(dev))
70 #define get_ctx_from_ippdrv(ippdrv) container_of(ippdrv,\
71 struct fimc_context, ippdrv);
88 static const char * const fimc_clock_names[] = {
89 [FIMC_CLK_LCLK] = "sclk_fimc",
90 [FIMC_CLK_GATE] = "fimc",
91 [FIMC_CLK_WB_A] = "pxl_async0",
92 [FIMC_CLK_WB_B] = "pxl_async1",
93 [FIMC_CLK_MUX] = "mux",
94 [FIMC_CLK_PARENT] = "parent",
97 #define FIMC_DEFAULT_LCLK_FREQUENCY 133000000UL
100 * A structure of scaler.
102 * @range: narrow, wide.
103 * @bypass: unused scaler path.
104 * @up_h: horizontal scale up.
105 * @up_v: vertical scale up.
106 * @hratio: horizontal ratio.
107 * @vratio: vertical ratio.
119 * A structure of scaler capability.
121 * find user manual table 43-1.
122 * @in_hori: scaler input horizontal size.
123 * @bypass: scaler bypass mode.
124 * @dst_h_wo_rot: target horizontal size without output rotation.
125 * @dst_h_rot: target horizontal size with output rotation.
126 * @rl_w_wo_rot: real width without input rotation.
127 * @rl_h_rot: real height without output rotation.
129 struct fimc_capability {
142 * A structure of fimc context.
144 * @ippdrv: prepare initialization using ippdrv.
145 * @regs_res: register resources.
146 * @regs: memory mapped io registers.
147 * @lock: locking of operations.
148 * @clocks: fimc clocks.
149 * @clk_frequency: LCLK clock frequency.
150 * @sysreg: handle to SYSREG block regmap.
151 * @sc: scaler infomations.
152 * @pol: porarity of writeback.
155 * @suspended: qos operations.
157 struct fimc_context {
158 struct exynos_drm_ippdrv ippdrv;
159 struct resource *regs_res;
162 struct clk *clocks[FIMC_CLKS_MAX];
164 struct regmap *sysreg;
165 struct fimc_scaler sc;
166 struct exynos_drm_ipp_pol pol;
172 static u32 fimc_read(struct fimc_context *ctx, u32 reg)
174 return readl(ctx->regs + reg);
177 static void fimc_write(struct fimc_context *ctx, u32 val, u32 reg)
179 writel(val, ctx->regs + reg);
182 static void fimc_set_bits(struct fimc_context *ctx, u32 reg, u32 bits)
184 void __iomem *r = ctx->regs + reg;
186 writel(readl(r) | bits, r);
189 static void fimc_clear_bits(struct fimc_context *ctx, u32 reg, u32 bits)
191 void __iomem *r = ctx->regs + reg;
193 writel(readl(r) & ~bits, r);
196 static void fimc_sw_reset(struct fimc_context *ctx)
200 /* stop dma operation */
201 cfg = fimc_read(ctx, EXYNOS_CISTATUS);
202 if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg))
203 fimc_clear_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID);
205 fimc_set_bits(ctx, EXYNOS_CISRCFMT, EXYNOS_CISRCFMT_ITU601_8BIT);
207 /* disable image capture */
208 fimc_clear_bits(ctx, EXYNOS_CIIMGCPT,
209 EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
212 fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_SWRST);
214 /* s/w reset complete */
215 fimc_clear_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_SWRST);
218 fimc_write(ctx, 0x0, EXYNOS_CIFCNTSEQ);
221 static int fimc_set_camblk_fimd0_wb(struct fimc_context *ctx)
223 return regmap_update_bits(ctx->sysreg, SYSREG_CAMERA_BLK,
224 SYSREG_FIMD0WB_DEST_MASK,
225 ctx->id << SYSREG_FIMD0WB_DEST_SHIFT);
228 static void fimc_set_type_ctrl(struct fimc_context *ctx, enum fimc_wb wb)
232 DRM_DEBUG_KMS("wb[%d]\n", wb);
234 cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
235 cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK |
236 EXYNOS_CIGCTRL_SELCAM_ITU_MASK |
237 EXYNOS_CIGCTRL_SELCAM_MIPI_MASK |
238 EXYNOS_CIGCTRL_SELCAM_FIMC_MASK |
239 EXYNOS_CIGCTRL_SELWB_CAMIF_MASK |
240 EXYNOS_CIGCTRL_SELWRITEBACK_MASK);
244 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_A |
245 EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK);
248 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_B |
249 EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK);
253 cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A |
254 EXYNOS_CIGCTRL_SELWRITEBACK_A |
255 EXYNOS_CIGCTRL_SELCAM_MIPI_A |
256 EXYNOS_CIGCTRL_SELCAM_FIMC_ITU);
260 fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
263 static void fimc_set_polarity(struct fimc_context *ctx,
264 struct exynos_drm_ipp_pol *pol)
268 DRM_DEBUG_KMS("inv_pclk[%d]inv_vsync[%d]\n",
269 pol->inv_pclk, pol->inv_vsync);
270 DRM_DEBUG_KMS("inv_href[%d]inv_hsync[%d]\n",
271 pol->inv_href, pol->inv_hsync);
273 cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
274 cfg &= ~(EXYNOS_CIGCTRL_INVPOLPCLK | EXYNOS_CIGCTRL_INVPOLVSYNC |
275 EXYNOS_CIGCTRL_INVPOLHREF | EXYNOS_CIGCTRL_INVPOLHSYNC);
278 cfg |= EXYNOS_CIGCTRL_INVPOLPCLK;
280 cfg |= EXYNOS_CIGCTRL_INVPOLVSYNC;
282 cfg |= EXYNOS_CIGCTRL_INVPOLHREF;
284 cfg |= EXYNOS_CIGCTRL_INVPOLHSYNC;
286 fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
289 static void fimc_handle_jpeg(struct fimc_context *ctx, bool enable)
293 DRM_DEBUG_KMS("enable[%d]\n", enable);
295 cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
297 cfg |= EXYNOS_CIGCTRL_CAM_JPEG;
299 cfg &= ~EXYNOS_CIGCTRL_CAM_JPEG;
301 fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
304 static void fimc_mask_irq(struct fimc_context *ctx, bool enable)
308 DRM_DEBUG_KMS("enable[%d]\n", enable);
310 cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
312 cfg &= ~EXYNOS_CIGCTRL_IRQ_OVFEN;
313 cfg |= EXYNOS_CIGCTRL_IRQ_ENABLE | EXYNOS_CIGCTRL_IRQ_LEVEL;
315 cfg &= ~EXYNOS_CIGCTRL_IRQ_ENABLE;
316 fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
319 static void fimc_clear_irq(struct fimc_context *ctx)
321 fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_CLR);
324 static bool fimc_check_ovf(struct fimc_context *ctx)
326 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
329 status = fimc_read(ctx, EXYNOS_CISTATUS);
330 flag = EXYNOS_CISTATUS_OVFIY | EXYNOS_CISTATUS_OVFICB |
331 EXYNOS_CISTATUS_OVFICR;
333 DRM_DEBUG_KMS("flag[0x%x]\n", flag);
336 fimc_set_bits(ctx, EXYNOS_CIWDOFST,
337 EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB |
338 EXYNOS_CIWDOFST_CLROVFICR);
340 dev_err(ippdrv->dev, "occurred overflow at %d, status 0x%x.\n",
348 static bool fimc_check_frame_end(struct fimc_context *ctx)
352 cfg = fimc_read(ctx, EXYNOS_CISTATUS);
354 DRM_DEBUG_KMS("cfg[0x%x]\n", cfg);
356 if (!(cfg & EXYNOS_CISTATUS_FRAMEEND))
359 cfg &= ~(EXYNOS_CISTATUS_FRAMEEND);
360 fimc_write(ctx, cfg, EXYNOS_CISTATUS);
365 static int fimc_get_buf_id(struct fimc_context *ctx)
368 int frame_cnt, buf_id;
370 cfg = fimc_read(ctx, EXYNOS_CISTATUS2);
371 frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg);
374 frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg);
376 DRM_DEBUG_KMS("present[%d]before[%d]\n",
377 EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg),
378 EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg));
380 if (frame_cnt == 0) {
381 DRM_ERROR("failed to get frame count.\n");
385 buf_id = frame_cnt - 1;
386 DRM_DEBUG_KMS("buf_id[%d]\n", buf_id);
391 static void fimc_handle_lastend(struct fimc_context *ctx, bool enable)
395 DRM_DEBUG_KMS("enable[%d]\n", enable);
397 cfg = fimc_read(ctx, EXYNOS_CIOCTRL);
399 cfg |= EXYNOS_CIOCTRL_LASTENDEN;
401 cfg &= ~EXYNOS_CIOCTRL_LASTENDEN;
403 fimc_write(ctx, cfg, EXYNOS_CIOCTRL);
407 static int fimc_src_set_fmt_order(struct fimc_context *ctx, u32 fmt)
409 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
412 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
415 cfg = fimc_read(ctx, EXYNOS_CISCCTRL);
416 cfg &= ~EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK;
419 case DRM_FORMAT_RGB565:
420 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB565;
421 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
423 case DRM_FORMAT_RGB888:
424 case DRM_FORMAT_XRGB8888:
425 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB888;
426 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
434 cfg = fimc_read(ctx, EXYNOS_MSCTRL);
435 cfg &= ~(EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK |
436 EXYNOS_MSCTRL_C_INT_IN_2PLANE |
437 EXYNOS_MSCTRL_ORDER422_YCBYCR);
440 case DRM_FORMAT_YUYV:
441 cfg |= EXYNOS_MSCTRL_ORDER422_YCBYCR;
443 case DRM_FORMAT_YVYU:
444 cfg |= EXYNOS_MSCTRL_ORDER422_YCRYCB;
446 case DRM_FORMAT_UYVY:
447 cfg |= EXYNOS_MSCTRL_ORDER422_CBYCRY;
449 case DRM_FORMAT_VYUY:
450 case DRM_FORMAT_YUV444:
451 cfg |= EXYNOS_MSCTRL_ORDER422_CRYCBY;
453 case DRM_FORMAT_NV21:
454 case DRM_FORMAT_NV61:
455 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CRCB |
456 EXYNOS_MSCTRL_C_INT_IN_2PLANE);
458 case DRM_FORMAT_YUV422:
459 case DRM_FORMAT_YUV420:
460 case DRM_FORMAT_YVU420:
461 cfg |= EXYNOS_MSCTRL_C_INT_IN_3PLANE;
463 case DRM_FORMAT_NV12:
464 case DRM_FORMAT_NV12MT:
465 case DRM_FORMAT_NV16:
466 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CBCR |
467 EXYNOS_MSCTRL_C_INT_IN_2PLANE);
470 dev_err(ippdrv->dev, "inavlid source yuv order 0x%x.\n", fmt);
474 fimc_write(ctx, cfg, EXYNOS_MSCTRL);
479 static int fimc_src_set_fmt(struct device *dev, u32 fmt)
481 struct fimc_context *ctx = get_fimc_context(dev);
482 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
485 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
487 cfg = fimc_read(ctx, EXYNOS_MSCTRL);
488 cfg &= ~EXYNOS_MSCTRL_INFORMAT_RGB;
491 case DRM_FORMAT_RGB565:
492 case DRM_FORMAT_RGB888:
493 case DRM_FORMAT_XRGB8888:
494 cfg |= EXYNOS_MSCTRL_INFORMAT_RGB;
496 case DRM_FORMAT_YUV444:
497 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
499 case DRM_FORMAT_YUYV:
500 case DRM_FORMAT_YVYU:
501 case DRM_FORMAT_UYVY:
502 case DRM_FORMAT_VYUY:
503 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE;
505 case DRM_FORMAT_NV16:
506 case DRM_FORMAT_NV61:
507 case DRM_FORMAT_YUV422:
508 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422;
510 case DRM_FORMAT_YUV420:
511 case DRM_FORMAT_YVU420:
512 case DRM_FORMAT_NV12:
513 case DRM_FORMAT_NV21:
514 case DRM_FORMAT_NV12MT:
515 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
518 dev_err(ippdrv->dev, "inavlid source format 0x%x.\n", fmt);
522 fimc_write(ctx, cfg, EXYNOS_MSCTRL);
524 cfg = fimc_read(ctx, EXYNOS_CIDMAPARAM);
525 cfg &= ~EXYNOS_CIDMAPARAM_R_MODE_MASK;
527 if (fmt == DRM_FORMAT_NV12MT)
528 cfg |= EXYNOS_CIDMAPARAM_R_MODE_64X32;
530 cfg |= EXYNOS_CIDMAPARAM_R_MODE_LINEAR;
532 fimc_write(ctx, cfg, EXYNOS_CIDMAPARAM);
534 return fimc_src_set_fmt_order(ctx, fmt);
537 static int fimc_src_set_transf(struct device *dev,
538 enum drm_exynos_degree degree,
539 enum drm_exynos_flip flip, bool *swap)
541 struct fimc_context *ctx = get_fimc_context(dev);
542 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
545 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
547 cfg1 = fimc_read(ctx, EXYNOS_MSCTRL);
548 cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR |
549 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
551 cfg2 = fimc_read(ctx, EXYNOS_CITRGFMT);
552 cfg2 &= ~EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
555 case EXYNOS_DRM_DEGREE_0:
556 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
557 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
558 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
559 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
561 case EXYNOS_DRM_DEGREE_90:
562 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
563 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
564 cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
565 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
566 cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
568 case EXYNOS_DRM_DEGREE_180:
569 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
570 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
571 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
572 cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
573 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
574 cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
576 case EXYNOS_DRM_DEGREE_270:
577 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
578 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
579 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
580 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
581 cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
582 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
583 cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
586 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
590 fimc_write(ctx, cfg1, EXYNOS_MSCTRL);
591 fimc_write(ctx, cfg2, EXYNOS_CITRGFMT);
592 *swap = (cfg2 & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) ? 1 : 0;
597 static int fimc_set_window(struct fimc_context *ctx,
598 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
600 u32 cfg, h1, h2, v1, v2;
604 h2 = sz->hsize - pos->w - pos->x;
606 v2 = sz->vsize - pos->h - pos->y;
608 DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]hsize[%d]vsize[%d]\n",
609 pos->x, pos->y, pos->w, pos->h, sz->hsize, sz->vsize);
610 DRM_DEBUG_KMS("h1[%d]h2[%d]v1[%d]v2[%d]\n", h1, h2, v1, v2);
613 * set window offset 1, 2 size
614 * check figure 43-21 in user manual
616 cfg = fimc_read(ctx, EXYNOS_CIWDOFST);
617 cfg &= ~(EXYNOS_CIWDOFST_WINHOROFST_MASK |
618 EXYNOS_CIWDOFST_WINVEROFST_MASK);
619 cfg |= (EXYNOS_CIWDOFST_WINHOROFST(h1) |
620 EXYNOS_CIWDOFST_WINVEROFST(v1));
621 cfg |= EXYNOS_CIWDOFST_WINOFSEN;
622 fimc_write(ctx, cfg, EXYNOS_CIWDOFST);
624 cfg = (EXYNOS_CIWDOFST2_WINHOROFST2(h2) |
625 EXYNOS_CIWDOFST2_WINVEROFST2(v2));
626 fimc_write(ctx, cfg, EXYNOS_CIWDOFST2);
631 static int fimc_src_set_size(struct device *dev, int swap,
632 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
634 struct fimc_context *ctx = get_fimc_context(dev);
635 struct drm_exynos_pos img_pos = *pos;
636 struct drm_exynos_sz img_sz = *sz;
639 DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n",
640 swap, sz->hsize, sz->vsize);
643 cfg = (EXYNOS_ORGISIZE_HORIZONTAL(img_sz.hsize) |
644 EXYNOS_ORGISIZE_VERTICAL(img_sz.vsize));
646 fimc_write(ctx, cfg, EXYNOS_ORGISIZE);
648 DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h);
653 img_sz.hsize = sz->vsize;
654 img_sz.vsize = sz->hsize;
657 /* set input DMA image size */
658 cfg = fimc_read(ctx, EXYNOS_CIREAL_ISIZE);
659 cfg &= ~(EXYNOS_CIREAL_ISIZE_HEIGHT_MASK |
660 EXYNOS_CIREAL_ISIZE_WIDTH_MASK);
661 cfg |= (EXYNOS_CIREAL_ISIZE_WIDTH(img_pos.w) |
662 EXYNOS_CIREAL_ISIZE_HEIGHT(img_pos.h));
663 fimc_write(ctx, cfg, EXYNOS_CIREAL_ISIZE);
666 * set input FIFO image size
667 * for now, we support only ITU601 8 bit mode
669 cfg = (EXYNOS_CISRCFMT_ITU601_8BIT |
670 EXYNOS_CISRCFMT_SOURCEHSIZE(img_sz.hsize) |
671 EXYNOS_CISRCFMT_SOURCEVSIZE(img_sz.vsize));
672 fimc_write(ctx, cfg, EXYNOS_CISRCFMT);
674 /* offset Y(RGB), Cb, Cr */
675 cfg = (EXYNOS_CIIYOFF_HORIZONTAL(img_pos.x) |
676 EXYNOS_CIIYOFF_VERTICAL(img_pos.y));
677 fimc_write(ctx, cfg, EXYNOS_CIIYOFF);
678 cfg = (EXYNOS_CIICBOFF_HORIZONTAL(img_pos.x) |
679 EXYNOS_CIICBOFF_VERTICAL(img_pos.y));
680 fimc_write(ctx, cfg, EXYNOS_CIICBOFF);
681 cfg = (EXYNOS_CIICROFF_HORIZONTAL(img_pos.x) |
682 EXYNOS_CIICROFF_VERTICAL(img_pos.y));
683 fimc_write(ctx, cfg, EXYNOS_CIICROFF);
685 return fimc_set_window(ctx, &img_pos, &img_sz);
688 static int fimc_src_set_addr(struct device *dev,
689 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
690 enum drm_exynos_ipp_buf_type buf_type)
692 struct fimc_context *ctx = get_fimc_context(dev);
693 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
694 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
695 struct drm_exynos_ipp_property *property;
696 struct drm_exynos_ipp_config *config;
699 DRM_ERROR("failed to get c_node.\n");
703 property = &c_node->property;
705 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
706 property->prop_id, buf_id, buf_type);
708 if (buf_id > FIMC_MAX_SRC) {
709 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
713 /* address register set */
715 case IPP_BUF_ENQUEUE:
716 config = &property->config[EXYNOS_DRM_OPS_SRC];
717 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_Y],
720 if (config->fmt == DRM_FORMAT_YVU420) {
721 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
723 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
726 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
728 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
732 case IPP_BUF_DEQUEUE:
733 fimc_write(ctx, 0x0, EXYNOS_CIIYSA0);
734 fimc_write(ctx, 0x0, EXYNOS_CIICBSA0);
735 fimc_write(ctx, 0x0, EXYNOS_CIICRSA0);
745 static struct exynos_drm_ipp_ops fimc_src_ops = {
746 .set_fmt = fimc_src_set_fmt,
747 .set_transf = fimc_src_set_transf,
748 .set_size = fimc_src_set_size,
749 .set_addr = fimc_src_set_addr,
752 static int fimc_dst_set_fmt_order(struct fimc_context *ctx, u32 fmt)
754 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
757 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
760 cfg = fimc_read(ctx, EXYNOS_CISCCTRL);
761 cfg &= ~EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK;
764 case DRM_FORMAT_RGB565:
765 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565;
766 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
768 case DRM_FORMAT_RGB888:
769 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888;
770 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
772 case DRM_FORMAT_XRGB8888:
773 cfg |= (EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888 |
774 EXYNOS_CISCCTRL_EXTRGB_EXTENSION);
775 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
783 cfg = fimc_read(ctx, EXYNOS_CIOCTRL);
784 cfg &= ~(EXYNOS_CIOCTRL_ORDER2P_MASK |
785 EXYNOS_CIOCTRL_ORDER422_MASK |
786 EXYNOS_CIOCTRL_YCBCR_PLANE_MASK);
789 case DRM_FORMAT_XRGB8888:
790 cfg |= EXYNOS_CIOCTRL_ALPHA_OUT;
792 case DRM_FORMAT_YUYV:
793 cfg |= EXYNOS_CIOCTRL_ORDER422_YCBYCR;
795 case DRM_FORMAT_YVYU:
796 cfg |= EXYNOS_CIOCTRL_ORDER422_YCRYCB;
798 case DRM_FORMAT_UYVY:
799 cfg |= EXYNOS_CIOCTRL_ORDER422_CBYCRY;
801 case DRM_FORMAT_VYUY:
802 cfg |= EXYNOS_CIOCTRL_ORDER422_CRYCBY;
804 case DRM_FORMAT_NV21:
805 case DRM_FORMAT_NV61:
806 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB;
807 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
809 case DRM_FORMAT_YUV422:
810 case DRM_FORMAT_YUV420:
811 case DRM_FORMAT_YVU420:
812 cfg |= EXYNOS_CIOCTRL_YCBCR_3PLANE;
814 case DRM_FORMAT_NV12:
815 case DRM_FORMAT_NV12MT:
816 case DRM_FORMAT_NV16:
817 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR;
818 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
821 dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt);
825 fimc_write(ctx, cfg, EXYNOS_CIOCTRL);
830 static int fimc_dst_set_fmt(struct device *dev, u32 fmt)
832 struct fimc_context *ctx = get_fimc_context(dev);
833 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
836 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
838 cfg = fimc_read(ctx, EXYNOS_CIEXTEN);
840 if (fmt == DRM_FORMAT_AYUV) {
841 cfg |= EXYNOS_CIEXTEN_YUV444_OUT;
842 fimc_write(ctx, cfg, EXYNOS_CIEXTEN);
844 cfg &= ~EXYNOS_CIEXTEN_YUV444_OUT;
845 fimc_write(ctx, cfg, EXYNOS_CIEXTEN);
847 cfg = fimc_read(ctx, EXYNOS_CITRGFMT);
848 cfg &= ~EXYNOS_CITRGFMT_OUTFORMAT_MASK;
851 case DRM_FORMAT_RGB565:
852 case DRM_FORMAT_RGB888:
853 case DRM_FORMAT_XRGB8888:
854 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_RGB;
856 case DRM_FORMAT_YUYV:
857 case DRM_FORMAT_YVYU:
858 case DRM_FORMAT_UYVY:
859 case DRM_FORMAT_VYUY:
860 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE;
862 case DRM_FORMAT_NV16:
863 case DRM_FORMAT_NV61:
864 case DRM_FORMAT_YUV422:
865 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422;
867 case DRM_FORMAT_YUV420:
868 case DRM_FORMAT_YVU420:
869 case DRM_FORMAT_NV12:
870 case DRM_FORMAT_NV12MT:
871 case DRM_FORMAT_NV21:
872 cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420;
875 dev_err(ippdrv->dev, "inavlid target format 0x%x.\n",
880 fimc_write(ctx, cfg, EXYNOS_CITRGFMT);
883 cfg = fimc_read(ctx, EXYNOS_CIDMAPARAM);
884 cfg &= ~EXYNOS_CIDMAPARAM_W_MODE_MASK;
886 if (fmt == DRM_FORMAT_NV12MT)
887 cfg |= EXYNOS_CIDMAPARAM_W_MODE_64X32;
889 cfg |= EXYNOS_CIDMAPARAM_W_MODE_LINEAR;
891 fimc_write(ctx, cfg, EXYNOS_CIDMAPARAM);
893 return fimc_dst_set_fmt_order(ctx, fmt);
896 static int fimc_dst_set_transf(struct device *dev,
897 enum drm_exynos_degree degree,
898 enum drm_exynos_flip flip, bool *swap)
900 struct fimc_context *ctx = get_fimc_context(dev);
901 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
904 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
906 cfg = fimc_read(ctx, EXYNOS_CITRGFMT);
907 cfg &= ~EXYNOS_CITRGFMT_FLIP_MASK;
908 cfg &= ~EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
911 case EXYNOS_DRM_DEGREE_0:
912 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
913 cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
914 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
915 cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
917 case EXYNOS_DRM_DEGREE_90:
918 cfg |= EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
919 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
920 cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
921 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
922 cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
924 case EXYNOS_DRM_DEGREE_180:
925 cfg |= (EXYNOS_CITRGFMT_FLIP_X_MIRROR |
926 EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
927 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
928 cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
929 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
930 cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
932 case EXYNOS_DRM_DEGREE_270:
933 cfg |= (EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE |
934 EXYNOS_CITRGFMT_FLIP_X_MIRROR |
935 EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
936 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
937 cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
938 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
939 cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
942 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
946 fimc_write(ctx, cfg, EXYNOS_CITRGFMT);
947 *swap = (cfg & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) ? 1 : 0;
952 static int fimc_set_prescaler(struct fimc_context *ctx, struct fimc_scaler *sc,
953 struct drm_exynos_pos *src, struct drm_exynos_pos *dst)
955 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
956 u32 cfg, cfg_ext, shfactor;
957 u32 pre_dst_width, pre_dst_height;
958 u32 hfactor, vfactor;
960 u32 src_w, src_h, dst_w, dst_h;
962 cfg_ext = fimc_read(ctx, EXYNOS_CITRGFMT);
963 if (cfg_ext & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) {
971 if (cfg_ext & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) {
979 /* fimc_ippdrv_check_property assures that dividers are not null */
980 hfactor = fls(src_w / dst_w / 2);
981 if (hfactor > FIMC_SHFACTOR / 2) {
982 dev_err(ippdrv->dev, "failed to get ratio horizontal.\n");
986 vfactor = fls(src_h / dst_h / 2);
987 if (vfactor > FIMC_SHFACTOR / 2) {
988 dev_err(ippdrv->dev, "failed to get ratio vertical.\n");
992 pre_dst_width = src_w >> hfactor;
993 pre_dst_height = src_h >> vfactor;
994 DRM_DEBUG_KMS("pre_dst_width[%d]pre_dst_height[%d]\n",
995 pre_dst_width, pre_dst_height);
996 DRM_DEBUG_KMS("hfactor[%d]vfactor[%d]\n", hfactor, vfactor);
998 sc->hratio = (src_w << 14) / (dst_w << hfactor);
999 sc->vratio = (src_h << 14) / (dst_h << vfactor);
1000 sc->up_h = (dst_w >= src_w) ? true : false;
1001 sc->up_v = (dst_h >= src_h) ? true : false;
1002 DRM_DEBUG_KMS("hratio[%d]vratio[%d]up_h[%d]up_v[%d]\n",
1003 sc->hratio, sc->vratio, sc->up_h, sc->up_v);
1005 shfactor = FIMC_SHFACTOR - (hfactor + vfactor);
1006 DRM_DEBUG_KMS("shfactor[%d]\n", shfactor);
1008 cfg = (EXYNOS_CISCPRERATIO_SHFACTOR(shfactor) |
1009 EXYNOS_CISCPRERATIO_PREHORRATIO(1 << hfactor) |
1010 EXYNOS_CISCPRERATIO_PREVERRATIO(1 << vfactor));
1011 fimc_write(ctx, cfg, EXYNOS_CISCPRERATIO);
1013 cfg = (EXYNOS_CISCPREDST_PREDSTWIDTH(pre_dst_width) |
1014 EXYNOS_CISCPREDST_PREDSTHEIGHT(pre_dst_height));
1015 fimc_write(ctx, cfg, EXYNOS_CISCPREDST);
1020 static void fimc_set_scaler(struct fimc_context *ctx, struct fimc_scaler *sc)
1024 DRM_DEBUG_KMS("range[%d]bypass[%d]up_h[%d]up_v[%d]\n",
1025 sc->range, sc->bypass, sc->up_h, sc->up_v);
1026 DRM_DEBUG_KMS("hratio[%d]vratio[%d]\n",
1027 sc->hratio, sc->vratio);
1029 cfg = fimc_read(ctx, EXYNOS_CISCCTRL);
1030 cfg &= ~(EXYNOS_CISCCTRL_SCALERBYPASS |
1031 EXYNOS_CISCCTRL_SCALEUP_H | EXYNOS_CISCCTRL_SCALEUP_V |
1032 EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK |
1033 EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK |
1034 EXYNOS_CISCCTRL_CSCR2Y_WIDE |
1035 EXYNOS_CISCCTRL_CSCY2R_WIDE);
1038 cfg |= (EXYNOS_CISCCTRL_CSCR2Y_WIDE |
1039 EXYNOS_CISCCTRL_CSCY2R_WIDE);
1041 cfg |= EXYNOS_CISCCTRL_SCALERBYPASS;
1043 cfg |= EXYNOS_CISCCTRL_SCALEUP_H;
1045 cfg |= EXYNOS_CISCCTRL_SCALEUP_V;
1047 cfg |= (EXYNOS_CISCCTRL_MAINHORRATIO((sc->hratio >> 6)) |
1048 EXYNOS_CISCCTRL_MAINVERRATIO((sc->vratio >> 6)));
1049 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
1051 cfg_ext = fimc_read(ctx, EXYNOS_CIEXTEN);
1052 cfg_ext &= ~EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK;
1053 cfg_ext &= ~EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK;
1054 cfg_ext |= (EXYNOS_CIEXTEN_MAINHORRATIO_EXT(sc->hratio) |
1055 EXYNOS_CIEXTEN_MAINVERRATIO_EXT(sc->vratio));
1056 fimc_write(ctx, cfg_ext, EXYNOS_CIEXTEN);
1059 static int fimc_dst_set_size(struct device *dev, int swap,
1060 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
1062 struct fimc_context *ctx = get_fimc_context(dev);
1063 struct drm_exynos_pos img_pos = *pos;
1064 struct drm_exynos_sz img_sz = *sz;
1067 DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n",
1068 swap, sz->hsize, sz->vsize);
1071 cfg = (EXYNOS_ORGOSIZE_HORIZONTAL(img_sz.hsize) |
1072 EXYNOS_ORGOSIZE_VERTICAL(img_sz.vsize));
1074 fimc_write(ctx, cfg, EXYNOS_ORGOSIZE);
1076 DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h);
1079 cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
1080 cfg &= ~EXYNOS_CIGCTRL_CSC_MASK;
1082 if (sz->hsize >= FIMC_WIDTH_ITU_709)
1083 cfg |= EXYNOS_CIGCTRL_CSC_ITU709;
1085 cfg |= EXYNOS_CIGCTRL_CSC_ITU601;
1087 fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
1092 img_sz.hsize = sz->vsize;
1093 img_sz.vsize = sz->hsize;
1096 /* target image size */
1097 cfg = fimc_read(ctx, EXYNOS_CITRGFMT);
1098 cfg &= ~(EXYNOS_CITRGFMT_TARGETH_MASK |
1099 EXYNOS_CITRGFMT_TARGETV_MASK);
1100 cfg |= (EXYNOS_CITRGFMT_TARGETHSIZE(img_pos.w) |
1101 EXYNOS_CITRGFMT_TARGETVSIZE(img_pos.h));
1102 fimc_write(ctx, cfg, EXYNOS_CITRGFMT);
1105 cfg = EXYNOS_CITAREA_TARGET_AREA(img_pos.w * img_pos.h);
1106 fimc_write(ctx, cfg, EXYNOS_CITAREA);
1108 /* offset Y(RGB), Cb, Cr */
1109 cfg = (EXYNOS_CIOYOFF_HORIZONTAL(img_pos.x) |
1110 EXYNOS_CIOYOFF_VERTICAL(img_pos.y));
1111 fimc_write(ctx, cfg, EXYNOS_CIOYOFF);
1112 cfg = (EXYNOS_CIOCBOFF_HORIZONTAL(img_pos.x) |
1113 EXYNOS_CIOCBOFF_VERTICAL(img_pos.y));
1114 fimc_write(ctx, cfg, EXYNOS_CIOCBOFF);
1115 cfg = (EXYNOS_CIOCROFF_HORIZONTAL(img_pos.x) |
1116 EXYNOS_CIOCROFF_VERTICAL(img_pos.y));
1117 fimc_write(ctx, cfg, EXYNOS_CIOCROFF);
1122 static void fimc_dst_set_buf_seq(struct fimc_context *ctx, u32 buf_id,
1123 enum drm_exynos_ipp_buf_type buf_type)
1125 unsigned long flags;
1129 DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type);
1131 spin_lock_irqsave(&ctx->lock, flags);
1133 cfg = fimc_read(ctx, EXYNOS_CIFCNTSEQ);
1135 if (buf_type == IPP_BUF_ENQUEUE)
1136 cfg |= (1 << buf_id);
1138 cfg &= ~(1 << buf_id);
1140 fimc_write(ctx, cfg, EXYNOS_CIFCNTSEQ);
1142 buf_num = hweight32(cfg);
1144 if (buf_type == IPP_BUF_ENQUEUE && buf_num >= FIMC_BUF_START)
1145 fimc_mask_irq(ctx, true);
1146 else if (buf_type == IPP_BUF_DEQUEUE && buf_num <= FIMC_BUF_STOP)
1147 fimc_mask_irq(ctx, false);
1149 spin_unlock_irqrestore(&ctx->lock, flags);
1152 static int fimc_dst_set_addr(struct device *dev,
1153 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
1154 enum drm_exynos_ipp_buf_type buf_type)
1156 struct fimc_context *ctx = get_fimc_context(dev);
1157 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1158 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1159 struct drm_exynos_ipp_property *property;
1160 struct drm_exynos_ipp_config *config;
1163 DRM_ERROR("failed to get c_node.\n");
1167 property = &c_node->property;
1169 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
1170 property->prop_id, buf_id, buf_type);
1172 if (buf_id > FIMC_MAX_DST) {
1173 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
1177 /* address register set */
1179 case IPP_BUF_ENQUEUE:
1180 config = &property->config[EXYNOS_DRM_OPS_DST];
1182 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_Y],
1183 EXYNOS_CIOYSA(buf_id));
1185 if (config->fmt == DRM_FORMAT_YVU420) {
1186 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
1187 EXYNOS_CIOCBSA(buf_id));
1188 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
1189 EXYNOS_CIOCRSA(buf_id));
1191 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
1192 EXYNOS_CIOCBSA(buf_id));
1193 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
1194 EXYNOS_CIOCRSA(buf_id));
1197 case IPP_BUF_DEQUEUE:
1198 fimc_write(ctx, 0x0, EXYNOS_CIOYSA(buf_id));
1199 fimc_write(ctx, 0x0, EXYNOS_CIOCBSA(buf_id));
1200 fimc_write(ctx, 0x0, EXYNOS_CIOCRSA(buf_id));
1207 fimc_dst_set_buf_seq(ctx, buf_id, buf_type);
1212 static struct exynos_drm_ipp_ops fimc_dst_ops = {
1213 .set_fmt = fimc_dst_set_fmt,
1214 .set_transf = fimc_dst_set_transf,
1215 .set_size = fimc_dst_set_size,
1216 .set_addr = fimc_dst_set_addr,
1219 static int fimc_clk_ctrl(struct fimc_context *ctx, bool enable)
1221 DRM_DEBUG_KMS("enable[%d]\n", enable);
1224 clk_prepare_enable(ctx->clocks[FIMC_CLK_GATE]);
1225 clk_prepare_enable(ctx->clocks[FIMC_CLK_WB_A]);
1226 ctx->suspended = false;
1228 clk_disable_unprepare(ctx->clocks[FIMC_CLK_GATE]);
1229 clk_disable_unprepare(ctx->clocks[FIMC_CLK_WB_A]);
1230 ctx->suspended = true;
1236 static irqreturn_t fimc_irq_handler(int irq, void *dev_id)
1238 struct fimc_context *ctx = dev_id;
1239 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1240 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1241 struct drm_exynos_ipp_event_work *event_work =
1245 DRM_DEBUG_KMS("fimc id[%d]\n", ctx->id);
1247 fimc_clear_irq(ctx);
1248 if (fimc_check_ovf(ctx))
1251 if (!fimc_check_frame_end(ctx))
1254 buf_id = fimc_get_buf_id(ctx);
1258 DRM_DEBUG_KMS("buf_id[%d]\n", buf_id);
1260 fimc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE);
1262 event_work->ippdrv = ippdrv;
1263 event_work->buf_id[EXYNOS_DRM_OPS_DST] = buf_id;
1264 queue_work(ippdrv->event_workq, &event_work->work);
1269 static int fimc_init_prop_list(struct exynos_drm_ippdrv *ippdrv)
1271 struct drm_exynos_ipp_prop_list *prop_list = &ippdrv->prop_list;
1273 prop_list->version = 1;
1274 prop_list->writeback = 1;
1275 prop_list->refresh_min = FIMC_REFRESH_MIN;
1276 prop_list->refresh_max = FIMC_REFRESH_MAX;
1277 prop_list->flip = (1 << EXYNOS_DRM_FLIP_NONE) |
1278 (1 << EXYNOS_DRM_FLIP_VERTICAL) |
1279 (1 << EXYNOS_DRM_FLIP_HORIZONTAL);
1280 prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) |
1281 (1 << EXYNOS_DRM_DEGREE_90) |
1282 (1 << EXYNOS_DRM_DEGREE_180) |
1283 (1 << EXYNOS_DRM_DEGREE_270);
1285 prop_list->crop = 1;
1286 prop_list->crop_max.hsize = FIMC_CROP_MAX;
1287 prop_list->crop_max.vsize = FIMC_CROP_MAX;
1288 prop_list->crop_min.hsize = FIMC_CROP_MIN;
1289 prop_list->crop_min.vsize = FIMC_CROP_MIN;
1290 prop_list->scale = 1;
1291 prop_list->scale_max.hsize = FIMC_SCALE_MAX;
1292 prop_list->scale_max.vsize = FIMC_SCALE_MAX;
1293 prop_list->scale_min.hsize = FIMC_SCALE_MIN;
1294 prop_list->scale_min.vsize = FIMC_SCALE_MIN;
1299 static inline bool fimc_check_drm_flip(enum drm_exynos_flip flip)
1302 case EXYNOS_DRM_FLIP_NONE:
1303 case EXYNOS_DRM_FLIP_VERTICAL:
1304 case EXYNOS_DRM_FLIP_HORIZONTAL:
1305 case EXYNOS_DRM_FLIP_BOTH:
1308 DRM_DEBUG_KMS("invalid flip\n");
1313 static int fimc_ippdrv_check_property(struct device *dev,
1314 struct drm_exynos_ipp_property *property)
1316 struct fimc_context *ctx = get_fimc_context(dev);
1317 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1318 struct drm_exynos_ipp_prop_list *pp = &ippdrv->prop_list;
1319 struct drm_exynos_ipp_config *config;
1320 struct drm_exynos_pos *pos;
1321 struct drm_exynos_sz *sz;
1325 for_each_ipp_ops(i) {
1326 if ((i == EXYNOS_DRM_OPS_SRC) &&
1327 (property->cmd == IPP_CMD_WB))
1330 config = &property->config[i];
1334 /* check for flip */
1335 if (!fimc_check_drm_flip(config->flip)) {
1336 DRM_ERROR("invalid flip.\n");
1340 /* check for degree */
1341 switch (config->degree) {
1342 case EXYNOS_DRM_DEGREE_90:
1343 case EXYNOS_DRM_DEGREE_270:
1346 case EXYNOS_DRM_DEGREE_0:
1347 case EXYNOS_DRM_DEGREE_180:
1351 DRM_ERROR("invalid degree.\n");
1355 /* check for buffer bound */
1356 if ((pos->x + pos->w > sz->hsize) ||
1357 (pos->y + pos->h > sz->vsize)) {
1358 DRM_ERROR("out of buf bound.\n");
1362 /* check for crop */
1363 if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) {
1365 if ((pos->h < pp->crop_min.hsize) ||
1366 (sz->vsize > pp->crop_max.hsize) ||
1367 (pos->w < pp->crop_min.vsize) ||
1368 (sz->hsize > pp->crop_max.vsize)) {
1369 DRM_ERROR("out of crop size.\n");
1373 if ((pos->w < pp->crop_min.hsize) ||
1374 (sz->hsize > pp->crop_max.hsize) ||
1375 (pos->h < pp->crop_min.vsize) ||
1376 (sz->vsize > pp->crop_max.vsize)) {
1377 DRM_ERROR("out of crop size.\n");
1383 /* check for scale */
1384 if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) {
1386 if ((pos->h < pp->scale_min.hsize) ||
1387 (sz->vsize > pp->scale_max.hsize) ||
1388 (pos->w < pp->scale_min.vsize) ||
1389 (sz->hsize > pp->scale_max.vsize)) {
1390 DRM_ERROR("out of scale size.\n");
1394 if ((pos->w < pp->scale_min.hsize) ||
1395 (sz->hsize > pp->scale_max.hsize) ||
1396 (pos->h < pp->scale_min.vsize) ||
1397 (sz->vsize > pp->scale_max.vsize)) {
1398 DRM_ERROR("out of scale size.\n");
1408 for_each_ipp_ops(i) {
1409 if ((i == EXYNOS_DRM_OPS_SRC) &&
1410 (property->cmd == IPP_CMD_WB))
1413 config = &property->config[i];
1417 DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n",
1418 i ? "dst" : "src", config->flip, config->degree,
1419 pos->x, pos->y, pos->w, pos->h,
1420 sz->hsize, sz->vsize);
1426 static void fimc_clear_addr(struct fimc_context *ctx)
1430 for (i = 0; i < FIMC_MAX_SRC; i++) {
1431 fimc_write(ctx, 0, EXYNOS_CIIYSA(i));
1432 fimc_write(ctx, 0, EXYNOS_CIICBSA(i));
1433 fimc_write(ctx, 0, EXYNOS_CIICRSA(i));
1436 for (i = 0; i < FIMC_MAX_DST; i++) {
1437 fimc_write(ctx, 0, EXYNOS_CIOYSA(i));
1438 fimc_write(ctx, 0, EXYNOS_CIOCBSA(i));
1439 fimc_write(ctx, 0, EXYNOS_CIOCRSA(i));
1443 static int fimc_ippdrv_reset(struct device *dev)
1445 struct fimc_context *ctx = get_fimc_context(dev);
1447 /* reset h/w block */
1450 /* reset scaler capability */
1451 memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1453 fimc_clear_addr(ctx);
1458 static int fimc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1460 struct fimc_context *ctx = get_fimc_context(dev);
1461 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1462 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1463 struct drm_exynos_ipp_property *property;
1464 struct drm_exynos_ipp_config *config;
1465 struct drm_exynos_pos img_pos[EXYNOS_DRM_OPS_MAX];
1466 struct drm_exynos_ipp_set_wb set_wb;
1470 DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1473 DRM_ERROR("failed to get c_node.\n");
1477 property = &c_node->property;
1479 fimc_mask_irq(ctx, true);
1481 for_each_ipp_ops(i) {
1482 config = &property->config[i];
1483 img_pos[i] = config->pos;
1486 ret = fimc_set_prescaler(ctx, &ctx->sc,
1487 &img_pos[EXYNOS_DRM_OPS_SRC],
1488 &img_pos[EXYNOS_DRM_OPS_DST]);
1490 dev_err(dev, "failed to set precalser.\n");
1494 /* If set ture, we can save jpeg about screen */
1495 fimc_handle_jpeg(ctx, false);
1496 fimc_set_scaler(ctx, &ctx->sc);
1497 fimc_set_polarity(ctx, &ctx->pol);
1501 fimc_set_type_ctrl(ctx, FIMC_WB_NONE);
1502 fimc_handle_lastend(ctx, false);
1505 cfg0 = fimc_read(ctx, EXYNOS_MSCTRL);
1506 cfg0 &= ~EXYNOS_MSCTRL_INPUT_MASK;
1507 cfg0 |= EXYNOS_MSCTRL_INPUT_MEMORY;
1508 fimc_write(ctx, cfg0, EXYNOS_MSCTRL);
1511 fimc_set_type_ctrl(ctx, FIMC_WB_A);
1512 fimc_handle_lastend(ctx, true);
1515 ret = fimc_set_camblk_fimd0_wb(ctx);
1517 dev_err(dev, "camblk setup failed.\n");
1522 set_wb.refresh = property->refresh_rate;
1523 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1525 case IPP_CMD_OUTPUT:
1528 dev_err(dev, "invalid operations.\n");
1533 fimc_write(ctx, 0x0, EXYNOS_CISTATUS);
1535 cfg0 = fimc_read(ctx, EXYNOS_CIIMGCPT);
1536 cfg0 &= ~EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1537 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1540 cfg1 = fimc_read(ctx, EXYNOS_CISCCTRL);
1541 cfg1 &= ~EXYNOS_CISCCTRL_SCAN_MASK;
1542 cfg1 |= (EXYNOS_CISCCTRL_PROGRESSIVE |
1543 EXYNOS_CISCCTRL_SCALERSTART);
1545 fimc_write(ctx, cfg1, EXYNOS_CISCCTRL);
1547 /* Enable image capture*/
1548 cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN;
1549 fimc_write(ctx, cfg0, EXYNOS_CIIMGCPT);
1551 /* Disable frame end irq */
1552 fimc_clear_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_END_DISABLE);
1554 fimc_clear_bits(ctx, EXYNOS_CIOCTRL, EXYNOS_CIOCTRL_WEAVE_MASK);
1556 if (cmd == IPP_CMD_M2M)
1557 fimc_set_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID);
1562 static void fimc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1564 struct fimc_context *ctx = get_fimc_context(dev);
1565 struct drm_exynos_ipp_set_wb set_wb = {0, 0};
1568 DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1573 cfg = fimc_read(ctx, EXYNOS_MSCTRL);
1574 cfg &= ~EXYNOS_MSCTRL_INPUT_MASK;
1575 cfg &= ~EXYNOS_MSCTRL_ENVID;
1576 fimc_write(ctx, cfg, EXYNOS_MSCTRL);
1579 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1581 case IPP_CMD_OUTPUT:
1583 dev_err(dev, "invalid operations.\n");
1587 fimc_mask_irq(ctx, false);
1589 /* reset sequence */
1590 fimc_write(ctx, 0x0, EXYNOS_CIFCNTSEQ);
1592 /* Scaler disable */
1593 fimc_clear_bits(ctx, EXYNOS_CISCCTRL, EXYNOS_CISCCTRL_SCALERSTART);
1595 /* Disable image capture */
1596 fimc_clear_bits(ctx, EXYNOS_CIIMGCPT,
1597 EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
1599 /* Enable frame end irq */
1600 fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_END_DISABLE);
1603 static void fimc_put_clocks(struct fimc_context *ctx)
1607 for (i = 0; i < FIMC_CLKS_MAX; i++) {
1608 if (IS_ERR(ctx->clocks[i]))
1610 clk_put(ctx->clocks[i]);
1611 ctx->clocks[i] = ERR_PTR(-EINVAL);
1615 static int fimc_setup_clocks(struct fimc_context *ctx)
1617 struct device *fimc_dev = ctx->ippdrv.dev;
1621 for (i = 0; i < FIMC_CLKS_MAX; i++)
1622 ctx->clocks[i] = ERR_PTR(-EINVAL);
1624 for (i = 0; i < FIMC_CLKS_MAX; i++) {
1625 if (i == FIMC_CLK_WB_A || i == FIMC_CLK_WB_B)
1626 dev = fimc_dev->parent;
1630 ctx->clocks[i] = clk_get(dev, fimc_clock_names[i]);
1631 if (IS_ERR(ctx->clocks[i])) {
1632 if (i >= FIMC_CLK_MUX)
1634 ret = PTR_ERR(ctx->clocks[i]);
1635 dev_err(fimc_dev, "failed to get clock: %s\n",
1636 fimc_clock_names[i]);
1641 /* Optional FIMC LCLK parent clock setting */
1642 if (!IS_ERR(ctx->clocks[FIMC_CLK_PARENT])) {
1643 ret = clk_set_parent(ctx->clocks[FIMC_CLK_MUX],
1644 ctx->clocks[FIMC_CLK_PARENT]);
1646 dev_err(fimc_dev, "failed to set parent.\n");
1651 ret = clk_set_rate(ctx->clocks[FIMC_CLK_LCLK], ctx->clk_frequency);
1655 ret = clk_prepare_enable(ctx->clocks[FIMC_CLK_LCLK]);
1659 fimc_put_clocks(ctx);
1663 static int fimc_parse_dt(struct fimc_context *ctx)
1665 struct device_node *node = ctx->ippdrv.dev->of_node;
1667 /* Handle only devices that support the LCD Writeback data path */
1668 if (!of_property_read_bool(node, "samsung,lcd-wb"))
1671 if (of_property_read_u32(node, "clock-frequency",
1672 &ctx->clk_frequency))
1673 ctx->clk_frequency = FIMC_DEFAULT_LCLK_FREQUENCY;
1675 ctx->id = of_alias_get_id(node, "fimc");
1678 dev_err(ctx->ippdrv.dev, "failed to get node alias id.\n");
1685 static int fimc_probe(struct platform_device *pdev)
1687 struct device *dev = &pdev->dev;
1688 struct fimc_context *ctx;
1689 struct resource *res;
1690 struct exynos_drm_ippdrv *ippdrv;
1693 if (!dev->of_node) {
1694 dev_err(dev, "device tree node not found.\n");
1698 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1702 ctx->ippdrv.dev = dev;
1704 ret = fimc_parse_dt(ctx);
1708 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1710 if (IS_ERR(ctx->sysreg)) {
1711 dev_err(dev, "syscon regmap lookup failed.\n");
1712 return PTR_ERR(ctx->sysreg);
1715 /* resource memory */
1716 ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1717 ctx->regs = devm_ioremap_resource(dev, ctx->regs_res);
1718 if (IS_ERR(ctx->regs))
1719 return PTR_ERR(ctx->regs);
1722 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1724 dev_err(dev, "failed to request irq resource.\n");
1728 ctx->irq = res->start;
1729 ret = devm_request_threaded_irq(dev, ctx->irq, NULL, fimc_irq_handler,
1730 IRQF_ONESHOT, "drm_fimc", ctx);
1732 dev_err(dev, "failed to request irq.\n");
1736 ret = fimc_setup_clocks(ctx);
1740 ippdrv = &ctx->ippdrv;
1741 ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &fimc_src_ops;
1742 ippdrv->ops[EXYNOS_DRM_OPS_DST] = &fimc_dst_ops;
1743 ippdrv->check_property = fimc_ippdrv_check_property;
1744 ippdrv->reset = fimc_ippdrv_reset;
1745 ippdrv->start = fimc_ippdrv_start;
1746 ippdrv->stop = fimc_ippdrv_stop;
1747 ret = fimc_init_prop_list(ippdrv);
1749 dev_err(dev, "failed to init property list.\n");
1753 DRM_DEBUG_KMS("id[%d]ippdrv[0x%x]\n", ctx->id, (int)ippdrv);
1755 spin_lock_init(&ctx->lock);
1756 platform_set_drvdata(pdev, ctx);
1758 pm_runtime_set_active(dev);
1759 pm_runtime_enable(dev);
1761 ret = exynos_drm_ippdrv_register(ippdrv);
1763 dev_err(dev, "failed to register drm fimc device.\n");
1767 dev_info(dev, "drm fimc registered successfully.\n");
1772 pm_runtime_disable(dev);
1774 fimc_put_clocks(ctx);
1779 static int fimc_remove(struct platform_device *pdev)
1781 struct device *dev = &pdev->dev;
1782 struct fimc_context *ctx = get_fimc_context(dev);
1783 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1785 exynos_drm_ippdrv_unregister(ippdrv);
1787 fimc_put_clocks(ctx);
1788 pm_runtime_set_suspended(dev);
1789 pm_runtime_disable(dev);
1794 #ifdef CONFIG_PM_SLEEP
1795 static int fimc_suspend(struct device *dev)
1797 struct fimc_context *ctx = get_fimc_context(dev);
1799 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1801 if (pm_runtime_suspended(dev))
1804 return fimc_clk_ctrl(ctx, false);
1807 static int fimc_resume(struct device *dev)
1809 struct fimc_context *ctx = get_fimc_context(dev);
1811 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1813 if (!pm_runtime_suspended(dev))
1814 return fimc_clk_ctrl(ctx, true);
1820 #ifdef CONFIG_PM_RUNTIME
1821 static int fimc_runtime_suspend(struct device *dev)
1823 struct fimc_context *ctx = get_fimc_context(dev);
1825 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1827 return fimc_clk_ctrl(ctx, false);
1830 static int fimc_runtime_resume(struct device *dev)
1832 struct fimc_context *ctx = get_fimc_context(dev);
1834 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1836 return fimc_clk_ctrl(ctx, true);
1840 static const struct dev_pm_ops fimc_pm_ops = {
1841 SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1842 SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1845 static const struct of_device_id fimc_of_match[] = {
1846 { .compatible = "samsung,exynos4210-fimc" },
1847 { .compatible = "samsung,exynos4212-fimc" },
1850 MODULE_DEVICE_TABLE(of, fimc_of_match);
1852 struct platform_driver fimc_driver = {
1853 .probe = fimc_probe,
1854 .remove = fimc_remove,
1856 .of_match_table = fimc_of_match,
1857 .name = "exynos-drm-fimc",
1858 .owner = THIS_MODULE,