drivers/gpu/drm/exynos/exynos_drm_fimd.c

   1 /* exynos_drm_fimd.c
   2  *
   3  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Inki Dae <inki.dae@samsung.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14 #include <drm/drmP.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/clk.h>
  20 #include <linux/pm_runtime.h>
  21
  22 #include <video/samsung_fimd.h>
  23 #include <drm/exynos_drm.h>
  24
  25 #include "exynos_drm_drv.h"
  26 #include "exynos_drm_fbdev.h"
  27 #include "exynos_drm_crtc.h"
  28 #include "exynos_drm_iommu.h"
  29
  30 /*
  31  * FIMD is stand for Fully Interactive Mobile Display and
  32  * as a display controller, it transfers contents drawn on memory
  33  * to a LCD Panel through Display Interfaces such as RGB or
  34  * CPU Interface.
  35  */
  36
  37 /* position control register for hardware window 0, 2 ~ 4.*/
  38 #define VIDOSD_A(win)           (VIDOSD_BASE + 0x00 + (win) * 16)
  39 #define VIDOSD_B(win)           (VIDOSD_BASE + 0x04 + (win) * 16)
  40 /* size control register for hardware window 0. */
  41 #define VIDOSD_C_SIZE_W0        (VIDOSD_BASE + 0x08)
  42 /* alpha control register for hardware window 1 ~ 4. */
  43 #define VIDOSD_C(win)           (VIDOSD_BASE + 0x18 + (win) * 16)
  44 /* size control register for hardware window 1 ~ 4. */
  45 #define VIDOSD_D(win)           (VIDOSD_BASE + 0x0C + (win) * 16)
  46
  47 #define VIDWx_BUF_START(win, buf)       (VIDW_BUF_START(buf) + (win) * 8)
  48 #define VIDWx_BUF_END(win, buf)         (VIDW_BUF_END(buf) + (win) * 8)
  49 #define VIDWx_BUF_SIZE(win, buf)        (VIDW_BUF_SIZE(buf) + (win) * 4)
  50
  51 /* color key control register for hardware window 1 ~ 4. */
  52 #define WKEYCON0_BASE(x)                ((WKEYCON0 + 0x140) + (x * 8))
  53 /* color key value register for hardware window 1 ~ 4. */
  54 #define WKEYCON1_BASE(x)                ((WKEYCON1 + 0x140) + (x * 8))
  55
  56 /* FIMD has totally five hardware windows. */
  57 #define WINDOWS_NR      5
  58
  59 #define get_fimd_context(dev)   platform_get_drvdata(to_platform_device(dev))
  60
  61 struct fimd_driver_data {
  62         unsigned int timing_base;
  63 };
  64
  65 static struct fimd_driver_data exynos4_fimd_driver_data = {
  66         .timing_base = 0x0,
  67 };
  68
  69 static struct fimd_driver_data exynos5_fimd_driver_data = {
  70         .timing_base = 0x20000,
  71 };
  72
  73 struct fimd_win_data {
  74         unsigned int            offset_x;
  75         unsigned int            offset_y;
  76         unsigned int            ovl_width;
  77         unsigned int            ovl_height;
  78         unsigned int            fb_width;
  79         unsigned int            fb_height;
  80         unsigned int            bpp;
  81         dma_addr_t              dma_addr;
  82         void __iomem            *vaddr;
  83         unsigned int            buf_offsize;
  84         unsigned int            line_size;      /* bytes */
  85         bool                    enabled;
  86 };
  87
  88 struct fimd_context {
  89         struct exynos_drm_subdrv        subdrv;
  90         int                             irq;
  91         struct drm_crtc                 *crtc;
  92         struct clk                      *bus_clk;
  93         struct clk                      *lcd_clk;
  94         void __iomem                    *regs;
  95         struct fimd_win_data            win_data[WINDOWS_NR];
  96         unsigned int                    clkdiv;
  97         unsigned int                    default_win;
  98         unsigned long                   irq_flags;
  99         u32                             vidcon0;
 100         u32                             vidcon1;
 101         bool                            suspended;
 102         struct mutex                    lock;
 103
 104         struct exynos_drm_panel_info *panel;
 105 };
 106
 107 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
 108         struct platform_device *pdev)
 109 {
 110         return (struct fimd_driver_data *)
 111                 platform_get_device_id(pdev)->driver_data;
 112 }
 113
 114 static bool fimd_display_is_connected(struct device *dev)
 115 {
 116         DRM_DEBUG_KMS("%s\n", __FILE__);
 117
 118         /* TODO. */
 119
 120         return true;
 121 }
 122
 123 static void *fimd_get_panel(struct device *dev)
 124 {
 125         struct fimd_context *ctx = get_fimd_context(dev);
 126
 127         DRM_DEBUG_KMS("%s\n", __FILE__);
 128
 129         return ctx->panel;
 130 }
 131
 132 static int fimd_check_timing(struct device *dev, void *timing)
 133 {
 134         DRM_DEBUG_KMS("%s\n", __FILE__);
 135
 136         /* TODO. */
 137
 138         return 0;
 139 }
 140
 141 static int fimd_display_power_on(struct device *dev, int mode)
 142 {
 143         DRM_DEBUG_KMS("%s\n", __FILE__);
 144
 145         /* TODO */
 146
 147         return 0;
 148 }
 149
 150 static struct exynos_drm_display_ops fimd_display_ops = {
 151         .type = EXYNOS_DISPLAY_TYPE_LCD,
 152         .is_connected = fimd_display_is_connected,
 153         .get_panel = fimd_get_panel,
 154         .check_timing = fimd_check_timing,
 155         .power_on = fimd_display_power_on,
 156 };
 157
 158 static void fimd_dpms(struct device *subdrv_dev, int mode)
 159 {
 160         struct fimd_context *ctx = get_fimd_context(subdrv_dev);
 161
 162         DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
 163
 164         mutex_lock(&ctx->lock);
 165
 166         switch (mode) {
 167         case DRM_MODE_DPMS_ON:
 168                 /*
 169                  * enable fimd hardware only if suspended status.
 170                  *
 171                  * P.S. fimd_dpms function would be called at booting time so
 172                  * clk_enable could be called double time.
 173                  */
 174                 if (ctx->suspended)
 175                         pm_runtime_get_sync(subdrv_dev);
 176                 break;
 177         case DRM_MODE_DPMS_STANDBY:
 178         case DRM_MODE_DPMS_SUSPEND:
 179         case DRM_MODE_DPMS_OFF:
 180                 if (!ctx->suspended)
 181                         pm_runtime_put_sync(subdrv_dev);
 182                 break;
 183         default:
 184                 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
 185                 break;
 186         }
 187
 188         mutex_unlock(&ctx->lock);
 189 }
 190
 191 static void fimd_apply(struct device *subdrv_dev)
 192 {
 193         struct fimd_context *ctx = get_fimd_context(subdrv_dev);
 194         struct exynos_drm_manager *mgr = ctx->subdrv.manager;
 195         struct exynos_drm_manager_ops *mgr_ops = mgr->ops;
 196         struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops;
 197         struct fimd_win_data *win_data;
 198         int i;
 199
 200         DRM_DEBUG_KMS("%s\n", __FILE__);
 201
 202         for (i = 0; i < WINDOWS_NR; i++) {
 203                 win_data = &ctx->win_data[i];
 204                 if (win_data->enabled && (ovl_ops && ovl_ops->commit))
 205                         ovl_ops->commit(subdrv_dev, i);
 206         }
 207
 208         if (mgr_ops && mgr_ops->commit)
 209                 mgr_ops->commit(subdrv_dev);
 210 }
 211
 212 static void fimd_commit(struct device *dev)
 213 {
 214         struct fimd_context *ctx = get_fimd_context(dev);
 215         struct exynos_drm_panel_info *panel = ctx->panel;
 216         struct fb_videomode *timing = &panel->timing;
 217         struct fimd_driver_data *driver_data;
 218         struct platform_device *pdev = to_platform_device(dev);
 219         u32 val;
 220
 221         driver_data = drm_fimd_get_driver_data(pdev);
 222         if (ctx->suspended)
 223                 return;
 224
 225         DRM_DEBUG_KMS("%s\n", __FILE__);
 226
 227         /* setup polarity values from machine code. */
 228         writel(ctx->vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
 229
 230         /* setup vertical timing values. */
 231         val = VIDTCON0_VBPD(timing->upper_margin - 1) |
 232                VIDTCON0_VFPD(timing->lower_margin - 1) |
 233                VIDTCON0_VSPW(timing->vsync_len - 1);
 234         writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
 235
 236         /* setup horizontal timing values.  */
 237         val = VIDTCON1_HBPD(timing->left_margin - 1) |
 238                VIDTCON1_HFPD(timing->right_margin - 1) |
 239                VIDTCON1_HSPW(timing->hsync_len - 1);
 240         writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
 241
 242         /* setup horizontal and vertical display size. */
 243         val = VIDTCON2_LINEVAL(timing->yres - 1) |
 244                VIDTCON2_HOZVAL(timing->xres - 1);
 245         writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
 246
 247         /* setup clock source, clock divider, enable dma. */
 248         val = ctx->vidcon0;
 249         val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
 250
 251         if (ctx->clkdiv > 1)
 252                 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
 253         else
 254                 val &= ~VIDCON0_CLKDIR; /* 1:1 clock */
 255
 256         /*
 257          * fields of register with prefix '_F' would be updated
 258          * at vsync(same as dma start)
 259          */
 260         val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 261         writel(val, ctx->regs + VIDCON0);
 262 }
 263
 264 static int fimd_enable_vblank(struct device *dev)
 265 {
 266         struct fimd_context *ctx = get_fimd_context(dev);
 267         u32 val;
 268
 269         DRM_DEBUG_KMS("%s\n", __FILE__);
 270
 271         if (ctx->suspended)
 272                 return -EPERM;
 273
 274         if (!test_and_set_bit(0, &ctx->irq_flags)) {
 275                 val = readl(ctx->regs + VIDINTCON0);
 276
 277                 val |= VIDINTCON0_INT_ENABLE;
 278                 val |= VIDINTCON0_INT_FRAME;
 279
 280                 val &= ~VIDINTCON0_FRAMESEL0_MASK;
 281                 val |= VIDINTCON0_FRAMESEL0_VSYNC;
 282                 val &= ~VIDINTCON0_FRAMESEL1_MASK;
 283                 val |= VIDINTCON0_FRAMESEL1_NONE;
 284
 285                 writel(val, ctx->regs + VIDINTCON0);
 286         }
 287
 288         return 0;
 289 }
 290
 291 static void fimd_disable_vblank(struct device *dev)
 292 {
 293         struct fimd_context *ctx = get_fimd_context(dev);
 294         u32 val;
 295
 296         DRM_DEBUG_KMS("%s\n", __FILE__);
 297
 298         if (ctx->suspended)
 299                 return;
 300
 301         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 302                 val = readl(ctx->regs + VIDINTCON0);
 303
 304                 val &= ~VIDINTCON0_INT_FRAME;
 305                 val &= ~VIDINTCON0_INT_ENABLE;
 306
 307                 writel(val, ctx->regs + VIDINTCON0);
 308         }
 309 }
 310
 311 static void fimd_wait_for_vblank(struct device *dev)
 312 {
 313         struct fimd_context *ctx = get_fimd_context(dev);
 314         int ret;
 315
 316         ret = wait_for((__raw_readl(ctx->regs + VIDCON1) &
 317                                         VIDCON1_VSTATUS_VSYNC), 50);
 318         if (ret < 0)
 319                 DRM_DEBUG_KMS("vblank wait timed out.\n");
 320 }
 321
 322 static struct exynos_drm_manager_ops fimd_manager_ops = {
 323         .dpms = fimd_dpms,
 324         .apply = fimd_apply,
 325         .commit = fimd_commit,
 326         .enable_vblank = fimd_enable_vblank,
 327         .disable_vblank = fimd_disable_vblank,
 328         .wait_for_vblank = fimd_wait_for_vblank,
 329 };
 330
 331 static void fimd_win_mode_set(struct device *dev,
 332                               struct exynos_drm_overlay *overlay)
 333 {
 334         struct fimd_context *ctx = get_fimd_context(dev);
 335         struct fimd_win_data *win_data;
 336         int win;
 337         unsigned long offset;
 338
 339         DRM_DEBUG_KMS("%s\n", __FILE__);
 340
 341         if (!overlay) {
 342                 dev_err(dev, "overlay is NULL\n");
 343                 return;
 344         }
 345
 346         win = overlay->zpos;
 347         if (win == DEFAULT_ZPOS)
 348                 win = ctx->default_win;
 349
 350         if (win < 0 || win > WINDOWS_NR)
 351                 return;
 352
 353         offset = overlay->fb_x * (overlay->bpp >> 3);
 354         offset += overlay->fb_y * overlay->pitch;
 355
 356         DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
 357
 358         win_data = &ctx->win_data[win];
 359
 360         win_data->offset_x = overlay->crtc_x;
 361         win_data->offset_y = overlay->crtc_y;
 362         win_data->ovl_width = overlay->crtc_width;
 363         win_data->ovl_height = overlay->crtc_height;
 364         win_data->fb_width = overlay->fb_width;
 365         win_data->fb_height = overlay->fb_height;
 366         win_data->dma_addr = overlay->dma_addr[0] + offset;
 367         win_data->vaddr = overlay->vaddr[0] + offset;
 368         win_data->bpp = overlay->bpp;
 369         win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
 370                                 (overlay->bpp >> 3);
 371         win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
 372
 373         DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
 374                         win_data->offset_x, win_data->offset_y);
 375         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 376                         win_data->ovl_width, win_data->ovl_height);
 377         DRM_DEBUG_KMS("paddr = 0x%lx, vaddr = 0x%lx\n",
 378                         (unsigned long)win_data->dma_addr,
 379                         (unsigned long)win_data->vaddr);
 380         DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
 381                         overlay->fb_width, overlay->crtc_width);
 382 }
 383
 384 static void fimd_win_set_pixfmt(struct device *dev, unsigned int win)
 385 {
 386         struct fimd_context *ctx = get_fimd_context(dev);
 387         struct fimd_win_data *win_data = &ctx->win_data[win];
 388         unsigned long val;
 389
 390         DRM_DEBUG_KMS("%s\n", __FILE__);
 391
 392         val = WINCONx_ENWIN;
 393
 394         switch (win_data->bpp) {
 395         case 1:
 396                 val |= WINCON0_BPPMODE_1BPP;
 397                 val |= WINCONx_BITSWP;
 398                 val |= WINCONx_BURSTLEN_4WORD;
 399                 break;
 400         case 2:
 401                 val |= WINCON0_BPPMODE_2BPP;
 402                 val |= WINCONx_BITSWP;
 403                 val |= WINCONx_BURSTLEN_8WORD;
 404                 break;
 405         case 4:
 406                 val |= WINCON0_BPPMODE_4BPP;
 407                 val |= WINCONx_BITSWP;
 408                 val |= WINCONx_BURSTLEN_8WORD;
 409                 break;
 410         case 8:
 411                 val |= WINCON0_BPPMODE_8BPP_PALETTE;
 412                 val |= WINCONx_BURSTLEN_8WORD;
 413                 val |= WINCONx_BYTSWP;
 414                 break;
 415         case 16:
 416                 val |= WINCON0_BPPMODE_16BPP_565;
 417                 val |= WINCONx_HAWSWP;
 418                 val |= WINCONx_BURSTLEN_16WORD;
 419                 break;
 420         case 24:
 421                 val |= WINCON0_BPPMODE_24BPP_888;
 422                 val |= WINCONx_WSWP;
 423                 val |= WINCONx_BURSTLEN_16WORD;
 424                 break;
 425         case 32:
 426                 val |= WINCON1_BPPMODE_28BPP_A4888
 427                         | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
 428                 val |= WINCONx_WSWP;
 429                 val |= WINCONx_BURSTLEN_16WORD;
 430                 break;
 431         default:
 432                 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
 433
 434                 val |= WINCON0_BPPMODE_24BPP_888;
 435                 val |= WINCONx_WSWP;
 436                 val |= WINCONx_BURSTLEN_16WORD;
 437                 break;
 438         }
 439
 440         DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
 441
 442         writel(val, ctx->regs + WINCON(win));
 443 }
 444
 445 static void fimd_win_set_colkey(struct device *dev, unsigned int win)
 446 {
 447         struct fimd_context *ctx = get_fimd_context(dev);
 448         unsigned int keycon0 = 0, keycon1 = 0;
 449
 450         DRM_DEBUG_KMS("%s\n", __FILE__);
 451
 452         keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
 453                         WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 454
 455         keycon1 = WxKEYCON1_COLVAL(0xffffffff);
 456
 457         writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
 458         writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
 459 }
 460
 461 static void fimd_win_commit(struct device *dev, int zpos)
 462 {
 463         struct fimd_context *ctx = get_fimd_context(dev);
 464         struct fimd_win_data *win_data;
 465         int win = zpos;
 466         unsigned long val, alpha, size;
 467
 468         DRM_DEBUG_KMS("%s\n", __FILE__);
 469
 470         if (ctx->suspended)
 471                 return;
 472
 473         if (win == DEFAULT_ZPOS)
 474                 win = ctx->default_win;
 475
 476         if (win < 0 || win > WINDOWS_NR)
 477                 return;
 478
 479         win_data = &ctx->win_data[win];
 480
 481         /*
 482          * SHADOWCON register is used for enabling timing.
 483          *
 484          * for example, once only width value of a register is set,
 485          * if the dma is started then fimd hardware could malfunction so
 486          * with protect window setting, the register fields with prefix '_F'
 487          * wouldn't be updated at vsync also but updated once unprotect window
 488          * is set.
 489          */
 490
 491         /* protect windows */
 492         val = readl(ctx->regs + SHADOWCON);
 493         val |= SHADOWCON_WINx_PROTECT(win);
 494         writel(val, ctx->regs + SHADOWCON);
 495
 496         /* buffer start address */
 497         val = (unsigned long)win_data->dma_addr;
 498         writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
 499
 500         /* buffer end address */
 501         size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
 502         val = (unsigned long)(win_data->dma_addr + size);
 503         writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
 504
 505         DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
 506                         (unsigned long)win_data->dma_addr, val, size);
 507         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 508                         win_data->ovl_width, win_data->ovl_height);
 509
 510         /* buffer size */
 511         val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
 512                 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size);
 513         writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
 514
 515         /* OSD position */
 516         val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
 517                 VIDOSDxA_TOPLEFT_Y(win_data->offset_y);
 518         writel(val, ctx->regs + VIDOSD_A(win));
 519
 520         val = VIDOSDxB_BOTRIGHT_X(win_data->offset_x +
 521                                         win_data->ovl_width - 1) |
 522                 VIDOSDxB_BOTRIGHT_Y(win_data->offset_y +
 523                                         win_data->ovl_height - 1);
 524         writel(val, ctx->regs + VIDOSD_B(win));
 525
 526         DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
 527                         win_data->offset_x, win_data->offset_y,
 528                         win_data->offset_x + win_data->ovl_width - 1,
 529                         win_data->offset_y + win_data->ovl_height - 1);
 530
 531         /* hardware window 0 doesn't support alpha channel. */
 532         if (win != 0) {
 533                 /* OSD alpha */
 534                 alpha = VIDISD14C_ALPHA1_R(0xf) |
 535                         VIDISD14C_ALPHA1_G(0xf) |
 536                         VIDISD14C_ALPHA1_B(0xf);
 537
 538                 writel(alpha, ctx->regs + VIDOSD_C(win));
 539         }
 540
 541         /* OSD size */
 542         if (win != 3 && win != 4) {
 543                 u32 offset = VIDOSD_D(win);
 544                 if (win == 0)
 545                         offset = VIDOSD_C_SIZE_W0;
 546                 val = win_data->ovl_width * win_data->ovl_height;
 547                 writel(val, ctx->regs + offset);
 548
 549                 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
 550         }
 551
 552         fimd_win_set_pixfmt(dev, win);
 553
 554         /* hardware window 0 doesn't support color key. */
 555         if (win != 0)
 556                 fimd_win_set_colkey(dev, win);
 557
 558         /* wincon */
 559         val = readl(ctx->regs + WINCON(win));
 560         val |= WINCONx_ENWIN;
 561         writel(val, ctx->regs + WINCON(win));
 562
 563         /* Enable DMA channel and unprotect windows */
 564         val = readl(ctx->regs + SHADOWCON);
 565         val |= SHADOWCON_CHx_ENABLE(win);
 566         val &= ~SHADOWCON_WINx_PROTECT(win);
 567         writel(val, ctx->regs + SHADOWCON);
 568
 569         win_data->enabled = true;
 570 }
 571
 572 static void fimd_win_disable(struct device *dev, int zpos)
 573 {
 574         struct fimd_context *ctx = get_fimd_context(dev);
 575         struct fimd_win_data *win_data;
 576         int win = zpos;
 577         u32 val;
 578
 579         DRM_DEBUG_KMS("%s\n", __FILE__);
 580
 581         if (win == DEFAULT_ZPOS)
 582                 win = ctx->default_win;
 583
 584         if (win < 0 || win > WINDOWS_NR)
 585                 return;
 586
 587         win_data = &ctx->win_data[win];
 588
 589         /* protect windows */
 590         val = readl(ctx->regs + SHADOWCON);
 591         val |= SHADOWCON_WINx_PROTECT(win);
 592         writel(val, ctx->regs + SHADOWCON);
 593
 594         /* wincon */
 595         val = readl(ctx->regs + WINCON(win));
 596         val &= ~WINCONx_ENWIN;
 597         writel(val, ctx->regs + WINCON(win));
 598
 599         /* unprotect windows */
 600         val = readl(ctx->regs + SHADOWCON);
 601         val &= ~SHADOWCON_CHx_ENABLE(win);
 602         val &= ~SHADOWCON_WINx_PROTECT(win);
 603         writel(val, ctx->regs + SHADOWCON);
 604
 605         win_data->enabled = false;
 606 }
 607
 608 static struct exynos_drm_overlay_ops fimd_overlay_ops = {
 609         .mode_set = fimd_win_mode_set,
 610         .commit = fimd_win_commit,
 611         .disable = fimd_win_disable,
 612 };
 613
 614 static struct exynos_drm_manager fimd_manager = {
 615         .pipe           = -1,
 616         .ops            = &fimd_manager_ops,
 617         .overlay_ops    = &fimd_overlay_ops,
 618         .display_ops    = &fimd_display_ops,
 619 };
 620
 621 static void fimd_finish_pageflip(struct drm_device *drm_dev, int crtc)
 622 {
 623         struct exynos_drm_private *dev_priv = drm_dev->dev_private;
 624         struct drm_pending_vblank_event *e, *t;
 625         struct timeval now;
 626         unsigned long flags;
 627
 628         spin_lock_irqsave(&drm_dev->event_lock, flags);
 629
 630         list_for_each_entry_safe(e, t, &dev_priv->pageflip_event_list,
 631                         base.link) {
 632                 /* if event's pipe isn't same as crtc then ignore it. */
 633                 if (crtc != e->pipe)
 634                         continue;
 635
 636                 do_gettimeofday(&now);
 637                 e->event.sequence = 0;
 638                 e->event.tv_sec = now.tv_sec;
 639                 e->event.tv_usec = now.tv_usec;
 640
 641                 list_move_tail(&e->base.link, &e->base.file_priv->event_list);
 642                 wake_up_interruptible(&e->base.file_priv->event_wait);
 643                 drm_vblank_put(drm_dev, crtc);
 644         }
 645
 646         spin_unlock_irqrestore(&drm_dev->event_lock, flags);
 647 }
 648
 649 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
 650 {
 651         struct fimd_context *ctx = (struct fimd_context *)dev_id;
 652         struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
 653         struct drm_device *drm_dev = subdrv->drm_dev;
 654         struct exynos_drm_manager *manager = subdrv->manager;
 655         u32 val;
 656
 657         val = readl(ctx->regs + VIDINTCON1);
 658
 659         if (val & VIDINTCON1_INT_FRAME)
 660                 /* VSYNC interrupt */
 661                 writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1);
 662
 663         /* check the crtc is detached already from encoder */
 664         if (manager->pipe < 0)
 665                 goto out;
 666
 667         drm_handle_vblank(drm_dev, manager->pipe);
 668         fimd_finish_pageflip(drm_dev, manager->pipe);
 669
 670 out:
 671         return IRQ_HANDLED;
 672 }
 673
 674 static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
 675 {
 676         DRM_DEBUG_KMS("%s\n", __FILE__);
 677
 678         /*
 679          * enable drm irq mode.
 680          * - with irq_enabled = 1, we can use the vblank feature.
 681          *
 682          * P.S. note that we wouldn't use drm irq handler but
 683          *      just specific driver own one instead because
 684          *      drm framework supports only one irq handler.
 685          */
 686         drm_dev->irq_enabled = 1;
 687
 688         /*
 689          * with vblank_disable_allowed = 1, vblank interrupt will be disabled
 690          * by drm timer once a current process gives up ownership of
 691          * vblank event.(after drm_vblank_put function is called)
 692          */
 693         drm_dev->vblank_disable_allowed = 1;
 694
 695         /* attach this sub driver to iommu mapping if supported. */
 696         if (is_drm_iommu_supported(drm_dev))
 697                 drm_iommu_attach_device(drm_dev, dev);
 698
 699         return 0;
 700 }
 701
 702 static void fimd_subdrv_remove(struct drm_device *drm_dev, struct device *dev)
 703 {
 704         DRM_DEBUG_KMS("%s\n", __FILE__);
 705
 706         /* detach this sub driver from iommu mapping if supported. */
 707         if (is_drm_iommu_supported(drm_dev))
 708                 drm_iommu_detach_device(drm_dev, dev);
 709 }
 710
 711 static int fimd_calc_clkdiv(struct fimd_context *ctx,
 712                             struct fb_videomode *timing)
 713 {
 714         unsigned long clk = clk_get_rate(ctx->lcd_clk);
 715         u32 retrace;
 716         u32 clkdiv;
 717         u32 best_framerate = 0;
 718         u32 framerate;
 719
 720         DRM_DEBUG_KMS("%s\n", __FILE__);
 721
 722         retrace = timing->left_margin + timing->hsync_len +
 723                                 timing->right_margin + timing->xres;
 724         retrace *= timing->upper_margin + timing->vsync_len +
 725                                 timing->lower_margin + timing->yres;
 726
 727         /* default framerate is 60Hz */
 728         if (!timing->refresh)
 729                 timing->refresh = 60;
 730
 731         clk /= retrace;
 732
 733         for (clkdiv = 1; clkdiv < 0x100; clkdiv++) {
 734                 int tmp;
 735
 736                 /* get best framerate */
 737                 framerate = clk / clkdiv;
 738                 tmp = timing->refresh - framerate;
 739                 if (tmp < 0) {
 740                         best_framerate = framerate;
 741                         continue;
 742                 } else {
 743                         if (!best_framerate)
 744                                 best_framerate = framerate;
 745                         else if (tmp < (best_framerate - framerate))
 746                                 best_framerate = framerate;
 747                         break;
 748                 }
 749         }
 750
 751         return clkdiv;
 752 }
 753
 754 static void fimd_clear_win(struct fimd_context *ctx, int win)
 755 {
 756         u32 val;
 757
 758         DRM_DEBUG_KMS("%s\n", __FILE__);
 759
 760         writel(0, ctx->regs + WINCON(win));
 761         writel(0, ctx->regs + VIDOSD_A(win));
 762         writel(0, ctx->regs + VIDOSD_B(win));
 763         writel(0, ctx->regs + VIDOSD_C(win));
 764
 765         if (win == 1 || win == 2)
 766                 writel(0, ctx->regs + VIDOSD_D(win));
 767
 768         val = readl(ctx->regs + SHADOWCON);
 769         val &= ~SHADOWCON_WINx_PROTECT(win);
 770         writel(val, ctx->regs + SHADOWCON);
 771 }
 772
 773 static int fimd_clock(struct fimd_context *ctx, bool enable)
 774 {
 775         DRM_DEBUG_KMS("%s\n", __FILE__);
 776
 777         if (enable) {
 778                 int ret;
 779
 780                 ret = clk_enable(ctx->bus_clk);
 781                 if (ret < 0)
 782                         return ret;
 783
 784                 ret = clk_enable(ctx->lcd_clk);
 785                 if  (ret < 0) {
 786                         clk_disable(ctx->bus_clk);
 787                         return ret;
 788                 }
 789         } else {
 790                 clk_disable(ctx->lcd_clk);
 791                 clk_disable(ctx->bus_clk);
 792         }
 793
 794         return 0;
 795 }
 796
 797 static int fimd_activate(struct fimd_context *ctx, bool enable)
 798 {
 799         if (enable) {
 800                 int ret;
 801                 struct device *dev = ctx->subdrv.dev;
 802
 803                 ret = fimd_clock(ctx, true);
 804                 if (ret < 0)
 805                         return ret;
 806
 807                 ctx->suspended = false;
 808
 809                 /* if vblank was enabled status, enable it again. */
 810                 if (test_and_clear_bit(0, &ctx->irq_flags))
 811                         fimd_enable_vblank(dev);
 812         } else {
 813                 fimd_clock(ctx, false);
 814                 ctx->suspended = true;
 815         }
 816
 817         return 0;
 818 }
 819
 820 static int __devinit fimd_probe(struct platform_device *pdev)
 821 {
 822         struct device *dev = &pdev->dev;
 823         struct fimd_context *ctx;
 824         struct exynos_drm_subdrv *subdrv;
 825         struct exynos_drm_fimd_pdata *pdata;
 826         struct exynos_drm_panel_info *panel;
 827         struct resource *res;
 828         int win;
 829         int ret = -EINVAL;
 830
 831         DRM_DEBUG_KMS("%s\n", __FILE__);
 832
 833         pdata = pdev->dev.platform_data;
 834         if (!pdata) {
 835                 dev_err(dev, "no platform data specified\n");
 836                 return -EINVAL;
 837         }
 838
 839         panel = &pdata->panel;
 840         if (!panel) {
 841                 dev_err(dev, "panel is null.\n");
 842                 return -EINVAL;
 843         }
 844
 845         ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
 846         if (!ctx)
 847                 return -ENOMEM;
 848
 849         ctx->bus_clk = devm_clk_get(dev, "fimd");
 850         if (IS_ERR(ctx->bus_clk)) {
 851                 dev_err(dev, "failed to get bus clock\n");
 852                 return PTR_ERR(ctx->bus_clk);
 853         }
 854
 855         ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
 856         if (IS_ERR(ctx->lcd_clk)) {
 857                 dev_err(dev, "failed to get lcd clock\n");
 858                 return PTR_ERR(ctx->lcd_clk);
 859         }
 860
 861         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 862
 863         ctx->regs = devm_request_and_ioremap(&pdev->dev, res);
 864         if (!ctx->regs) {
 865                 dev_err(dev, "failed to map registers\n");
 866                 return -ENXIO;
 867         }
 868
 869         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 870         if (!res) {
 871                 dev_err(dev, "irq request failed.\n");
 872                 return -ENXIO;
 873         }
 874
 875         ctx->irq = res->start;
 876
 877         ret = devm_request_irq(&pdev->dev, ctx->irq, fimd_irq_handler,
 878                                                         0, "drm_fimd", ctx);
 879         if (ret) {
 880                 dev_err(dev, "irq request failed.\n");
 881                 return ret;
 882         }
 883
 884         ctx->vidcon0 = pdata->vidcon0;
 885         ctx->vidcon1 = pdata->vidcon1;
 886         ctx->default_win = pdata->default_win;
 887         ctx->panel = panel;
 888
 889         subdrv = &ctx->subdrv;
 890
 891         subdrv->dev = dev;
 892         subdrv->manager = &fimd_manager;
 893         subdrv->probe = fimd_subdrv_probe;
 894         subdrv->remove = fimd_subdrv_remove;
 895
 896         mutex_init(&ctx->lock);
 897
 898         platform_set_drvdata(pdev, ctx);
 899
 900         pm_runtime_enable(dev);
 901         pm_runtime_get_sync(dev);
 902
 903         ctx->clkdiv = fimd_calc_clkdiv(ctx, &panel->timing);
 904         panel->timing.pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
 905
 906         DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
 907                         panel->timing.pixclock, ctx->clkdiv);
 908
 909         for (win = 0; win < WINDOWS_NR; win++)
 910                 fimd_clear_win(ctx, win);
 911
 912         exynos_drm_subdrv_register(subdrv);
 913
 914         return 0;
 915 }
 916
 917 static int __devexit fimd_remove(struct platform_device *pdev)
 918 {
 919         struct device *dev = &pdev->dev;
 920         struct fimd_context *ctx = platform_get_drvdata(pdev);
 921
 922         DRM_DEBUG_KMS("%s\n", __FILE__);
 923
 924         exynos_drm_subdrv_unregister(&ctx->subdrv);
 925
 926         if (ctx->suspended)
 927                 goto out;
 928
 929         clk_disable(ctx->lcd_clk);
 930         clk_disable(ctx->bus_clk);
 931
 932         pm_runtime_set_suspended(dev);
 933         pm_runtime_put_sync(dev);
 934
 935 out:
 936         pm_runtime_disable(dev);
 937
 938         return 0;
 939 }
 940
 941 #ifdef CONFIG_PM_SLEEP
 942 static int fimd_suspend(struct device *dev)
 943 {
 944         struct fimd_context *ctx = get_fimd_context(dev);
 945
 946         /*
 947          * do not use pm_runtime_suspend(). if pm_runtime_suspend() is
 948          * called here, an error would be returned by that interface
 949          * because the usage_count of pm runtime is more than 1.
 950          */
 951         if (!pm_runtime_suspended(dev))
 952                 return fimd_activate(ctx, false);
 953
 954         return 0;
 955 }
 956
 957 static int fimd_resume(struct device *dev)
 958 {
 959         struct fimd_context *ctx = get_fimd_context(dev);
 960
 961         /*
 962          * if entered to sleep when lcd panel was on, the usage_count
 963          * of pm runtime would still be 1 so in this case, fimd driver
 964          * should be on directly not drawing on pm runtime interface.
 965          */
 966         if (pm_runtime_suspended(dev)) {
 967                 int ret;
 968
 969                 ret = fimd_activate(ctx, true);
 970                 if (ret < 0)
 971                         return ret;
 972
 973                 /*
 974                  * in case of dpms on(standby), fimd_apply function will
 975                  * be called by encoder's dpms callback to update fimd's
 976                  * registers but in case of sleep wakeup, it's not.
 977                  * so fimd_apply function should be called at here.
 978                  */
 979                 fimd_apply(dev);
 980         }
 981
 982         return 0;
 983 }
 984 #endif
 985
 986 #ifdef CONFIG_PM_RUNTIME
 987 static int fimd_runtime_suspend(struct device *dev)
 988 {
 989         struct fimd_context *ctx = get_fimd_context(dev);
 990
 991         DRM_DEBUG_KMS("%s\n", __FILE__);
 992
 993         return fimd_activate(ctx, false);
 994 }
 995
 996 static int fimd_runtime_resume(struct device *dev)
 997 {
 998         struct fimd_context *ctx = get_fimd_context(dev);
 999
1000         DRM_DEBUG_KMS("%s\n", __FILE__);
1001
1002         return fimd_activate(ctx, true);
1003 }
1004 #endif
1005
1006 static struct platform_device_id fimd_driver_ids[] = {
1007         {
1008                 .name           = "exynos4-fb",
1009                 .driver_data    = (unsigned long)&exynos4_fimd_driver_data,
1010         }, {
1011                 .name           = "exynos5-fb",
1012                 .driver_data    = (unsigned long)&exynos5_fimd_driver_data,
1013         },
1014         {},
1015 };
1016 MODULE_DEVICE_TABLE(platform, fimd_driver_ids);
1017
1018 static const struct dev_pm_ops fimd_pm_ops = {
1019         SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume)
1020         SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL)
1021 };
1022
1023 struct platform_driver fimd_driver = {
1024         .probe          = fimd_probe,
1025         .remove         = __devexit_p(fimd_remove),
1026         .id_table       = fimd_driver_ids,
1027         .driver         = {
1028                 .name   = "exynos4-fb",
1029                 .owner  = THIS_MODULE,
1030                 .pm     = &fimd_pm_ops,
1031         },
1032 };