drivers/gpu/drm/exynos/exynos_drm_fimd.c

   1 /* exynos_drm_fimd.c
   2  *
   3  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Inki Dae <inki.dae@samsung.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14 #include "drmP.h"
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/clk.h>
  20 #include <linux/pm_runtime.h>
  21
  22 #include <drm/exynos_drm.h>
  23 #include <plat/regs-fb-v4.h>
  24
  25 #include "exynos_drm_drv.h"
  26 #include "exynos_drm_fbdev.h"
  27 #include "exynos_drm_crtc.h"
  28
  29 /*
  30  * FIMD is stand for Fully Interactive Mobile Display and
  31  * as a display controller, it transfers contents drawn on memory
  32  * to a LCD Panel through Display Interfaces such as RGB or
  33  * CPU Interface.
  34  */
  35
  36 /* position control register for hardware window 0, 2 ~ 4.*/
  37 #define VIDOSD_A(win)           (VIDOSD_BASE + 0x00 + (win) * 16)
  38 #define VIDOSD_B(win)           (VIDOSD_BASE + 0x04 + (win) * 16)
  39 /* size control register for hardware window 0. */
  40 #define VIDOSD_C_SIZE_W0        (VIDOSD_BASE + 0x08)
  41 /* alpha control register for hardware window 1 ~ 4. */
  42 #define VIDOSD_C(win)           (VIDOSD_BASE + 0x18 + (win) * 16)
  43 /* size control register for hardware window 1 ~ 4. */
  44 #define VIDOSD_D(win)           (VIDOSD_BASE + 0x0C + (win) * 16)
  45
  46 #define VIDWx_BUF_START(win, buf)       (VIDW_BUF_START(buf) + (win) * 8)
  47 #define VIDWx_BUF_END(win, buf)         (VIDW_BUF_END(buf) + (win) * 8)
  48 #define VIDWx_BUF_SIZE(win, buf)        (VIDW_BUF_SIZE(buf) + (win) * 4)
  49
  50 /* color key control register for hardware window 1 ~ 4. */
  51 #define WKEYCON0_BASE(x)                ((WKEYCON0 + 0x140) + (x * 8))
  52 /* color key value register for hardware window 1 ~ 4. */
  53 #define WKEYCON1_BASE(x)                ((WKEYCON1 + 0x140) + (x * 8))
  54
  55 /* FIMD has totally five hardware windows. */
  56 #define WINDOWS_NR      5
  57
  58 #define get_fimd_context(dev)   platform_get_drvdata(to_platform_device(dev))
  59
  60 struct fimd_win_data {
  61         unsigned int            offset_x;
  62         unsigned int            offset_y;
  63         unsigned int            ovl_width;
  64         unsigned int            ovl_height;
  65         unsigned int            fb_width;
  66         unsigned int            fb_height;
  67         unsigned int            bpp;
  68         dma_addr_t              dma_addr;
  69         void __iomem            *vaddr;
  70         unsigned int            buf_offsize;
  71         unsigned int            line_size;      /* bytes */
  72         bool                    enabled;
  73 };
  74
  75 struct fimd_context {
  76         struct exynos_drm_subdrv        subdrv;
  77         int                             irq;
  78         struct drm_crtc                 *crtc;
  79         struct clk                      *bus_clk;
  80         struct clk                      *lcd_clk;
  81         struct resource                 *regs_res;
  82         void __iomem                    *regs;
  83         struct fimd_win_data            win_data[WINDOWS_NR];
  84         unsigned int                    clkdiv;
  85         unsigned int                    default_win;
  86         unsigned long                   irq_flags;
  87         u32                             vidcon0;
  88         u32                             vidcon1;
  89         bool                            suspended;
  90
  91         struct fb_videomode             *timing;
  92 };
  93
  94 static bool fimd_display_is_connected(struct device *dev)
  95 {
  96         DRM_DEBUG_KMS("%s\n", __FILE__);
  97
  98         /* TODO. */
  99
 100         return true;
 101 }
 102
 103 static void *fimd_get_timing(struct device *dev)
 104 {
 105         struct fimd_context *ctx = get_fimd_context(dev);
 106
 107         DRM_DEBUG_KMS("%s\n", __FILE__);
 108
 109         return ctx->timing;
 110 }
 111
 112 static int fimd_check_timing(struct device *dev, void *timing)
 113 {
 114         DRM_DEBUG_KMS("%s\n", __FILE__);
 115
 116         /* TODO. */
 117
 118         return 0;
 119 }
 120
 121 static int fimd_display_power_on(struct device *dev, int mode)
 122 {
 123         DRM_DEBUG_KMS("%s\n", __FILE__);
 124
 125         /* TODO */
 126
 127         return 0;
 128 }
 129
 130 static struct exynos_drm_display_ops fimd_display_ops = {
 131         .type = EXYNOS_DISPLAY_TYPE_LCD,
 132         .is_connected = fimd_display_is_connected,
 133         .get_timing = fimd_get_timing,
 134         .check_timing = fimd_check_timing,
 135         .power_on = fimd_display_power_on,
 136 };
 137
 138 static void fimd_dpms(struct device *subdrv_dev, int mode)
 139 {
 140         DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
 141
 142         switch (mode) {
 143         case DRM_MODE_DPMS_ON:
 144                 pm_runtime_get_sync(subdrv_dev);
 145                 break;
 146         case DRM_MODE_DPMS_STANDBY:
 147         case DRM_MODE_DPMS_SUSPEND:
 148         case DRM_MODE_DPMS_OFF:
 149                 pm_runtime_put_sync(subdrv_dev);
 150                 break;
 151         default:
 152                 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
 153                 break;
 154         }
 155 }
 156
 157 static void fimd_apply(struct device *subdrv_dev)
 158 {
 159         struct fimd_context *ctx = get_fimd_context(subdrv_dev);
 160         struct exynos_drm_manager *mgr = &ctx->subdrv.manager;
 161         struct exynos_drm_manager_ops *mgr_ops = mgr->ops;
 162         struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops;
 163         struct fimd_win_data *win_data;
 164         int i;
 165
 166         DRM_DEBUG_KMS("%s\n", __FILE__);
 167
 168         for (i = 0; i < WINDOWS_NR; i++) {
 169                 win_data = &ctx->win_data[i];
 170                 if (win_data->enabled && (ovl_ops && ovl_ops->commit))
 171                         ovl_ops->commit(subdrv_dev, i);
 172         }
 173
 174         if (mgr_ops && mgr_ops->commit)
 175                 mgr_ops->commit(subdrv_dev);
 176 }
 177
 178 static void fimd_commit(struct device *dev)
 179 {
 180         struct fimd_context *ctx = get_fimd_context(dev);
 181         struct fb_videomode *timing = ctx->timing;
 182         u32 val;
 183
 184         DRM_DEBUG_KMS("%s\n", __FILE__);
 185
 186         /* setup polarity values from machine code. */
 187         writel(ctx->vidcon1, ctx->regs + VIDCON1);
 188
 189         /* setup vertical timing values. */
 190         val = VIDTCON0_VBPD(timing->upper_margin - 1) |
 191                VIDTCON0_VFPD(timing->lower_margin - 1) |
 192                VIDTCON0_VSPW(timing->vsync_len - 1);
 193         writel(val, ctx->regs + VIDTCON0);
 194
 195         /* setup horizontal timing values.  */
 196         val = VIDTCON1_HBPD(timing->left_margin - 1) |
 197                VIDTCON1_HFPD(timing->right_margin - 1) |
 198                VIDTCON1_HSPW(timing->hsync_len - 1);
 199         writel(val, ctx->regs + VIDTCON1);
 200
 201         /* setup horizontal and vertical display size. */
 202         val = VIDTCON2_LINEVAL(timing->yres - 1) |
 203                VIDTCON2_HOZVAL(timing->xres - 1);
 204         writel(val, ctx->regs + VIDTCON2);
 205
 206         /* setup clock source, clock divider, enable dma. */
 207         val = ctx->vidcon0;
 208         val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
 209
 210         if (ctx->clkdiv > 1)
 211                 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
 212         else
 213                 val &= ~VIDCON0_CLKDIR; /* 1:1 clock */
 214
 215         /*
 216          * fields of register with prefix '_F' would be updated
 217          * at vsync(same as dma start)
 218          */
 219         val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 220         writel(val, ctx->regs + VIDCON0);
 221 }
 222
 223 static int fimd_enable_vblank(struct device *dev)
 224 {
 225         struct fimd_context *ctx = get_fimd_context(dev);
 226         u32 val;
 227
 228         DRM_DEBUG_KMS("%s\n", __FILE__);
 229
 230         if (ctx->suspended)
 231                 return -EPERM;
 232
 233         if (!test_and_set_bit(0, &ctx->irq_flags)) {
 234                 val = readl(ctx->regs + VIDINTCON0);
 235
 236                 val |= VIDINTCON0_INT_ENABLE;
 237                 val |= VIDINTCON0_INT_FRAME;
 238
 239                 val &= ~VIDINTCON0_FRAMESEL0_MASK;
 240                 val |= VIDINTCON0_FRAMESEL0_VSYNC;
 241                 val &= ~VIDINTCON0_FRAMESEL1_MASK;
 242                 val |= VIDINTCON0_FRAMESEL1_NONE;
 243
 244                 writel(val, ctx->regs + VIDINTCON0);
 245         }
 246
 247         return 0;
 248 }
 249
 250 static void fimd_disable_vblank(struct device *dev)
 251 {
 252         struct fimd_context *ctx = get_fimd_context(dev);
 253         u32 val;
 254
 255         DRM_DEBUG_KMS("%s\n", __FILE__);
 256
 257         if (ctx->suspended)
 258                 return;
 259
 260         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 261                 val = readl(ctx->regs + VIDINTCON0);
 262
 263                 val &= ~VIDINTCON0_INT_FRAME;
 264                 val &= ~VIDINTCON0_INT_ENABLE;
 265
 266                 writel(val, ctx->regs + VIDINTCON0);
 267         }
 268 }
 269
 270 static struct exynos_drm_manager_ops fimd_manager_ops = {
 271         .dpms = fimd_dpms,
 272         .apply = fimd_apply,
 273         .commit = fimd_commit,
 274         .enable_vblank = fimd_enable_vblank,
 275         .disable_vblank = fimd_disable_vblank,
 276 };
 277
 278 static void fimd_win_mode_set(struct device *dev,
 279                               struct exynos_drm_overlay *overlay)
 280 {
 281         struct fimd_context *ctx = get_fimd_context(dev);
 282         struct fimd_win_data *win_data;
 283         int win;
 284         unsigned long offset;
 285
 286         DRM_DEBUG_KMS("%s\n", __FILE__);
 287
 288         if (!overlay) {
 289                 dev_err(dev, "overlay is NULL\n");
 290                 return;
 291         }
 292
 293         win = overlay->zpos;
 294         if (win == DEFAULT_ZPOS)
 295                 win = ctx->default_win;
 296
 297         if (win < 0 || win > WINDOWS_NR)
 298                 return;
 299
 300         offset = overlay->fb_x * (overlay->bpp >> 3);
 301         offset += overlay->fb_y * overlay->pitch;
 302
 303         DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
 304
 305         win_data = &ctx->win_data[win];
 306
 307         win_data->offset_x = overlay->crtc_x;
 308         win_data->offset_y = overlay->crtc_y;
 309         win_data->ovl_width = overlay->crtc_width;
 310         win_data->ovl_height = overlay->crtc_height;
 311         win_data->fb_width = overlay->fb_width;
 312         win_data->fb_height = overlay->fb_height;
 313         win_data->dma_addr = overlay->dma_addr + offset;
 314         win_data->vaddr = overlay->vaddr + offset;
 315         win_data->bpp = overlay->bpp;
 316         win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
 317                                 (overlay->bpp >> 3);
 318         win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
 319
 320         DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
 321                         win_data->offset_x, win_data->offset_y);
 322         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 323                         win_data->ovl_width, win_data->ovl_height);
 324         DRM_DEBUG_KMS("paddr = 0x%lx, vaddr = 0x%lx\n",
 325                         (unsigned long)win_data->dma_addr,
 326                         (unsigned long)win_data->vaddr);
 327         DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
 328                         overlay->fb_width, overlay->crtc_width);
 329 }
 330
 331 static void fimd_win_set_pixfmt(struct device *dev, unsigned int win)
 332 {
 333         struct fimd_context *ctx = get_fimd_context(dev);
 334         struct fimd_win_data *win_data = &ctx->win_data[win];
 335         unsigned long val;
 336
 337         DRM_DEBUG_KMS("%s\n", __FILE__);
 338
 339         val = WINCONx_ENWIN;
 340
 341         switch (win_data->bpp) {
 342         case 1:
 343                 val |= WINCON0_BPPMODE_1BPP;
 344                 val |= WINCONx_BITSWP;
 345                 val |= WINCONx_BURSTLEN_4WORD;
 346                 break;
 347         case 2:
 348                 val |= WINCON0_BPPMODE_2BPP;
 349                 val |= WINCONx_BITSWP;
 350                 val |= WINCONx_BURSTLEN_8WORD;
 351                 break;
 352         case 4:
 353                 val |= WINCON0_BPPMODE_4BPP;
 354                 val |= WINCONx_BITSWP;
 355                 val |= WINCONx_BURSTLEN_8WORD;
 356                 break;
 357         case 8:
 358                 val |= WINCON0_BPPMODE_8BPP_PALETTE;
 359                 val |= WINCONx_BURSTLEN_8WORD;
 360                 val |= WINCONx_BYTSWP;
 361                 break;
 362         case 16:
 363                 val |= WINCON0_BPPMODE_16BPP_565;
 364                 val |= WINCONx_HAWSWP;
 365                 val |= WINCONx_BURSTLEN_16WORD;
 366                 break;
 367         case 24:
 368                 val |= WINCON0_BPPMODE_24BPP_888;
 369                 val |= WINCONx_WSWP;
 370                 val |= WINCONx_BURSTLEN_16WORD;
 371                 break;
 372         case 32:
 373                 val |= WINCON1_BPPMODE_28BPP_A4888
 374                         | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
 375                 val |= WINCONx_WSWP;
 376                 val |= WINCONx_BURSTLEN_16WORD;
 377                 break;
 378         default:
 379                 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
 380
 381                 val |= WINCON0_BPPMODE_24BPP_888;
 382                 val |= WINCONx_WSWP;
 383                 val |= WINCONx_BURSTLEN_16WORD;
 384                 break;
 385         }
 386
 387         DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
 388
 389         writel(val, ctx->regs + WINCON(win));
 390 }
 391
 392 static void fimd_win_set_colkey(struct device *dev, unsigned int win)
 393 {
 394         struct fimd_context *ctx = get_fimd_context(dev);
 395         unsigned int keycon0 = 0, keycon1 = 0;
 396
 397         DRM_DEBUG_KMS("%s\n", __FILE__);
 398
 399         keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
 400                         WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 401
 402         keycon1 = WxKEYCON1_COLVAL(0xffffffff);
 403
 404         writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
 405         writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
 406 }
 407
 408 static void fimd_win_commit(struct device *dev, int zpos)
 409 {
 410         struct fimd_context *ctx = get_fimd_context(dev);
 411         struct fimd_win_data *win_data;
 412         int win = zpos;
 413         unsigned long val, alpha, size;
 414
 415         DRM_DEBUG_KMS("%s\n", __FILE__);
 416
 417         if (win == DEFAULT_ZPOS)
 418                 win = ctx->default_win;
 419
 420         if (win < 0 || win > WINDOWS_NR)
 421                 return;
 422
 423         win_data = &ctx->win_data[win];
 424
 425         /*
 426          * SHADOWCON register is used for enabling timing.
 427          *
 428          * for example, once only width value of a register is set,
 429          * if the dma is started then fimd hardware could malfunction so
 430          * with protect window setting, the register fields with prefix '_F'
 431          * wouldn't be updated at vsync also but updated once unprotect window
 432          * is set.
 433          */
 434
 435         /* protect windows */
 436         val = readl(ctx->regs + SHADOWCON);
 437         val |= SHADOWCON_WINx_PROTECT(win);
 438         writel(val, ctx->regs + SHADOWCON);
 439
 440         /* buffer start address */
 441         val = (unsigned long)win_data->dma_addr;
 442         writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
 443
 444         /* buffer end address */
 445         size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
 446         val = (unsigned long)(win_data->dma_addr + size);
 447         writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
 448
 449         DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
 450                         (unsigned long)win_data->dma_addr, val, size);
 451         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 452                         win_data->ovl_width, win_data->ovl_height);
 453
 454         /* buffer size */
 455         val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
 456                 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size);
 457         writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
 458
 459         /* OSD position */
 460         val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
 461                 VIDOSDxA_TOPLEFT_Y(win_data->offset_y);
 462         writel(val, ctx->regs + VIDOSD_A(win));
 463
 464         val = VIDOSDxB_BOTRIGHT_X(win_data->offset_x +
 465                                         win_data->ovl_width - 1) |
 466                 VIDOSDxB_BOTRIGHT_Y(win_data->offset_y +
 467                                         win_data->ovl_height - 1);
 468         writel(val, ctx->regs + VIDOSD_B(win));
 469
 470         DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
 471                         win_data->offset_x, win_data->offset_y,
 472                         win_data->offset_x + win_data->ovl_width - 1,
 473                         win_data->offset_y + win_data->ovl_height - 1);
 474
 475         /* hardware window 0 doesn't support alpha channel. */
 476         if (win != 0) {
 477                 /* OSD alpha */
 478                 alpha = VIDISD14C_ALPHA1_R(0xf) |
 479                         VIDISD14C_ALPHA1_G(0xf) |
 480                         VIDISD14C_ALPHA1_B(0xf);
 481
 482                 writel(alpha, ctx->regs + VIDOSD_C(win));
 483         }
 484
 485         /* OSD size */
 486         if (win != 3 && win != 4) {
 487                 u32 offset = VIDOSD_D(win);
 488                 if (win == 0)
 489                         offset = VIDOSD_C_SIZE_W0;
 490                 val = win_data->ovl_width * win_data->ovl_height;
 491                 writel(val, ctx->regs + offset);
 492
 493                 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
 494         }
 495
 496         fimd_win_set_pixfmt(dev, win);
 497
 498         /* hardware window 0 doesn't support color key. */
 499         if (win != 0)
 500                 fimd_win_set_colkey(dev, win);
 501
 502         /* wincon */
 503         val = readl(ctx->regs + WINCON(win));
 504         val |= WINCONx_ENWIN;
 505         writel(val, ctx->regs + WINCON(win));
 506
 507         /* Enable DMA channel and unprotect windows */
 508         val = readl(ctx->regs + SHADOWCON);
 509         val |= SHADOWCON_CHx_ENABLE(win);
 510         val &= ~SHADOWCON_WINx_PROTECT(win);
 511         writel(val, ctx->regs + SHADOWCON);
 512
 513         win_data->enabled = true;
 514 }
 515
 516 static void fimd_win_disable(struct device *dev, int zpos)
 517 {
 518         struct fimd_context *ctx = get_fimd_context(dev);
 519         struct fimd_win_data *win_data;
 520         int win = zpos;
 521         u32 val;
 522
 523         DRM_DEBUG_KMS("%s\n", __FILE__);
 524
 525         if (win == DEFAULT_ZPOS)
 526                 win = ctx->default_win;
 527
 528         if (win < 0 || win > WINDOWS_NR)
 529                 return;
 530
 531         win_data = &ctx->win_data[win];
 532
 533         /* protect windows */
 534         val = readl(ctx->regs + SHADOWCON);
 535         val |= SHADOWCON_WINx_PROTECT(win);
 536         writel(val, ctx->regs + SHADOWCON);
 537
 538         /* wincon */
 539         val = readl(ctx->regs + WINCON(win));
 540         val &= ~WINCONx_ENWIN;
 541         writel(val, ctx->regs + WINCON(win));
 542
 543         /* unprotect windows */
 544         val = readl(ctx->regs + SHADOWCON);
 545         val &= ~SHADOWCON_CHx_ENABLE(win);
 546         val &= ~SHADOWCON_WINx_PROTECT(win);
 547         writel(val, ctx->regs + SHADOWCON);
 548
 549         win_data->enabled = false;
 550 }
 551
 552 static struct exynos_drm_overlay_ops fimd_overlay_ops = {
 553         .mode_set = fimd_win_mode_set,
 554         .commit = fimd_win_commit,
 555         .disable = fimd_win_disable,
 556 };
 557
 558 static void fimd_finish_pageflip(struct drm_device *drm_dev, int crtc)
 559 {
 560         struct exynos_drm_private *dev_priv = drm_dev->dev_private;
 561         struct drm_pending_vblank_event *e, *t;
 562         struct timeval now;
 563         unsigned long flags;
 564         bool is_checked = false;
 565
 566         spin_lock_irqsave(&drm_dev->event_lock, flags);
 567
 568         list_for_each_entry_safe(e, t, &dev_priv->pageflip_event_list,
 569                         base.link) {
 570                 /* if event's pipe isn't same as crtc then ignore it. */
 571                 if (crtc != e->pipe)
 572                         continue;
 573
 574                 is_checked = true;
 575
 576                 do_gettimeofday(&now);
 577                 e->event.sequence = 0;
 578                 e->event.tv_sec = now.tv_sec;
 579                 e->event.tv_usec = now.tv_usec;
 580
 581                 list_move_tail(&e->base.link, &e->base.file_priv->event_list);
 582                 wake_up_interruptible(&e->base.file_priv->event_wait);
 583         }
 584
 585         if (is_checked) {
 586                 drm_vblank_put(drm_dev, crtc);
 587
 588                 /*
 589                  * don't off vblank if vblank_disable_allowed is 1,
 590                  * because vblank would be off by timer handler.
 591                  */
 592                 if (!drm_dev->vblank_disable_allowed)
 593                         drm_vblank_off(drm_dev, crtc);
 594         }
 595
 596         spin_unlock_irqrestore(&drm_dev->event_lock, flags);
 597 }
 598
 599 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
 600 {
 601         struct fimd_context *ctx = (struct fimd_context *)dev_id;
 602         struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
 603         struct drm_device *drm_dev = subdrv->drm_dev;
 604         struct exynos_drm_manager *manager = &subdrv->manager;
 605         u32 val;
 606
 607         val = readl(ctx->regs + VIDINTCON1);
 608
 609         if (val & VIDINTCON1_INT_FRAME)
 610                 /* VSYNC interrupt */
 611                 writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1);
 612
 613         /* check the crtc is detached already from encoder */
 614         if (manager->pipe < 0)
 615                 goto out;
 616
 617         drm_handle_vblank(drm_dev, manager->pipe);
 618         fimd_finish_pageflip(drm_dev, manager->pipe);
 619
 620 out:
 621         return IRQ_HANDLED;
 622 }
 623
 624 static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
 625 {
 626         DRM_DEBUG_KMS("%s\n", __FILE__);
 627
 628         /*
 629          * enable drm irq mode.
 630          * - with irq_enabled = 1, we can use the vblank feature.
 631          *
 632          * P.S. note that we wouldn't use drm irq handler but
 633          *      just specific driver own one instead because
 634          *      drm framework supports only one irq handler.
 635          */
 636         drm_dev->irq_enabled = 1;
 637
 638         /*
 639          * with vblank_disable_allowed = 1, vblank interrupt will be disabled
 640          * by drm timer once a current process gives up ownership of
 641          * vblank event.(after drm_vblank_put function is called)
 642          */
 643         drm_dev->vblank_disable_allowed = 1;
 644
 645         return 0;
 646 }
 647
 648 static void fimd_subdrv_remove(struct drm_device *drm_dev)
 649 {
 650         DRM_DEBUG_KMS("%s\n", __FILE__);
 651
 652         /* TODO. */
 653 }
 654
 655 static int fimd_calc_clkdiv(struct fimd_context *ctx,
 656                             struct fb_videomode *timing)
 657 {
 658         unsigned long clk = clk_get_rate(ctx->lcd_clk);
 659         u32 retrace;
 660         u32 clkdiv;
 661         u32 best_framerate = 0;
 662         u32 framerate;
 663
 664         DRM_DEBUG_KMS("%s\n", __FILE__);
 665
 666         retrace = timing->left_margin + timing->hsync_len +
 667                                 timing->right_margin + timing->xres;
 668         retrace *= timing->upper_margin + timing->vsync_len +
 669                                 timing->lower_margin + timing->yres;
 670
 671         /* default framerate is 60Hz */
 672         if (!timing->refresh)
 673                 timing->refresh = 60;
 674
 675         clk /= retrace;
 676
 677         for (clkdiv = 1; clkdiv < 0x100; clkdiv++) {
 678                 int tmp;
 679
 680                 /* get best framerate */
 681                 framerate = clk / clkdiv;
 682                 tmp = timing->refresh - framerate;
 683                 if (tmp < 0) {
 684                         best_framerate = framerate;
 685                         continue;
 686                 } else {
 687                         if (!best_framerate)
 688                                 best_framerate = framerate;
 689                         else if (tmp < (best_framerate - framerate))
 690                                 best_framerate = framerate;
 691                         break;
 692                 }
 693         }
 694
 695         return clkdiv;
 696 }
 697
 698 static void fimd_clear_win(struct fimd_context *ctx, int win)
 699 {
 700         u32 val;
 701
 702         DRM_DEBUG_KMS("%s\n", __FILE__);
 703
 704         writel(0, ctx->regs + WINCON(win));
 705         writel(0, ctx->regs + VIDOSD_A(win));
 706         writel(0, ctx->regs + VIDOSD_B(win));
 707         writel(0, ctx->regs + VIDOSD_C(win));
 708
 709         if (win == 1 || win == 2)
 710                 writel(0, ctx->regs + VIDOSD_D(win));
 711
 712         val = readl(ctx->regs + SHADOWCON);
 713         val &= ~SHADOWCON_WINx_PROTECT(win);
 714         writel(val, ctx->regs + SHADOWCON);
 715 }
 716
 717 static int __devinit fimd_probe(struct platform_device *pdev)
 718 {
 719         struct device *dev = &pdev->dev;
 720         struct fimd_context *ctx;
 721         struct exynos_drm_subdrv *subdrv;
 722         struct exynos_drm_fimd_pdata *pdata;
 723         struct fb_videomode *timing;
 724         struct resource *res;
 725         int win;
 726         int ret = -EINVAL;
 727
 728         DRM_DEBUG_KMS("%s\n", __FILE__);
 729
 730         pdata = pdev->dev.platform_data;
 731         if (!pdata) {
 732                 dev_err(dev, "no platform data specified\n");
 733                 return -EINVAL;
 734         }
 735
 736         timing = &pdata->timing;
 737         if (!timing) {
 738                 dev_err(dev, "timing is null.\n");
 739                 return -EINVAL;
 740         }
 741
 742         ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
 743         if (!ctx)
 744                 return -ENOMEM;
 745
 746         ctx->bus_clk = clk_get(dev, "fimd");
 747         if (IS_ERR(ctx->bus_clk)) {
 748                 dev_err(dev, "failed to get bus clock\n");
 749                 ret = PTR_ERR(ctx->bus_clk);
 750                 goto err_clk_get;
 751         }
 752
 753         clk_enable(ctx->bus_clk);
 754
 755         ctx->lcd_clk = clk_get(dev, "sclk_fimd");
 756         if (IS_ERR(ctx->lcd_clk)) {
 757                 dev_err(dev, "failed to get lcd clock\n");
 758                 ret = PTR_ERR(ctx->lcd_clk);
 759                 goto err_bus_clk;
 760         }
 761
 762         clk_enable(ctx->lcd_clk);
 763
 764         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 765         if (!res) {
 766                 dev_err(dev, "failed to find registers\n");
 767                 ret = -ENOENT;
 768                 goto err_clk;
 769         }
 770
 771         ctx->regs_res = request_mem_region(res->start, resource_size(res),
 772                                            dev_name(dev));
 773         if (!ctx->regs_res) {
 774                 dev_err(dev, "failed to claim register region\n");
 775                 ret = -ENOENT;
 776                 goto err_clk;
 777         }
 778
 779         ctx->regs = ioremap(res->start, resource_size(res));
 780         if (!ctx->regs) {
 781                 dev_err(dev, "failed to map registers\n");
 782                 ret = -ENXIO;
 783                 goto err_req_region_io;
 784         }
 785
 786         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 787         if (!res) {
 788                 dev_err(dev, "irq request failed.\n");
 789                 goto err_req_region_irq;
 790         }
 791
 792         ctx->irq = res->start;
 793
 794         ret = request_irq(ctx->irq, fimd_irq_handler, 0, "drm_fimd", ctx);
 795         if (ret < 0) {
 796                 dev_err(dev, "irq request failed.\n");
 797                 goto err_req_irq;
 798         }
 799
 800         pm_runtime_set_active(dev);
 801         pm_runtime_enable(dev);
 802         pm_runtime_get_sync(dev);
 803
 804         for (win = 0; win < WINDOWS_NR; win++)
 805                 fimd_clear_win(ctx, win);
 806
 807         ctx->clkdiv = fimd_calc_clkdiv(ctx, timing);
 808         ctx->vidcon0 = pdata->vidcon0;
 809         ctx->vidcon1 = pdata->vidcon1;
 810         ctx->default_win = pdata->default_win;
 811         ctx->timing = timing;
 812
 813         timing->pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
 814
 815         DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
 816                         timing->pixclock, ctx->clkdiv);
 817
 818         subdrv = &ctx->subdrv;
 819
 820         subdrv->probe = fimd_subdrv_probe;
 821         subdrv->remove = fimd_subdrv_remove;
 822         subdrv->manager.pipe = -1;
 823         subdrv->manager.ops = &fimd_manager_ops;
 824         subdrv->manager.overlay_ops = &fimd_overlay_ops;
 825         subdrv->manager.display_ops = &fimd_display_ops;
 826         subdrv->manager.dev = dev;
 827
 828         platform_set_drvdata(pdev, ctx);
 829         exynos_drm_subdrv_register(subdrv);
 830
 831         return 0;
 832
 833 err_req_irq:
 834 err_req_region_irq:
 835         iounmap(ctx->regs);
 836
 837 err_req_region_io:
 838         release_resource(ctx->regs_res);
 839         kfree(ctx->regs_res);
 840
 841 err_clk:
 842         clk_disable(ctx->lcd_clk);
 843         clk_put(ctx->lcd_clk);
 844
 845 err_bus_clk:
 846         clk_disable(ctx->bus_clk);
 847         clk_put(ctx->bus_clk);
 848
 849 err_clk_get:
 850         kfree(ctx);
 851         return ret;
 852 }
 853
 854 static int __devexit fimd_remove(struct platform_device *pdev)
 855 {
 856         struct device *dev = &pdev->dev;
 857         struct fimd_context *ctx = platform_get_drvdata(pdev);
 858
 859         DRM_DEBUG_KMS("%s\n", __FILE__);
 860
 861         exynos_drm_subdrv_unregister(&ctx->subdrv);
 862
 863         if (ctx->suspended)
 864                 goto out;
 865
 866         clk_disable(ctx->lcd_clk);
 867         clk_disable(ctx->bus_clk);
 868
 869         pm_runtime_set_suspended(dev);
 870         pm_runtime_put_sync(dev);
 871
 872 out:
 873         pm_runtime_disable(dev);
 874
 875         clk_put(ctx->lcd_clk);
 876         clk_put(ctx->bus_clk);
 877
 878         iounmap(ctx->regs);
 879         release_resource(ctx->regs_res);
 880         kfree(ctx->regs_res);
 881         free_irq(ctx->irq, ctx);
 882
 883         kfree(ctx);
 884
 885         return 0;
 886 }
 887
 888 #ifdef CONFIG_PM_RUNTIME
 889 static int fimd_runtime_suspend(struct device *dev)
 890 {
 891         struct fimd_context *ctx = get_fimd_context(dev);
 892
 893         DRM_DEBUG_KMS("%s\n", __FILE__);
 894
 895         clk_disable(ctx->lcd_clk);
 896         clk_disable(ctx->bus_clk);
 897
 898         ctx->suspended = true;
 899         return 0;
 900 }
 901
 902 static int fimd_runtime_resume(struct device *dev)
 903 {
 904         struct fimd_context *ctx = get_fimd_context(dev);
 905         int ret;
 906
 907         DRM_DEBUG_KMS("%s\n", __FILE__);
 908
 909         ret = clk_enable(ctx->bus_clk);
 910         if (ret < 0)
 911                 return ret;
 912
 913         ret = clk_enable(ctx->lcd_clk);
 914         if  (ret < 0) {
 915                 clk_disable(ctx->bus_clk);
 916                 return ret;
 917         }
 918
 919         ctx->suspended = false;
 920         return 0;
 921 }
 922 #endif
 923
 924 static const struct dev_pm_ops fimd_pm_ops = {
 925         SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL)
 926 };
 927
 928 static struct platform_driver fimd_driver = {
 929         .probe          = fimd_probe,
 930         .remove         = __devexit_p(fimd_remove),
 931         .driver         = {
 932                 .name   = "exynos4-fb",
 933                 .owner  = THIS_MODULE,
 934                 .pm     = &fimd_pm_ops,
 935         },
 936 };
 937
 938 static int __init fimd_init(void)
 939 {
 940         return platform_driver_register(&fimd_driver);
 941 }
 942
 943 static void __exit fimd_exit(void)
 944 {
 945         platform_driver_unregister(&fimd_driver);
 946 }
 947
 948 module_init(fimd_init);
 949 module_exit(fimd_exit);
 950
 951 MODULE_AUTHOR("Joonyoung Shim <jy0922.shim@samsung.com>");
 952 MODULE_AUTHOR("Inki Dae <inki.dae@samsung.com>");
 953 MODULE_DESCRIPTION("Samsung DRM FIMD Driver");
 954 MODULE_LICENSE("GPL");