3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/component.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/samsung_fimd.h>
29 #include <drm/exynos_drm.h>
31 #include "exynos_drm_drv.h"
32 #include "exynos_drm_fbdev.h"
33 #include "exynos_drm_crtc.h"
34 #include "exynos_drm_iommu.h"
37 * FIMD stands for Fully Interactive Mobile Display and
38 * as a display controller, it transfers contents drawn on memory
39 * to a LCD Panel through Display Interfaces such as RGB or
43 #define FIMD_DEFAULT_FRAMERATE 60
44 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
46 /* position control register for hardware window 0, 2 ~ 4.*/
47 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
48 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
50 * size control register for hardware windows 0 and alpha control register
51 * for hardware windows 1 ~ 4
53 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
54 /* size control register for hardware windows 1 ~ 2. */
55 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
57 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
58 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
59 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
61 /* color key control register for hardware window 1 ~ 4. */
62 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
63 /* color key value register for hardware window 1 ~ 4. */
64 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
66 /* I80 / RGB trigger control register */
68 #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
69 #define SWTRGCMD_I80_RGB_ENABLE (1 << 1)
71 /* display mode change control register except exynos4 */
72 #define VIDOUT_CON 0x000
73 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
75 /* I80 interface control for main LDI register */
76 #define I80IFCONFAx(x) (0x1B0 + (x) * 4)
77 #define I80IFCONFBx(x) (0x1B8 + (x) * 4)
78 #define LCD_CS_SETUP(x) ((x) << 16)
79 #define LCD_WR_SETUP(x) ((x) << 12)
80 #define LCD_WR_ACTIVE(x) ((x) << 8)
81 #define LCD_WR_HOLD(x) ((x) << 4)
82 #define I80IFEN_ENABLE (1 << 0)
84 /* FIMD has totally five hardware windows. */
87 struct fimd_driver_data {
88 unsigned int timing_base;
89 unsigned int lcdblk_offset;
90 unsigned int lcdblk_vt_shift;
91 unsigned int lcdblk_bypass_shift;
93 unsigned int has_shadowcon:1;
94 unsigned int has_clksel:1;
95 unsigned int has_limited_fmt:1;
96 unsigned int has_vidoutcon:1;
97 unsigned int has_vtsel:1;
100 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
103 .has_limited_fmt = 1,
106 static struct fimd_driver_data exynos3_fimd_driver_data = {
107 .timing_base = 0x20000,
108 .lcdblk_offset = 0x210,
109 .lcdblk_bypass_shift = 1,
114 static struct fimd_driver_data exynos4_fimd_driver_data = {
116 .lcdblk_offset = 0x210,
117 .lcdblk_vt_shift = 10,
118 .lcdblk_bypass_shift = 1,
123 static struct fimd_driver_data exynos4415_fimd_driver_data = {
124 .timing_base = 0x20000,
125 .lcdblk_offset = 0x210,
126 .lcdblk_vt_shift = 10,
127 .lcdblk_bypass_shift = 1,
133 static struct fimd_driver_data exynos5_fimd_driver_data = {
134 .timing_base = 0x20000,
135 .lcdblk_offset = 0x214,
136 .lcdblk_vt_shift = 24,
137 .lcdblk_bypass_shift = 15,
143 struct fimd_win_data {
144 unsigned int offset_x;
145 unsigned int offset_y;
146 unsigned int ovl_width;
147 unsigned int ovl_height;
148 unsigned int fb_width;
149 unsigned int fb_height;
151 unsigned int pixel_format;
153 unsigned int buf_offsize;
154 unsigned int line_size; /* bytes */
159 struct fimd_context {
160 struct exynos_drm_manager manager;
162 struct drm_device *drm_dev;
166 struct regmap *sysreg;
167 struct drm_display_mode mode;
168 struct fimd_win_data win_data[WINDOWS_NR];
169 unsigned int default_win;
170 unsigned long irq_flags;
178 wait_queue_head_t wait_vsync_queue;
179 atomic_t wait_vsync_event;
180 atomic_t win_updated;
183 struct exynos_drm_panel_info panel;
184 struct fimd_driver_data *driver_data;
185 struct exynos_drm_display *display;
188 static inline struct fimd_context *mgr_to_fimd(struct exynos_drm_manager *mgr)
190 return container_of(mgr, struct fimd_context, manager);
193 static const struct of_device_id fimd_driver_dt_match[] = {
194 { .compatible = "samsung,s3c6400-fimd",
195 .data = &s3c64xx_fimd_driver_data },
196 { .compatible = "samsung,exynos3250-fimd",
197 .data = &exynos3_fimd_driver_data },
198 { .compatible = "samsung,exynos4210-fimd",
199 .data = &exynos4_fimd_driver_data },
200 { .compatible = "samsung,exynos4415-fimd",
201 .data = &exynos4415_fimd_driver_data },
202 { .compatible = "samsung,exynos5250-fimd",
203 .data = &exynos5_fimd_driver_data },
206 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
208 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
209 struct platform_device *pdev)
211 const struct of_device_id *of_id =
212 of_match_device(fimd_driver_dt_match, &pdev->dev);
214 return (struct fimd_driver_data *)of_id->data;
217 static void fimd_wait_for_vblank(struct exynos_drm_manager *mgr)
219 struct fimd_context *ctx = mgr_to_fimd(mgr);
224 atomic_set(&ctx->wait_vsync_event, 1);
227 * wait for FIMD to signal VSYNC interrupt or return after
228 * timeout which is set to 50ms (refresh rate of 20).
230 if (!wait_event_timeout(ctx->wait_vsync_queue,
231 !atomic_read(&ctx->wait_vsync_event),
233 DRM_DEBUG_KMS("vblank wait timed out.\n");
236 static void fimd_enable_video_output(struct fimd_context *ctx, int win,
239 u32 val = readl(ctx->regs + WINCON(win));
242 val |= WINCONx_ENWIN;
244 val &= ~WINCONx_ENWIN;
246 writel(val, ctx->regs + WINCON(win));
249 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, int win,
252 u32 val = readl(ctx->regs + SHADOWCON);
255 val |= SHADOWCON_CHx_ENABLE(win);
257 val &= ~SHADOWCON_CHx_ENABLE(win);
259 writel(val, ctx->regs + SHADOWCON);
262 static void fimd_clear_channel(struct exynos_drm_manager *mgr)
264 struct fimd_context *ctx = mgr_to_fimd(mgr);
265 int win, ch_enabled = 0;
267 DRM_DEBUG_KMS("%s\n", __FILE__);
269 /* Check if any channel is enabled. */
270 for (win = 0; win < WINDOWS_NR; win++) {
271 u32 val = readl(ctx->regs + WINCON(win));
273 if (val & WINCONx_ENWIN) {
274 fimd_enable_video_output(ctx, win, false);
276 if (ctx->driver_data->has_shadowcon)
277 fimd_enable_shadow_channel_path(ctx, win,
284 /* Wait for vsync, as disable channel takes effect at next vsync */
286 unsigned int state = ctx->suspended;
289 fimd_wait_for_vblank(mgr);
290 ctx->suspended = state;
294 static int fimd_mgr_initialize(struct exynos_drm_manager *mgr,
295 struct drm_device *drm_dev)
297 struct fimd_context *ctx = mgr_to_fimd(mgr);
298 struct exynos_drm_private *priv;
299 priv = drm_dev->dev_private;
301 mgr->drm_dev = ctx->drm_dev = drm_dev;
302 mgr->pipe = ctx->pipe = priv->pipe++;
304 /* attach this sub driver to iommu mapping if supported. */
305 if (is_drm_iommu_supported(ctx->drm_dev)) {
307 * If any channel is already active, iommu will throw
308 * a PAGE FAULT when enabled. So clear any channel if enabled.
310 fimd_clear_channel(mgr);
311 drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
317 static void fimd_mgr_remove(struct exynos_drm_manager *mgr)
319 struct fimd_context *ctx = mgr_to_fimd(mgr);
321 /* detach this sub driver from iommu mapping if supported. */
322 if (is_drm_iommu_supported(ctx->drm_dev))
323 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
326 static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
327 const struct drm_display_mode *mode)
329 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
334 * The frame done interrupt should be occurred prior to the
340 /* Find the clock divider value that gets us closest to ideal_clk */
341 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
343 return (clkdiv < 0x100) ? clkdiv : 0xff;
346 static bool fimd_mode_fixup(struct exynos_drm_manager *mgr,
347 const struct drm_display_mode *mode,
348 struct drm_display_mode *adjusted_mode)
350 if (adjusted_mode->vrefresh == 0)
351 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE;
356 static void fimd_mode_set(struct exynos_drm_manager *mgr,
357 const struct drm_display_mode *in_mode)
359 struct fimd_context *ctx = mgr_to_fimd(mgr);
361 drm_mode_copy(&ctx->mode, in_mode);
364 static void fimd_commit(struct exynos_drm_manager *mgr)
366 struct fimd_context *ctx = mgr_to_fimd(mgr);
367 struct drm_display_mode *mode = &ctx->mode;
368 struct fimd_driver_data *driver_data = ctx->driver_data;
369 void *timing_base = ctx->regs + driver_data->timing_base;
375 /* nothing to do if we haven't set the mode yet */
376 if (mode->htotal == 0 || mode->vtotal == 0)
380 val = ctx->i80ifcon | I80IFEN_ENABLE;
381 writel(val, timing_base + I80IFCONFAx(0));
383 /* disable auto frame rate */
384 writel(0, timing_base + I80IFCONFBx(0));
386 /* set video type selection to I80 interface */
387 if (driver_data->has_vtsel && ctx->sysreg &&
388 regmap_update_bits(ctx->sysreg,
389 driver_data->lcdblk_offset,
390 0x3 << driver_data->lcdblk_vt_shift,
391 0x1 << driver_data->lcdblk_vt_shift)) {
392 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
396 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
399 /* setup polarity values */
400 vidcon1 = ctx->vidcon1;
401 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
402 vidcon1 |= VIDCON1_INV_VSYNC;
403 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
404 vidcon1 |= VIDCON1_INV_HSYNC;
405 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
407 /* setup vertical timing values. */
408 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
409 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
410 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
412 val = VIDTCON0_VBPD(vbpd - 1) |
413 VIDTCON0_VFPD(vfpd - 1) |
414 VIDTCON0_VSPW(vsync_len - 1);
415 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
417 /* setup horizontal timing values. */
418 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
419 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
420 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
422 val = VIDTCON1_HBPD(hbpd - 1) |
423 VIDTCON1_HFPD(hfpd - 1) |
424 VIDTCON1_HSPW(hsync_len - 1);
425 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
428 if (driver_data->has_vidoutcon)
429 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
431 /* set bypass selection */
432 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
433 driver_data->lcdblk_offset,
434 0x1 << driver_data->lcdblk_bypass_shift,
435 0x1 << driver_data->lcdblk_bypass_shift)) {
436 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
440 /* setup horizontal and vertical display size. */
441 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
442 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
443 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
444 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
445 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
448 * fields of register with prefix '_F' would be updated
449 * at vsync(same as dma start)
452 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
454 if (ctx->driver_data->has_clksel)
455 val |= VIDCON0_CLKSEL_LCD;
457 clkdiv = fimd_calc_clkdiv(ctx, mode);
459 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
461 writel(val, ctx->regs + VIDCON0);
464 static int fimd_enable_vblank(struct exynos_drm_manager *mgr)
466 struct fimd_context *ctx = mgr_to_fimd(mgr);
472 if (!test_and_set_bit(0, &ctx->irq_flags)) {
473 val = readl(ctx->regs + VIDINTCON0);
475 val |= VIDINTCON0_INT_ENABLE;
478 val |= VIDINTCON0_INT_I80IFDONE;
479 val |= VIDINTCON0_INT_SYSMAINCON;
480 val &= ~VIDINTCON0_INT_SYSSUBCON;
482 val |= VIDINTCON0_INT_FRAME;
484 val &= ~VIDINTCON0_FRAMESEL0_MASK;
485 val |= VIDINTCON0_FRAMESEL0_VSYNC;
486 val &= ~VIDINTCON0_FRAMESEL1_MASK;
487 val |= VIDINTCON0_FRAMESEL1_NONE;
490 writel(val, ctx->regs + VIDINTCON0);
496 static void fimd_disable_vblank(struct exynos_drm_manager *mgr)
498 struct fimd_context *ctx = mgr_to_fimd(mgr);
504 if (test_and_clear_bit(0, &ctx->irq_flags)) {
505 val = readl(ctx->regs + VIDINTCON0);
507 val &= ~VIDINTCON0_INT_ENABLE;
510 val &= ~VIDINTCON0_INT_I80IFDONE;
511 val &= ~VIDINTCON0_INT_SYSMAINCON;
512 val &= ~VIDINTCON0_INT_SYSSUBCON;
514 val &= ~VIDINTCON0_INT_FRAME;
516 writel(val, ctx->regs + VIDINTCON0);
520 static void fimd_win_mode_set(struct exynos_drm_manager *mgr,
521 struct exynos_drm_overlay *overlay)
523 struct fimd_context *ctx = mgr_to_fimd(mgr);
524 struct fimd_win_data *win_data;
526 unsigned long offset;
529 DRM_ERROR("overlay is NULL\n");
534 if (win == DEFAULT_ZPOS)
535 win = ctx->default_win;
537 if (win < 0 || win >= WINDOWS_NR)
540 offset = overlay->fb_x * (overlay->bpp >> 3);
541 offset += overlay->fb_y * overlay->pitch;
543 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
545 win_data = &ctx->win_data[win];
547 win_data->offset_x = overlay->crtc_x;
548 win_data->offset_y = overlay->crtc_y;
549 win_data->ovl_width = overlay->crtc_width;
550 win_data->ovl_height = overlay->crtc_height;
551 win_data->fb_width = overlay->fb_width;
552 win_data->fb_height = overlay->fb_height;
553 win_data->dma_addr = overlay->dma_addr[0] + offset;
554 win_data->bpp = overlay->bpp;
555 win_data->pixel_format = overlay->pixel_format;
556 win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
558 win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
560 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
561 win_data->offset_x, win_data->offset_y);
562 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
563 win_data->ovl_width, win_data->ovl_height);
564 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
565 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
566 overlay->fb_width, overlay->crtc_width);
569 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win)
571 struct fimd_win_data *win_data = &ctx->win_data[win];
577 * In case of s3c64xx, window 0 doesn't support alpha channel.
578 * So the request format is ARGB8888 then change it to XRGB8888.
580 if (ctx->driver_data->has_limited_fmt && !win) {
581 if (win_data->pixel_format == DRM_FORMAT_ARGB8888)
582 win_data->pixel_format = DRM_FORMAT_XRGB8888;
585 switch (win_data->pixel_format) {
587 val |= WINCON0_BPPMODE_8BPP_PALETTE;
588 val |= WINCONx_BURSTLEN_8WORD;
589 val |= WINCONx_BYTSWP;
591 case DRM_FORMAT_XRGB1555:
592 val |= WINCON0_BPPMODE_16BPP_1555;
593 val |= WINCONx_HAWSWP;
594 val |= WINCONx_BURSTLEN_16WORD;
596 case DRM_FORMAT_RGB565:
597 val |= WINCON0_BPPMODE_16BPP_565;
598 val |= WINCONx_HAWSWP;
599 val |= WINCONx_BURSTLEN_16WORD;
601 case DRM_FORMAT_XRGB8888:
602 val |= WINCON0_BPPMODE_24BPP_888;
604 val |= WINCONx_BURSTLEN_16WORD;
606 case DRM_FORMAT_ARGB8888:
607 val |= WINCON1_BPPMODE_25BPP_A1888
608 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
610 val |= WINCONx_BURSTLEN_16WORD;
613 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
615 val |= WINCON0_BPPMODE_24BPP_888;
617 val |= WINCONx_BURSTLEN_16WORD;
621 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
624 * In case of exynos, setting dma-burst to 16Word causes permanent
625 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
626 * switching which is based on overlay size is not recommended as
627 * overlay size varies alot towards the end of the screen and rapid
628 * movement causes unstable DMA which results into iommu crash/tear.
631 if (win_data->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
632 val &= ~WINCONx_BURSTLEN_MASK;
633 val |= WINCONx_BURSTLEN_4WORD;
636 writel(val, ctx->regs + WINCON(win));
639 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
641 unsigned int keycon0 = 0, keycon1 = 0;
643 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
644 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
646 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
648 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
649 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
653 * shadow_protect_win() - disable updating values from shadow registers at vsync
655 * @win: window to protect registers for
656 * @protect: 1 to protect (disable updates)
658 static void fimd_shadow_protect_win(struct fimd_context *ctx,
659 int win, bool protect)
663 if (ctx->driver_data->has_shadowcon) {
665 bits = SHADOWCON_WINx_PROTECT(win);
668 bits = PRTCON_PROTECT;
671 val = readl(ctx->regs + reg);
676 writel(val, ctx->regs + reg);
679 static void fimd_win_commit(struct exynos_drm_manager *mgr, int zpos)
681 struct fimd_context *ctx = mgr_to_fimd(mgr);
682 struct fimd_win_data *win_data;
684 unsigned long val, alpha, size;
691 if (win == DEFAULT_ZPOS)
692 win = ctx->default_win;
694 if (win < 0 || win >= WINDOWS_NR)
697 win_data = &ctx->win_data[win];
699 /* If suspended, enable this on resume */
700 if (ctx->suspended) {
701 win_data->resume = true;
706 * SHADOWCON/PRTCON register is used for enabling timing.
708 * for example, once only width value of a register is set,
709 * if the dma is started then fimd hardware could malfunction so
710 * with protect window setting, the register fields with prefix '_F'
711 * wouldn't be updated at vsync also but updated once unprotect window
715 /* protect windows */
716 fimd_shadow_protect_win(ctx, win, true);
718 /* buffer start address */
719 val = (unsigned long)win_data->dma_addr;
720 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
722 /* buffer end address */
723 size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
724 val = (unsigned long)(win_data->dma_addr + size);
725 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
727 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
728 (unsigned long)win_data->dma_addr, val, size);
729 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
730 win_data->ovl_width, win_data->ovl_height);
733 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
734 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) |
735 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) |
736 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size);
737 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
740 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
741 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) |
742 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) |
743 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y);
744 writel(val, ctx->regs + VIDOSD_A(win));
746 last_x = win_data->offset_x + win_data->ovl_width;
749 last_y = win_data->offset_y + win_data->ovl_height;
753 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
754 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
756 writel(val, ctx->regs + VIDOSD_B(win));
758 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
759 win_data->offset_x, win_data->offset_y, last_x, last_y);
761 /* hardware window 0 doesn't support alpha channel. */
764 alpha = VIDISD14C_ALPHA1_R(0xf) |
765 VIDISD14C_ALPHA1_G(0xf) |
766 VIDISD14C_ALPHA1_B(0xf);
768 writel(alpha, ctx->regs + VIDOSD_C(win));
772 if (win != 3 && win != 4) {
773 u32 offset = VIDOSD_D(win);
775 offset = VIDOSD_C(win);
776 val = win_data->ovl_width * win_data->ovl_height;
777 writel(val, ctx->regs + offset);
779 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
782 fimd_win_set_pixfmt(ctx, win);
784 /* hardware window 0 doesn't support color key. */
786 fimd_win_set_colkey(ctx, win);
788 fimd_enable_video_output(ctx, win, true);
790 if (ctx->driver_data->has_shadowcon)
791 fimd_enable_shadow_channel_path(ctx, win, true);
793 /* Enable DMA channel and unprotect windows */
794 fimd_shadow_protect_win(ctx, win, false);
796 win_data->enabled = true;
799 atomic_set(&ctx->win_updated, 1);
802 static void fimd_win_disable(struct exynos_drm_manager *mgr, int zpos)
804 struct fimd_context *ctx = mgr_to_fimd(mgr);
805 struct fimd_win_data *win_data;
808 if (win == DEFAULT_ZPOS)
809 win = ctx->default_win;
811 if (win < 0 || win >= WINDOWS_NR)
814 win_data = &ctx->win_data[win];
816 if (ctx->suspended) {
817 /* do not resume this window*/
818 win_data->resume = false;
822 /* protect windows */
823 fimd_shadow_protect_win(ctx, win, true);
825 fimd_enable_video_output(ctx, win, false);
827 if (ctx->driver_data->has_shadowcon)
828 fimd_enable_shadow_channel_path(ctx, win, false);
830 /* unprotect windows */
831 fimd_shadow_protect_win(ctx, win, false);
833 win_data->enabled = false;
836 static void fimd_window_suspend(struct exynos_drm_manager *mgr)
838 struct fimd_context *ctx = mgr_to_fimd(mgr);
839 struct fimd_win_data *win_data;
842 for (i = 0; i < WINDOWS_NR; i++) {
843 win_data = &ctx->win_data[i];
844 win_data->resume = win_data->enabled;
845 if (win_data->enabled)
846 fimd_win_disable(mgr, i);
850 static void fimd_window_resume(struct exynos_drm_manager *mgr)
852 struct fimd_context *ctx = mgr_to_fimd(mgr);
853 struct fimd_win_data *win_data;
856 for (i = 0; i < WINDOWS_NR; i++) {
857 win_data = &ctx->win_data[i];
858 win_data->enabled = win_data->resume;
859 win_data->resume = false;
863 static void fimd_apply(struct exynos_drm_manager *mgr)
865 struct fimd_context *ctx = mgr_to_fimd(mgr);
866 struct fimd_win_data *win_data;
869 for (i = 0; i < WINDOWS_NR; i++) {
870 win_data = &ctx->win_data[i];
871 if (win_data->enabled)
872 fimd_win_commit(mgr, i);
874 fimd_win_disable(mgr, i);
880 static int fimd_poweron(struct exynos_drm_manager *mgr)
882 struct fimd_context *ctx = mgr_to_fimd(mgr);
888 ctx->suspended = false;
890 pm_runtime_get_sync(ctx->dev);
892 ret = clk_prepare_enable(ctx->bus_clk);
894 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
898 ret = clk_prepare_enable(ctx->lcd_clk);
900 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
904 /* if vblank was enabled status, enable it again. */
905 if (test_and_clear_bit(0, &ctx->irq_flags)) {
906 ret = fimd_enable_vblank(mgr);
908 DRM_ERROR("Failed to re-enable vblank [%d]\n", ret);
909 goto enable_vblank_err;
913 fimd_window_resume(mgr);
920 clk_disable_unprepare(ctx->lcd_clk);
922 clk_disable_unprepare(ctx->bus_clk);
924 ctx->suspended = true;
928 static int fimd_poweroff(struct exynos_drm_manager *mgr)
930 struct fimd_context *ctx = mgr_to_fimd(mgr);
936 * We need to make sure that all windows are disabled before we
937 * suspend that connector. Otherwise we might try to scan from
938 * a destroyed buffer later.
940 fimd_window_suspend(mgr);
942 clk_disable_unprepare(ctx->lcd_clk);
943 clk_disable_unprepare(ctx->bus_clk);
945 pm_runtime_put_sync(ctx->dev);
947 ctx->suspended = true;
951 static void fimd_dpms(struct exynos_drm_manager *mgr, int mode)
953 DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
956 case DRM_MODE_DPMS_ON:
959 case DRM_MODE_DPMS_STANDBY:
960 case DRM_MODE_DPMS_SUSPEND:
961 case DRM_MODE_DPMS_OFF:
965 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
970 static void fimd_trigger(struct device *dev)
972 struct fimd_context *ctx = dev_get_drvdata(dev);
973 struct fimd_driver_data *driver_data = ctx->driver_data;
974 void *timing_base = ctx->regs + driver_data->timing_base;
978 * Skips triggering if in triggering state, because multiple triggering
979 * requests can cause panel reset.
981 if (atomic_read(&ctx->triggering))
984 /* Enters triggering mode */
985 atomic_set(&ctx->triggering, 1);
987 reg = readl(timing_base + TRIGCON);
988 reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
989 writel(reg, timing_base + TRIGCON);
992 * Exits triggering mode if vblank is not enabled yet, because when the
993 * VIDINTCON0 register is not set, it can not exit from triggering mode.
995 if (!test_bit(0, &ctx->irq_flags))
996 atomic_set(&ctx->triggering, 0);
999 static void fimd_te_handler(struct exynos_drm_manager *mgr)
1001 struct fimd_context *ctx = mgr_to_fimd(mgr);
1003 /* Checks the crtc is detached already from encoder */
1004 if (ctx->pipe < 0 || !ctx->drm_dev)
1008 * If there is a page flip request, triggers and handles the page flip
1009 * event so that current fb can be updated into panel GRAM.
1011 if (atomic_add_unless(&ctx->win_updated, -1, 0))
1012 fimd_trigger(ctx->dev);
1014 /* Wakes up vsync event queue */
1015 if (atomic_read(&ctx->wait_vsync_event)) {
1016 atomic_set(&ctx->wait_vsync_event, 0);
1017 wake_up(&ctx->wait_vsync_queue);
1020 if (test_bit(0, &ctx->irq_flags))
1021 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1024 static struct exynos_drm_manager_ops fimd_manager_ops = {
1026 .mode_fixup = fimd_mode_fixup,
1027 .mode_set = fimd_mode_set,
1028 .commit = fimd_commit,
1029 .enable_vblank = fimd_enable_vblank,
1030 .disable_vblank = fimd_disable_vblank,
1031 .wait_for_vblank = fimd_wait_for_vblank,
1032 .win_mode_set = fimd_win_mode_set,
1033 .win_commit = fimd_win_commit,
1034 .win_disable = fimd_win_disable,
1035 .te_handler = fimd_te_handler,
1038 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
1040 struct fimd_context *ctx = (struct fimd_context *)dev_id;
1043 val = readl(ctx->regs + VIDINTCON1);
1045 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
1046 if (val & clear_bit)
1047 writel(clear_bit, ctx->regs + VIDINTCON1);
1049 /* check the crtc is detached already from encoder */
1050 if (ctx->pipe < 0 || !ctx->drm_dev)
1054 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1056 /* Exits triggering mode */
1057 atomic_set(&ctx->triggering, 0);
1059 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1060 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1062 /* set wait vsync event to zero and wake up queue. */
1063 if (atomic_read(&ctx->wait_vsync_event)) {
1064 atomic_set(&ctx->wait_vsync_event, 0);
1065 wake_up(&ctx->wait_vsync_queue);
1073 static int fimd_bind(struct device *dev, struct device *master, void *data)
1075 struct fimd_context *ctx = dev_get_drvdata(dev);
1076 struct drm_device *drm_dev = data;
1078 fimd_mgr_initialize(&ctx->manager, drm_dev);
1079 exynos_drm_crtc_create(&ctx->manager);
1081 exynos_drm_create_enc_conn(drm_dev, ctx->display);
1087 static void fimd_unbind(struct device *dev, struct device *master,
1090 struct fimd_context *ctx = dev_get_drvdata(dev);
1092 fimd_dpms(&ctx->manager, DRM_MODE_DPMS_OFF);
1095 exynos_dpi_remove(ctx->display);
1097 fimd_mgr_remove(&ctx->manager);
1100 static const struct component_ops fimd_component_ops = {
1102 .unbind = fimd_unbind,
1105 static int fimd_probe(struct platform_device *pdev)
1107 struct device *dev = &pdev->dev;
1108 struct fimd_context *ctx;
1109 struct device_node *i80_if_timings;
1110 struct resource *res;
1116 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1120 ctx->manager.type = EXYNOS_DISPLAY_TYPE_LCD;
1121 ctx->manager.ops = &fimd_manager_ops;
1123 ret = exynos_drm_component_add(dev, EXYNOS_DEVICE_TYPE_CRTC,
1129 ctx->suspended = true;
1130 ctx->driver_data = drm_fimd_get_driver_data(pdev);
1132 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1133 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1134 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1135 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1137 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1138 if (i80_if_timings) {
1143 if (ctx->driver_data->has_vidoutcon)
1144 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1146 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1148 * The user manual describes that this "DSI_EN" bit is required
1149 * to enable I80 24-bit data interface.
1151 ctx->vidcon0 |= VIDCON0_DSI_EN;
1153 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1155 ctx->i80ifcon = LCD_CS_SETUP(val);
1156 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1158 ctx->i80ifcon |= LCD_WR_SETUP(val);
1159 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1161 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1162 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1164 ctx->i80ifcon |= LCD_WR_HOLD(val);
1166 of_node_put(i80_if_timings);
1168 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1170 if (IS_ERR(ctx->sysreg)) {
1171 dev_warn(dev, "failed to get system register.\n");
1175 ctx->bus_clk = devm_clk_get(dev, "fimd");
1176 if (IS_ERR(ctx->bus_clk)) {
1177 dev_err(dev, "failed to get bus clock\n");
1178 ret = PTR_ERR(ctx->bus_clk);
1179 goto err_del_component;
1182 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1183 if (IS_ERR(ctx->lcd_clk)) {
1184 dev_err(dev, "failed to get lcd clock\n");
1185 ret = PTR_ERR(ctx->lcd_clk);
1186 goto err_del_component;
1189 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1191 ctx->regs = devm_ioremap_resource(dev, res);
1192 if (IS_ERR(ctx->regs)) {
1193 ret = PTR_ERR(ctx->regs);
1194 goto err_del_component;
1197 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1198 ctx->i80_if ? "lcd_sys" : "vsync");
1200 dev_err(dev, "irq request failed.\n");
1202 goto err_del_component;
1205 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1206 0, "drm_fimd", ctx);
1208 dev_err(dev, "irq request failed.\n");
1209 goto err_del_component;
1212 init_waitqueue_head(&ctx->wait_vsync_queue);
1213 atomic_set(&ctx->wait_vsync_event, 0);
1215 platform_set_drvdata(pdev, ctx);
1217 ctx->display = exynos_dpi_probe(dev);
1218 if (IS_ERR(ctx->display)) {
1219 ret = PTR_ERR(ctx->display);
1220 goto err_del_component;
1223 pm_runtime_enable(dev);
1225 ret = component_add(dev, &fimd_component_ops);
1227 goto err_disable_pm_runtime;
1231 err_disable_pm_runtime:
1232 pm_runtime_disable(dev);
1235 exynos_drm_component_del(dev, EXYNOS_DEVICE_TYPE_CRTC);
1239 static int fimd_remove(struct platform_device *pdev)
1241 pm_runtime_disable(&pdev->dev);
1243 component_del(&pdev->dev, &fimd_component_ops);
1244 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1249 struct platform_driver fimd_driver = {
1250 .probe = fimd_probe,
1251 .remove = fimd_remove,
1253 .name = "exynos4-fb",
1254 .owner = THIS_MODULE,
1255 .of_match_table = fimd_driver_dt_match,