drivers/gpu/drm/exynos/exynos_drm_fimd.c

   1 /* exynos_drm_fimd.c
   2  *
   3  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Inki Dae <inki.dae@samsung.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14 #include <drm/drmP.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/clk.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/component.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/regmap.h>
  25
  26 #include <video/of_display_timing.h>
  27 #include <video/of_videomode.h>
  28 #include <video/samsung_fimd.h>
  29 #include <drm/exynos_drm.h>
  30
  31 #include "exynos_drm_drv.h"
  32 #include "exynos_drm_fbdev.h"
  33 #include "exynos_drm_crtc.h"
  34 #include "exynos_drm_iommu.h"
  35
  36 /*
  37  * FIMD stands for Fully Interactive Mobile Display and
  38  * as a display controller, it transfers contents drawn on memory
  39  * to a LCD Panel through Display Interfaces such as RGB or
  40  * CPU Interface.
  41  */
  42
  43 #define FIMD_DEFAULT_FRAMERATE 60
  44 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
  45
  46 /* position control register for hardware window 0, 2 ~ 4.*/
  47 #define VIDOSD_A(win)           (VIDOSD_BASE + 0x00 + (win) * 16)
  48 #define VIDOSD_B(win)           (VIDOSD_BASE + 0x04 + (win) * 16)
  49 /*
  50  * size control register for hardware windows 0 and alpha control register
  51  * for hardware windows 1 ~ 4
  52  */
  53 #define VIDOSD_C(win)           (VIDOSD_BASE + 0x08 + (win) * 16)
  54 /* size control register for hardware windows 1 ~ 2. */
  55 #define VIDOSD_D(win)           (VIDOSD_BASE + 0x0C + (win) * 16)
  56
  57 #define VIDWx_BUF_START(win, buf)       (VIDW_BUF_START(buf) + (win) * 8)
  58 #define VIDWx_BUF_END(win, buf)         (VIDW_BUF_END(buf) + (win) * 8)
  59 #define VIDWx_BUF_SIZE(win, buf)        (VIDW_BUF_SIZE(buf) + (win) * 4)
  60
  61 /* color key control register for hardware window 1 ~ 4. */
  62 #define WKEYCON0_BASE(x)                ((WKEYCON0 + 0x140) + ((x - 1) * 8))
  63 /* color key value register for hardware window 1 ~ 4. */
  64 #define WKEYCON1_BASE(x)                ((WKEYCON1 + 0x140) + ((x - 1) * 8))
  65
  66 /* I80 / RGB trigger control register */
  67 #define TRIGCON                         0x1A4
  68 #define TRGMODE_I80_RGB_ENABLE_I80      (1 << 0)
  69 #define SWTRGCMD_I80_RGB_ENABLE         (1 << 1)
  70
  71 /* display mode change control register except exynos4 */
  72 #define VIDOUT_CON                      0x000
  73 #define VIDOUT_CON_F_I80_LDI0           (0x2 << 8)
  74
  75 /* I80 interface control for main LDI register */
  76 #define I80IFCONFAx(x)                  (0x1B0 + (x) * 4)
  77 #define I80IFCONFBx(x)                  (0x1B8 + (x) * 4)
  78 #define LCD_CS_SETUP(x)                 ((x) << 16)
  79 #define LCD_WR_SETUP(x)                 ((x) << 12)
  80 #define LCD_WR_ACTIVE(x)                ((x) << 8)
  81 #define LCD_WR_HOLD(x)                  ((x) << 4)
  82 #define I80IFEN_ENABLE                  (1 << 0)
  83
  84 /* FIMD has totally five hardware windows. */
  85 #define WINDOWS_NR      5
  86
  87 struct fimd_driver_data {
  88         unsigned int timing_base;
  89         unsigned int lcdblk_offset;
  90         unsigned int lcdblk_vt_shift;
  91         unsigned int lcdblk_bypass_shift;
  92
  93         unsigned int has_shadowcon:1;
  94         unsigned int has_clksel:1;
  95         unsigned int has_limited_fmt:1;
  96         unsigned int has_vidoutcon:1;
  97         unsigned int has_vtsel:1;
  98 };
  99
 100 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
 101         .timing_base = 0x0,
 102         .has_clksel = 1,
 103         .has_limited_fmt = 1,
 104 };
 105
 106 static struct fimd_driver_data exynos3_fimd_driver_data = {
 107         .timing_base = 0x20000,
 108         .lcdblk_offset = 0x210,
 109         .lcdblk_bypass_shift = 1,
 110         .has_shadowcon = 1,
 111         .has_vidoutcon = 1,
 112 };
 113
 114 static struct fimd_driver_data exynos4_fimd_driver_data = {
 115         .timing_base = 0x0,
 116         .lcdblk_offset = 0x210,
 117         .lcdblk_vt_shift = 10,
 118         .lcdblk_bypass_shift = 1,
 119         .has_shadowcon = 1,
 120         .has_vtsel = 1,
 121 };
 122
 123 static struct fimd_driver_data exynos4415_fimd_driver_data = {
 124         .timing_base = 0x20000,
 125         .lcdblk_offset = 0x210,
 126         .lcdblk_vt_shift = 10,
 127         .lcdblk_bypass_shift = 1,
 128         .has_shadowcon = 1,
 129         .has_vidoutcon = 1,
 130         .has_vtsel = 1,
 131 };
 132
 133 static struct fimd_driver_data exynos5_fimd_driver_data = {
 134         .timing_base = 0x20000,
 135         .lcdblk_offset = 0x214,
 136         .lcdblk_vt_shift = 24,
 137         .lcdblk_bypass_shift = 15,
 138         .has_shadowcon = 1,
 139         .has_vidoutcon = 1,
 140         .has_vtsel = 1,
 141 };
 142
 143 struct fimd_win_data {
 144         unsigned int            offset_x;
 145         unsigned int            offset_y;
 146         unsigned int            ovl_width;
 147         unsigned int            ovl_height;
 148         unsigned int            fb_width;
 149         unsigned int            fb_height;
 150         unsigned int            bpp;
 151         unsigned int            pixel_format;
 152         dma_addr_t              dma_addr;
 153         unsigned int            buf_offsize;
 154         unsigned int            line_size;      /* bytes */
 155         bool                    enabled;
 156         bool                    resume;
 157 };
 158
 159 struct fimd_context {
 160         struct device                   *dev;
 161         struct drm_device               *drm_dev;
 162         struct exynos_drm_crtc          *crtc;
 163         struct clk                      *bus_clk;
 164         struct clk                      *lcd_clk;
 165         void __iomem                    *regs;
 166         struct regmap                   *sysreg;
 167         struct drm_display_mode         mode;
 168         struct fimd_win_data            win_data[WINDOWS_NR];
 169         unsigned int                    default_win;
 170         unsigned long                   irq_flags;
 171         u32                             vidcon0;
 172         u32                             vidcon1;
 173         u32                             vidout_con;
 174         u32                             i80ifcon;
 175         bool                            i80_if;
 176         bool                            suspended;
 177         int                             pipe;
 178         wait_queue_head_t               wait_vsync_queue;
 179         atomic_t                        wait_vsync_event;
 180         atomic_t                        win_updated;
 181         atomic_t                        triggering;
 182
 183         struct exynos_drm_panel_info panel;
 184         struct fimd_driver_data *driver_data;
 185         struct exynos_drm_display *display;
 186 };
 187
 188 static const struct of_device_id fimd_driver_dt_match[] = {
 189         { .compatible = "samsung,s3c6400-fimd",
 190           .data = &s3c64xx_fimd_driver_data },
 191         { .compatible = "samsung,exynos3250-fimd",
 192           .data = &exynos3_fimd_driver_data },
 193         { .compatible = "samsung,exynos4210-fimd",
 194           .data = &exynos4_fimd_driver_data },
 195         { .compatible = "samsung,exynos4415-fimd",
 196           .data = &exynos4415_fimd_driver_data },
 197         { .compatible = "samsung,exynos5250-fimd",
 198           .data = &exynos5_fimd_driver_data },
 199         {},
 200 };
 201 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
 202
 203 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
 204         struct platform_device *pdev)
 205 {
 206         const struct of_device_id *of_id =
 207                         of_match_device(fimd_driver_dt_match, &pdev->dev);
 208
 209         return (struct fimd_driver_data *)of_id->data;
 210 }
 211
 212 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
 213 {
 214         struct fimd_context *ctx = crtc->ctx;
 215
 216         if (ctx->suspended)
 217                 return;
 218
 219         atomic_set(&ctx->wait_vsync_event, 1);
 220
 221         /*
 222          * wait for FIMD to signal VSYNC interrupt or return after
 223          * timeout which is set to 50ms (refresh rate of 20).
 224          */
 225         if (!wait_event_timeout(ctx->wait_vsync_queue,
 226                                 !atomic_read(&ctx->wait_vsync_event),
 227                                 HZ/20))
 228                 DRM_DEBUG_KMS("vblank wait timed out.\n");
 229 }
 230
 231 static void fimd_enable_video_output(struct fimd_context *ctx, int win,
 232                                         bool enable)
 233 {
 234         u32 val = readl(ctx->regs + WINCON(win));
 235
 236         if (enable)
 237                 val |= WINCONx_ENWIN;
 238         else
 239                 val &= ~WINCONx_ENWIN;
 240
 241         writel(val, ctx->regs + WINCON(win));
 242 }
 243
 244 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, int win,
 245                                                 bool enable)
 246 {
 247         u32 val = readl(ctx->regs + SHADOWCON);
 248
 249         if (enable)
 250                 val |= SHADOWCON_CHx_ENABLE(win);
 251         else
 252                 val &= ~SHADOWCON_CHx_ENABLE(win);
 253
 254         writel(val, ctx->regs + SHADOWCON);
 255 }
 256
 257 static void fimd_clear_channel(struct exynos_drm_crtc *crtc)
 258 {
 259         struct fimd_context *ctx = crtc->ctx;
 260         int win, ch_enabled = 0;
 261
 262         DRM_DEBUG_KMS("%s\n", __FILE__);
 263
 264         /* Check if any channel is enabled. */
 265         for (win = 0; win < WINDOWS_NR; win++) {
 266                 u32 val = readl(ctx->regs + WINCON(win));
 267
 268                 if (val & WINCONx_ENWIN) {
 269                         fimd_enable_video_output(ctx, win, false);
 270
 271                         if (ctx->driver_data->has_shadowcon)
 272                                 fimd_enable_shadow_channel_path(ctx, win,
 273                                                                 false);
 274
 275                         ch_enabled = 1;
 276                 }
 277         }
 278
 279         /* Wait for vsync, as disable channel takes effect at next vsync */
 280         if (ch_enabled) {
 281                 unsigned int state = ctx->suspended;
 282
 283                 ctx->suspended = 0;
 284                 fimd_wait_for_vblank(crtc);
 285                 ctx->suspended = state;
 286         }
 287 }
 288
 289 static int fimd_ctx_initialize(struct fimd_context *ctx,
 290                         struct drm_device *drm_dev)
 291 {
 292         struct exynos_drm_private *priv;
 293         priv = drm_dev->dev_private;
 294
 295         ctx->drm_dev = drm_dev;
 296         ctx->pipe = priv->pipe++;
 297
 298         /* attach this sub driver to iommu mapping if supported. */
 299         if (is_drm_iommu_supported(ctx->drm_dev)) {
 300                 /*
 301                  * If any channel is already active, iommu will throw
 302                  * a PAGE FAULT when enabled. So clear any channel if enabled.
 303                  */
 304                 fimd_clear_channel(ctx->crtc);
 305                 drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
 306         }
 307
 308         return 0;
 309 }
 310
 311 static void fimd_ctx_remove(struct fimd_context *ctx)
 312 {
 313         /* detach this sub driver from iommu mapping if supported. */
 314         if (is_drm_iommu_supported(ctx->drm_dev))
 315                 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
 316 }
 317
 318 static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
 319                 const struct drm_display_mode *mode)
 320 {
 321         unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
 322         u32 clkdiv;
 323
 324         if (ctx->i80_if) {
 325                 /*
 326                  * The frame done interrupt should be occurred prior to the
 327                  * next TE signal.
 328                  */
 329                 ideal_clk *= 2;
 330         }
 331
 332         /* Find the clock divider value that gets us closest to ideal_clk */
 333         clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
 334
 335         return (clkdiv < 0x100) ? clkdiv : 0xff;
 336 }
 337
 338 static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc,
 339                 const struct drm_display_mode *mode,
 340                 struct drm_display_mode *adjusted_mode)
 341 {
 342         if (adjusted_mode->vrefresh == 0)
 343                 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE;
 344
 345         return true;
 346 }
 347
 348 static void fimd_mode_set(struct exynos_drm_crtc *crtc,
 349                 const struct drm_display_mode *in_mode)
 350 {
 351         struct fimd_context *ctx = crtc->ctx;
 352
 353         drm_mode_copy(&ctx->mode, in_mode);
 354 }
 355
 356 static void fimd_commit(struct exynos_drm_crtc *crtc)
 357 {
 358         struct fimd_context *ctx = crtc->ctx;
 359         struct drm_display_mode *mode = &ctx->mode;
 360         struct fimd_driver_data *driver_data = ctx->driver_data;
 361         void *timing_base = ctx->regs + driver_data->timing_base;
 362         u32 val, clkdiv;
 363
 364         if (ctx->suspended)
 365                 return;
 366
 367         /* nothing to do if we haven't set the mode yet */
 368         if (mode->htotal == 0 || mode->vtotal == 0)
 369                 return;
 370
 371         if (ctx->i80_if) {
 372                 val = ctx->i80ifcon | I80IFEN_ENABLE;
 373                 writel(val, timing_base + I80IFCONFAx(0));
 374
 375                 /* disable auto frame rate */
 376                 writel(0, timing_base + I80IFCONFBx(0));
 377
 378                 /* set video type selection to I80 interface */
 379                 if (driver_data->has_vtsel && ctx->sysreg &&
 380                                 regmap_update_bits(ctx->sysreg,
 381                                         driver_data->lcdblk_offset,
 382                                         0x3 << driver_data->lcdblk_vt_shift,
 383                                         0x1 << driver_data->lcdblk_vt_shift)) {
 384                         DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
 385                         return;
 386                 }
 387         } else {
 388                 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
 389                 u32 vidcon1;
 390
 391                 /* setup polarity values */
 392                 vidcon1 = ctx->vidcon1;
 393                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 394                         vidcon1 |= VIDCON1_INV_VSYNC;
 395                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 396                         vidcon1 |= VIDCON1_INV_HSYNC;
 397                 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
 398
 399                 /* setup vertical timing values. */
 400                 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
 401                 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
 402                 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
 403
 404                 val = VIDTCON0_VBPD(vbpd - 1) |
 405                         VIDTCON0_VFPD(vfpd - 1) |
 406                         VIDTCON0_VSPW(vsync_len - 1);
 407                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
 408
 409                 /* setup horizontal timing values.  */
 410                 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
 411                 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
 412                 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
 413
 414                 val = VIDTCON1_HBPD(hbpd - 1) |
 415                         VIDTCON1_HFPD(hfpd - 1) |
 416                         VIDTCON1_HSPW(hsync_len - 1);
 417                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
 418         }
 419
 420         if (driver_data->has_vidoutcon)
 421                 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
 422
 423         /* set bypass selection */
 424         if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
 425                                 driver_data->lcdblk_offset,
 426                                 0x1 << driver_data->lcdblk_bypass_shift,
 427                                 0x1 << driver_data->lcdblk_bypass_shift)) {
 428                 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
 429                 return;
 430         }
 431
 432         /* setup horizontal and vertical display size. */
 433         val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
 434                VIDTCON2_HOZVAL(mode->hdisplay - 1) |
 435                VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
 436                VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
 437         writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
 438
 439         /*
 440          * fields of register with prefix '_F' would be updated
 441          * at vsync(same as dma start)
 442          */
 443         val = ctx->vidcon0;
 444         val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 445
 446         if (ctx->driver_data->has_clksel)
 447                 val |= VIDCON0_CLKSEL_LCD;
 448
 449         clkdiv = fimd_calc_clkdiv(ctx, mode);
 450         if (clkdiv > 1)
 451                 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
 452
 453         writel(val, ctx->regs + VIDCON0);
 454 }
 455
 456 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
 457 {
 458         struct fimd_context *ctx = crtc->ctx;
 459         u32 val;
 460
 461         if (ctx->suspended)
 462                 return -EPERM;
 463
 464         if (!test_and_set_bit(0, &ctx->irq_flags)) {
 465                 val = readl(ctx->regs + VIDINTCON0);
 466
 467                 val |= VIDINTCON0_INT_ENABLE;
 468
 469                 if (ctx->i80_if) {
 470                         val |= VIDINTCON0_INT_I80IFDONE;
 471                         val |= VIDINTCON0_INT_SYSMAINCON;
 472                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 473                 } else {
 474                         val |= VIDINTCON0_INT_FRAME;
 475
 476                         val &= ~VIDINTCON0_FRAMESEL0_MASK;
 477                         val |= VIDINTCON0_FRAMESEL0_VSYNC;
 478                         val &= ~VIDINTCON0_FRAMESEL1_MASK;
 479                         val |= VIDINTCON0_FRAMESEL1_NONE;
 480                 }
 481
 482                 writel(val, ctx->regs + VIDINTCON0);
 483         }
 484
 485         return 0;
 486 }
 487
 488 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
 489 {
 490         struct fimd_context *ctx = crtc->ctx;
 491         u32 val;
 492
 493         if (ctx->suspended)
 494                 return;
 495
 496         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 497                 val = readl(ctx->regs + VIDINTCON0);
 498
 499                 val &= ~VIDINTCON0_INT_ENABLE;
 500
 501                 if (ctx->i80_if) {
 502                         val &= ~VIDINTCON0_INT_I80IFDONE;
 503                         val &= ~VIDINTCON0_INT_SYSMAINCON;
 504                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 505                 } else
 506                         val &= ~VIDINTCON0_INT_FRAME;
 507
 508                 writel(val, ctx->regs + VIDINTCON0);
 509         }
 510 }
 511
 512 static void fimd_win_mode_set(struct exynos_drm_crtc *crtc,
 513                         struct exynos_drm_plane *plane)
 514 {
 515         struct fimd_context *ctx = crtc->ctx;
 516         struct fimd_win_data *win_data;
 517         int win;
 518         unsigned long offset;
 519
 520         if (!plane) {
 521                 DRM_ERROR("plane is NULL\n");
 522                 return;
 523         }
 524
 525         win = plane->zpos;
 526         if (win == DEFAULT_ZPOS)
 527                 win = ctx->default_win;
 528
 529         if (win < 0 || win >= WINDOWS_NR)
 530                 return;
 531
 532         offset = plane->fb_x * (plane->bpp >> 3);
 533         offset += plane->fb_y * plane->pitch;
 534
 535         DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, plane->pitch);
 536
 537         win_data = &ctx->win_data[win];
 538
 539         win_data->offset_x = plane->crtc_x;
 540         win_data->offset_y = plane->crtc_y;
 541         win_data->ovl_width = plane->crtc_width;
 542         win_data->ovl_height = plane->crtc_height;
 543         win_data->fb_width = plane->fb_width;
 544         win_data->fb_height = plane->fb_height;
 545         win_data->dma_addr = plane->dma_addr[0] + offset;
 546         win_data->bpp = plane->bpp;
 547         win_data->pixel_format = plane->pixel_format;
 548         win_data->buf_offsize = (plane->fb_width - plane->crtc_width) *
 549                                 (plane->bpp >> 3);
 550         win_data->line_size = plane->crtc_width * (plane->bpp >> 3);
 551
 552         DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
 553                         win_data->offset_x, win_data->offset_y);
 554         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 555                         win_data->ovl_width, win_data->ovl_height);
 556         DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
 557         DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
 558                         plane->fb_width, plane->crtc_width);
 559 }
 560
 561 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win)
 562 {
 563         struct fimd_win_data *win_data = &ctx->win_data[win];
 564         unsigned long val;
 565
 566         val = WINCONx_ENWIN;
 567
 568         /*
 569          * In case of s3c64xx, window 0 doesn't support alpha channel.
 570          * So the request format is ARGB8888 then change it to XRGB8888.
 571          */
 572         if (ctx->driver_data->has_limited_fmt && !win) {
 573                 if (win_data->pixel_format == DRM_FORMAT_ARGB8888)
 574                         win_data->pixel_format = DRM_FORMAT_XRGB8888;
 575         }
 576
 577         switch (win_data->pixel_format) {
 578         case DRM_FORMAT_C8:
 579                 val |= WINCON0_BPPMODE_8BPP_PALETTE;
 580                 val |= WINCONx_BURSTLEN_8WORD;
 581                 val |= WINCONx_BYTSWP;
 582                 break;
 583         case DRM_FORMAT_XRGB1555:
 584                 val |= WINCON0_BPPMODE_16BPP_1555;
 585                 val |= WINCONx_HAWSWP;
 586                 val |= WINCONx_BURSTLEN_16WORD;
 587                 break;
 588         case DRM_FORMAT_RGB565:
 589                 val |= WINCON0_BPPMODE_16BPP_565;
 590                 val |= WINCONx_HAWSWP;
 591                 val |= WINCONx_BURSTLEN_16WORD;
 592                 break;
 593         case DRM_FORMAT_XRGB8888:
 594                 val |= WINCON0_BPPMODE_24BPP_888;
 595                 val |= WINCONx_WSWP;
 596                 val |= WINCONx_BURSTLEN_16WORD;
 597                 break;
 598         case DRM_FORMAT_ARGB8888:
 599                 val |= WINCON1_BPPMODE_25BPP_A1888
 600                         | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
 601                 val |= WINCONx_WSWP;
 602                 val |= WINCONx_BURSTLEN_16WORD;
 603                 break;
 604         default:
 605                 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
 606
 607                 val |= WINCON0_BPPMODE_24BPP_888;
 608                 val |= WINCONx_WSWP;
 609                 val |= WINCONx_BURSTLEN_16WORD;
 610                 break;
 611         }
 612
 613         DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
 614
 615         /*
 616          * In case of exynos, setting dma-burst to 16Word causes permanent
 617          * tearing for very small buffers, e.g. cursor buffer. Burst Mode
 618          * switching which is based on plane size is not recommended as
 619          * plane size varies alot towards the end of the screen and rapid
 620          * movement causes unstable DMA which results into iommu crash/tear.
 621          */
 622
 623         if (win_data->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 624                 val &= ~WINCONx_BURSTLEN_MASK;
 625                 val |= WINCONx_BURSTLEN_4WORD;
 626         }
 627
 628         writel(val, ctx->regs + WINCON(win));
 629 }
 630
 631 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
 632 {
 633         unsigned int keycon0 = 0, keycon1 = 0;
 634
 635         keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
 636                         WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 637
 638         keycon1 = WxKEYCON1_COLVAL(0xffffffff);
 639
 640         writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
 641         writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
 642 }
 643
 644 /**
 645  * shadow_protect_win() - disable updating values from shadow registers at vsync
 646  *
 647  * @win: window to protect registers for
 648  * @protect: 1 to protect (disable updates)
 649  */
 650 static void fimd_shadow_protect_win(struct fimd_context *ctx,
 651                                                         int win, bool protect)
 652 {
 653         u32 reg, bits, val;
 654
 655         if (ctx->driver_data->has_shadowcon) {
 656                 reg = SHADOWCON;
 657                 bits = SHADOWCON_WINx_PROTECT(win);
 658         } else {
 659                 reg = PRTCON;
 660                 bits = PRTCON_PROTECT;
 661         }
 662
 663         val = readl(ctx->regs + reg);
 664         if (protect)
 665                 val |= bits;
 666         else
 667                 val &= ~bits;
 668         writel(val, ctx->regs + reg);
 669 }
 670
 671 static void fimd_win_commit(struct exynos_drm_crtc *crtc, int zpos)
 672 {
 673         struct fimd_context *ctx = crtc->ctx;
 674         struct fimd_win_data *win_data;
 675         int win = zpos;
 676         unsigned long val, alpha, size;
 677         unsigned int last_x;
 678         unsigned int last_y;
 679
 680         if (ctx->suspended)
 681                 return;
 682
 683         if (win == DEFAULT_ZPOS)
 684                 win = ctx->default_win;
 685
 686         if (win < 0 || win >= WINDOWS_NR)
 687                 return;
 688
 689         win_data = &ctx->win_data[win];
 690
 691         /* If suspended, enable this on resume */
 692         if (ctx->suspended) {
 693                 win_data->resume = true;
 694                 return;
 695         }
 696
 697         /*
 698          * SHADOWCON/PRTCON register is used for enabling timing.
 699          *
 700          * for example, once only width value of a register is set,
 701          * if the dma is started then fimd hardware could malfunction so
 702          * with protect window setting, the register fields with prefix '_F'
 703          * wouldn't be updated at vsync also but updated once unprotect window
 704          * is set.
 705          */
 706
 707         /* protect windows */
 708         fimd_shadow_protect_win(ctx, win, true);
 709
 710         /* buffer start address */
 711         val = (unsigned long)win_data->dma_addr;
 712         writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
 713
 714         /* buffer end address */
 715         size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
 716         val = (unsigned long)(win_data->dma_addr + size);
 717         writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
 718
 719         DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
 720                         (unsigned long)win_data->dma_addr, val, size);
 721         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 722                         win_data->ovl_width, win_data->ovl_height);
 723
 724         /* buffer size */
 725         val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
 726                 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) |
 727                 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) |
 728                 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size);
 729         writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
 730
 731         /* OSD position */
 732         val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
 733                 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) |
 734                 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) |
 735                 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y);
 736         writel(val, ctx->regs + VIDOSD_A(win));
 737
 738         last_x = win_data->offset_x + win_data->ovl_width;
 739         if (last_x)
 740                 last_x--;
 741         last_y = win_data->offset_y + win_data->ovl_height;
 742         if (last_y)
 743                 last_y--;
 744
 745         val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
 746                 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
 747
 748         writel(val, ctx->regs + VIDOSD_B(win));
 749
 750         DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
 751                         win_data->offset_x, win_data->offset_y, last_x, last_y);
 752
 753         /* hardware window 0 doesn't support alpha channel. */
 754         if (win != 0) {
 755                 /* OSD alpha */
 756                 alpha = VIDISD14C_ALPHA1_R(0xf) |
 757                         VIDISD14C_ALPHA1_G(0xf) |
 758                         VIDISD14C_ALPHA1_B(0xf);
 759
 760                 writel(alpha, ctx->regs + VIDOSD_C(win));
 761         }
 762
 763         /* OSD size */
 764         if (win != 3 && win != 4) {
 765                 u32 offset = VIDOSD_D(win);
 766                 if (win == 0)
 767                         offset = VIDOSD_C(win);
 768                 val = win_data->ovl_width * win_data->ovl_height;
 769                 writel(val, ctx->regs + offset);
 770
 771                 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
 772         }
 773
 774         fimd_win_set_pixfmt(ctx, win);
 775
 776         /* hardware window 0 doesn't support color key. */
 777         if (win != 0)
 778                 fimd_win_set_colkey(ctx, win);
 779
 780         fimd_enable_video_output(ctx, win, true);
 781
 782         if (ctx->driver_data->has_shadowcon)
 783                 fimd_enable_shadow_channel_path(ctx, win, true);
 784
 785         /* Enable DMA channel and unprotect windows */
 786         fimd_shadow_protect_win(ctx, win, false);
 787
 788         win_data->enabled = true;
 789
 790         if (ctx->i80_if)
 791                 atomic_set(&ctx->win_updated, 1);
 792 }
 793
 794 static void fimd_win_disable(struct exynos_drm_crtc *crtc, int zpos)
 795 {
 796         struct fimd_context *ctx = crtc->ctx;
 797         struct fimd_win_data *win_data;
 798         int win = zpos;
 799
 800         if (win == DEFAULT_ZPOS)
 801                 win = ctx->default_win;
 802
 803         if (win < 0 || win >= WINDOWS_NR)
 804                 return;
 805
 806         win_data = &ctx->win_data[win];
 807
 808         if (ctx->suspended) {
 809                 /* do not resume this window*/
 810                 win_data->resume = false;
 811                 return;
 812         }
 813
 814         /* protect windows */
 815         fimd_shadow_protect_win(ctx, win, true);
 816
 817         fimd_enable_video_output(ctx, win, false);
 818
 819         if (ctx->driver_data->has_shadowcon)
 820                 fimd_enable_shadow_channel_path(ctx, win, false);
 821
 822         /* unprotect windows */
 823         fimd_shadow_protect_win(ctx, win, false);
 824
 825         win_data->enabled = false;
 826 }
 827
 828 static void fimd_window_suspend(struct exynos_drm_crtc *crtc)
 829 {
 830         struct fimd_context *ctx = crtc->ctx;
 831         struct fimd_win_data *win_data;
 832         int i;
 833
 834         for (i = 0; i < WINDOWS_NR; i++) {
 835                 win_data = &ctx->win_data[i];
 836                 win_data->resume = win_data->enabled;
 837                 if (win_data->enabled)
 838                         fimd_win_disable(crtc, i);
 839         }
 840 }
 841
 842 static void fimd_window_resume(struct exynos_drm_crtc *crtc)
 843 {
 844         struct fimd_context *ctx = crtc->ctx;
 845         struct fimd_win_data *win_data;
 846         int i;
 847
 848         for (i = 0; i < WINDOWS_NR; i++) {
 849                 win_data = &ctx->win_data[i];
 850                 win_data->enabled = win_data->resume;
 851                 win_data->resume = false;
 852         }
 853 }
 854
 855 static void fimd_apply(struct exynos_drm_crtc *crtc)
 856 {
 857         struct fimd_context *ctx = crtc->ctx;
 858         struct fimd_win_data *win_data;
 859         int i;
 860
 861         for (i = 0; i < WINDOWS_NR; i++) {
 862                 win_data = &ctx->win_data[i];
 863                 if (win_data->enabled)
 864                         fimd_win_commit(crtc, i);
 865                 else
 866                         fimd_win_disable(crtc, i);
 867         }
 868
 869         fimd_commit(crtc);
 870 }
 871
 872 static int fimd_poweron(struct exynos_drm_crtc *crtc)
 873 {
 874         struct fimd_context *ctx = crtc->ctx;
 875         int ret;
 876
 877         if (!ctx->suspended)
 878                 return 0;
 879
 880         ctx->suspended = false;
 881
 882         pm_runtime_get_sync(ctx->dev);
 883
 884         ret = clk_prepare_enable(ctx->bus_clk);
 885         if (ret < 0) {
 886                 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
 887                 goto bus_clk_err;
 888         }
 889
 890         ret = clk_prepare_enable(ctx->lcd_clk);
 891         if  (ret < 0) {
 892                 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
 893                 goto lcd_clk_err;
 894         }
 895
 896         /* if vblank was enabled status, enable it again. */
 897         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 898                 ret = fimd_enable_vblank(crtc);
 899                 if (ret) {
 900                         DRM_ERROR("Failed to re-enable vblank [%d]\n", ret);
 901                         goto enable_vblank_err;
 902                 }
 903         }
 904
 905         fimd_window_resume(crtc);
 906
 907         fimd_apply(crtc);
 908
 909         return 0;
 910
 911 enable_vblank_err:
 912         clk_disable_unprepare(ctx->lcd_clk);
 913 lcd_clk_err:
 914         clk_disable_unprepare(ctx->bus_clk);
 915 bus_clk_err:
 916         ctx->suspended = true;
 917         return ret;
 918 }
 919
 920 static int fimd_poweroff(struct exynos_drm_crtc *crtc)
 921 {
 922         struct fimd_context *ctx = crtc->ctx;
 923
 924         if (ctx->suspended)
 925                 return 0;
 926
 927         /*
 928          * We need to make sure that all windows are disabled before we
 929          * suspend that connector. Otherwise we might try to scan from
 930          * a destroyed buffer later.
 931          */
 932         fimd_window_suspend(crtc);
 933
 934         clk_disable_unprepare(ctx->lcd_clk);
 935         clk_disable_unprepare(ctx->bus_clk);
 936
 937         pm_runtime_put_sync(ctx->dev);
 938
 939         ctx->suspended = true;
 940         return 0;
 941 }
 942
 943 static void fimd_dpms(struct exynos_drm_crtc *crtc, int mode)
 944 {
 945         DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
 946
 947         switch (mode) {
 948         case DRM_MODE_DPMS_ON:
 949                 fimd_poweron(crtc);
 950                 break;
 951         case DRM_MODE_DPMS_STANDBY:
 952         case DRM_MODE_DPMS_SUSPEND:
 953         case DRM_MODE_DPMS_OFF:
 954                 fimd_poweroff(crtc);
 955                 break;
 956         default:
 957                 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
 958                 break;
 959         }
 960 }
 961
 962 static void fimd_trigger(struct device *dev)
 963 {
 964         struct fimd_context *ctx = dev_get_drvdata(dev);
 965         struct fimd_driver_data *driver_data = ctx->driver_data;
 966         void *timing_base = ctx->regs + driver_data->timing_base;
 967         u32 reg;
 968
 969          /*
 970           * Skips triggering if in triggering state, because multiple triggering
 971           * requests can cause panel reset.
 972           */
 973         if (atomic_read(&ctx->triggering))
 974                 return;
 975
 976         /* Enters triggering mode */
 977         atomic_set(&ctx->triggering, 1);
 978
 979         reg = readl(timing_base + TRIGCON);
 980         reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
 981         writel(reg, timing_base + TRIGCON);
 982
 983         /*
 984          * Exits triggering mode if vblank is not enabled yet, because when the
 985          * VIDINTCON0 register is not set, it can not exit from triggering mode.
 986          */
 987         if (!test_bit(0, &ctx->irq_flags))
 988                 atomic_set(&ctx->triggering, 0);
 989 }
 990
 991 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
 992 {
 993         struct fimd_context *ctx = crtc->ctx;
 994
 995         /* Checks the crtc is detached already from encoder */
 996         if (ctx->pipe < 0 || !ctx->drm_dev)
 997                 return;
 998
 999         /*
1000          * If there is a page flip request, triggers and handles the page flip
1001          * event so that current fb can be updated into panel GRAM.
1002          */
1003         if (atomic_add_unless(&ctx->win_updated, -1, 0))
1004                 fimd_trigger(ctx->dev);
1005
1006         /* Wakes up vsync event queue */
1007         if (atomic_read(&ctx->wait_vsync_event)) {
1008                 atomic_set(&ctx->wait_vsync_event, 0);
1009                 wake_up(&ctx->wait_vsync_queue);
1010         }
1011
1012         if (test_bit(0, &ctx->irq_flags))
1013                 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1014 }
1015
1016 static struct exynos_drm_crtc_ops fimd_crtc_ops = {
1017         .dpms = fimd_dpms,
1018         .mode_fixup = fimd_mode_fixup,
1019         .mode_set = fimd_mode_set,
1020         .commit = fimd_commit,
1021         .enable_vblank = fimd_enable_vblank,
1022         .disable_vblank = fimd_disable_vblank,
1023         .wait_for_vblank = fimd_wait_for_vblank,
1024         .win_mode_set = fimd_win_mode_set,
1025         .win_commit = fimd_win_commit,
1026         .win_disable = fimd_win_disable,
1027         .te_handler = fimd_te_handler,
1028 };
1029
1030 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
1031 {
1032         struct fimd_context *ctx = (struct fimd_context *)dev_id;
1033         u32 val, clear_bit;
1034
1035         val = readl(ctx->regs + VIDINTCON1);
1036
1037         clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
1038         if (val & clear_bit)
1039                 writel(clear_bit, ctx->regs + VIDINTCON1);
1040
1041         /* check the crtc is detached already from encoder */
1042         if (ctx->pipe < 0 || !ctx->drm_dev)
1043                 goto out;
1044
1045         if (ctx->i80_if) {
1046                 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1047
1048                 /* Exits triggering mode */
1049                 atomic_set(&ctx->triggering, 0);
1050         } else {
1051                 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1052                 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1053
1054                 /* set wait vsync event to zero and wake up queue. */
1055                 if (atomic_read(&ctx->wait_vsync_event)) {
1056                         atomic_set(&ctx->wait_vsync_event, 0);
1057                         wake_up(&ctx->wait_vsync_queue);
1058                 }
1059         }
1060
1061 out:
1062         return IRQ_HANDLED;
1063 }
1064
1065 static int fimd_bind(struct device *dev, struct device *master, void *data)
1066 {
1067         struct fimd_context *ctx = dev_get_drvdata(dev);
1068         struct drm_device *drm_dev = data;
1069
1070         ctx->crtc = exynos_drm_crtc_create(drm_dev, ctx->pipe,
1071                                            EXYNOS_DISPLAY_TYPE_LCD,
1072                                            &fimd_crtc_ops, ctx);
1073         if (IS_ERR(ctx->crtc))
1074                 return PTR_ERR(ctx->crtc);
1075
1076         fimd_ctx_initialize(ctx, drm_dev);
1077
1078         if (ctx->display)
1079                 exynos_drm_create_enc_conn(drm_dev, ctx->display);
1080
1081         return 0;
1082
1083 }
1084
1085 static void fimd_unbind(struct device *dev, struct device *master,
1086                         void *data)
1087 {
1088         struct fimd_context *ctx = dev_get_drvdata(dev);
1089
1090         fimd_dpms(ctx->crtc, DRM_MODE_DPMS_OFF);
1091
1092         if (ctx->display)
1093                 exynos_dpi_remove(ctx->display);
1094
1095         fimd_ctx_remove(ctx);
1096 }
1097
1098 static const struct component_ops fimd_component_ops = {
1099         .bind   = fimd_bind,
1100         .unbind = fimd_unbind,
1101 };
1102
1103 static int fimd_probe(struct platform_device *pdev)
1104 {
1105         struct device *dev = &pdev->dev;
1106         struct fimd_context *ctx;
1107         struct device_node *i80_if_timings;
1108         struct resource *res;
1109         int ret;
1110
1111         if (!dev->of_node)
1112                 return -ENODEV;
1113
1114         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1115         if (!ctx)
1116                 return -ENOMEM;
1117
1118         ret = exynos_drm_component_add(dev, EXYNOS_DEVICE_TYPE_CRTC,
1119                                        EXYNOS_DISPLAY_TYPE_LCD);
1120         if (ret)
1121                 return ret;
1122
1123         ctx->dev = dev;
1124         ctx->suspended = true;
1125         ctx->driver_data = drm_fimd_get_driver_data(pdev);
1126
1127         if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1128                 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1129         if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1130                 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1131
1132         i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1133         if (i80_if_timings) {
1134                 u32 val;
1135
1136                 ctx->i80_if = true;
1137
1138                 if (ctx->driver_data->has_vidoutcon)
1139                         ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1140                 else
1141                         ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1142                 /*
1143                  * The user manual describes that this "DSI_EN" bit is required
1144                  * to enable I80 24-bit data interface.
1145                  */
1146                 ctx->vidcon0 |= VIDCON0_DSI_EN;
1147
1148                 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1149                         val = 0;
1150                 ctx->i80ifcon = LCD_CS_SETUP(val);
1151                 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1152                         val = 0;
1153                 ctx->i80ifcon |= LCD_WR_SETUP(val);
1154                 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1155                         val = 1;
1156                 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1157                 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1158                         val = 0;
1159                 ctx->i80ifcon |= LCD_WR_HOLD(val);
1160         }
1161         of_node_put(i80_if_timings);
1162
1163         ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1164                                                         "samsung,sysreg");
1165         if (IS_ERR(ctx->sysreg)) {
1166                 dev_warn(dev, "failed to get system register.\n");
1167                 ctx->sysreg = NULL;
1168         }
1169
1170         ctx->bus_clk = devm_clk_get(dev, "fimd");
1171         if (IS_ERR(ctx->bus_clk)) {
1172                 dev_err(dev, "failed to get bus clock\n");
1173                 ret = PTR_ERR(ctx->bus_clk);
1174                 goto err_del_component;
1175         }
1176
1177         ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1178         if (IS_ERR(ctx->lcd_clk)) {
1179                 dev_err(dev, "failed to get lcd clock\n");
1180                 ret = PTR_ERR(ctx->lcd_clk);
1181                 goto err_del_component;
1182         }
1183
1184         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1185
1186         ctx->regs = devm_ioremap_resource(dev, res);
1187         if (IS_ERR(ctx->regs)) {
1188                 ret = PTR_ERR(ctx->regs);
1189                 goto err_del_component;
1190         }
1191
1192         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1193                                            ctx->i80_if ? "lcd_sys" : "vsync");
1194         if (!res) {
1195                 dev_err(dev, "irq request failed.\n");
1196                 ret = -ENXIO;
1197                 goto err_del_component;
1198         }
1199
1200         ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1201                                                         0, "drm_fimd", ctx);
1202         if (ret) {
1203                 dev_err(dev, "irq request failed.\n");
1204                 goto err_del_component;
1205         }
1206
1207         init_waitqueue_head(&ctx->wait_vsync_queue);
1208         atomic_set(&ctx->wait_vsync_event, 0);
1209
1210         platform_set_drvdata(pdev, ctx);
1211
1212         ctx->display = exynos_dpi_probe(dev);
1213         if (IS_ERR(ctx->display)) {
1214                 ret = PTR_ERR(ctx->display);
1215                 goto err_del_component;
1216         }
1217
1218         pm_runtime_enable(dev);
1219
1220         ret = component_add(dev, &fimd_component_ops);
1221         if (ret)
1222                 goto err_disable_pm_runtime;
1223
1224         return ret;
1225
1226 err_disable_pm_runtime:
1227         pm_runtime_disable(dev);
1228
1229 err_del_component:
1230         exynos_drm_component_del(dev, EXYNOS_DEVICE_TYPE_CRTC);
1231         return ret;
1232 }
1233
1234 static int fimd_remove(struct platform_device *pdev)
1235 {
1236         pm_runtime_disable(&pdev->dev);
1237
1238         component_del(&pdev->dev, &fimd_component_ops);
1239         exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1240
1241         return 0;
1242 }
1243
1244 struct platform_driver fimd_driver = {
1245         .probe          = fimd_probe,
1246         .remove         = fimd_remove,
1247         .driver         = {
1248                 .name   = "exynos4-fb",
1249                 .owner  = THIS_MODULE,
1250                 .of_match_table = fimd_driver_dt_match,
1251         },
1252 };