drivers/gpu/drm/exynos/exynos_drm_fimd.c

   1 /* exynos_drm_fimd.c
   2  *
   3  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Inki Dae <inki.dae@samsung.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14 #include <drm/drmP.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/clk.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/component.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/regmap.h>
  25
  26 #include <video/of_display_timing.h>
  27 #include <video/of_videomode.h>
  28 #include <video/samsung_fimd.h>
  29 #include <drm/exynos_drm.h>
  30
  31 #include "exynos_drm_drv.h"
  32 #include "exynos_drm_fbdev.h"
  33 #include "exynos_drm_crtc.h"
  34 #include "exynos_drm_iommu.h"
  35
  36 /*
  37  * FIMD stands for Fully Interactive Mobile Display and
  38  * as a display controller, it transfers contents drawn on memory
  39  * to a LCD Panel through Display Interfaces such as RGB or
  40  * CPU Interface.
  41  */
  42
  43 #define FIMD_DEFAULT_FRAMERATE 60
  44 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
  45
  46 /* position control register for hardware window 0, 2 ~ 4.*/
  47 #define VIDOSD_A(win)           (VIDOSD_BASE + 0x00 + (win) * 16)
  48 #define VIDOSD_B(win)           (VIDOSD_BASE + 0x04 + (win) * 16)
  49 /*
  50  * size control register for hardware windows 0 and alpha control register
  51  * for hardware windows 1 ~ 4
  52  */
  53 #define VIDOSD_C(win)           (VIDOSD_BASE + 0x08 + (win) * 16)
  54 /* size control register for hardware windows 1 ~ 2. */
  55 #define VIDOSD_D(win)           (VIDOSD_BASE + 0x0C + (win) * 16)
  56
  57 #define VIDWx_BUF_START(win, buf)       (VIDW_BUF_START(buf) + (win) * 8)
  58 #define VIDWx_BUF_END(win, buf)         (VIDW_BUF_END(buf) + (win) * 8)
  59 #define VIDWx_BUF_SIZE(win, buf)        (VIDW_BUF_SIZE(buf) + (win) * 4)
  60
  61 /* color key control register for hardware window 1 ~ 4. */
  62 #define WKEYCON0_BASE(x)                ((WKEYCON0 + 0x140) + ((x - 1) * 8))
  63 /* color key value register for hardware window 1 ~ 4. */
  64 #define WKEYCON1_BASE(x)                ((WKEYCON1 + 0x140) + ((x - 1) * 8))
  65
  66 /* I80 / RGB trigger control register */
  67 #define TRIGCON                         0x1A4
  68 #define TRGMODE_I80_RGB_ENABLE_I80      (1 << 0)
  69 #define SWTRGCMD_I80_RGB_ENABLE         (1 << 1)
  70
  71 /* display mode change control register except exynos4 */
  72 #define VIDOUT_CON                      0x000
  73 #define VIDOUT_CON_F_I80_LDI0           (0x2 << 8)
  74
  75 /* I80 interface control for main LDI register */
  76 #define I80IFCONFAx(x)                  (0x1B0 + (x) * 4)
  77 #define I80IFCONFBx(x)                  (0x1B8 + (x) * 4)
  78 #define LCD_CS_SETUP(x)                 ((x) << 16)
  79 #define LCD_WR_SETUP(x)                 ((x) << 12)
  80 #define LCD_WR_ACTIVE(x)                ((x) << 8)
  81 #define LCD_WR_HOLD(x)                  ((x) << 4)
  82 #define I80IFEN_ENABLE                  (1 << 0)
  83
  84 /* FIMD has totally five hardware windows. */
  85 #define WINDOWS_NR      5
  86
  87 struct fimd_driver_data {
  88         unsigned int timing_base;
  89         unsigned int lcdblk_offset;
  90         unsigned int lcdblk_vt_shift;
  91         unsigned int lcdblk_bypass_shift;
  92
  93         unsigned int has_shadowcon:1;
  94         unsigned int has_clksel:1;
  95         unsigned int has_limited_fmt:1;
  96         unsigned int has_vidoutcon:1;
  97         unsigned int has_vtsel:1;
  98 };
  99
 100 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
 101         .timing_base = 0x0,
 102         .has_clksel = 1,
 103         .has_limited_fmt = 1,
 104 };
 105
 106 static struct fimd_driver_data exynos3_fimd_driver_data = {
 107         .timing_base = 0x20000,
 108         .lcdblk_offset = 0x210,
 109         .lcdblk_bypass_shift = 1,
 110         .has_shadowcon = 1,
 111         .has_vidoutcon = 1,
 112 };
 113
 114 static struct fimd_driver_data exynos4_fimd_driver_data = {
 115         .timing_base = 0x0,
 116         .lcdblk_offset = 0x210,
 117         .lcdblk_vt_shift = 10,
 118         .lcdblk_bypass_shift = 1,
 119         .has_shadowcon = 1,
 120         .has_vtsel = 1,
 121 };
 122
 123 static struct fimd_driver_data exynos4415_fimd_driver_data = {
 124         .timing_base = 0x20000,
 125         .lcdblk_offset = 0x210,
 126         .lcdblk_vt_shift = 10,
 127         .lcdblk_bypass_shift = 1,
 128         .has_shadowcon = 1,
 129         .has_vidoutcon = 1,
 130         .has_vtsel = 1,
 131 };
 132
 133 static struct fimd_driver_data exynos5_fimd_driver_data = {
 134         .timing_base = 0x20000,
 135         .lcdblk_offset = 0x214,
 136         .lcdblk_vt_shift = 24,
 137         .lcdblk_bypass_shift = 15,
 138         .has_shadowcon = 1,
 139         .has_vidoutcon = 1,
 140         .has_vtsel = 1,
 141 };
 142
 143 struct fimd_win_data {
 144         unsigned int            offset_x;
 145         unsigned int            offset_y;
 146         unsigned int            ovl_width;
 147         unsigned int            ovl_height;
 148         unsigned int            fb_width;
 149         unsigned int            fb_height;
 150         unsigned int            bpp;
 151         unsigned int            pixel_format;
 152         dma_addr_t              dma_addr;
 153         unsigned int            buf_offsize;
 154         unsigned int            line_size;      /* bytes */
 155         bool                    enabled;
 156         bool                    resume;
 157 };
 158
 159 struct fimd_context {
 160         struct device                   *dev;
 161         struct drm_device               *drm_dev;
 162         struct exynos_drm_crtc          *crtc;
 163         struct clk                      *bus_clk;
 164         struct clk                      *lcd_clk;
 165         void __iomem                    *regs;
 166         struct regmap                   *sysreg;
 167         struct fimd_win_data            win_data[WINDOWS_NR];
 168         unsigned int                    default_win;
 169         unsigned long                   irq_flags;
 170         u32                             vidcon0;
 171         u32                             vidcon1;
 172         u32                             vidout_con;
 173         u32                             i80ifcon;
 174         bool                            i80_if;
 175         bool                            suspended;
 176         int                             pipe;
 177         wait_queue_head_t               wait_vsync_queue;
 178         atomic_t                        wait_vsync_event;
 179         atomic_t                        win_updated;
 180         atomic_t                        triggering;
 181
 182         struct exynos_drm_panel_info panel;
 183         struct fimd_driver_data *driver_data;
 184         struct exynos_drm_display *display;
 185 };
 186
 187 static const struct of_device_id fimd_driver_dt_match[] = {
 188         { .compatible = "samsung,s3c6400-fimd",
 189           .data = &s3c64xx_fimd_driver_data },
 190         { .compatible = "samsung,exynos3250-fimd",
 191           .data = &exynos3_fimd_driver_data },
 192         { .compatible = "samsung,exynos4210-fimd",
 193           .data = &exynos4_fimd_driver_data },
 194         { .compatible = "samsung,exynos4415-fimd",
 195           .data = &exynos4415_fimd_driver_data },
 196         { .compatible = "samsung,exynos5250-fimd",
 197           .data = &exynos5_fimd_driver_data },
 198         {},
 199 };
 200 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
 201
 202 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
 203         struct platform_device *pdev)
 204 {
 205         const struct of_device_id *of_id =
 206                         of_match_device(fimd_driver_dt_match, &pdev->dev);
 207
 208         return (struct fimd_driver_data *)of_id->data;
 209 }
 210
 211 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
 212 {
 213         struct fimd_context *ctx = crtc->ctx;
 214
 215         if (ctx->suspended)
 216                 return;
 217
 218         atomic_set(&ctx->wait_vsync_event, 1);
 219
 220         /*
 221          * wait for FIMD to signal VSYNC interrupt or return after
 222          * timeout which is set to 50ms (refresh rate of 20).
 223          */
 224         if (!wait_event_timeout(ctx->wait_vsync_queue,
 225                                 !atomic_read(&ctx->wait_vsync_event),
 226                                 HZ/20))
 227                 DRM_DEBUG_KMS("vblank wait timed out.\n");
 228 }
 229
 230 static void fimd_enable_video_output(struct fimd_context *ctx, int win,
 231                                         bool enable)
 232 {
 233         u32 val = readl(ctx->regs + WINCON(win));
 234
 235         if (enable)
 236                 val |= WINCONx_ENWIN;
 237         else
 238                 val &= ~WINCONx_ENWIN;
 239
 240         writel(val, ctx->regs + WINCON(win));
 241 }
 242
 243 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, int win,
 244                                                 bool enable)
 245 {
 246         u32 val = readl(ctx->regs + SHADOWCON);
 247
 248         if (enable)
 249                 val |= SHADOWCON_CHx_ENABLE(win);
 250         else
 251                 val &= ~SHADOWCON_CHx_ENABLE(win);
 252
 253         writel(val, ctx->regs + SHADOWCON);
 254 }
 255
 256 static void fimd_clear_channel(struct exynos_drm_crtc *crtc)
 257 {
 258         struct fimd_context *ctx = crtc->ctx;
 259         int win, ch_enabled = 0;
 260
 261         DRM_DEBUG_KMS("%s\n", __FILE__);
 262
 263         /* Check if any channel is enabled. */
 264         for (win = 0; win < WINDOWS_NR; win++) {
 265                 u32 val = readl(ctx->regs + WINCON(win));
 266
 267                 if (val & WINCONx_ENWIN) {
 268                         fimd_enable_video_output(ctx, win, false);
 269
 270                         if (ctx->driver_data->has_shadowcon)
 271                                 fimd_enable_shadow_channel_path(ctx, win,
 272                                                                 false);
 273
 274                         ch_enabled = 1;
 275                 }
 276         }
 277
 278         /* Wait for vsync, as disable channel takes effect at next vsync */
 279         if (ch_enabled) {
 280                 unsigned int state = ctx->suspended;
 281
 282                 ctx->suspended = 0;
 283                 fimd_wait_for_vblank(crtc);
 284                 ctx->suspended = state;
 285         }
 286 }
 287
 288 static int fimd_ctx_initialize(struct fimd_context *ctx,
 289                         struct drm_device *drm_dev)
 290 {
 291         struct exynos_drm_private *priv;
 292         priv = drm_dev->dev_private;
 293
 294         ctx->drm_dev = drm_dev;
 295         ctx->pipe = priv->pipe++;
 296
 297         /* attach this sub driver to iommu mapping if supported. */
 298         if (is_drm_iommu_supported(ctx->drm_dev)) {
 299                 int ret;
 300
 301                 /*
 302                  * If any channel is already active, iommu will throw
 303                  * a PAGE FAULT when enabled. So clear any channel if enabled.
 304                  */
 305                 fimd_clear_channel(ctx->crtc);
 306                 ret = drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
 307                 if (ret) {
 308                         DRM_ERROR("drm_iommu_attach failed.\n");
 309                         return ret;
 310                 }
 311
 312         }
 313
 314         return 0;
 315 }
 316
 317 static void fimd_ctx_remove(struct fimd_context *ctx)
 318 {
 319         /* detach this sub driver from iommu mapping if supported. */
 320         if (is_drm_iommu_supported(ctx->drm_dev))
 321                 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
 322 }
 323
 324 static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
 325                 const struct drm_display_mode *mode)
 326 {
 327         unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
 328         u32 clkdiv;
 329
 330         if (ctx->i80_if) {
 331                 /*
 332                  * The frame done interrupt should be occurred prior to the
 333                  * next TE signal.
 334                  */
 335                 ideal_clk *= 2;
 336         }
 337
 338         /* Find the clock divider value that gets us closest to ideal_clk */
 339         clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
 340
 341         return (clkdiv < 0x100) ? clkdiv : 0xff;
 342 }
 343
 344 static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc,
 345                 const struct drm_display_mode *mode,
 346                 struct drm_display_mode *adjusted_mode)
 347 {
 348         if (adjusted_mode->vrefresh == 0)
 349                 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE;
 350
 351         return true;
 352 }
 353
 354 static void fimd_commit(struct exynos_drm_crtc *crtc)
 355 {
 356         struct fimd_context *ctx = crtc->ctx;
 357         struct drm_display_mode *mode = &crtc->base.mode;
 358         struct fimd_driver_data *driver_data = ctx->driver_data;
 359         void *timing_base = ctx->regs + driver_data->timing_base;
 360         u32 val, clkdiv;
 361
 362         if (ctx->suspended)
 363                 return;
 364
 365         /* nothing to do if we haven't set the mode yet */
 366         if (mode->htotal == 0 || mode->vtotal == 0)
 367                 return;
 368
 369         if (ctx->i80_if) {
 370                 val = ctx->i80ifcon | I80IFEN_ENABLE;
 371                 writel(val, timing_base + I80IFCONFAx(0));
 372
 373                 /* disable auto frame rate */
 374                 writel(0, timing_base + I80IFCONFBx(0));
 375
 376                 /* set video type selection to I80 interface */
 377                 if (driver_data->has_vtsel && ctx->sysreg &&
 378                                 regmap_update_bits(ctx->sysreg,
 379                                         driver_data->lcdblk_offset,
 380                                         0x3 << driver_data->lcdblk_vt_shift,
 381                                         0x1 << driver_data->lcdblk_vt_shift)) {
 382                         DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
 383                         return;
 384                 }
 385         } else {
 386                 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
 387                 u32 vidcon1;
 388
 389                 /* setup polarity values */
 390                 vidcon1 = ctx->vidcon1;
 391                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 392                         vidcon1 |= VIDCON1_INV_VSYNC;
 393                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 394                         vidcon1 |= VIDCON1_INV_HSYNC;
 395                 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
 396
 397                 /* setup vertical timing values. */
 398                 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
 399                 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
 400                 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
 401
 402                 val = VIDTCON0_VBPD(vbpd - 1) |
 403                         VIDTCON0_VFPD(vfpd - 1) |
 404                         VIDTCON0_VSPW(vsync_len - 1);
 405                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
 406
 407                 /* setup horizontal timing values.  */
 408                 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
 409                 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
 410                 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
 411
 412                 val = VIDTCON1_HBPD(hbpd - 1) |
 413                         VIDTCON1_HFPD(hfpd - 1) |
 414                         VIDTCON1_HSPW(hsync_len - 1);
 415                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
 416         }
 417
 418         if (driver_data->has_vidoutcon)
 419                 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
 420
 421         /* set bypass selection */
 422         if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
 423                                 driver_data->lcdblk_offset,
 424                                 0x1 << driver_data->lcdblk_bypass_shift,
 425                                 0x1 << driver_data->lcdblk_bypass_shift)) {
 426                 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
 427                 return;
 428         }
 429
 430         /* setup horizontal and vertical display size. */
 431         val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
 432                VIDTCON2_HOZVAL(mode->hdisplay - 1) |
 433                VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
 434                VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
 435         writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
 436
 437         /*
 438          * fields of register with prefix '_F' would be updated
 439          * at vsync(same as dma start)
 440          */
 441         val = ctx->vidcon0;
 442         val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 443
 444         if (ctx->driver_data->has_clksel)
 445                 val |= VIDCON0_CLKSEL_LCD;
 446
 447         clkdiv = fimd_calc_clkdiv(ctx, mode);
 448         if (clkdiv > 1)
 449                 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
 450
 451         writel(val, ctx->regs + VIDCON0);
 452 }
 453
 454 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
 455 {
 456         struct fimd_context *ctx = crtc->ctx;
 457         u32 val;
 458
 459         if (ctx->suspended)
 460                 return -EPERM;
 461
 462         if (!test_and_set_bit(0, &ctx->irq_flags)) {
 463                 val = readl(ctx->regs + VIDINTCON0);
 464
 465                 val |= VIDINTCON0_INT_ENABLE;
 466
 467                 if (ctx->i80_if) {
 468                         val |= VIDINTCON0_INT_I80IFDONE;
 469                         val |= VIDINTCON0_INT_SYSMAINCON;
 470                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 471                 } else {
 472                         val |= VIDINTCON0_INT_FRAME;
 473
 474                         val &= ~VIDINTCON0_FRAMESEL0_MASK;
 475                         val |= VIDINTCON0_FRAMESEL0_VSYNC;
 476                         val &= ~VIDINTCON0_FRAMESEL1_MASK;
 477                         val |= VIDINTCON0_FRAMESEL1_NONE;
 478                 }
 479
 480                 writel(val, ctx->regs + VIDINTCON0);
 481         }
 482
 483         return 0;
 484 }
 485
 486 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
 487 {
 488         struct fimd_context *ctx = crtc->ctx;
 489         u32 val;
 490
 491         if (ctx->suspended)
 492                 return;
 493
 494         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 495                 val = readl(ctx->regs + VIDINTCON0);
 496
 497                 val &= ~VIDINTCON0_INT_ENABLE;
 498
 499                 if (ctx->i80_if) {
 500                         val &= ~VIDINTCON0_INT_I80IFDONE;
 501                         val &= ~VIDINTCON0_INT_SYSMAINCON;
 502                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 503                 } else
 504                         val &= ~VIDINTCON0_INT_FRAME;
 505
 506                 writel(val, ctx->regs + VIDINTCON0);
 507         }
 508 }
 509
 510 static void fimd_win_mode_set(struct exynos_drm_crtc *crtc,
 511                         struct exynos_drm_plane *plane)
 512 {
 513         struct fimd_context *ctx = crtc->ctx;
 514         struct fimd_win_data *win_data;
 515         int win;
 516         unsigned long offset;
 517
 518         if (!plane) {
 519                 DRM_ERROR("plane is NULL\n");
 520                 return;
 521         }
 522
 523         win = plane->zpos;
 524         if (win == DEFAULT_ZPOS)
 525                 win = ctx->default_win;
 526
 527         if (win < 0 || win >= WINDOWS_NR)
 528                 return;
 529
 530         offset = plane->fb_x * (plane->bpp >> 3);
 531         offset += plane->fb_y * plane->pitch;
 532
 533         DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, plane->pitch);
 534
 535         win_data = &ctx->win_data[win];
 536
 537         win_data->offset_x = plane->crtc_x;
 538         win_data->offset_y = plane->crtc_y;
 539         win_data->ovl_width = plane->crtc_width;
 540         win_data->ovl_height = plane->crtc_height;
 541         win_data->fb_width = plane->fb_width;
 542         win_data->fb_height = plane->fb_height;
 543         win_data->dma_addr = plane->dma_addr[0] + offset;
 544         win_data->bpp = plane->bpp;
 545         win_data->pixel_format = plane->pixel_format;
 546         win_data->buf_offsize = (plane->fb_width - plane->crtc_width) *
 547                                 (plane->bpp >> 3);
 548         win_data->line_size = plane->crtc_width * (plane->bpp >> 3);
 549
 550         DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
 551                         win_data->offset_x, win_data->offset_y);
 552         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 553                         win_data->ovl_width, win_data->ovl_height);
 554         DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
 555         DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
 556                         plane->fb_width, plane->crtc_width);
 557 }
 558
 559 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win)
 560 {
 561         struct fimd_win_data *win_data = &ctx->win_data[win];
 562         unsigned long val;
 563
 564         val = WINCONx_ENWIN;
 565
 566         /*
 567          * In case of s3c64xx, window 0 doesn't support alpha channel.
 568          * So the request format is ARGB8888 then change it to XRGB8888.
 569          */
 570         if (ctx->driver_data->has_limited_fmt && !win) {
 571                 if (win_data->pixel_format == DRM_FORMAT_ARGB8888)
 572                         win_data->pixel_format = DRM_FORMAT_XRGB8888;
 573         }
 574
 575         switch (win_data->pixel_format) {
 576         case DRM_FORMAT_C8:
 577                 val |= WINCON0_BPPMODE_8BPP_PALETTE;
 578                 val |= WINCONx_BURSTLEN_8WORD;
 579                 val |= WINCONx_BYTSWP;
 580                 break;
 581         case DRM_FORMAT_XRGB1555:
 582                 val |= WINCON0_BPPMODE_16BPP_1555;
 583                 val |= WINCONx_HAWSWP;
 584                 val |= WINCONx_BURSTLEN_16WORD;
 585                 break;
 586         case DRM_FORMAT_RGB565:
 587                 val |= WINCON0_BPPMODE_16BPP_565;
 588                 val |= WINCONx_HAWSWP;
 589                 val |= WINCONx_BURSTLEN_16WORD;
 590                 break;
 591         case DRM_FORMAT_XRGB8888:
 592                 val |= WINCON0_BPPMODE_24BPP_888;
 593                 val |= WINCONx_WSWP;
 594                 val |= WINCONx_BURSTLEN_16WORD;
 595                 break;
 596         case DRM_FORMAT_ARGB8888:
 597                 val |= WINCON1_BPPMODE_25BPP_A1888
 598                         | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
 599                 val |= WINCONx_WSWP;
 600                 val |= WINCONx_BURSTLEN_16WORD;
 601                 break;
 602         default:
 603                 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
 604
 605                 val |= WINCON0_BPPMODE_24BPP_888;
 606                 val |= WINCONx_WSWP;
 607                 val |= WINCONx_BURSTLEN_16WORD;
 608                 break;
 609         }
 610
 611         DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
 612
 613         /*
 614          * In case of exynos, setting dma-burst to 16Word causes permanent
 615          * tearing for very small buffers, e.g. cursor buffer. Burst Mode
 616          * switching which is based on plane size is not recommended as
 617          * plane size varies alot towards the end of the screen and rapid
 618          * movement causes unstable DMA which results into iommu crash/tear.
 619          */
 620
 621         if (win_data->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 622                 val &= ~WINCONx_BURSTLEN_MASK;
 623                 val |= WINCONx_BURSTLEN_4WORD;
 624         }
 625
 626         writel(val, ctx->regs + WINCON(win));
 627 }
 628
 629 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
 630 {
 631         unsigned int keycon0 = 0, keycon1 = 0;
 632
 633         keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
 634                         WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 635
 636         keycon1 = WxKEYCON1_COLVAL(0xffffffff);
 637
 638         writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
 639         writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
 640 }
 641
 642 /**
 643  * shadow_protect_win() - disable updating values from shadow registers at vsync
 644  *
 645  * @win: window to protect registers for
 646  * @protect: 1 to protect (disable updates)
 647  */
 648 static void fimd_shadow_protect_win(struct fimd_context *ctx,
 649                                                         int win, bool protect)
 650 {
 651         u32 reg, bits, val;
 652
 653         if (ctx->driver_data->has_shadowcon) {
 654                 reg = SHADOWCON;
 655                 bits = SHADOWCON_WINx_PROTECT(win);
 656         } else {
 657                 reg = PRTCON;
 658                 bits = PRTCON_PROTECT;
 659         }
 660
 661         val = readl(ctx->regs + reg);
 662         if (protect)
 663                 val |= bits;
 664         else
 665                 val &= ~bits;
 666         writel(val, ctx->regs + reg);
 667 }
 668
 669 static void fimd_win_commit(struct exynos_drm_crtc *crtc, int zpos)
 670 {
 671         struct fimd_context *ctx = crtc->ctx;
 672         struct fimd_win_data *win_data;
 673         int win = zpos;
 674         unsigned long val, alpha, size;
 675         unsigned int last_x;
 676         unsigned int last_y;
 677
 678         if (ctx->suspended)
 679                 return;
 680
 681         if (win == DEFAULT_ZPOS)
 682                 win = ctx->default_win;
 683
 684         if (win < 0 || win >= WINDOWS_NR)
 685                 return;
 686
 687         win_data = &ctx->win_data[win];
 688
 689         /* If suspended, enable this on resume */
 690         if (ctx->suspended) {
 691                 win_data->resume = true;
 692                 return;
 693         }
 694
 695         /*
 696          * SHADOWCON/PRTCON register is used for enabling timing.
 697          *
 698          * for example, once only width value of a register is set,
 699          * if the dma is started then fimd hardware could malfunction so
 700          * with protect window setting, the register fields with prefix '_F'
 701          * wouldn't be updated at vsync also but updated once unprotect window
 702          * is set.
 703          */
 704
 705         /* protect windows */
 706         fimd_shadow_protect_win(ctx, win, true);
 707
 708         /* buffer start address */
 709         val = (unsigned long)win_data->dma_addr;
 710         writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
 711
 712         /* buffer end address */
 713         size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
 714         val = (unsigned long)(win_data->dma_addr + size);
 715         writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
 716
 717         DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
 718                         (unsigned long)win_data->dma_addr, val, size);
 719         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 720                         win_data->ovl_width, win_data->ovl_height);
 721
 722         /* buffer size */
 723         val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
 724                 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) |
 725                 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) |
 726                 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size);
 727         writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
 728
 729         /* OSD position */
 730         val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
 731                 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) |
 732                 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) |
 733                 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y);
 734         writel(val, ctx->regs + VIDOSD_A(win));
 735
 736         last_x = win_data->offset_x + win_data->ovl_width;
 737         if (last_x)
 738                 last_x--;
 739         last_y = win_data->offset_y + win_data->ovl_height;
 740         if (last_y)
 741                 last_y--;
 742
 743         val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
 744                 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
 745
 746         writel(val, ctx->regs + VIDOSD_B(win));
 747
 748         DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
 749                         win_data->offset_x, win_data->offset_y, last_x, last_y);
 750
 751         /* hardware window 0 doesn't support alpha channel. */
 752         if (win != 0) {
 753                 /* OSD alpha */
 754                 alpha = VIDISD14C_ALPHA1_R(0xf) |
 755                         VIDISD14C_ALPHA1_G(0xf) |
 756                         VIDISD14C_ALPHA1_B(0xf);
 757
 758                 writel(alpha, ctx->regs + VIDOSD_C(win));
 759         }
 760
 761         /* OSD size */
 762         if (win != 3 && win != 4) {
 763                 u32 offset = VIDOSD_D(win);
 764                 if (win == 0)
 765                         offset = VIDOSD_C(win);
 766                 val = win_data->ovl_width * win_data->ovl_height;
 767                 writel(val, ctx->regs + offset);
 768
 769                 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
 770         }
 771
 772         fimd_win_set_pixfmt(ctx, win);
 773
 774         /* hardware window 0 doesn't support color key. */
 775         if (win != 0)
 776                 fimd_win_set_colkey(ctx, win);
 777
 778         fimd_enable_video_output(ctx, win, true);
 779
 780         if (ctx->driver_data->has_shadowcon)
 781                 fimd_enable_shadow_channel_path(ctx, win, true);
 782
 783         /* Enable DMA channel and unprotect windows */
 784         fimd_shadow_protect_win(ctx, win, false);
 785
 786         win_data->enabled = true;
 787
 788         if (ctx->i80_if)
 789                 atomic_set(&ctx->win_updated, 1);
 790 }
 791
 792 static void fimd_win_disable(struct exynos_drm_crtc *crtc, int zpos)
 793 {
 794         struct fimd_context *ctx = crtc->ctx;
 795         struct fimd_win_data *win_data;
 796         int win = zpos;
 797
 798         if (win == DEFAULT_ZPOS)
 799                 win = ctx->default_win;
 800
 801         if (win < 0 || win >= WINDOWS_NR)
 802                 return;
 803
 804         win_data = &ctx->win_data[win];
 805
 806         if (ctx->suspended) {
 807                 /* do not resume this window*/
 808                 win_data->resume = false;
 809                 return;
 810         }
 811
 812         /* protect windows */
 813         fimd_shadow_protect_win(ctx, win, true);
 814
 815         fimd_enable_video_output(ctx, win, false);
 816
 817         if (ctx->driver_data->has_shadowcon)
 818                 fimd_enable_shadow_channel_path(ctx, win, false);
 819
 820         /* unprotect windows */
 821         fimd_shadow_protect_win(ctx, win, false);
 822
 823         win_data->enabled = false;
 824 }
 825
 826 static void fimd_window_suspend(struct exynos_drm_crtc *crtc)
 827 {
 828         struct fimd_context *ctx = crtc->ctx;
 829         struct fimd_win_data *win_data;
 830         int i;
 831
 832         for (i = 0; i < WINDOWS_NR; i++) {
 833                 win_data = &ctx->win_data[i];
 834                 win_data->resume = win_data->enabled;
 835                 if (win_data->enabled)
 836                         fimd_win_disable(crtc, i);
 837         }
 838 }
 839
 840 static void fimd_window_resume(struct exynos_drm_crtc *crtc)
 841 {
 842         struct fimd_context *ctx = crtc->ctx;
 843         struct fimd_win_data *win_data;
 844         int i;
 845
 846         for (i = 0; i < WINDOWS_NR; i++) {
 847                 win_data = &ctx->win_data[i];
 848                 win_data->enabled = win_data->resume;
 849                 win_data->resume = false;
 850         }
 851 }
 852
 853 static void fimd_apply(struct exynos_drm_crtc *crtc)
 854 {
 855         struct fimd_context *ctx = crtc->ctx;
 856         struct fimd_win_data *win_data;
 857         int i;
 858
 859         for (i = 0; i < WINDOWS_NR; i++) {
 860                 win_data = &ctx->win_data[i];
 861                 if (win_data->enabled)
 862                         fimd_win_commit(crtc, i);
 863                 else
 864                         fimd_win_disable(crtc, i);
 865         }
 866
 867         fimd_commit(crtc);
 868 }
 869
 870 static int fimd_poweron(struct exynos_drm_crtc *crtc)
 871 {
 872         struct fimd_context *ctx = crtc->ctx;
 873         int ret;
 874
 875         if (!ctx->suspended)
 876                 return 0;
 877
 878         ctx->suspended = false;
 879
 880         pm_runtime_get_sync(ctx->dev);
 881
 882         ret = clk_prepare_enable(ctx->bus_clk);
 883         if (ret < 0) {
 884                 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
 885                 goto bus_clk_err;
 886         }
 887
 888         ret = clk_prepare_enable(ctx->lcd_clk);
 889         if  (ret < 0) {
 890                 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
 891                 goto lcd_clk_err;
 892         }
 893
 894         /* if vblank was enabled status, enable it again. */
 895         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 896                 ret = fimd_enable_vblank(crtc);
 897                 if (ret) {
 898                         DRM_ERROR("Failed to re-enable vblank [%d]\n", ret);
 899                         goto enable_vblank_err;
 900                 }
 901         }
 902
 903         fimd_window_resume(crtc);
 904
 905         fimd_apply(crtc);
 906
 907         return 0;
 908
 909 enable_vblank_err:
 910         clk_disable_unprepare(ctx->lcd_clk);
 911 lcd_clk_err:
 912         clk_disable_unprepare(ctx->bus_clk);
 913 bus_clk_err:
 914         ctx->suspended = true;
 915         return ret;
 916 }
 917
 918 static int fimd_poweroff(struct exynos_drm_crtc *crtc)
 919 {
 920         struct fimd_context *ctx = crtc->ctx;
 921
 922         if (ctx->suspended)
 923                 return 0;
 924
 925         /*
 926          * We need to make sure that all windows are disabled before we
 927          * suspend that connector. Otherwise we might try to scan from
 928          * a destroyed buffer later.
 929          */
 930         fimd_window_suspend(crtc);
 931
 932         clk_disable_unprepare(ctx->lcd_clk);
 933         clk_disable_unprepare(ctx->bus_clk);
 934
 935         pm_runtime_put_sync(ctx->dev);
 936
 937         ctx->suspended = true;
 938         return 0;
 939 }
 940
 941 static void fimd_dpms(struct exynos_drm_crtc *crtc, int mode)
 942 {
 943         DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
 944
 945         switch (mode) {
 946         case DRM_MODE_DPMS_ON:
 947                 fimd_poweron(crtc);
 948                 break;
 949         case DRM_MODE_DPMS_STANDBY:
 950         case DRM_MODE_DPMS_SUSPEND:
 951         case DRM_MODE_DPMS_OFF:
 952                 fimd_poweroff(crtc);
 953                 break;
 954         default:
 955                 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
 956                 break;
 957         }
 958 }
 959
 960 static void fimd_trigger(struct device *dev)
 961 {
 962         struct fimd_context *ctx = dev_get_drvdata(dev);
 963         struct fimd_driver_data *driver_data = ctx->driver_data;
 964         void *timing_base = ctx->regs + driver_data->timing_base;
 965         u32 reg;
 966
 967          /*
 968           * Skips triggering if in triggering state, because multiple triggering
 969           * requests can cause panel reset.
 970           */
 971         if (atomic_read(&ctx->triggering))
 972                 return;
 973
 974         /* Enters triggering mode */
 975         atomic_set(&ctx->triggering, 1);
 976
 977         reg = readl(timing_base + TRIGCON);
 978         reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
 979         writel(reg, timing_base + TRIGCON);
 980
 981         /*
 982          * Exits triggering mode if vblank is not enabled yet, because when the
 983          * VIDINTCON0 register is not set, it can not exit from triggering mode.
 984          */
 985         if (!test_bit(0, &ctx->irq_flags))
 986                 atomic_set(&ctx->triggering, 0);
 987 }
 988
 989 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
 990 {
 991         struct fimd_context *ctx = crtc->ctx;
 992
 993         /* Checks the crtc is detached already from encoder */
 994         if (ctx->pipe < 0 || !ctx->drm_dev)
 995                 return;
 996
 997         /*
 998          * If there is a page flip request, triggers and handles the page flip
 999          * event so that current fb can be updated into panel GRAM.
1000          */
1001         if (atomic_add_unless(&ctx->win_updated, -1, 0))
1002                 fimd_trigger(ctx->dev);
1003
1004         /* Wakes up vsync event queue */
1005         if (atomic_read(&ctx->wait_vsync_event)) {
1006                 atomic_set(&ctx->wait_vsync_event, 0);
1007                 wake_up(&ctx->wait_vsync_queue);
1008         }
1009
1010         if (test_bit(0, &ctx->irq_flags))
1011                 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1012 }
1013
1014 static struct exynos_drm_crtc_ops fimd_crtc_ops = {
1015         .dpms = fimd_dpms,
1016         .mode_fixup = fimd_mode_fixup,
1017         .commit = fimd_commit,
1018         .enable_vblank = fimd_enable_vblank,
1019         .disable_vblank = fimd_disable_vblank,
1020         .wait_for_vblank = fimd_wait_for_vblank,
1021         .win_mode_set = fimd_win_mode_set,
1022         .win_commit = fimd_win_commit,
1023         .win_disable = fimd_win_disable,
1024         .te_handler = fimd_te_handler,
1025 };
1026
1027 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
1028 {
1029         struct fimd_context *ctx = (struct fimd_context *)dev_id;
1030         u32 val, clear_bit;
1031
1032         val = readl(ctx->regs + VIDINTCON1);
1033
1034         clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
1035         if (val & clear_bit)
1036                 writel(clear_bit, ctx->regs + VIDINTCON1);
1037
1038         /* check the crtc is detached already from encoder */
1039         if (ctx->pipe < 0 || !ctx->drm_dev)
1040                 goto out;
1041
1042         if (ctx->i80_if) {
1043                 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1044
1045                 /* Exits triggering mode */
1046                 atomic_set(&ctx->triggering, 0);
1047         } else {
1048                 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1049                 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1050
1051                 /* set wait vsync event to zero and wake up queue. */
1052                 if (atomic_read(&ctx->wait_vsync_event)) {
1053                         atomic_set(&ctx->wait_vsync_event, 0);
1054                         wake_up(&ctx->wait_vsync_queue);
1055                 }
1056         }
1057
1058 out:
1059         return IRQ_HANDLED;
1060 }
1061
1062 static int fimd_bind(struct device *dev, struct device *master, void *data)
1063 {
1064         struct fimd_context *ctx = dev_get_drvdata(dev);
1065         struct drm_device *drm_dev = data;
1066         int ret;
1067
1068         ctx->crtc = exynos_drm_crtc_create(drm_dev, ctx->pipe,
1069                                            EXYNOS_DISPLAY_TYPE_LCD,
1070                                            &fimd_crtc_ops, ctx);
1071         if (IS_ERR(ctx->crtc))
1072                 return PTR_ERR(ctx->crtc);
1073
1074         ret = fimd_ctx_initialize(ctx, drm_dev);
1075         if (ret) {
1076                 DRM_ERROR("fimd_ctx_initialize failed.\n");
1077                 return ret;
1078         }
1079
1080
1081         if (ctx->display)
1082                 exynos_drm_create_enc_conn(drm_dev, ctx->display);
1083
1084         return 0;
1085
1086 }
1087
1088 static void fimd_unbind(struct device *dev, struct device *master,
1089                         void *data)
1090 {
1091         struct fimd_context *ctx = dev_get_drvdata(dev);
1092
1093         fimd_dpms(ctx->crtc, DRM_MODE_DPMS_OFF);
1094
1095         if (ctx->display)
1096                 exynos_dpi_remove(ctx->display);
1097
1098         fimd_ctx_remove(ctx);
1099 }
1100
1101 static const struct component_ops fimd_component_ops = {
1102         .bind   = fimd_bind,
1103         .unbind = fimd_unbind,
1104 };
1105
1106 static int fimd_probe(struct platform_device *pdev)
1107 {
1108         struct device *dev = &pdev->dev;
1109         struct fimd_context *ctx;
1110         struct device_node *i80_if_timings;
1111         struct resource *res;
1112         int ret;
1113
1114         if (!dev->of_node)
1115                 return -ENODEV;
1116
1117         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1118         if (!ctx)
1119                 return -ENOMEM;
1120
1121         ret = exynos_drm_component_add(dev, EXYNOS_DEVICE_TYPE_CRTC,
1122                                        EXYNOS_DISPLAY_TYPE_LCD);
1123         if (ret)
1124                 return ret;
1125
1126         ctx->dev = dev;
1127         ctx->suspended = true;
1128         ctx->driver_data = drm_fimd_get_driver_data(pdev);
1129
1130         if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1131                 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1132         if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1133                 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1134
1135         i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1136         if (i80_if_timings) {
1137                 u32 val;
1138
1139                 ctx->i80_if = true;
1140
1141                 if (ctx->driver_data->has_vidoutcon)
1142                         ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1143                 else
1144                         ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1145                 /*
1146                  * The user manual describes that this "DSI_EN" bit is required
1147                  * to enable I80 24-bit data interface.
1148                  */
1149                 ctx->vidcon0 |= VIDCON0_DSI_EN;
1150
1151                 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1152                         val = 0;
1153                 ctx->i80ifcon = LCD_CS_SETUP(val);
1154                 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1155                         val = 0;
1156                 ctx->i80ifcon |= LCD_WR_SETUP(val);
1157                 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1158                         val = 1;
1159                 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1160                 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1161                         val = 0;
1162                 ctx->i80ifcon |= LCD_WR_HOLD(val);
1163         }
1164         of_node_put(i80_if_timings);
1165
1166         ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1167                                                         "samsung,sysreg");
1168         if (IS_ERR(ctx->sysreg)) {
1169                 dev_warn(dev, "failed to get system register.\n");
1170                 ctx->sysreg = NULL;
1171         }
1172
1173         ctx->bus_clk = devm_clk_get(dev, "fimd");
1174         if (IS_ERR(ctx->bus_clk)) {
1175                 dev_err(dev, "failed to get bus clock\n");
1176                 ret = PTR_ERR(ctx->bus_clk);
1177                 goto err_del_component;
1178         }
1179
1180         ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1181         if (IS_ERR(ctx->lcd_clk)) {
1182                 dev_err(dev, "failed to get lcd clock\n");
1183                 ret = PTR_ERR(ctx->lcd_clk);
1184                 goto err_del_component;
1185         }
1186
1187         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1188
1189         ctx->regs = devm_ioremap_resource(dev, res);
1190         if (IS_ERR(ctx->regs)) {
1191                 ret = PTR_ERR(ctx->regs);
1192                 goto err_del_component;
1193         }
1194
1195         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1196                                            ctx->i80_if ? "lcd_sys" : "vsync");
1197         if (!res) {
1198                 dev_err(dev, "irq request failed.\n");
1199                 ret = -ENXIO;
1200                 goto err_del_component;
1201         }
1202
1203         ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1204                                                         0, "drm_fimd", ctx);
1205         if (ret) {
1206                 dev_err(dev, "irq request failed.\n");
1207                 goto err_del_component;
1208         }
1209
1210         init_waitqueue_head(&ctx->wait_vsync_queue);
1211         atomic_set(&ctx->wait_vsync_event, 0);
1212
1213         platform_set_drvdata(pdev, ctx);
1214
1215         ctx->display = exynos_dpi_probe(dev);
1216         if (IS_ERR(ctx->display)) {
1217                 ret = PTR_ERR(ctx->display);
1218                 goto err_del_component;
1219         }
1220
1221         pm_runtime_enable(dev);
1222
1223         ret = component_add(dev, &fimd_component_ops);
1224         if (ret)
1225                 goto err_disable_pm_runtime;
1226
1227         return ret;
1228
1229 err_disable_pm_runtime:
1230         pm_runtime_disable(dev);
1231
1232 err_del_component:
1233         exynos_drm_component_del(dev, EXYNOS_DEVICE_TYPE_CRTC);
1234         return ret;
1235 }
1236
1237 static int fimd_remove(struct platform_device *pdev)
1238 {
1239         pm_runtime_disable(&pdev->dev);
1240
1241         component_del(&pdev->dev, &fimd_component_ops);
1242         exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1243
1244         return 0;
1245 }
1246
1247 struct platform_driver fimd_driver = {
1248         .probe          = fimd_probe,
1249         .remove         = fimd_remove,
1250         .driver         = {
1251                 .name   = "exynos4-fb",
1252                 .owner  = THIS_MODULE,
1253                 .of_match_table = fimd_driver_dt_match,
1254         },
1255 };