3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/component.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/samsung_fimd.h>
29 #include <drm/exynos_drm.h>
31 #include "exynos_drm_drv.h"
32 #include "exynos_drm_fbdev.h"
33 #include "exynos_drm_crtc.h"
34 #include "exynos_drm_iommu.h"
37 * FIMD stands for Fully Interactive Mobile Display and
38 * as a display controller, it transfers contents drawn on memory
39 * to a LCD Panel through Display Interfaces such as RGB or
43 #define FIMD_DEFAULT_FRAMERATE 60
44 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
46 /* position control register for hardware window 0, 2 ~ 4.*/
47 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
48 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
50 * size control register for hardware windows 0 and alpha control register
51 * for hardware windows 1 ~ 4
53 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
54 /* size control register for hardware windows 1 ~ 2. */
55 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
57 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
58 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
59 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
61 /* color key control register for hardware window 1 ~ 4. */
62 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
63 /* color key value register for hardware window 1 ~ 4. */
64 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
66 /* I80 / RGB trigger control register */
68 #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
69 #define SWTRGCMD_I80_RGB_ENABLE (1 << 1)
71 /* display mode change control register except exynos4 */
72 #define VIDOUT_CON 0x000
73 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
75 /* I80 interface control for main LDI register */
76 #define I80IFCONFAx(x) (0x1B0 + (x) * 4)
77 #define I80IFCONFBx(x) (0x1B8 + (x) * 4)
78 #define LCD_CS_SETUP(x) ((x) << 16)
79 #define LCD_WR_SETUP(x) ((x) << 12)
80 #define LCD_WR_ACTIVE(x) ((x) << 8)
81 #define LCD_WR_HOLD(x) ((x) << 4)
82 #define I80IFEN_ENABLE (1 << 0)
84 /* FIMD has totally five hardware windows. */
87 struct fimd_driver_data {
88 unsigned int timing_base;
89 unsigned int lcdblk_offset;
90 unsigned int lcdblk_vt_shift;
91 unsigned int lcdblk_bypass_shift;
93 unsigned int has_shadowcon:1;
94 unsigned int has_clksel:1;
95 unsigned int has_limited_fmt:1;
96 unsigned int has_vidoutcon:1;
97 unsigned int has_vtsel:1;
100 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
103 .has_limited_fmt = 1,
106 static struct fimd_driver_data exynos3_fimd_driver_data = {
107 .timing_base = 0x20000,
108 .lcdblk_offset = 0x210,
109 .lcdblk_bypass_shift = 1,
114 static struct fimd_driver_data exynos4_fimd_driver_data = {
116 .lcdblk_offset = 0x210,
117 .lcdblk_vt_shift = 10,
118 .lcdblk_bypass_shift = 1,
123 static struct fimd_driver_data exynos4415_fimd_driver_data = {
124 .timing_base = 0x20000,
125 .lcdblk_offset = 0x210,
126 .lcdblk_vt_shift = 10,
127 .lcdblk_bypass_shift = 1,
133 static struct fimd_driver_data exynos5_fimd_driver_data = {
134 .timing_base = 0x20000,
135 .lcdblk_offset = 0x214,
136 .lcdblk_vt_shift = 24,
137 .lcdblk_bypass_shift = 15,
143 struct fimd_win_data {
144 unsigned int offset_x;
145 unsigned int offset_y;
146 unsigned int ovl_width;
147 unsigned int ovl_height;
148 unsigned int fb_width;
149 unsigned int fb_height;
151 unsigned int pixel_format;
153 unsigned int buf_offsize;
154 unsigned int line_size; /* bytes */
159 struct fimd_context {
161 struct drm_device *drm_dev;
162 struct exynos_drm_crtc *crtc;
166 struct regmap *sysreg;
167 struct fimd_win_data win_data[WINDOWS_NR];
168 unsigned int default_win;
169 unsigned long irq_flags;
177 wait_queue_head_t wait_vsync_queue;
178 atomic_t wait_vsync_event;
179 atomic_t win_updated;
182 struct exynos_drm_panel_info panel;
183 struct fimd_driver_data *driver_data;
184 struct exynos_drm_display *display;
187 static const struct of_device_id fimd_driver_dt_match[] = {
188 { .compatible = "samsung,s3c6400-fimd",
189 .data = &s3c64xx_fimd_driver_data },
190 { .compatible = "samsung,exynos3250-fimd",
191 .data = &exynos3_fimd_driver_data },
192 { .compatible = "samsung,exynos4210-fimd",
193 .data = &exynos4_fimd_driver_data },
194 { .compatible = "samsung,exynos4415-fimd",
195 .data = &exynos4415_fimd_driver_data },
196 { .compatible = "samsung,exynos5250-fimd",
197 .data = &exynos5_fimd_driver_data },
200 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
202 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
203 struct platform_device *pdev)
205 const struct of_device_id *of_id =
206 of_match_device(fimd_driver_dt_match, &pdev->dev);
208 return (struct fimd_driver_data *)of_id->data;
211 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
213 struct fimd_context *ctx = crtc->ctx;
218 atomic_set(&ctx->wait_vsync_event, 1);
221 * wait for FIMD to signal VSYNC interrupt or return after
222 * timeout which is set to 50ms (refresh rate of 20).
224 if (!wait_event_timeout(ctx->wait_vsync_queue,
225 !atomic_read(&ctx->wait_vsync_event),
227 DRM_DEBUG_KMS("vblank wait timed out.\n");
230 static void fimd_enable_video_output(struct fimd_context *ctx, int win,
233 u32 val = readl(ctx->regs + WINCON(win));
236 val |= WINCONx_ENWIN;
238 val &= ~WINCONx_ENWIN;
240 writel(val, ctx->regs + WINCON(win));
243 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx, int win,
246 u32 val = readl(ctx->regs + SHADOWCON);
249 val |= SHADOWCON_CHx_ENABLE(win);
251 val &= ~SHADOWCON_CHx_ENABLE(win);
253 writel(val, ctx->regs + SHADOWCON);
256 static void fimd_clear_channel(struct fimd_context *ctx)
258 int win, ch_enabled = 0;
260 DRM_DEBUG_KMS("%s\n", __FILE__);
262 /* Check if any channel is enabled. */
263 for (win = 0; win < WINDOWS_NR; win++) {
264 u32 val = readl(ctx->regs + WINCON(win));
266 if (val & WINCONx_ENWIN) {
267 fimd_enable_video_output(ctx, win, false);
269 if (ctx->driver_data->has_shadowcon)
270 fimd_enable_shadow_channel_path(ctx, win,
277 /* Wait for vsync, as disable channel takes effect at next vsync */
279 unsigned int state = ctx->suspended;
282 fimd_wait_for_vblank(ctx->crtc);
283 ctx->suspended = state;
287 static int fimd_ctx_initialize(struct fimd_context *ctx,
288 struct drm_device *drm_dev)
290 struct exynos_drm_private *priv;
291 priv = drm_dev->dev_private;
293 ctx->drm_dev = drm_dev;
294 ctx->pipe = priv->pipe++;
296 /* attach this sub driver to iommu mapping if supported. */
297 if (is_drm_iommu_supported(ctx->drm_dev)) {
301 * If any channel is already active, iommu will throw
302 * a PAGE FAULT when enabled. So clear any channel if enabled.
304 fimd_clear_channel(ctx);
305 ret = drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
307 DRM_ERROR("drm_iommu_attach failed.\n");
316 static void fimd_ctx_remove(struct fimd_context *ctx)
318 /* detach this sub driver from iommu mapping if supported. */
319 if (is_drm_iommu_supported(ctx->drm_dev))
320 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
323 static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
324 const struct drm_display_mode *mode)
326 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
331 * The frame done interrupt should be occurred prior to the
337 /* Find the clock divider value that gets us closest to ideal_clk */
338 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
340 return (clkdiv < 0x100) ? clkdiv : 0xff;
343 static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc,
344 const struct drm_display_mode *mode,
345 struct drm_display_mode *adjusted_mode)
347 if (adjusted_mode->vrefresh == 0)
348 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE;
353 static void fimd_commit(struct exynos_drm_crtc *crtc)
355 struct fimd_context *ctx = crtc->ctx;
356 struct drm_display_mode *mode = &crtc->base.mode;
357 struct fimd_driver_data *driver_data = ctx->driver_data;
358 void *timing_base = ctx->regs + driver_data->timing_base;
364 /* nothing to do if we haven't set the mode yet */
365 if (mode->htotal == 0 || mode->vtotal == 0)
369 val = ctx->i80ifcon | I80IFEN_ENABLE;
370 writel(val, timing_base + I80IFCONFAx(0));
372 /* disable auto frame rate */
373 writel(0, timing_base + I80IFCONFBx(0));
375 /* set video type selection to I80 interface */
376 if (driver_data->has_vtsel && ctx->sysreg &&
377 regmap_update_bits(ctx->sysreg,
378 driver_data->lcdblk_offset,
379 0x3 << driver_data->lcdblk_vt_shift,
380 0x1 << driver_data->lcdblk_vt_shift)) {
381 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
385 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
388 /* setup polarity values */
389 vidcon1 = ctx->vidcon1;
390 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
391 vidcon1 |= VIDCON1_INV_VSYNC;
392 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
393 vidcon1 |= VIDCON1_INV_HSYNC;
394 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
396 /* setup vertical timing values. */
397 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
398 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
399 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
401 val = VIDTCON0_VBPD(vbpd - 1) |
402 VIDTCON0_VFPD(vfpd - 1) |
403 VIDTCON0_VSPW(vsync_len - 1);
404 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
406 /* setup horizontal timing values. */
407 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
408 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
409 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
411 val = VIDTCON1_HBPD(hbpd - 1) |
412 VIDTCON1_HFPD(hfpd - 1) |
413 VIDTCON1_HSPW(hsync_len - 1);
414 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
417 if (driver_data->has_vidoutcon)
418 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
420 /* set bypass selection */
421 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
422 driver_data->lcdblk_offset,
423 0x1 << driver_data->lcdblk_bypass_shift,
424 0x1 << driver_data->lcdblk_bypass_shift)) {
425 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
429 /* setup horizontal and vertical display size. */
430 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
431 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
432 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
433 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
434 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
437 * fields of register with prefix '_F' would be updated
438 * at vsync(same as dma start)
441 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
443 if (ctx->driver_data->has_clksel)
444 val |= VIDCON0_CLKSEL_LCD;
446 clkdiv = fimd_calc_clkdiv(ctx, mode);
448 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
450 writel(val, ctx->regs + VIDCON0);
453 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
455 struct fimd_context *ctx = crtc->ctx;
461 if (!test_and_set_bit(0, &ctx->irq_flags)) {
462 val = readl(ctx->regs + VIDINTCON0);
464 val |= VIDINTCON0_INT_ENABLE;
467 val |= VIDINTCON0_INT_I80IFDONE;
468 val |= VIDINTCON0_INT_SYSMAINCON;
469 val &= ~VIDINTCON0_INT_SYSSUBCON;
471 val |= VIDINTCON0_INT_FRAME;
473 val &= ~VIDINTCON0_FRAMESEL0_MASK;
474 val |= VIDINTCON0_FRAMESEL0_VSYNC;
475 val &= ~VIDINTCON0_FRAMESEL1_MASK;
476 val |= VIDINTCON0_FRAMESEL1_NONE;
479 writel(val, ctx->regs + VIDINTCON0);
485 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
487 struct fimd_context *ctx = crtc->ctx;
493 if (test_and_clear_bit(0, &ctx->irq_flags)) {
494 val = readl(ctx->regs + VIDINTCON0);
496 val &= ~VIDINTCON0_INT_ENABLE;
499 val &= ~VIDINTCON0_INT_I80IFDONE;
500 val &= ~VIDINTCON0_INT_SYSMAINCON;
501 val &= ~VIDINTCON0_INT_SYSSUBCON;
503 val &= ~VIDINTCON0_INT_FRAME;
505 writel(val, ctx->regs + VIDINTCON0);
509 static void fimd_win_mode_set(struct exynos_drm_crtc *crtc,
510 struct exynos_drm_plane *plane)
512 struct fimd_context *ctx = crtc->ctx;
513 struct fimd_win_data *win_data;
515 unsigned long offset;
518 DRM_ERROR("plane is NULL\n");
523 if (win == DEFAULT_ZPOS)
524 win = ctx->default_win;
526 if (win < 0 || win >= WINDOWS_NR)
529 offset = plane->fb_x * (plane->bpp >> 3);
530 offset += plane->fb_y * plane->pitch;
532 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, plane->pitch);
534 win_data = &ctx->win_data[win];
536 win_data->offset_x = plane->crtc_x;
537 win_data->offset_y = plane->crtc_y;
538 win_data->ovl_width = plane->crtc_width;
539 win_data->ovl_height = plane->crtc_height;
540 win_data->fb_width = plane->fb_width;
541 win_data->fb_height = plane->fb_height;
542 win_data->dma_addr = plane->dma_addr[0] + offset;
543 win_data->bpp = plane->bpp;
544 win_data->pixel_format = plane->pixel_format;
545 win_data->buf_offsize = (plane->fb_width - plane->crtc_width) *
547 win_data->line_size = plane->crtc_width * (plane->bpp >> 3);
549 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
550 win_data->offset_x, win_data->offset_y);
551 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
552 win_data->ovl_width, win_data->ovl_height);
553 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
554 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
555 plane->fb_width, plane->crtc_width);
558 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win)
560 struct fimd_win_data *win_data = &ctx->win_data[win];
566 * In case of s3c64xx, window 0 doesn't support alpha channel.
567 * So the request format is ARGB8888 then change it to XRGB8888.
569 if (ctx->driver_data->has_limited_fmt && !win) {
570 if (win_data->pixel_format == DRM_FORMAT_ARGB8888)
571 win_data->pixel_format = DRM_FORMAT_XRGB8888;
574 switch (win_data->pixel_format) {
576 val |= WINCON0_BPPMODE_8BPP_PALETTE;
577 val |= WINCONx_BURSTLEN_8WORD;
578 val |= WINCONx_BYTSWP;
580 case DRM_FORMAT_XRGB1555:
581 val |= WINCON0_BPPMODE_16BPP_1555;
582 val |= WINCONx_HAWSWP;
583 val |= WINCONx_BURSTLEN_16WORD;
585 case DRM_FORMAT_RGB565:
586 val |= WINCON0_BPPMODE_16BPP_565;
587 val |= WINCONx_HAWSWP;
588 val |= WINCONx_BURSTLEN_16WORD;
590 case DRM_FORMAT_XRGB8888:
591 val |= WINCON0_BPPMODE_24BPP_888;
593 val |= WINCONx_BURSTLEN_16WORD;
595 case DRM_FORMAT_ARGB8888:
596 val |= WINCON1_BPPMODE_25BPP_A1888
597 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
599 val |= WINCONx_BURSTLEN_16WORD;
602 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
604 val |= WINCON0_BPPMODE_24BPP_888;
606 val |= WINCONx_BURSTLEN_16WORD;
610 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
613 * In case of exynos, setting dma-burst to 16Word causes permanent
614 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
615 * switching which is based on plane size is not recommended as
616 * plane size varies alot towards the end of the screen and rapid
617 * movement causes unstable DMA which results into iommu crash/tear.
620 if (win_data->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
621 val &= ~WINCONx_BURSTLEN_MASK;
622 val |= WINCONx_BURSTLEN_4WORD;
625 writel(val, ctx->regs + WINCON(win));
628 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
630 unsigned int keycon0 = 0, keycon1 = 0;
632 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
633 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
635 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
637 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
638 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
642 * shadow_protect_win() - disable updating values from shadow registers at vsync
644 * @win: window to protect registers for
645 * @protect: 1 to protect (disable updates)
647 static void fimd_shadow_protect_win(struct fimd_context *ctx,
648 int win, bool protect)
652 if (ctx->driver_data->has_shadowcon) {
654 bits = SHADOWCON_WINx_PROTECT(win);
657 bits = PRTCON_PROTECT;
660 val = readl(ctx->regs + reg);
665 writel(val, ctx->regs + reg);
668 static void fimd_win_commit(struct exynos_drm_crtc *crtc, int zpos)
670 struct fimd_context *ctx = crtc->ctx;
671 struct fimd_win_data *win_data;
673 unsigned long val, alpha, size;
680 if (win == DEFAULT_ZPOS)
681 win = ctx->default_win;
683 if (win < 0 || win >= WINDOWS_NR)
686 win_data = &ctx->win_data[win];
688 /* If suspended, enable this on resume */
689 if (ctx->suspended) {
690 win_data->resume = true;
695 * SHADOWCON/PRTCON register is used for enabling timing.
697 * for example, once only width value of a register is set,
698 * if the dma is started then fimd hardware could malfunction so
699 * with protect window setting, the register fields with prefix '_F'
700 * wouldn't be updated at vsync also but updated once unprotect window
704 /* protect windows */
705 fimd_shadow_protect_win(ctx, win, true);
707 /* buffer start address */
708 val = (unsigned long)win_data->dma_addr;
709 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
711 /* buffer end address */
712 size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
713 val = (unsigned long)(win_data->dma_addr + size);
714 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
716 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
717 (unsigned long)win_data->dma_addr, val, size);
718 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
719 win_data->ovl_width, win_data->ovl_height);
722 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
723 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) |
724 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) |
725 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size);
726 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
729 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
730 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) |
731 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) |
732 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y);
733 writel(val, ctx->regs + VIDOSD_A(win));
735 last_x = win_data->offset_x + win_data->ovl_width;
738 last_y = win_data->offset_y + win_data->ovl_height;
742 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
743 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
745 writel(val, ctx->regs + VIDOSD_B(win));
747 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
748 win_data->offset_x, win_data->offset_y, last_x, last_y);
750 /* hardware window 0 doesn't support alpha channel. */
753 alpha = VIDISD14C_ALPHA1_R(0xf) |
754 VIDISD14C_ALPHA1_G(0xf) |
755 VIDISD14C_ALPHA1_B(0xf);
757 writel(alpha, ctx->regs + VIDOSD_C(win));
761 if (win != 3 && win != 4) {
762 u32 offset = VIDOSD_D(win);
764 offset = VIDOSD_C(win);
765 val = win_data->ovl_width * win_data->ovl_height;
766 writel(val, ctx->regs + offset);
768 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
771 fimd_win_set_pixfmt(ctx, win);
773 /* hardware window 0 doesn't support color key. */
775 fimd_win_set_colkey(ctx, win);
777 fimd_enable_video_output(ctx, win, true);
779 if (ctx->driver_data->has_shadowcon)
780 fimd_enable_shadow_channel_path(ctx, win, true);
782 /* Enable DMA channel and unprotect windows */
783 fimd_shadow_protect_win(ctx, win, false);
785 win_data->enabled = true;
788 atomic_set(&ctx->win_updated, 1);
791 static void fimd_win_disable(struct exynos_drm_crtc *crtc, int zpos)
793 struct fimd_context *ctx = crtc->ctx;
794 struct fimd_win_data *win_data;
797 if (win == DEFAULT_ZPOS)
798 win = ctx->default_win;
800 if (win < 0 || win >= WINDOWS_NR)
803 win_data = &ctx->win_data[win];
805 if (ctx->suspended) {
806 /* do not resume this window*/
807 win_data->resume = false;
811 /* protect windows */
812 fimd_shadow_protect_win(ctx, win, true);
814 fimd_enable_video_output(ctx, win, false);
816 if (ctx->driver_data->has_shadowcon)
817 fimd_enable_shadow_channel_path(ctx, win, false);
819 /* unprotect windows */
820 fimd_shadow_protect_win(ctx, win, false);
822 win_data->enabled = false;
825 static void fimd_window_suspend(struct fimd_context *ctx)
827 struct fimd_win_data *win_data;
830 for (i = 0; i < WINDOWS_NR; i++) {
831 win_data = &ctx->win_data[i];
832 win_data->resume = win_data->enabled;
833 if (win_data->enabled)
834 fimd_win_disable(ctx->crtc, i);
838 static void fimd_window_resume(struct fimd_context *ctx)
840 struct fimd_win_data *win_data;
843 for (i = 0; i < WINDOWS_NR; i++) {
844 win_data = &ctx->win_data[i];
845 win_data->enabled = win_data->resume;
846 win_data->resume = false;
850 static void fimd_apply(struct fimd_context *ctx)
852 struct fimd_win_data *win_data;
855 for (i = 0; i < WINDOWS_NR; i++) {
856 win_data = &ctx->win_data[i];
857 if (win_data->enabled)
858 fimd_win_commit(ctx->crtc, i);
860 fimd_win_disable(ctx->crtc, i);
863 fimd_commit(ctx->crtc);
866 static int fimd_poweron(struct fimd_context *ctx)
873 ctx->suspended = false;
875 pm_runtime_get_sync(ctx->dev);
877 ret = clk_prepare_enable(ctx->bus_clk);
879 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
883 ret = clk_prepare_enable(ctx->lcd_clk);
885 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
889 /* if vblank was enabled status, enable it again. */
890 if (test_and_clear_bit(0, &ctx->irq_flags)) {
891 ret = fimd_enable_vblank(ctx->crtc);
893 DRM_ERROR("Failed to re-enable vblank [%d]\n", ret);
894 goto enable_vblank_err;
898 fimd_window_resume(ctx);
905 clk_disable_unprepare(ctx->lcd_clk);
907 clk_disable_unprepare(ctx->bus_clk);
909 ctx->suspended = true;
913 static int fimd_poweroff(struct fimd_context *ctx)
919 * We need to make sure that all windows are disabled before we
920 * suspend that connector. Otherwise we might try to scan from
921 * a destroyed buffer later.
923 fimd_window_suspend(ctx);
925 clk_disable_unprepare(ctx->lcd_clk);
926 clk_disable_unprepare(ctx->bus_clk);
928 pm_runtime_put_sync(ctx->dev);
930 ctx->suspended = true;
934 static void fimd_dpms(struct exynos_drm_crtc *crtc, int mode)
936 DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
939 case DRM_MODE_DPMS_ON:
940 fimd_poweron(crtc->ctx);
942 case DRM_MODE_DPMS_STANDBY:
943 case DRM_MODE_DPMS_SUSPEND:
944 case DRM_MODE_DPMS_OFF:
945 fimd_poweroff(crtc->ctx);
948 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
953 static void fimd_trigger(struct device *dev)
955 struct fimd_context *ctx = dev_get_drvdata(dev);
956 struct fimd_driver_data *driver_data = ctx->driver_data;
957 void *timing_base = ctx->regs + driver_data->timing_base;
961 * Skips triggering if in triggering state, because multiple triggering
962 * requests can cause panel reset.
964 if (atomic_read(&ctx->triggering))
967 /* Enters triggering mode */
968 atomic_set(&ctx->triggering, 1);
970 reg = readl(timing_base + TRIGCON);
971 reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
972 writel(reg, timing_base + TRIGCON);
975 * Exits triggering mode if vblank is not enabled yet, because when the
976 * VIDINTCON0 register is not set, it can not exit from triggering mode.
978 if (!test_bit(0, &ctx->irq_flags))
979 atomic_set(&ctx->triggering, 0);
982 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
984 struct fimd_context *ctx = crtc->ctx;
986 /* Checks the crtc is detached already from encoder */
987 if (ctx->pipe < 0 || !ctx->drm_dev)
991 * If there is a page flip request, triggers and handles the page flip
992 * event so that current fb can be updated into panel GRAM.
994 if (atomic_add_unless(&ctx->win_updated, -1, 0))
995 fimd_trigger(ctx->dev);
997 /* Wakes up vsync event queue */
998 if (atomic_read(&ctx->wait_vsync_event)) {
999 atomic_set(&ctx->wait_vsync_event, 0);
1000 wake_up(&ctx->wait_vsync_queue);
1003 if (test_bit(0, &ctx->irq_flags))
1004 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1007 static struct exynos_drm_crtc_ops fimd_crtc_ops = {
1009 .mode_fixup = fimd_mode_fixup,
1010 .commit = fimd_commit,
1011 .enable_vblank = fimd_enable_vblank,
1012 .disable_vblank = fimd_disable_vblank,
1013 .wait_for_vblank = fimd_wait_for_vblank,
1014 .win_mode_set = fimd_win_mode_set,
1015 .win_commit = fimd_win_commit,
1016 .win_disable = fimd_win_disable,
1017 .te_handler = fimd_te_handler,
1020 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
1022 struct fimd_context *ctx = (struct fimd_context *)dev_id;
1025 val = readl(ctx->regs + VIDINTCON1);
1027 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
1028 if (val & clear_bit)
1029 writel(clear_bit, ctx->regs + VIDINTCON1);
1031 /* check the crtc is detached already from encoder */
1032 if (ctx->pipe < 0 || !ctx->drm_dev)
1036 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1038 /* Exits triggering mode */
1039 atomic_set(&ctx->triggering, 0);
1041 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1042 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1044 /* set wait vsync event to zero and wake up queue. */
1045 if (atomic_read(&ctx->wait_vsync_event)) {
1046 atomic_set(&ctx->wait_vsync_event, 0);
1047 wake_up(&ctx->wait_vsync_queue);
1055 static int fimd_bind(struct device *dev, struct device *master, void *data)
1057 struct fimd_context *ctx = dev_get_drvdata(dev);
1058 struct drm_device *drm_dev = data;
1061 ret = fimd_ctx_initialize(ctx, drm_dev);
1063 DRM_ERROR("fimd_ctx_initialize failed.\n");
1067 ctx->crtc = exynos_drm_crtc_create(drm_dev, ctx->pipe,
1068 EXYNOS_DISPLAY_TYPE_LCD,
1069 &fimd_crtc_ops, ctx);
1070 if (IS_ERR(ctx->crtc)) {
1071 fimd_ctx_remove(ctx);
1072 return PTR_ERR(ctx->crtc);
1076 exynos_drm_create_enc_conn(drm_dev, ctx->display);
1082 static void fimd_unbind(struct device *dev, struct device *master,
1085 struct fimd_context *ctx = dev_get_drvdata(dev);
1087 fimd_dpms(ctx->crtc, DRM_MODE_DPMS_OFF);
1090 exynos_dpi_remove(ctx->display);
1092 fimd_ctx_remove(ctx);
1095 static const struct component_ops fimd_component_ops = {
1097 .unbind = fimd_unbind,
1100 static int fimd_probe(struct platform_device *pdev)
1102 struct device *dev = &pdev->dev;
1103 struct fimd_context *ctx;
1104 struct device_node *i80_if_timings;
1105 struct resource *res;
1111 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1115 ret = exynos_drm_component_add(dev, EXYNOS_DEVICE_TYPE_CRTC,
1116 EXYNOS_DISPLAY_TYPE_LCD);
1121 ctx->suspended = true;
1122 ctx->driver_data = drm_fimd_get_driver_data(pdev);
1124 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1125 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1126 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1127 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1129 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1130 if (i80_if_timings) {
1135 if (ctx->driver_data->has_vidoutcon)
1136 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1138 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1140 * The user manual describes that this "DSI_EN" bit is required
1141 * to enable I80 24-bit data interface.
1143 ctx->vidcon0 |= VIDCON0_DSI_EN;
1145 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1147 ctx->i80ifcon = LCD_CS_SETUP(val);
1148 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1150 ctx->i80ifcon |= LCD_WR_SETUP(val);
1151 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1153 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1154 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1156 ctx->i80ifcon |= LCD_WR_HOLD(val);
1158 of_node_put(i80_if_timings);
1160 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1162 if (IS_ERR(ctx->sysreg)) {
1163 dev_warn(dev, "failed to get system register.\n");
1167 ctx->bus_clk = devm_clk_get(dev, "fimd");
1168 if (IS_ERR(ctx->bus_clk)) {
1169 dev_err(dev, "failed to get bus clock\n");
1170 ret = PTR_ERR(ctx->bus_clk);
1171 goto err_del_component;
1174 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1175 if (IS_ERR(ctx->lcd_clk)) {
1176 dev_err(dev, "failed to get lcd clock\n");
1177 ret = PTR_ERR(ctx->lcd_clk);
1178 goto err_del_component;
1181 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1183 ctx->regs = devm_ioremap_resource(dev, res);
1184 if (IS_ERR(ctx->regs)) {
1185 ret = PTR_ERR(ctx->regs);
1186 goto err_del_component;
1189 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1190 ctx->i80_if ? "lcd_sys" : "vsync");
1192 dev_err(dev, "irq request failed.\n");
1194 goto err_del_component;
1197 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1198 0, "drm_fimd", ctx);
1200 dev_err(dev, "irq request failed.\n");
1201 goto err_del_component;
1204 init_waitqueue_head(&ctx->wait_vsync_queue);
1205 atomic_set(&ctx->wait_vsync_event, 0);
1207 platform_set_drvdata(pdev, ctx);
1209 ctx->display = exynos_dpi_probe(dev);
1210 if (IS_ERR(ctx->display)) {
1211 ret = PTR_ERR(ctx->display);
1212 goto err_del_component;
1215 pm_runtime_enable(dev);
1217 ret = component_add(dev, &fimd_component_ops);
1219 goto err_disable_pm_runtime;
1223 err_disable_pm_runtime:
1224 pm_runtime_disable(dev);
1227 exynos_drm_component_del(dev, EXYNOS_DEVICE_TYPE_CRTC);
1231 static int fimd_remove(struct platform_device *pdev)
1233 pm_runtime_disable(&pdev->dev);
1235 component_del(&pdev->dev, &fimd_component_ops);
1236 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1241 struct platform_driver fimd_driver = {
1242 .probe = fimd_probe,
1243 .remove = fimd_remove,
1245 .name = "exynos4-fb",
1246 .owner = THIS_MODULE,
1247 .of_match_table = fimd_driver_dt_match,