3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <linux/pm_runtime.h>
22 #include <drm/exynos_drm.h>
23 #include <plat/regs-fb-v4.h>
25 #include "exynos_drm_drv.h"
26 #include "exynos_drm_fbdev.h"
27 #include "exynos_drm_crtc.h"
30 * FIMD is stand for Fully Interactive Mobile Display and
31 * as a display controller, it transfers contents drawn on memory
32 * to a LCD Panel through Display Interfaces such as RGB or
36 /* position control register for hardware window 0, 2 ~ 4.*/
37 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
38 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
39 /* size control register for hardware window 0. */
40 #define VIDOSD_C_SIZE_W0 (VIDOSD_BASE + 0x08)
41 /* alpha control register for hardware window 1 ~ 4. */
42 #define VIDOSD_C(win) (VIDOSD_BASE + 0x18 + (win) * 16)
43 /* size control register for hardware window 1 ~ 4. */
44 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
46 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
47 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
48 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
50 /* color key control register for hardware window 1 ~ 4. */
51 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + (x * 8))
52 /* color key value register for hardware window 1 ~ 4. */
53 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + (x * 8))
55 /* FIMD has totally five hardware windows. */
58 #define get_fimd_context(dev) platform_get_drvdata(to_platform_device(dev))
60 struct fimd_win_data {
61 unsigned int offset_x;
62 unsigned int offset_y;
63 unsigned int ovl_width;
64 unsigned int ovl_height;
65 unsigned int fb_width;
66 unsigned int fb_height;
70 unsigned int buf_offsize;
71 unsigned int line_size; /* bytes */
76 struct exynos_drm_subdrv subdrv;
78 struct drm_crtc *crtc;
81 struct resource *regs_res;
83 struct fimd_win_data win_data[WINDOWS_NR];
85 unsigned int default_win;
86 unsigned long irq_flags;
91 struct fb_videomode *timing;
94 static bool fimd_display_is_connected(struct device *dev)
96 DRM_DEBUG_KMS("%s\n", __FILE__);
103 static void *fimd_get_timing(struct device *dev)
105 struct fimd_context *ctx = get_fimd_context(dev);
107 DRM_DEBUG_KMS("%s\n", __FILE__);
112 static int fimd_check_timing(struct device *dev, void *timing)
114 DRM_DEBUG_KMS("%s\n", __FILE__);
121 static int fimd_display_power_on(struct device *dev, int mode)
123 DRM_DEBUG_KMS("%s\n", __FILE__);
130 static struct exynos_drm_display_ops fimd_display_ops = {
131 .type = EXYNOS_DISPLAY_TYPE_LCD,
132 .is_connected = fimd_display_is_connected,
133 .get_timing = fimd_get_timing,
134 .check_timing = fimd_check_timing,
135 .power_on = fimd_display_power_on,
138 static void fimd_dpms(struct device *subdrv_dev, int mode)
140 DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
143 case DRM_MODE_DPMS_ON:
144 pm_runtime_get_sync(subdrv_dev);
146 case DRM_MODE_DPMS_STANDBY:
147 case DRM_MODE_DPMS_SUSPEND:
148 case DRM_MODE_DPMS_OFF:
149 pm_runtime_put_sync(subdrv_dev);
152 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
157 static void fimd_apply(struct device *subdrv_dev)
159 struct fimd_context *ctx = get_fimd_context(subdrv_dev);
160 struct exynos_drm_manager *mgr = &ctx->subdrv.manager;
161 struct exynos_drm_manager_ops *mgr_ops = mgr->ops;
162 struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops;
163 struct fimd_win_data *win_data;
166 DRM_DEBUG_KMS("%s\n", __FILE__);
168 for (i = 0; i < WINDOWS_NR; i++) {
169 win_data = &ctx->win_data[i];
170 if (win_data->enabled && (ovl_ops && ovl_ops->commit))
171 ovl_ops->commit(subdrv_dev, i);
174 if (mgr_ops && mgr_ops->commit)
175 mgr_ops->commit(subdrv_dev);
178 static void fimd_commit(struct device *dev)
180 struct fimd_context *ctx = get_fimd_context(dev);
181 struct fb_videomode *timing = ctx->timing;
187 DRM_DEBUG_KMS("%s\n", __FILE__);
189 /* setup polarity values from machine code. */
190 writel(ctx->vidcon1, ctx->regs + VIDCON1);
192 /* setup vertical timing values. */
193 val = VIDTCON0_VBPD(timing->upper_margin - 1) |
194 VIDTCON0_VFPD(timing->lower_margin - 1) |
195 VIDTCON0_VSPW(timing->vsync_len - 1);
196 writel(val, ctx->regs + VIDTCON0);
198 /* setup horizontal timing values. */
199 val = VIDTCON1_HBPD(timing->left_margin - 1) |
200 VIDTCON1_HFPD(timing->right_margin - 1) |
201 VIDTCON1_HSPW(timing->hsync_len - 1);
202 writel(val, ctx->regs + VIDTCON1);
204 /* setup horizontal and vertical display size. */
205 val = VIDTCON2_LINEVAL(timing->yres - 1) |
206 VIDTCON2_HOZVAL(timing->xres - 1);
207 writel(val, ctx->regs + VIDTCON2);
209 /* setup clock source, clock divider, enable dma. */
211 val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
214 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
216 val &= ~VIDCON0_CLKDIR; /* 1:1 clock */
219 * fields of register with prefix '_F' would be updated
220 * at vsync(same as dma start)
222 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
223 writel(val, ctx->regs + VIDCON0);
226 static int fimd_enable_vblank(struct device *dev)
228 struct fimd_context *ctx = get_fimd_context(dev);
231 DRM_DEBUG_KMS("%s\n", __FILE__);
236 if (!test_and_set_bit(0, &ctx->irq_flags)) {
237 val = readl(ctx->regs + VIDINTCON0);
239 val |= VIDINTCON0_INT_ENABLE;
240 val |= VIDINTCON0_INT_FRAME;
242 val &= ~VIDINTCON0_FRAMESEL0_MASK;
243 val |= VIDINTCON0_FRAMESEL0_VSYNC;
244 val &= ~VIDINTCON0_FRAMESEL1_MASK;
245 val |= VIDINTCON0_FRAMESEL1_NONE;
247 writel(val, ctx->regs + VIDINTCON0);
253 static void fimd_disable_vblank(struct device *dev)
255 struct fimd_context *ctx = get_fimd_context(dev);
258 DRM_DEBUG_KMS("%s\n", __FILE__);
263 if (test_and_clear_bit(0, &ctx->irq_flags)) {
264 val = readl(ctx->regs + VIDINTCON0);
266 val &= ~VIDINTCON0_INT_FRAME;
267 val &= ~VIDINTCON0_INT_ENABLE;
269 writel(val, ctx->regs + VIDINTCON0);
273 static struct exynos_drm_manager_ops fimd_manager_ops = {
276 .commit = fimd_commit,
277 .enable_vblank = fimd_enable_vblank,
278 .disable_vblank = fimd_disable_vblank,
281 static void fimd_win_mode_set(struct device *dev,
282 struct exynos_drm_overlay *overlay)
284 struct fimd_context *ctx = get_fimd_context(dev);
285 struct fimd_win_data *win_data;
287 unsigned long offset;
289 DRM_DEBUG_KMS("%s\n", __FILE__);
292 dev_err(dev, "overlay is NULL\n");
297 if (win == DEFAULT_ZPOS)
298 win = ctx->default_win;
300 if (win < 0 || win > WINDOWS_NR)
303 offset = overlay->fb_x * (overlay->bpp >> 3);
304 offset += overlay->fb_y * overlay->pitch;
306 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
308 win_data = &ctx->win_data[win];
310 win_data->offset_x = overlay->crtc_x;
311 win_data->offset_y = overlay->crtc_y;
312 win_data->ovl_width = overlay->crtc_width;
313 win_data->ovl_height = overlay->crtc_height;
314 win_data->fb_width = overlay->fb_width;
315 win_data->fb_height = overlay->fb_height;
316 win_data->dma_addr = overlay->dma_addr + offset;
317 win_data->vaddr = overlay->vaddr + offset;
318 win_data->bpp = overlay->bpp;
319 win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
321 win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
323 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
324 win_data->offset_x, win_data->offset_y);
325 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
326 win_data->ovl_width, win_data->ovl_height);
327 DRM_DEBUG_KMS("paddr = 0x%lx, vaddr = 0x%lx\n",
328 (unsigned long)win_data->dma_addr,
329 (unsigned long)win_data->vaddr);
330 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
331 overlay->fb_width, overlay->crtc_width);
334 static void fimd_win_set_pixfmt(struct device *dev, unsigned int win)
336 struct fimd_context *ctx = get_fimd_context(dev);
337 struct fimd_win_data *win_data = &ctx->win_data[win];
340 DRM_DEBUG_KMS("%s\n", __FILE__);
344 switch (win_data->bpp) {
346 val |= WINCON0_BPPMODE_1BPP;
347 val |= WINCONx_BITSWP;
348 val |= WINCONx_BURSTLEN_4WORD;
351 val |= WINCON0_BPPMODE_2BPP;
352 val |= WINCONx_BITSWP;
353 val |= WINCONx_BURSTLEN_8WORD;
356 val |= WINCON0_BPPMODE_4BPP;
357 val |= WINCONx_BITSWP;
358 val |= WINCONx_BURSTLEN_8WORD;
361 val |= WINCON0_BPPMODE_8BPP_PALETTE;
362 val |= WINCONx_BURSTLEN_8WORD;
363 val |= WINCONx_BYTSWP;
366 val |= WINCON0_BPPMODE_16BPP_565;
367 val |= WINCONx_HAWSWP;
368 val |= WINCONx_BURSTLEN_16WORD;
371 val |= WINCON0_BPPMODE_24BPP_888;
373 val |= WINCONx_BURSTLEN_16WORD;
376 val |= WINCON1_BPPMODE_28BPP_A4888
377 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
379 val |= WINCONx_BURSTLEN_16WORD;
382 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
384 val |= WINCON0_BPPMODE_24BPP_888;
386 val |= WINCONx_BURSTLEN_16WORD;
390 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
392 writel(val, ctx->regs + WINCON(win));
395 static void fimd_win_set_colkey(struct device *dev, unsigned int win)
397 struct fimd_context *ctx = get_fimd_context(dev);
398 unsigned int keycon0 = 0, keycon1 = 0;
400 DRM_DEBUG_KMS("%s\n", __FILE__);
402 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
403 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
405 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
407 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
408 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
411 static void fimd_win_commit(struct device *dev, int zpos)
413 struct fimd_context *ctx = get_fimd_context(dev);
414 struct fimd_win_data *win_data;
416 unsigned long val, alpha, size;
418 DRM_DEBUG_KMS("%s\n", __FILE__);
423 if (win == DEFAULT_ZPOS)
424 win = ctx->default_win;
426 if (win < 0 || win > WINDOWS_NR)
429 win_data = &ctx->win_data[win];
432 * SHADOWCON register is used for enabling timing.
434 * for example, once only width value of a register is set,
435 * if the dma is started then fimd hardware could malfunction so
436 * with protect window setting, the register fields with prefix '_F'
437 * wouldn't be updated at vsync also but updated once unprotect window
441 /* protect windows */
442 val = readl(ctx->regs + SHADOWCON);
443 val |= SHADOWCON_WINx_PROTECT(win);
444 writel(val, ctx->regs + SHADOWCON);
446 /* buffer start address */
447 val = (unsigned long)win_data->dma_addr;
448 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
450 /* buffer end address */
451 size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
452 val = (unsigned long)(win_data->dma_addr + size);
453 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
455 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
456 (unsigned long)win_data->dma_addr, val, size);
457 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
458 win_data->ovl_width, win_data->ovl_height);
461 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
462 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size);
463 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
466 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
467 VIDOSDxA_TOPLEFT_Y(win_data->offset_y);
468 writel(val, ctx->regs + VIDOSD_A(win));
470 val = VIDOSDxB_BOTRIGHT_X(win_data->offset_x +
471 win_data->ovl_width - 1) |
472 VIDOSDxB_BOTRIGHT_Y(win_data->offset_y +
473 win_data->ovl_height - 1);
474 writel(val, ctx->regs + VIDOSD_B(win));
476 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
477 win_data->offset_x, win_data->offset_y,
478 win_data->offset_x + win_data->ovl_width - 1,
479 win_data->offset_y + win_data->ovl_height - 1);
481 /* hardware window 0 doesn't support alpha channel. */
484 alpha = VIDISD14C_ALPHA1_R(0xf) |
485 VIDISD14C_ALPHA1_G(0xf) |
486 VIDISD14C_ALPHA1_B(0xf);
488 writel(alpha, ctx->regs + VIDOSD_C(win));
492 if (win != 3 && win != 4) {
493 u32 offset = VIDOSD_D(win);
495 offset = VIDOSD_C_SIZE_W0;
496 val = win_data->ovl_width * win_data->ovl_height;
497 writel(val, ctx->regs + offset);
499 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
502 fimd_win_set_pixfmt(dev, win);
504 /* hardware window 0 doesn't support color key. */
506 fimd_win_set_colkey(dev, win);
509 val = readl(ctx->regs + WINCON(win));
510 val |= WINCONx_ENWIN;
511 writel(val, ctx->regs + WINCON(win));
513 /* Enable DMA channel and unprotect windows */
514 val = readl(ctx->regs + SHADOWCON);
515 val |= SHADOWCON_CHx_ENABLE(win);
516 val &= ~SHADOWCON_WINx_PROTECT(win);
517 writel(val, ctx->regs + SHADOWCON);
519 win_data->enabled = true;
522 static void fimd_win_disable(struct device *dev, int zpos)
524 struct fimd_context *ctx = get_fimd_context(dev);
525 struct fimd_win_data *win_data;
529 DRM_DEBUG_KMS("%s\n", __FILE__);
531 if (win == DEFAULT_ZPOS)
532 win = ctx->default_win;
534 if (win < 0 || win > WINDOWS_NR)
537 win_data = &ctx->win_data[win];
539 /* protect windows */
540 val = readl(ctx->regs + SHADOWCON);
541 val |= SHADOWCON_WINx_PROTECT(win);
542 writel(val, ctx->regs + SHADOWCON);
545 val = readl(ctx->regs + WINCON(win));
546 val &= ~WINCONx_ENWIN;
547 writel(val, ctx->regs + WINCON(win));
549 /* unprotect windows */
550 val = readl(ctx->regs + SHADOWCON);
551 val &= ~SHADOWCON_CHx_ENABLE(win);
552 val &= ~SHADOWCON_WINx_PROTECT(win);
553 writel(val, ctx->regs + SHADOWCON);
555 win_data->enabled = false;
558 static struct exynos_drm_overlay_ops fimd_overlay_ops = {
559 .mode_set = fimd_win_mode_set,
560 .commit = fimd_win_commit,
561 .disable = fimd_win_disable,
564 static void fimd_finish_pageflip(struct drm_device *drm_dev, int crtc)
566 struct exynos_drm_private *dev_priv = drm_dev->dev_private;
567 struct drm_pending_vblank_event *e, *t;
570 bool is_checked = false;
572 spin_lock_irqsave(&drm_dev->event_lock, flags);
574 list_for_each_entry_safe(e, t, &dev_priv->pageflip_event_list,
576 /* if event's pipe isn't same as crtc then ignore it. */
582 do_gettimeofday(&now);
583 e->event.sequence = 0;
584 e->event.tv_sec = now.tv_sec;
585 e->event.tv_usec = now.tv_usec;
587 list_move_tail(&e->base.link, &e->base.file_priv->event_list);
588 wake_up_interruptible(&e->base.file_priv->event_wait);
592 drm_vblank_put(drm_dev, crtc);
595 * don't off vblank if vblank_disable_allowed is 1,
596 * because vblank would be off by timer handler.
598 if (!drm_dev->vblank_disable_allowed)
599 drm_vblank_off(drm_dev, crtc);
602 spin_unlock_irqrestore(&drm_dev->event_lock, flags);
605 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
607 struct fimd_context *ctx = (struct fimd_context *)dev_id;
608 struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
609 struct drm_device *drm_dev = subdrv->drm_dev;
610 struct exynos_drm_manager *manager = &subdrv->manager;
613 val = readl(ctx->regs + VIDINTCON1);
615 if (val & VIDINTCON1_INT_FRAME)
616 /* VSYNC interrupt */
617 writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1);
619 /* check the crtc is detached already from encoder */
620 if (manager->pipe < 0)
623 drm_handle_vblank(drm_dev, manager->pipe);
624 fimd_finish_pageflip(drm_dev, manager->pipe);
630 static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
632 DRM_DEBUG_KMS("%s\n", __FILE__);
635 * enable drm irq mode.
636 * - with irq_enabled = 1, we can use the vblank feature.
638 * P.S. note that we wouldn't use drm irq handler but
639 * just specific driver own one instead because
640 * drm framework supports only one irq handler.
642 drm_dev->irq_enabled = 1;
645 * with vblank_disable_allowed = 1, vblank interrupt will be disabled
646 * by drm timer once a current process gives up ownership of
647 * vblank event.(after drm_vblank_put function is called)
649 drm_dev->vblank_disable_allowed = 1;
654 static void fimd_subdrv_remove(struct drm_device *drm_dev)
656 DRM_DEBUG_KMS("%s\n", __FILE__);
661 static int fimd_calc_clkdiv(struct fimd_context *ctx,
662 struct fb_videomode *timing)
664 unsigned long clk = clk_get_rate(ctx->lcd_clk);
667 u32 best_framerate = 0;
670 DRM_DEBUG_KMS("%s\n", __FILE__);
672 retrace = timing->left_margin + timing->hsync_len +
673 timing->right_margin + timing->xres;
674 retrace *= timing->upper_margin + timing->vsync_len +
675 timing->lower_margin + timing->yres;
677 /* default framerate is 60Hz */
678 if (!timing->refresh)
679 timing->refresh = 60;
683 for (clkdiv = 1; clkdiv < 0x100; clkdiv++) {
686 /* get best framerate */
687 framerate = clk / clkdiv;
688 tmp = timing->refresh - framerate;
690 best_framerate = framerate;
694 best_framerate = framerate;
695 else if (tmp < (best_framerate - framerate))
696 best_framerate = framerate;
704 static void fimd_clear_win(struct fimd_context *ctx, int win)
708 DRM_DEBUG_KMS("%s\n", __FILE__);
710 writel(0, ctx->regs + WINCON(win));
711 writel(0, ctx->regs + VIDOSD_A(win));
712 writel(0, ctx->regs + VIDOSD_B(win));
713 writel(0, ctx->regs + VIDOSD_C(win));
715 if (win == 1 || win == 2)
716 writel(0, ctx->regs + VIDOSD_D(win));
718 val = readl(ctx->regs + SHADOWCON);
719 val &= ~SHADOWCON_WINx_PROTECT(win);
720 writel(val, ctx->regs + SHADOWCON);
723 static int __devinit fimd_probe(struct platform_device *pdev)
725 struct device *dev = &pdev->dev;
726 struct fimd_context *ctx;
727 struct exynos_drm_subdrv *subdrv;
728 struct exynos_drm_fimd_pdata *pdata;
729 struct fb_videomode *timing;
730 struct resource *res;
734 DRM_DEBUG_KMS("%s\n", __FILE__);
736 pdata = pdev->dev.platform_data;
738 dev_err(dev, "no platform data specified\n");
742 timing = &pdata->timing;
744 dev_err(dev, "timing is null.\n");
748 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
752 ctx->bus_clk = clk_get(dev, "fimd");
753 if (IS_ERR(ctx->bus_clk)) {
754 dev_err(dev, "failed to get bus clock\n");
755 ret = PTR_ERR(ctx->bus_clk);
759 clk_enable(ctx->bus_clk);
761 ctx->lcd_clk = clk_get(dev, "sclk_fimd");
762 if (IS_ERR(ctx->lcd_clk)) {
763 dev_err(dev, "failed to get lcd clock\n");
764 ret = PTR_ERR(ctx->lcd_clk);
768 clk_enable(ctx->lcd_clk);
770 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
772 dev_err(dev, "failed to find registers\n");
777 ctx->regs_res = request_mem_region(res->start, resource_size(res),
779 if (!ctx->regs_res) {
780 dev_err(dev, "failed to claim register region\n");
785 ctx->regs = ioremap(res->start, resource_size(res));
787 dev_err(dev, "failed to map registers\n");
789 goto err_req_region_io;
792 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
794 dev_err(dev, "irq request failed.\n");
795 goto err_req_region_irq;
798 ctx->irq = res->start;
800 ret = request_irq(ctx->irq, fimd_irq_handler, 0, "drm_fimd", ctx);
802 dev_err(dev, "irq request failed.\n");
806 pm_runtime_set_active(dev);
807 pm_runtime_enable(dev);
808 pm_runtime_get_sync(dev);
810 for (win = 0; win < WINDOWS_NR; win++)
811 fimd_clear_win(ctx, win);
813 ctx->clkdiv = fimd_calc_clkdiv(ctx, timing);
814 ctx->vidcon0 = pdata->vidcon0;
815 ctx->vidcon1 = pdata->vidcon1;
816 ctx->default_win = pdata->default_win;
817 ctx->timing = timing;
819 timing->pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
821 DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
822 timing->pixclock, ctx->clkdiv);
824 subdrv = &ctx->subdrv;
826 subdrv->probe = fimd_subdrv_probe;
827 subdrv->remove = fimd_subdrv_remove;
828 subdrv->manager.pipe = -1;
829 subdrv->manager.ops = &fimd_manager_ops;
830 subdrv->manager.overlay_ops = &fimd_overlay_ops;
831 subdrv->manager.display_ops = &fimd_display_ops;
832 subdrv->manager.dev = dev;
834 platform_set_drvdata(pdev, ctx);
835 exynos_drm_subdrv_register(subdrv);
844 release_resource(ctx->regs_res);
845 kfree(ctx->regs_res);
848 clk_disable(ctx->lcd_clk);
849 clk_put(ctx->lcd_clk);
852 clk_disable(ctx->bus_clk);
853 clk_put(ctx->bus_clk);
860 static int __devexit fimd_remove(struct platform_device *pdev)
862 struct device *dev = &pdev->dev;
863 struct fimd_context *ctx = platform_get_drvdata(pdev);
865 DRM_DEBUG_KMS("%s\n", __FILE__);
867 exynos_drm_subdrv_unregister(&ctx->subdrv);
872 clk_disable(ctx->lcd_clk);
873 clk_disable(ctx->bus_clk);
875 pm_runtime_set_suspended(dev);
876 pm_runtime_put_sync(dev);
879 pm_runtime_disable(dev);
881 clk_put(ctx->lcd_clk);
882 clk_put(ctx->bus_clk);
885 release_resource(ctx->regs_res);
886 kfree(ctx->regs_res);
887 free_irq(ctx->irq, ctx);
894 #ifdef CONFIG_PM_SLEEP
895 static int fimd_suspend(struct device *dev)
897 struct fimd_context *ctx = get_fimd_context(dev);
900 if (pm_runtime_suspended(dev))
903 ret = pm_runtime_suspend(dev);
907 ctx->suspended = true;
911 static int fimd_resume(struct device *dev)
913 struct fimd_context *ctx = get_fimd_context(dev);
916 ret = pm_runtime_resume(dev);
918 DRM_ERROR("failed to resume runtime pm.\n");
922 pm_runtime_disable(dev);
924 ret = pm_runtime_set_active(dev);
926 DRM_ERROR("failed to active runtime pm.\n");
927 pm_runtime_enable(dev);
928 pm_runtime_suspend(dev);
932 pm_runtime_enable(dev);
934 ctx->suspended = false;
939 #ifdef CONFIG_PM_RUNTIME
940 static int fimd_runtime_suspend(struct device *dev)
942 struct fimd_context *ctx = get_fimd_context(dev);
944 DRM_DEBUG_KMS("%s\n", __FILE__);
946 clk_disable(ctx->lcd_clk);
947 clk_disable(ctx->bus_clk);
949 ctx->suspended = true;
953 static int fimd_runtime_resume(struct device *dev)
955 struct fimd_context *ctx = get_fimd_context(dev);
958 DRM_DEBUG_KMS("%s\n", __FILE__);
960 ret = clk_enable(ctx->bus_clk);
964 ret = clk_enable(ctx->lcd_clk);
966 clk_disable(ctx->bus_clk);
970 ctx->suspended = false;
972 /* if vblank was enabled status, enable it again. */
973 if (test_and_clear_bit(0, &ctx->irq_flags))
974 fimd_enable_vblank(dev);
982 static const struct dev_pm_ops fimd_pm_ops = {
983 SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume)
984 SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL)
987 static struct platform_driver fimd_driver = {
989 .remove = __devexit_p(fimd_remove),
991 .name = "exynos4-fb",
992 .owner = THIS_MODULE,
997 static int __init fimd_init(void)
999 return platform_driver_register(&fimd_driver);
1002 static void __exit fimd_exit(void)
1004 platform_driver_unregister(&fimd_driver);
1007 module_init(fimd_init);
1008 module_exit(fimd_exit);
1010 MODULE_AUTHOR("Joonyoung Shim <jy0922.shim@samsung.com>");
1011 MODULE_AUTHOR("Inki Dae <inki.dae@samsung.com>");
1012 MODULE_DESCRIPTION("Samsung DRM FIMD Driver");
1013 MODULE_LICENSE("GPL");