2 * Copyright (C) 2012 Samsung Electronics Co.Ltd
4 * Eunchul Kim <chulspro.kim@samsung.com>
5 * Jinyoung Jeon <jy0.jeon@samsung.com>
6 * Sangmin Lee <lsmin.lee@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/clk.h>
17 #include <linux/pm_runtime.h>
18 #include <plat/map-base.h>
21 #include <drm/exynos_drm.h>
23 #include "exynos_drm_drv.h"
24 #include "exynos_drm_ipp.h"
25 #include "exynos_drm_gsc.h"
28 * GSC stands for General SCaler and
29 * supports image scaler/rotator and input/output DMA operations.
30 * input DMA reads image data from the memory.
31 * output DMA writes image data to memory.
32 * GSC supports image rotation and image effect functions.
34 * M2M operation : supports crop/scale/rotation/csc so on.
35 * Memory ----> GSC H/W ----> Memory.
36 * Writeback operation : supports cloned screen with FIMD.
37 * FIMD ----> GSC H/W ----> Memory.
38 * Output operation : supports direct display using local path.
39 * Memory ----> GSC H/W ----> FIMD, Mixer.
44 * 1. check suspend/resume api if needed.
45 * 2. need to check use case platform_device_id.
46 * 3. check src/dst size with, height.
47 * 4. added check_prepare api for right register.
48 * 5. need to add supported list in prop_list.
49 * 6. check prescaler/scaler optimization.
52 #define GSC_MAX_DEVS 4
54 #define GSC_MAX_DST 16
55 #define GSC_RESET_TIMEOUT 50
56 #define GSC_BUF_STOP 1
57 #define GSC_BUF_START 2
59 #define GSC_WIDTH_ITU_709 1280
60 #define GSC_SC_UP_MAX_RATIO 65536
61 #define GSC_SC_DOWN_RATIO_7_8 74898
62 #define GSC_SC_DOWN_RATIO_6_8 87381
63 #define GSC_SC_DOWN_RATIO_5_8 104857
64 #define GSC_SC_DOWN_RATIO_4_8 131072
65 #define GSC_SC_DOWN_RATIO_3_8 174762
66 #define GSC_SC_DOWN_RATIO_2_8 262144
67 #define GSC_REFRESH_MIN 12
68 #define GSC_REFRESH_MAX 60
69 #define GSC_CROP_MAX 8192
70 #define GSC_CROP_MIN 32
71 #define GSC_SCALE_MAX 4224
72 #define GSC_SCALE_MIN 32
73 #define GSC_COEF_RATIO 7
74 #define GSC_COEF_PHASE 9
75 #define GSC_COEF_ATTR 16
76 #define GSC_COEF_H_8T 8
77 #define GSC_COEF_V_4T 4
78 #define GSC_COEF_DEPTH 3
80 #define get_gsc_context(dev) platform_get_drvdata(to_platform_device(dev))
81 #define get_ctx_from_ippdrv(ippdrv) container_of(ippdrv,\
82 struct gsc_context, ippdrv);
83 #define gsc_read(offset) readl(ctx->regs + (offset))
84 #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset))
87 * A structure of scaler.
89 * @range: narrow, wide.
90 * @pre_shfactor: pre sclaer shift factor.
91 * @pre_hratio: horizontal ratio of the prescaler.
92 * @pre_vratio: vertical ratio of the prescaler.
93 * @main_hratio: the main scaler's horizontal ratio.
94 * @main_vratio: the main scaler's vertical ratio.
101 unsigned long main_hratio;
102 unsigned long main_vratio;
106 * A structure of scaler capability.
108 * find user manual 49.2 features.
109 * @tile_w: tile mode or rotation width.
110 * @tile_h: tile mode or rotation height.
111 * @w: other cases width.
112 * @h: other cases height.
114 struct gsc_capability {
115 /* tile or rotation */
124 * A structure of gsc context.
126 * @ippdrv: prepare initialization using ippdrv.
127 * @regs_res: register resources.
128 * @regs: memory mapped io registers.
129 * @lock: locking of operations.
130 * @gsc_clk: gsc gate clock.
131 * @sc: scaler infomations.
134 * @rotation: supports rotation of src.
135 * @suspended: qos operations.
138 struct exynos_drm_ippdrv ippdrv;
139 struct resource *regs_res;
143 struct gsc_scaler sc;
150 /* 8-tap Filter Coefficient */
151 static const int h_coef_8t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_H_8T] = {
152 { /* Ratio <= 65536 (~8:8) */
153 { 0, 0, 0, 128, 0, 0, 0, 0 },
154 { -1, 2, -6, 127, 7, -2, 1, 0 },
155 { -1, 4, -12, 125, 16, -5, 1, 0 },
156 { -1, 5, -15, 120, 25, -8, 2, 0 },
157 { -1, 6, -18, 114, 35, -10, 3, -1 },
158 { -1, 6, -20, 107, 46, -13, 4, -1 },
159 { -2, 7, -21, 99, 57, -16, 5, -1 },
160 { -1, 6, -20, 89, 68, -18, 5, -1 },
161 { -1, 6, -20, 79, 79, -20, 6, -1 },
162 { -1, 5, -18, 68, 89, -20, 6, -1 },
163 { -1, 5, -16, 57, 99, -21, 7, -2 },
164 { -1, 4, -13, 46, 107, -20, 6, -1 },
165 { -1, 3, -10, 35, 114, -18, 6, -1 },
166 { 0, 2, -8, 25, 120, -15, 5, -1 },
167 { 0, 1, -5, 16, 125, -12, 4, -1 },
168 { 0, 1, -2, 7, 127, -6, 2, -1 }
169 }, { /* 65536 < Ratio <= 74898 (~8:7) */
170 { 3, -8, 14, 111, 13, -8, 3, 0 },
171 { 2, -6, 7, 112, 21, -10, 3, -1 },
172 { 2, -4, 1, 110, 28, -12, 4, -1 },
173 { 1, -2, -3, 106, 36, -13, 4, -1 },
174 { 1, -1, -7, 103, 44, -15, 4, -1 },
175 { 1, 1, -11, 97, 53, -16, 4, -1 },
176 { 0, 2, -13, 91, 61, -16, 4, -1 },
177 { 0, 3, -15, 85, 69, -17, 4, -1 },
178 { 0, 3, -16, 77, 77, -16, 3, 0 },
179 { -1, 4, -17, 69, 85, -15, 3, 0 },
180 { -1, 4, -16, 61, 91, -13, 2, 0 },
181 { -1, 4, -16, 53, 97, -11, 1, 1 },
182 { -1, 4, -15, 44, 103, -7, -1, 1 },
183 { -1, 4, -13, 36, 106, -3, -2, 1 },
184 { -1, 4, -12, 28, 110, 1, -4, 2 },
185 { -1, 3, -10, 21, 112, 7, -6, 2 }
186 }, { /* 74898 < Ratio <= 87381 (~8:6) */
187 { 2, -11, 25, 96, 25, -11, 2, 0 },
188 { 2, -10, 19, 96, 31, -12, 2, 0 },
189 { 2, -9, 14, 94, 37, -12, 2, 0 },
190 { 2, -8, 10, 92, 43, -12, 1, 0 },
191 { 2, -7, 5, 90, 49, -12, 1, 0 },
192 { 2, -5, 1, 86, 55, -12, 0, 1 },
193 { 2, -4, -2, 82, 61, -11, -1, 1 },
194 { 1, -3, -5, 77, 67, -9, -1, 1 },
195 { 1, -2, -7, 72, 72, -7, -2, 1 },
196 { 1, -1, -9, 67, 77, -5, -3, 1 },
197 { 1, -1, -11, 61, 82, -2, -4, 2 },
198 { 1, 0, -12, 55, 86, 1, -5, 2 },
199 { 0, 1, -12, 49, 90, 5, -7, 2 },
200 { 0, 1, -12, 43, 92, 10, -8, 2 },
201 { 0, 2, -12, 37, 94, 14, -9, 2 },
202 { 0, 2, -12, 31, 96, 19, -10, 2 }
203 }, { /* 87381 < Ratio <= 104857 (~8:5) */
204 { -1, -8, 33, 80, 33, -8, -1, 0 },
205 { -1, -8, 28, 80, 37, -7, -2, 1 },
206 { 0, -8, 24, 79, 41, -7, -2, 1 },
207 { 0, -8, 20, 78, 46, -6, -3, 1 },
208 { 0, -8, 16, 76, 50, -4, -3, 1 },
209 { 0, -7, 13, 74, 54, -3, -4, 1 },
210 { 1, -7, 10, 71, 58, -1, -5, 1 },
211 { 1, -6, 6, 68, 62, 1, -5, 1 },
212 { 1, -6, 4, 65, 65, 4, -6, 1 },
213 { 1, -5, 1, 62, 68, 6, -6, 1 },
214 { 1, -5, -1, 58, 71, 10, -7, 1 },
215 { 1, -4, -3, 54, 74, 13, -7, 0 },
216 { 1, -3, -4, 50, 76, 16, -8, 0 },
217 { 1, -3, -6, 46, 78, 20, -8, 0 },
218 { 1, -2, -7, 41, 79, 24, -8, 0 },
219 { 1, -2, -7, 37, 80, 28, -8, -1 }
220 }, { /* 104857 < Ratio <= 131072 (~8:4) */
221 { -3, 0, 35, 64, 35, 0, -3, 0 },
222 { -3, -1, 32, 64, 38, 1, -3, 0 },
223 { -2, -2, 29, 63, 41, 2, -3, 0 },
224 { -2, -3, 27, 63, 43, 4, -4, 0 },
225 { -2, -3, 24, 61, 46, 6, -4, 0 },
226 { -2, -3, 21, 60, 49, 7, -4, 0 },
227 { -1, -4, 19, 59, 51, 9, -4, -1 },
228 { -1, -4, 16, 57, 53, 12, -4, -1 },
229 { -1, -4, 14, 55, 55, 14, -4, -1 },
230 { -1, -4, 12, 53, 57, 16, -4, -1 },
231 { -1, -4, 9, 51, 59, 19, -4, -1 },
232 { 0, -4, 7, 49, 60, 21, -3, -2 },
233 { 0, -4, 6, 46, 61, 24, -3, -2 },
234 { 0, -4, 4, 43, 63, 27, -3, -2 },
235 { 0, -3, 2, 41, 63, 29, -2, -2 },
236 { 0, -3, 1, 38, 64, 32, -1, -3 }
237 }, { /* 131072 < Ratio <= 174762 (~8:3) */
238 { -1, 8, 33, 48, 33, 8, -1, 0 },
239 { -1, 7, 31, 49, 35, 9, -1, -1 },
240 { -1, 6, 30, 49, 36, 10, -1, -1 },
241 { -1, 5, 28, 48, 38, 12, -1, -1 },
242 { -1, 4, 26, 48, 39, 13, 0, -1 },
243 { -1, 3, 24, 47, 41, 15, 0, -1 },
244 { -1, 2, 23, 47, 42, 16, 0, -1 },
245 { -1, 2, 21, 45, 43, 18, 1, -1 },
246 { -1, 1, 19, 45, 45, 19, 1, -1 },
247 { -1, 1, 18, 43, 45, 21, 2, -1 },
248 { -1, 0, 16, 42, 47, 23, 2, -1 },
249 { -1, 0, 15, 41, 47, 24, 3, -1 },
250 { -1, 0, 13, 39, 48, 26, 4, -1 },
251 { -1, -1, 12, 38, 48, 28, 5, -1 },
252 { -1, -1, 10, 36, 49, 30, 6, -1 },
253 { -1, -1, 9, 35, 49, 31, 7, -1 }
254 }, { /* 174762 < Ratio <= 262144 (~8:2) */
255 { 2, 13, 30, 38, 30, 13, 2, 0 },
256 { 2, 12, 29, 38, 30, 14, 3, 0 },
257 { 2, 11, 28, 38, 31, 15, 3, 0 },
258 { 2, 10, 26, 38, 32, 16, 4, 0 },
259 { 1, 10, 26, 37, 33, 17, 4, 0 },
260 { 1, 9, 24, 37, 34, 18, 5, 0 },
261 { 1, 8, 24, 37, 34, 19, 5, 0 },
262 { 1, 7, 22, 36, 35, 20, 6, 1 },
263 { 1, 6, 21, 36, 36, 21, 6, 1 },
264 { 1, 6, 20, 35, 36, 22, 7, 1 },
265 { 0, 5, 19, 34, 37, 24, 8, 1 },
266 { 0, 5, 18, 34, 37, 24, 9, 1 },
267 { 0, 4, 17, 33, 37, 26, 10, 1 },
268 { 0, 4, 16, 32, 38, 26, 10, 2 },
269 { 0, 3, 15, 31, 38, 28, 11, 2 },
270 { 0, 3, 14, 30, 38, 29, 12, 2 }
274 /* 4-tap Filter Coefficient */
275 static const int v_coef_4t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_V_4T] = {
276 { /* Ratio <= 65536 (~8:8) */
293 }, { /* 65536 < Ratio <= 74898 (~8:7) */
310 }, { /* 74898 < Ratio <= 87381 (~8:6) */
327 }, { /* 87381 < Ratio <= 104857 (~8:5) */
344 }, { /* 104857 < Ratio <= 131072 (~8:4) */
361 }, { /* 131072 < Ratio <= 174762 (~8:3) */
378 }, { /* 174762 < Ratio <= 262144 (~8:2) */
398 static int gsc_sw_reset(struct gsc_context *ctx)
401 int count = GSC_RESET_TIMEOUT;
404 cfg = (GSC_SW_RESET_SRESET);
405 gsc_write(cfg, GSC_SW_RESET);
407 /* wait s/w reset complete */
409 cfg = gsc_read(GSC_SW_RESET);
412 usleep_range(1000, 2000);
416 DRM_ERROR("failed to reset gsc h/w.\n");
421 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
422 cfg |= (GSC_IN_BASE_ADDR_MASK |
423 GSC_IN_BASE_ADDR_PINGPONG(0));
424 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
425 gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
426 gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
428 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
429 cfg |= (GSC_OUT_BASE_ADDR_MASK |
430 GSC_OUT_BASE_ADDR_PINGPONG(0));
431 gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
432 gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
433 gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
438 static void gsc_set_gscblk_fimd_wb(struct gsc_context *ctx, bool enable)
442 gscblk_cfg = readl(SYSREG_GSCBLK_CFG1);
445 gscblk_cfg |= GSC_BLK_DISP1WB_DEST(ctx->id) |
446 GSC_BLK_GSCL_WB_IN_SRC_SEL(ctx->id) |
447 GSC_BLK_SW_RESET_WB_DEST(ctx->id);
449 gscblk_cfg |= GSC_BLK_PXLASYNC_LO_MASK_WB(ctx->id);
451 writel(gscblk_cfg, SYSREG_GSCBLK_CFG1);
454 static void gsc_handle_irq(struct gsc_context *ctx, bool enable,
455 bool overflow, bool done)
459 DRM_DEBUG_KMS("enable[%d]overflow[%d]level[%d]\n",
460 enable, overflow, done);
462 cfg = gsc_read(GSC_IRQ);
463 cfg |= (GSC_IRQ_OR_MASK | GSC_IRQ_FRMDONE_MASK);
466 cfg |= GSC_IRQ_ENABLE;
468 cfg &= ~GSC_IRQ_ENABLE;
471 cfg &= ~GSC_IRQ_OR_MASK;
473 cfg |= GSC_IRQ_OR_MASK;
476 cfg &= ~GSC_IRQ_FRMDONE_MASK;
478 cfg |= GSC_IRQ_FRMDONE_MASK;
480 gsc_write(cfg, GSC_IRQ);
484 static int gsc_src_set_fmt(struct device *dev, u32 fmt)
486 struct gsc_context *ctx = get_gsc_context(dev);
487 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
490 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
492 cfg = gsc_read(GSC_IN_CON);
493 cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK |
494 GSC_IN_CHROMA_ORDER_MASK | GSC_IN_FORMAT_MASK |
495 GSC_IN_TILE_TYPE_MASK | GSC_IN_TILE_MODE |
496 GSC_IN_CHROM_STRIDE_SEL_MASK | GSC_IN_RB_SWAP_MASK);
499 case DRM_FORMAT_RGB565:
500 cfg |= GSC_IN_RGB565;
502 case DRM_FORMAT_XRGB8888:
503 cfg |= GSC_IN_XRGB8888;
505 case DRM_FORMAT_BGRX8888:
506 cfg |= (GSC_IN_XRGB8888 | GSC_IN_RB_SWAP);
508 case DRM_FORMAT_YUYV:
509 cfg |= (GSC_IN_YUV422_1P |
510 GSC_IN_YUV422_1P_ORDER_LSB_Y |
511 GSC_IN_CHROMA_ORDER_CBCR);
513 case DRM_FORMAT_YVYU:
514 cfg |= (GSC_IN_YUV422_1P |
515 GSC_IN_YUV422_1P_ORDER_LSB_Y |
516 GSC_IN_CHROMA_ORDER_CRCB);
518 case DRM_FORMAT_UYVY:
519 cfg |= (GSC_IN_YUV422_1P |
520 GSC_IN_YUV422_1P_OEDER_LSB_C |
521 GSC_IN_CHROMA_ORDER_CBCR);
523 case DRM_FORMAT_VYUY:
524 cfg |= (GSC_IN_YUV422_1P |
525 GSC_IN_YUV422_1P_OEDER_LSB_C |
526 GSC_IN_CHROMA_ORDER_CRCB);
528 case DRM_FORMAT_NV21:
529 case DRM_FORMAT_NV61:
530 cfg |= (GSC_IN_CHROMA_ORDER_CRCB |
533 case DRM_FORMAT_YUV422:
534 cfg |= GSC_IN_YUV422_3P;
536 case DRM_FORMAT_YUV420:
537 case DRM_FORMAT_YVU420:
538 cfg |= GSC_IN_YUV420_3P;
540 case DRM_FORMAT_NV12:
541 case DRM_FORMAT_NV16:
542 cfg |= (GSC_IN_CHROMA_ORDER_CBCR |
545 case DRM_FORMAT_NV12MT:
546 cfg |= (GSC_IN_TILE_C_16x8 | GSC_IN_TILE_MODE);
549 dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt);
553 gsc_write(cfg, GSC_IN_CON);
558 static int gsc_src_set_transf(struct device *dev,
559 enum drm_exynos_degree degree,
560 enum drm_exynos_flip flip, bool *swap)
562 struct gsc_context *ctx = get_gsc_context(dev);
563 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
566 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
568 cfg = gsc_read(GSC_IN_CON);
569 cfg &= ~GSC_IN_ROT_MASK;
572 case EXYNOS_DRM_DEGREE_0:
573 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
574 cfg |= GSC_IN_ROT_XFLIP;
575 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
576 cfg |= GSC_IN_ROT_YFLIP;
578 case EXYNOS_DRM_DEGREE_90:
579 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
580 cfg |= GSC_IN_ROT_90_XFLIP;
581 else if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
582 cfg |= GSC_IN_ROT_90_YFLIP;
584 cfg |= GSC_IN_ROT_90;
586 case EXYNOS_DRM_DEGREE_180:
587 cfg |= GSC_IN_ROT_180;
589 case EXYNOS_DRM_DEGREE_270:
590 cfg |= GSC_IN_ROT_270;
593 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
597 gsc_write(cfg, GSC_IN_CON);
599 ctx->rotation = cfg &
600 (GSC_IN_ROT_90 | GSC_IN_ROT_270) ? 1 : 0;
601 *swap = ctx->rotation;
606 static int gsc_src_set_size(struct device *dev, int swap,
607 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
609 struct gsc_context *ctx = get_gsc_context(dev);
610 struct drm_exynos_pos img_pos = *pos;
611 struct gsc_scaler *sc = &ctx->sc;
614 DRM_DEBUG_KMS("swap[%d]x[%d]y[%d]w[%d]h[%d]\n",
615 swap, pos->x, pos->y, pos->w, pos->h);
623 cfg = (GSC_SRCIMG_OFFSET_X(img_pos.x) |
624 GSC_SRCIMG_OFFSET_Y(img_pos.y));
625 gsc_write(cfg, GSC_SRCIMG_OFFSET);
628 cfg = (GSC_CROPPED_WIDTH(img_pos.w) |
629 GSC_CROPPED_HEIGHT(img_pos.h));
630 gsc_write(cfg, GSC_CROPPED_SIZE);
632 DRM_DEBUG_KMS("hsize[%d]vsize[%d]\n", sz->hsize, sz->vsize);
635 cfg = gsc_read(GSC_SRCIMG_SIZE);
636 cfg &= ~(GSC_SRCIMG_HEIGHT_MASK |
637 GSC_SRCIMG_WIDTH_MASK);
639 cfg |= (GSC_SRCIMG_WIDTH(sz->hsize) |
640 GSC_SRCIMG_HEIGHT(sz->vsize));
642 gsc_write(cfg, GSC_SRCIMG_SIZE);
644 cfg = gsc_read(GSC_IN_CON);
645 cfg &= ~GSC_IN_RGB_TYPE_MASK;
647 DRM_DEBUG_KMS("width[%d]range[%d]\n", pos->w, sc->range);
649 if (pos->w >= GSC_WIDTH_ITU_709)
651 cfg |= GSC_IN_RGB_HD_WIDE;
653 cfg |= GSC_IN_RGB_HD_NARROW;
656 cfg |= GSC_IN_RGB_SD_WIDE;
658 cfg |= GSC_IN_RGB_SD_NARROW;
660 gsc_write(cfg, GSC_IN_CON);
665 static int gsc_src_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
666 enum drm_exynos_ipp_buf_type buf_type)
668 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
671 u32 mask = 0x00000001 << buf_id;
673 DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type);
675 /* mask register set */
676 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
679 case IPP_BUF_ENQUEUE:
682 case IPP_BUF_DEQUEUE:
686 dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n");
692 cfg |= masked << buf_id;
693 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
694 gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
695 gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
700 static int gsc_src_set_addr(struct device *dev,
701 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
702 enum drm_exynos_ipp_buf_type buf_type)
704 struct gsc_context *ctx = get_gsc_context(dev);
705 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
706 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
707 struct drm_exynos_ipp_property *property;
710 DRM_ERROR("failed to get c_node.\n");
714 property = &c_node->property;
716 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
717 property->prop_id, buf_id, buf_type);
719 if (buf_id > GSC_MAX_SRC) {
720 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
724 /* address register set */
726 case IPP_BUF_ENQUEUE:
727 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
728 GSC_IN_BASE_ADDR_Y(buf_id));
729 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
730 GSC_IN_BASE_ADDR_CB(buf_id));
731 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
732 GSC_IN_BASE_ADDR_CR(buf_id));
734 case IPP_BUF_DEQUEUE:
735 gsc_write(0x0, GSC_IN_BASE_ADDR_Y(buf_id));
736 gsc_write(0x0, GSC_IN_BASE_ADDR_CB(buf_id));
737 gsc_write(0x0, GSC_IN_BASE_ADDR_CR(buf_id));
744 return gsc_src_set_buf_seq(ctx, buf_id, buf_type);
747 static struct exynos_drm_ipp_ops gsc_src_ops = {
748 .set_fmt = gsc_src_set_fmt,
749 .set_transf = gsc_src_set_transf,
750 .set_size = gsc_src_set_size,
751 .set_addr = gsc_src_set_addr,
754 static int gsc_dst_set_fmt(struct device *dev, u32 fmt)
756 struct gsc_context *ctx = get_gsc_context(dev);
757 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
760 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
762 cfg = gsc_read(GSC_OUT_CON);
763 cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK |
764 GSC_OUT_CHROMA_ORDER_MASK | GSC_OUT_FORMAT_MASK |
765 GSC_OUT_CHROM_STRIDE_SEL_MASK | GSC_OUT_RB_SWAP_MASK |
766 GSC_OUT_GLOBAL_ALPHA_MASK);
769 case DRM_FORMAT_RGB565:
770 cfg |= GSC_OUT_RGB565;
772 case DRM_FORMAT_XRGB8888:
773 cfg |= GSC_OUT_XRGB8888;
775 case DRM_FORMAT_BGRX8888:
776 cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_RB_SWAP);
778 case DRM_FORMAT_YUYV:
779 cfg |= (GSC_OUT_YUV422_1P |
780 GSC_OUT_YUV422_1P_ORDER_LSB_Y |
781 GSC_OUT_CHROMA_ORDER_CBCR);
783 case DRM_FORMAT_YVYU:
784 cfg |= (GSC_OUT_YUV422_1P |
785 GSC_OUT_YUV422_1P_ORDER_LSB_Y |
786 GSC_OUT_CHROMA_ORDER_CRCB);
788 case DRM_FORMAT_UYVY:
789 cfg |= (GSC_OUT_YUV422_1P |
790 GSC_OUT_YUV422_1P_OEDER_LSB_C |
791 GSC_OUT_CHROMA_ORDER_CBCR);
793 case DRM_FORMAT_VYUY:
794 cfg |= (GSC_OUT_YUV422_1P |
795 GSC_OUT_YUV422_1P_OEDER_LSB_C |
796 GSC_OUT_CHROMA_ORDER_CRCB);
798 case DRM_FORMAT_NV21:
799 case DRM_FORMAT_NV61:
800 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_2P);
802 case DRM_FORMAT_YUV422:
803 case DRM_FORMAT_YUV420:
804 case DRM_FORMAT_YVU420:
805 cfg |= GSC_OUT_YUV420_3P;
807 case DRM_FORMAT_NV12:
808 case DRM_FORMAT_NV16:
809 cfg |= (GSC_OUT_CHROMA_ORDER_CBCR |
812 case DRM_FORMAT_NV12MT:
813 cfg |= (GSC_OUT_TILE_C_16x8 | GSC_OUT_TILE_MODE);
816 dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt);
820 gsc_write(cfg, GSC_OUT_CON);
825 static int gsc_dst_set_transf(struct device *dev,
826 enum drm_exynos_degree degree,
827 enum drm_exynos_flip flip, bool *swap)
829 struct gsc_context *ctx = get_gsc_context(dev);
830 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
833 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
835 cfg = gsc_read(GSC_IN_CON);
836 cfg &= ~GSC_IN_ROT_MASK;
839 case EXYNOS_DRM_DEGREE_0:
840 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
841 cfg |= GSC_IN_ROT_XFLIP;
842 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
843 cfg |= GSC_IN_ROT_YFLIP;
845 case EXYNOS_DRM_DEGREE_90:
846 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
847 cfg |= GSC_IN_ROT_90_XFLIP;
848 else if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
849 cfg |= GSC_IN_ROT_90_YFLIP;
851 cfg |= GSC_IN_ROT_90;
853 case EXYNOS_DRM_DEGREE_180:
854 cfg |= GSC_IN_ROT_180;
856 case EXYNOS_DRM_DEGREE_270:
857 cfg |= GSC_IN_ROT_270;
860 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
864 gsc_write(cfg, GSC_IN_CON);
866 ctx->rotation = cfg &
867 (GSC_IN_ROT_90 | GSC_IN_ROT_270) ? 1 : 0;
868 *swap = ctx->rotation;
873 static int gsc_get_ratio_shift(u32 src, u32 dst, u32 *ratio)
875 DRM_DEBUG_KMS("src[%d]dst[%d]\n", src, dst);
877 if (src >= dst * 8) {
878 DRM_ERROR("failed to make ratio and shift.\n");
880 } else if (src >= dst * 4)
882 else if (src >= dst * 2)
890 static void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *shfactor)
892 if (hratio == 4 && vratio == 4)
894 else if ((hratio == 4 && vratio == 2) ||
895 (hratio == 2 && vratio == 4))
897 else if ((hratio == 4 && vratio == 1) ||
898 (hratio == 1 && vratio == 4) ||
899 (hratio == 2 && vratio == 2))
901 else if (hratio == 1 && vratio == 1)
907 static int gsc_set_prescaler(struct gsc_context *ctx, struct gsc_scaler *sc,
908 struct drm_exynos_pos *src, struct drm_exynos_pos *dst)
910 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
912 u32 src_w, src_h, dst_w, dst_h;
926 ret = gsc_get_ratio_shift(src_w, dst_w, &sc->pre_hratio);
928 dev_err(ippdrv->dev, "failed to get ratio horizontal.\n");
932 ret = gsc_get_ratio_shift(src_h, dst_h, &sc->pre_vratio);
934 dev_err(ippdrv->dev, "failed to get ratio vertical.\n");
938 DRM_DEBUG_KMS("pre_hratio[%d]pre_vratio[%d]\n",
939 sc->pre_hratio, sc->pre_vratio);
941 sc->main_hratio = (src_w << 16) / dst_w;
942 sc->main_vratio = (src_h << 16) / dst_h;
944 DRM_DEBUG_KMS("main_hratio[%ld]main_vratio[%ld]\n",
945 sc->main_hratio, sc->main_vratio);
947 gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio,
950 DRM_DEBUG_KMS("pre_shfactor[%d]\n", sc->pre_shfactor);
952 cfg = (GSC_PRESC_SHFACTOR(sc->pre_shfactor) |
953 GSC_PRESC_H_RATIO(sc->pre_hratio) |
954 GSC_PRESC_V_RATIO(sc->pre_vratio));
955 gsc_write(cfg, GSC_PRE_SCALE_RATIO);
960 static void gsc_set_h_coef(struct gsc_context *ctx, unsigned long main_hratio)
962 int i, j, k, sc_ratio;
964 if (main_hratio <= GSC_SC_UP_MAX_RATIO)
966 else if (main_hratio <= GSC_SC_DOWN_RATIO_7_8)
968 else if (main_hratio <= GSC_SC_DOWN_RATIO_6_8)
970 else if (main_hratio <= GSC_SC_DOWN_RATIO_5_8)
972 else if (main_hratio <= GSC_SC_DOWN_RATIO_4_8)
974 else if (main_hratio <= GSC_SC_DOWN_RATIO_3_8)
979 for (i = 0; i < GSC_COEF_PHASE; i++)
980 for (j = 0; j < GSC_COEF_H_8T; j++)
981 for (k = 0; k < GSC_COEF_DEPTH; k++)
982 gsc_write(h_coef_8t[sc_ratio][i][j],
986 static void gsc_set_v_coef(struct gsc_context *ctx, unsigned long main_vratio)
988 int i, j, k, sc_ratio;
990 if (main_vratio <= GSC_SC_UP_MAX_RATIO)
992 else if (main_vratio <= GSC_SC_DOWN_RATIO_7_8)
994 else if (main_vratio <= GSC_SC_DOWN_RATIO_6_8)
996 else if (main_vratio <= GSC_SC_DOWN_RATIO_5_8)
998 else if (main_vratio <= GSC_SC_DOWN_RATIO_4_8)
1000 else if (main_vratio <= GSC_SC_DOWN_RATIO_3_8)
1005 for (i = 0; i < GSC_COEF_PHASE; i++)
1006 for (j = 0; j < GSC_COEF_V_4T; j++)
1007 for (k = 0; k < GSC_COEF_DEPTH; k++)
1008 gsc_write(v_coef_4t[sc_ratio][i][j],
1009 GSC_VCOEF(i, j, k));
1012 static void gsc_set_scaler(struct gsc_context *ctx, struct gsc_scaler *sc)
1016 DRM_DEBUG_KMS("main_hratio[%ld]main_vratio[%ld]\n",
1017 sc->main_hratio, sc->main_vratio);
1019 gsc_set_h_coef(ctx, sc->main_hratio);
1020 cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio);
1021 gsc_write(cfg, GSC_MAIN_H_RATIO);
1023 gsc_set_v_coef(ctx, sc->main_vratio);
1024 cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio);
1025 gsc_write(cfg, GSC_MAIN_V_RATIO);
1028 static int gsc_dst_set_size(struct device *dev, int swap,
1029 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
1031 struct gsc_context *ctx = get_gsc_context(dev);
1032 struct drm_exynos_pos img_pos = *pos;
1033 struct gsc_scaler *sc = &ctx->sc;
1036 DRM_DEBUG_KMS("swap[%d]x[%d]y[%d]w[%d]h[%d]\n",
1037 swap, pos->x, pos->y, pos->w, pos->h);
1045 cfg = (GSC_DSTIMG_OFFSET_X(pos->x) |
1046 GSC_DSTIMG_OFFSET_Y(pos->y));
1047 gsc_write(cfg, GSC_DSTIMG_OFFSET);
1050 cfg = (GSC_SCALED_WIDTH(img_pos.w) | GSC_SCALED_HEIGHT(img_pos.h));
1051 gsc_write(cfg, GSC_SCALED_SIZE);
1053 DRM_DEBUG_KMS("hsize[%d]vsize[%d]\n", sz->hsize, sz->vsize);
1056 cfg = gsc_read(GSC_DSTIMG_SIZE);
1057 cfg &= ~(GSC_DSTIMG_HEIGHT_MASK |
1058 GSC_DSTIMG_WIDTH_MASK);
1059 cfg |= (GSC_DSTIMG_WIDTH(sz->hsize) |
1060 GSC_DSTIMG_HEIGHT(sz->vsize));
1061 gsc_write(cfg, GSC_DSTIMG_SIZE);
1063 cfg = gsc_read(GSC_OUT_CON);
1064 cfg &= ~GSC_OUT_RGB_TYPE_MASK;
1066 DRM_DEBUG_KMS("width[%d]range[%d]\n", pos->w, sc->range);
1068 if (pos->w >= GSC_WIDTH_ITU_709)
1070 cfg |= GSC_OUT_RGB_HD_WIDE;
1072 cfg |= GSC_OUT_RGB_HD_NARROW;
1075 cfg |= GSC_OUT_RGB_SD_WIDE;
1077 cfg |= GSC_OUT_RGB_SD_NARROW;
1079 gsc_write(cfg, GSC_OUT_CON);
1084 static int gsc_dst_get_buf_seq(struct gsc_context *ctx)
1086 u32 cfg, i, buf_num = GSC_REG_SZ;
1087 u32 mask = 0x00000001;
1089 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
1091 for (i = 0; i < GSC_REG_SZ; i++)
1092 if (cfg & (mask << i))
1095 DRM_DEBUG_KMS("buf_num[%d]\n", buf_num);
1100 static int gsc_dst_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
1101 enum drm_exynos_ipp_buf_type buf_type)
1103 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1106 u32 mask = 0x00000001 << buf_id;
1109 DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type);
1111 mutex_lock(&ctx->lock);
1113 /* mask register set */
1114 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
1117 case IPP_BUF_ENQUEUE:
1120 case IPP_BUF_DEQUEUE:
1124 dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n");
1131 cfg |= masked << buf_id;
1132 gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
1133 gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
1134 gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
1136 /* interrupt enable */
1137 if (buf_type == IPP_BUF_ENQUEUE &&
1138 gsc_dst_get_buf_seq(ctx) >= GSC_BUF_START)
1139 gsc_handle_irq(ctx, true, false, true);
1141 /* interrupt disable */
1142 if (buf_type == IPP_BUF_DEQUEUE &&
1143 gsc_dst_get_buf_seq(ctx) <= GSC_BUF_STOP)
1144 gsc_handle_irq(ctx, false, false, true);
1147 mutex_unlock(&ctx->lock);
1151 static int gsc_dst_set_addr(struct device *dev,
1152 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
1153 enum drm_exynos_ipp_buf_type buf_type)
1155 struct gsc_context *ctx = get_gsc_context(dev);
1156 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1157 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1158 struct drm_exynos_ipp_property *property;
1161 DRM_ERROR("failed to get c_node.\n");
1165 property = &c_node->property;
1167 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
1168 property->prop_id, buf_id, buf_type);
1170 if (buf_id > GSC_MAX_DST) {
1171 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
1175 /* address register set */
1177 case IPP_BUF_ENQUEUE:
1178 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
1179 GSC_OUT_BASE_ADDR_Y(buf_id));
1180 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
1181 GSC_OUT_BASE_ADDR_CB(buf_id));
1182 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
1183 GSC_OUT_BASE_ADDR_CR(buf_id));
1185 case IPP_BUF_DEQUEUE:
1186 gsc_write(0x0, GSC_OUT_BASE_ADDR_Y(buf_id));
1187 gsc_write(0x0, GSC_OUT_BASE_ADDR_CB(buf_id));
1188 gsc_write(0x0, GSC_OUT_BASE_ADDR_CR(buf_id));
1195 return gsc_dst_set_buf_seq(ctx, buf_id, buf_type);
1198 static struct exynos_drm_ipp_ops gsc_dst_ops = {
1199 .set_fmt = gsc_dst_set_fmt,
1200 .set_transf = gsc_dst_set_transf,
1201 .set_size = gsc_dst_set_size,
1202 .set_addr = gsc_dst_set_addr,
1205 static int gsc_clk_ctrl(struct gsc_context *ctx, bool enable)
1207 DRM_DEBUG_KMS("enable[%d]\n", enable);
1210 clk_enable(ctx->gsc_clk);
1211 ctx->suspended = false;
1213 clk_disable(ctx->gsc_clk);
1214 ctx->suspended = true;
1220 static int gsc_get_src_buf_index(struct gsc_context *ctx)
1222 u32 cfg, curr_index, i;
1223 u32 buf_id = GSC_MAX_SRC;
1226 DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id);
1228 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
1229 curr_index = GSC_IN_CURR_GET_INDEX(cfg);
1231 for (i = curr_index; i < GSC_MAX_SRC; i++) {
1232 if (!((cfg >> i) & 0x1)) {
1238 if (buf_id == GSC_MAX_SRC) {
1239 DRM_ERROR("failed to get in buffer index.\n");
1243 ret = gsc_src_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE);
1245 DRM_ERROR("failed to dequeue.\n");
1249 DRM_DEBUG_KMS("cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
1250 curr_index, buf_id);
1255 static int gsc_get_dst_buf_index(struct gsc_context *ctx)
1257 u32 cfg, curr_index, i;
1258 u32 buf_id = GSC_MAX_DST;
1261 DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id);
1263 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
1264 curr_index = GSC_OUT_CURR_GET_INDEX(cfg);
1266 for (i = curr_index; i < GSC_MAX_DST; i++) {
1267 if (!((cfg >> i) & 0x1)) {
1273 if (buf_id == GSC_MAX_DST) {
1274 DRM_ERROR("failed to get out buffer index.\n");
1278 ret = gsc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE);
1280 DRM_ERROR("failed to dequeue.\n");
1284 DRM_DEBUG_KMS("cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
1285 curr_index, buf_id);
1290 static irqreturn_t gsc_irq_handler(int irq, void *dev_id)
1292 struct gsc_context *ctx = dev_id;
1293 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1294 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1295 struct drm_exynos_ipp_event_work *event_work =
1298 int buf_id[EXYNOS_DRM_OPS_MAX];
1300 DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id);
1302 status = gsc_read(GSC_IRQ);
1303 if (status & GSC_IRQ_STATUS_OR_IRQ) {
1304 dev_err(ippdrv->dev, "occurred overflow at %d, status 0x%x.\n",
1309 if (status & GSC_IRQ_STATUS_OR_FRM_DONE) {
1310 dev_dbg(ippdrv->dev, "occurred frame done at %d, status 0x%x.\n",
1313 buf_id[EXYNOS_DRM_OPS_SRC] = gsc_get_src_buf_index(ctx);
1314 if (buf_id[EXYNOS_DRM_OPS_SRC] < 0)
1317 buf_id[EXYNOS_DRM_OPS_DST] = gsc_get_dst_buf_index(ctx);
1318 if (buf_id[EXYNOS_DRM_OPS_DST] < 0)
1321 DRM_DEBUG_KMS("buf_id_src[%d]buf_id_dst[%d]\n",
1322 buf_id[EXYNOS_DRM_OPS_SRC], buf_id[EXYNOS_DRM_OPS_DST]);
1324 event_work->ippdrv = ippdrv;
1325 event_work->buf_id[EXYNOS_DRM_OPS_SRC] =
1326 buf_id[EXYNOS_DRM_OPS_SRC];
1327 event_work->buf_id[EXYNOS_DRM_OPS_DST] =
1328 buf_id[EXYNOS_DRM_OPS_DST];
1329 queue_work(ippdrv->event_workq, &event_work->work);
1335 static int gsc_init_prop_list(struct exynos_drm_ippdrv *ippdrv)
1337 struct drm_exynos_ipp_prop_list *prop_list = &ippdrv->prop_list;
1339 prop_list->version = 1;
1340 prop_list->writeback = 1;
1341 prop_list->refresh_min = GSC_REFRESH_MIN;
1342 prop_list->refresh_max = GSC_REFRESH_MAX;
1343 prop_list->flip = (1 << EXYNOS_DRM_FLIP_VERTICAL) |
1344 (1 << EXYNOS_DRM_FLIP_HORIZONTAL);
1345 prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) |
1346 (1 << EXYNOS_DRM_DEGREE_90) |
1347 (1 << EXYNOS_DRM_DEGREE_180) |
1348 (1 << EXYNOS_DRM_DEGREE_270);
1350 prop_list->crop = 1;
1351 prop_list->crop_max.hsize = GSC_CROP_MAX;
1352 prop_list->crop_max.vsize = GSC_CROP_MAX;
1353 prop_list->crop_min.hsize = GSC_CROP_MIN;
1354 prop_list->crop_min.vsize = GSC_CROP_MIN;
1355 prop_list->scale = 1;
1356 prop_list->scale_max.hsize = GSC_SCALE_MAX;
1357 prop_list->scale_max.vsize = GSC_SCALE_MAX;
1358 prop_list->scale_min.hsize = GSC_SCALE_MIN;
1359 prop_list->scale_min.vsize = GSC_SCALE_MIN;
1364 static inline bool gsc_check_drm_flip(enum drm_exynos_flip flip)
1367 case EXYNOS_DRM_FLIP_NONE:
1368 case EXYNOS_DRM_FLIP_VERTICAL:
1369 case EXYNOS_DRM_FLIP_HORIZONTAL:
1370 case EXYNOS_DRM_FLIP_BOTH:
1373 DRM_DEBUG_KMS("invalid flip\n");
1378 static int gsc_ippdrv_check_property(struct device *dev,
1379 struct drm_exynos_ipp_property *property)
1381 struct gsc_context *ctx = get_gsc_context(dev);
1382 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1383 struct drm_exynos_ipp_prop_list *pp = &ippdrv->prop_list;
1384 struct drm_exynos_ipp_config *config;
1385 struct drm_exynos_pos *pos;
1386 struct drm_exynos_sz *sz;
1390 for_each_ipp_ops(i) {
1391 if ((i == EXYNOS_DRM_OPS_SRC) &&
1392 (property->cmd == IPP_CMD_WB))
1395 config = &property->config[i];
1399 /* check for flip */
1400 if (!gsc_check_drm_flip(config->flip)) {
1401 DRM_ERROR("invalid flip.\n");
1405 /* check for degree */
1406 switch (config->degree) {
1407 case EXYNOS_DRM_DEGREE_90:
1408 case EXYNOS_DRM_DEGREE_270:
1411 case EXYNOS_DRM_DEGREE_0:
1412 case EXYNOS_DRM_DEGREE_180:
1416 DRM_ERROR("invalid degree.\n");
1420 /* check for buffer bound */
1421 if ((pos->x + pos->w > sz->hsize) ||
1422 (pos->y + pos->h > sz->vsize)) {
1423 DRM_ERROR("out of buf bound.\n");
1427 /* check for crop */
1428 if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) {
1430 if ((pos->h < pp->crop_min.hsize) ||
1431 (sz->vsize > pp->crop_max.hsize) ||
1432 (pos->w < pp->crop_min.vsize) ||
1433 (sz->hsize > pp->crop_max.vsize)) {
1434 DRM_ERROR("out of crop size.\n");
1438 if ((pos->w < pp->crop_min.hsize) ||
1439 (sz->hsize > pp->crop_max.hsize) ||
1440 (pos->h < pp->crop_min.vsize) ||
1441 (sz->vsize > pp->crop_max.vsize)) {
1442 DRM_ERROR("out of crop size.\n");
1448 /* check for scale */
1449 if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) {
1451 if ((pos->h < pp->scale_min.hsize) ||
1452 (sz->vsize > pp->scale_max.hsize) ||
1453 (pos->w < pp->scale_min.vsize) ||
1454 (sz->hsize > pp->scale_max.vsize)) {
1455 DRM_ERROR("out of scale size.\n");
1459 if ((pos->w < pp->scale_min.hsize) ||
1460 (sz->hsize > pp->scale_max.hsize) ||
1461 (pos->h < pp->scale_min.vsize) ||
1462 (sz->vsize > pp->scale_max.vsize)) {
1463 DRM_ERROR("out of scale size.\n");
1473 for_each_ipp_ops(i) {
1474 if ((i == EXYNOS_DRM_OPS_SRC) &&
1475 (property->cmd == IPP_CMD_WB))
1478 config = &property->config[i];
1482 DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n",
1483 i ? "dst" : "src", config->flip, config->degree,
1484 pos->x, pos->y, pos->w, pos->h,
1485 sz->hsize, sz->vsize);
1492 static int gsc_ippdrv_reset(struct device *dev)
1494 struct gsc_context *ctx = get_gsc_context(dev);
1495 struct gsc_scaler *sc = &ctx->sc;
1498 /* reset h/w block */
1499 ret = gsc_sw_reset(ctx);
1501 dev_err(dev, "failed to reset hardware.\n");
1505 /* scaler setting */
1506 memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1512 static int gsc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1514 struct gsc_context *ctx = get_gsc_context(dev);
1515 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1516 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1517 struct drm_exynos_ipp_property *property;
1518 struct drm_exynos_ipp_config *config;
1519 struct drm_exynos_pos img_pos[EXYNOS_DRM_OPS_MAX];
1520 struct drm_exynos_ipp_set_wb set_wb;
1524 DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1527 DRM_ERROR("failed to get c_node.\n");
1531 property = &c_node->property;
1533 gsc_handle_irq(ctx, true, false, true);
1535 for_each_ipp_ops(i) {
1536 config = &property->config[i];
1537 img_pos[i] = config->pos;
1542 /* enable one shot */
1543 cfg = gsc_read(GSC_ENABLE);
1544 cfg &= ~(GSC_ENABLE_ON_CLEAR_MASK |
1545 GSC_ENABLE_CLK_GATE_MODE_MASK);
1546 cfg |= GSC_ENABLE_ON_CLEAR_ONESHOT;
1547 gsc_write(cfg, GSC_ENABLE);
1549 /* src dma memory */
1550 cfg = gsc_read(GSC_IN_CON);
1551 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1552 cfg |= GSC_IN_PATH_MEMORY;
1553 gsc_write(cfg, GSC_IN_CON);
1555 /* dst dma memory */
1556 cfg = gsc_read(GSC_OUT_CON);
1557 cfg |= GSC_OUT_PATH_MEMORY;
1558 gsc_write(cfg, GSC_OUT_CON);
1562 set_wb.refresh = property->refresh_rate;
1563 gsc_set_gscblk_fimd_wb(ctx, set_wb.enable);
1564 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1566 /* src local path */
1567 cfg = gsc_read(GSC_IN_CON);
1568 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1569 cfg |= (GSC_IN_PATH_LOCAL | GSC_IN_LOCAL_FIMD_WB);
1570 gsc_write(cfg, GSC_IN_CON);
1572 /* dst dma memory */
1573 cfg = gsc_read(GSC_OUT_CON);
1574 cfg |= GSC_OUT_PATH_MEMORY;
1575 gsc_write(cfg, GSC_OUT_CON);
1577 case IPP_CMD_OUTPUT:
1578 /* src dma memory */
1579 cfg = gsc_read(GSC_IN_CON);
1580 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1581 cfg |= GSC_IN_PATH_MEMORY;
1582 gsc_write(cfg, GSC_IN_CON);
1584 /* dst local path */
1585 cfg = gsc_read(GSC_OUT_CON);
1586 cfg |= GSC_OUT_PATH_MEMORY;
1587 gsc_write(cfg, GSC_OUT_CON);
1591 dev_err(dev, "invalid operations.\n");
1595 ret = gsc_set_prescaler(ctx, &ctx->sc,
1596 &img_pos[EXYNOS_DRM_OPS_SRC],
1597 &img_pos[EXYNOS_DRM_OPS_DST]);
1599 dev_err(dev, "failed to set precalser.\n");
1603 gsc_set_scaler(ctx, &ctx->sc);
1605 cfg = gsc_read(GSC_ENABLE);
1606 cfg |= GSC_ENABLE_ON;
1607 gsc_write(cfg, GSC_ENABLE);
1612 static void gsc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1614 struct gsc_context *ctx = get_gsc_context(dev);
1615 struct drm_exynos_ipp_set_wb set_wb = {0, 0};
1618 DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1625 gsc_set_gscblk_fimd_wb(ctx, set_wb.enable);
1626 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1628 case IPP_CMD_OUTPUT:
1630 dev_err(dev, "invalid operations.\n");
1634 gsc_handle_irq(ctx, false, false, true);
1636 /* reset sequence */
1637 gsc_write(0xff, GSC_OUT_BASE_ADDR_Y_MASK);
1638 gsc_write(0xff, GSC_OUT_BASE_ADDR_CB_MASK);
1639 gsc_write(0xff, GSC_OUT_BASE_ADDR_CR_MASK);
1641 cfg = gsc_read(GSC_ENABLE);
1642 cfg &= ~GSC_ENABLE_ON;
1643 gsc_write(cfg, GSC_ENABLE);
1646 static int gsc_probe(struct platform_device *pdev)
1648 struct device *dev = &pdev->dev;
1649 struct gsc_context *ctx;
1650 struct resource *res;
1651 struct exynos_drm_ippdrv *ippdrv;
1654 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1659 ctx->gsc_clk = devm_clk_get(dev, "gscl");
1660 if (IS_ERR(ctx->gsc_clk)) {
1661 dev_err(dev, "failed to get gsc clock.\n");
1662 return PTR_ERR(ctx->gsc_clk);
1665 /* resource memory */
1666 ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1667 ctx->regs = devm_ioremap_resource(dev, ctx->regs_res);
1668 if (IS_ERR(ctx->regs))
1669 return PTR_ERR(ctx->regs);
1672 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1674 dev_err(dev, "failed to request irq resource.\n");
1678 ctx->irq = res->start;
1679 ret = devm_request_threaded_irq(dev, ctx->irq, NULL, gsc_irq_handler,
1680 IRQF_ONESHOT, "drm_gsc", ctx);
1682 dev_err(dev, "failed to request irq.\n");
1686 /* context initailization */
1689 ippdrv = &ctx->ippdrv;
1691 ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &gsc_src_ops;
1692 ippdrv->ops[EXYNOS_DRM_OPS_DST] = &gsc_dst_ops;
1693 ippdrv->check_property = gsc_ippdrv_check_property;
1694 ippdrv->reset = gsc_ippdrv_reset;
1695 ippdrv->start = gsc_ippdrv_start;
1696 ippdrv->stop = gsc_ippdrv_stop;
1697 ret = gsc_init_prop_list(ippdrv);
1699 dev_err(dev, "failed to init property list.\n");
1703 DRM_DEBUG_KMS("id[%d]ippdrv[0x%x]\n", ctx->id, (int)ippdrv);
1705 mutex_init(&ctx->lock);
1706 platform_set_drvdata(pdev, ctx);
1708 pm_runtime_set_active(dev);
1709 pm_runtime_enable(dev);
1711 ret = exynos_drm_ippdrv_register(ippdrv);
1713 dev_err(dev, "failed to register drm gsc device.\n");
1714 goto err_ippdrv_register;
1717 dev_info(dev, "drm gsc registered successfully.\n");
1721 err_ippdrv_register:
1722 pm_runtime_disable(dev);
1726 static int gsc_remove(struct platform_device *pdev)
1728 struct device *dev = &pdev->dev;
1729 struct gsc_context *ctx = get_gsc_context(dev);
1730 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1732 exynos_drm_ippdrv_unregister(ippdrv);
1733 mutex_destroy(&ctx->lock);
1735 pm_runtime_set_suspended(dev);
1736 pm_runtime_disable(dev);
1741 #ifdef CONFIG_PM_SLEEP
1742 static int gsc_suspend(struct device *dev)
1744 struct gsc_context *ctx = get_gsc_context(dev);
1746 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1748 if (pm_runtime_suspended(dev))
1751 return gsc_clk_ctrl(ctx, false);
1754 static int gsc_resume(struct device *dev)
1756 struct gsc_context *ctx = get_gsc_context(dev);
1758 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1760 if (!pm_runtime_suspended(dev))
1761 return gsc_clk_ctrl(ctx, true);
1768 static int gsc_runtime_suspend(struct device *dev)
1770 struct gsc_context *ctx = get_gsc_context(dev);
1772 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1774 return gsc_clk_ctrl(ctx, false);
1777 static int gsc_runtime_resume(struct device *dev)
1779 struct gsc_context *ctx = get_gsc_context(dev);
1781 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1783 return gsc_clk_ctrl(ctx, true);
1787 static const struct dev_pm_ops gsc_pm_ops = {
1788 SET_SYSTEM_SLEEP_PM_OPS(gsc_suspend, gsc_resume)
1789 SET_RUNTIME_PM_OPS(gsc_runtime_suspend, gsc_runtime_resume, NULL)
1792 struct platform_driver gsc_driver = {
1794 .remove = gsc_remove,
1796 .name = "exynos-drm-gsc",
1797 .owner = THIS_MODULE,