2 * Copyright (C) 2015 Samsung Electronics Co.Ltd
4 * Hyungwon Hwang <human.hwang@samsung.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundationr
11 #include <linux/platform_device.h>
12 #include <video/of_videomode.h>
13 #include <linux/of_address.h>
14 #include <video/videomode.h>
15 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/mutex.h>
19 #include <linux/of_graph.h>
20 #include <linux/clk.h>
22 #include <linux/mfd/syscon.h>
23 #include <linux/regmap.h>
25 /* Sysreg registers for MIC */
26 #define DSD_CFG_MUX 0x1004
27 #define MIC0_RGB_MUX (1 << 0)
28 #define MIC0_I80_MUX (1 << 1)
29 #define MIC0_ON_MUX (1 << 5)
33 #define MIC_IP_VER 0x0004
34 #define MIC_V_TIMING_0 0x0008
35 #define MIC_V_TIMING_1 0x000C
36 #define MIC_IMG_SIZE 0x0010
37 #define MIC_INPUT_TIMING_0 0x0014
38 #define MIC_INPUT_TIMING_1 0x0018
39 #define MIC_2D_OUTPUT_TIMING_0 0x001C
40 #define MIC_2D_OUTPUT_TIMING_1 0x0020
41 #define MIC_2D_OUTPUT_TIMING_2 0x0024
42 #define MIC_3D_OUTPUT_TIMING_0 0x0028
43 #define MIC_3D_OUTPUT_TIMING_1 0x002C
44 #define MIC_3D_OUTPUT_TIMING_2 0x0030
45 #define MIC_CORE_PARA_0 0x0034
46 #define MIC_CORE_PARA_1 0x0038
47 #define MIC_CTC_CTRL 0x0040
48 #define MIC_RD_DATA 0x0044
50 #define MIC_UPD_REG (1 << 31)
51 #define MIC_ON_REG (1 << 30)
52 #define MIC_TD_ON_REG (1 << 29)
53 #define MIC_BS_CHG_OUT (1 << 16)
54 #define MIC_VIDEO_TYPE(x) (((x) & 0xf) << 12)
55 #define MIC_PSR_EN (1 << 5)
56 #define MIC_SW_RST (1 << 4)
57 #define MIC_ALL_RST (1 << 3)
58 #define MIC_CORE_VER_CONTROL (1 << 2)
59 #define MIC_MODE_SEL_COMMAND_MODE (1 << 1)
60 #define MIC_MODE_SEL_MASK (1 << 1)
61 #define MIC_CORE_EN (1 << 0)
63 #define MIC_V_PULSE_WIDTH(x) (((x) & 0x3fff) << 16)
64 #define MIC_V_PERIOD_LINE(x) ((x) & 0x3fff)
66 #define MIC_VBP_SIZE(x) (((x) & 0x3fff) << 16)
67 #define MIC_VFP_SIZE(x) ((x) & 0x3fff)
69 #define MIC_IMG_V_SIZE(x) (((x) & 0x3fff) << 16)
70 #define MIC_IMG_H_SIZE(x) ((x) & 0x3fff)
72 #define MIC_H_PULSE_WIDTH_IN(x) (((x) & 0x3fff) << 16)
73 #define MIC_H_PERIOD_PIXEL_IN(x) ((x) & 0x3fff)
75 #define MIC_HBP_SIZE_IN(x) (((x) & 0x3fff) << 16)
76 #define MIC_HFP_SIZE_IN(x) ((x) & 0x3fff)
78 #define MIC_H_PULSE_WIDTH_2D(x) (((x) & 0x3fff) << 16)
79 #define MIC_H_PERIOD_PIXEL_2D(x) ((x) & 0x3fff)
81 #define MIC_HBP_SIZE_2D(x) (((x) & 0x3fff) << 16)
82 #define MIC_HFP_SIZE_2D(x) ((x) & 0x3fff)
84 #define MIC_BS_SIZE_2D(x) ((x) & 0x3fff)
92 static char *clk_names[] = { "pclk_mic0", "sclk_rgb_vclk_to_mic0" };
93 #define NUM_CLKS ARRAY_SIZE(clk_names)
94 static DEFINE_MUTEX(mic_mutex);
99 struct regmap *sysreg;
100 struct clk *clks[NUM_CLKS];
104 struct drm_encoder *encoder;
105 struct drm_bridge bridge;
110 static void mic_set_path(struct exynos_mic *mic, bool enable)
115 ret = regmap_read(mic->sysreg, DSD_CFG_MUX, &val);
117 DRM_ERROR("mic: Failed to read system register\n");
129 val &= ~(MIC0_RGB_MUX | MIC0_I80_MUX | MIC0_ON_MUX);
131 regmap_write(mic->sysreg, DSD_CFG_MUX, val);
133 DRM_ERROR("mic: Failed to read system register\n");
136 static int mic_sw_reset(struct exynos_mic *mic)
138 unsigned int retry = 100;
141 writel(MIC_SW_RST, mic->reg + MIC_OP);
143 while (retry-- > 0) {
144 ret = readl(mic->reg + MIC_OP);
145 if (!(ret & MIC_SW_RST))
154 static void mic_set_porch_timing(struct exynos_mic *mic)
156 struct videomode vm = mic->vm;
159 reg = MIC_V_PULSE_WIDTH(vm.vsync_len) +
160 MIC_V_PERIOD_LINE(vm.vsync_len + vm.vactive +
161 vm.vback_porch + vm.vfront_porch);
162 writel(reg, mic->reg + MIC_V_TIMING_0);
164 reg = MIC_VBP_SIZE(vm.vback_porch) +
165 MIC_VFP_SIZE(vm.vfront_porch);
166 writel(reg, mic->reg + MIC_V_TIMING_1);
168 reg = MIC_V_PULSE_WIDTH(vm.hsync_len) +
169 MIC_V_PERIOD_LINE(vm.hsync_len + vm.hactive +
170 vm.hback_porch + vm.hfront_porch);
171 writel(reg, mic->reg + MIC_INPUT_TIMING_0);
173 reg = MIC_VBP_SIZE(vm.hback_porch) +
174 MIC_VFP_SIZE(vm.hfront_porch);
175 writel(reg, mic->reg + MIC_INPUT_TIMING_1);
178 static void mic_set_img_size(struct exynos_mic *mic)
180 struct videomode *vm = &mic->vm;
183 reg = MIC_IMG_H_SIZE(vm->hactive) +
184 MIC_IMG_V_SIZE(vm->vactive);
186 writel(reg, mic->reg + MIC_IMG_SIZE);
189 static void mic_set_output_timing(struct exynos_mic *mic)
191 struct videomode vm = mic->vm;
194 DRM_DEBUG("w: %u, h: %u\n", vm.hactive, vm.vactive);
195 bs_size_2d = ((vm.hactive >> 2) << 1) + (vm.vactive % 4);
196 reg = MIC_BS_SIZE_2D(bs_size_2d);
197 writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_2);
199 if (!mic->i80_mode) {
200 reg = MIC_H_PULSE_WIDTH_2D(vm.hsync_len) +
201 MIC_H_PERIOD_PIXEL_2D(vm.hsync_len + bs_size_2d +
202 vm.hback_porch + vm.hfront_porch);
203 writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_0);
205 reg = MIC_HBP_SIZE_2D(vm.hback_porch) +
206 MIC_H_PERIOD_PIXEL_2D(vm.hfront_porch);
207 writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_1);
211 static void mic_set_reg_on(struct exynos_mic *mic, bool enable)
213 u32 reg = readl(mic->reg + MIC_OP);
216 reg &= ~(MIC_MODE_SEL_MASK | MIC_CORE_VER_CONTROL | MIC_PSR_EN);
217 reg |= (MIC_CORE_EN | MIC_BS_CHG_OUT | MIC_ON_REG);
219 reg &= ~MIC_MODE_SEL_COMMAND_MODE;
221 reg |= MIC_MODE_SEL_COMMAND_MODE;
227 writel(reg, mic->reg + MIC_OP);
230 static struct device_node *get_remote_node(struct device_node *from, int reg)
232 struct device_node *endpoint = NULL, *remote_node = NULL;
234 endpoint = of_graph_get_endpoint_by_regs(from, reg, -1);
236 DRM_ERROR("mic: Failed to find remote port from %s",
241 remote_node = of_graph_get_remote_port_parent(endpoint);
243 DRM_ERROR("mic: Failed to find remote port parent from %s",
249 of_node_put(endpoint);
253 static int parse_dt(struct exynos_mic *mic)
256 struct device_node *remote_node;
257 struct device_node *nodes[3];
260 * The order of endpoints does matter.
261 * The first node must be for decon and the second one must be for dsi.
263 for (i = 0, j = 0; i < NUM_ENDPOINTS; i++) {
264 remote_node = get_remote_node(mic->dev->of_node, i);
269 nodes[j++] = remote_node;
272 case ENDPOINT_DECON_NODE:
274 if (of_get_child_by_name(remote_node,
279 case ENDPOINT_DSI_NODE:
281 remote_node = get_remote_node(remote_node, 1);
286 nodes[j++] = remote_node;
288 ret = of_get_videomode(remote_node,
291 DRM_ERROR("mic: failed to get videomode");
297 DRM_ERROR("mic: Unknown endpoint from MIC");
304 of_node_put(nodes[j]);
309 void mic_disable(struct drm_bridge *bridge) { }
311 void mic_post_disable(struct drm_bridge *bridge)
313 struct exynos_mic *mic = bridge->driver_private;
316 mutex_lock(&mic_mutex);
318 goto already_disabled;
320 mic_set_path(mic, 0);
322 for (i = NUM_CLKS - 1; i > -1; i--)
323 clk_disable_unprepare(mic->clks[i]);
328 mutex_unlock(&mic_mutex);
331 void mic_pre_enable(struct drm_bridge *bridge)
333 struct exynos_mic *mic = bridge->driver_private;
336 mutex_lock(&mic_mutex);
338 goto already_enabled;
340 for (i = 0; i < NUM_CLKS; i++) {
341 ret = clk_prepare_enable(mic->clks[i]);
343 DRM_ERROR("Failed to enable clock (%s)\n",
349 mic_set_path(mic, 1);
351 ret = mic_sw_reset(mic);
353 DRM_ERROR("Failed to reset\n");
358 mic_set_porch_timing(mic);
359 mic_set_img_size(mic);
360 mic_set_output_timing(mic);
361 mic_set_reg_on(mic, 1);
363 mutex_unlock(&mic_mutex);
369 clk_disable_unprepare(mic->clks[i]);
371 mutex_unlock(&mic_mutex);
374 void mic_enable(struct drm_bridge *bridge) { }
376 void mic_destroy(struct drm_bridge *bridge)
378 struct exynos_mic *mic = bridge->driver_private;
381 mutex_lock(&mic_mutex);
383 goto already_disabled;
385 for (i = NUM_CLKS - 1; i > -1; i--)
386 clk_disable_unprepare(mic->clks[i]);
389 mutex_unlock(&mic_mutex);
392 struct drm_bridge_funcs mic_bridge_funcs = {
393 .disable = mic_disable,
394 .post_disable = mic_post_disable,
395 .pre_enable = mic_pre_enable,
396 .enable = mic_enable,
399 int exynos_mic_probe(struct platform_device *pdev)
401 struct device *dev = &pdev->dev;
402 struct exynos_mic *mic;
406 mic = devm_kzalloc(dev, sizeof(*mic), GFP_KERNEL);
408 DRM_ERROR("mic: Failed to allocate memory for MIC object\n");
419 ret = of_address_to_resource(dev->of_node, 0, &res);
421 DRM_ERROR("mic: Failed to get mem region for MIC\n");
424 mic->reg = devm_ioremap(dev, res.start, resource_size(&res));
426 DRM_ERROR("mic: Failed to remap for MIC\n");
431 mic->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
432 "samsung,disp-syscon");
433 if (IS_ERR(mic->sysreg)) {
434 DRM_ERROR("mic: Failed to get system register.\n");
438 mic->bridge.funcs = &mic_bridge_funcs;
439 mic->bridge.of_node = dev->of_node;
440 mic->bridge.driver_private = mic;
441 ret = drm_bridge_add(&mic->bridge);
443 DRM_ERROR("mic: Failed to add MIC to the global bridge list\n");
447 for (i = 0; i < NUM_CLKS; i++) {
448 mic->clks[i] = of_clk_get_by_name(dev->of_node, clk_names[i]);
449 if (IS_ERR(mic->clks[i])) {
450 DRM_ERROR("mic: Failed to get clock (%s)\n",
452 ret = PTR_ERR(mic->clks[i]);
457 DRM_DEBUG_KMS("MIC has been probed\n");
463 static int exynos_mic_remove(struct platform_device *pdev)
465 struct exynos_mic *mic = platform_get_drvdata(pdev);
468 drm_bridge_remove(&mic->bridge);
470 for (i = NUM_CLKS - 1; i > -1; i--)
471 clk_put(mic->clks[i]);
476 static const struct of_device_id exynos_mic_of_match[] = {
477 { .compatible = "samsung,exynos5433-mic" },
480 MODULE_DEVICE_TABLE(of, exynos_mic_of_match);
482 struct platform_driver mic_driver = {
483 .probe = exynos_mic_probe,
484 .remove = exynos_mic_remove,
486 .name = "exynos-mic",
487 .owner = THIS_MODULE,
488 .of_match_table = exynos_mic_of_match,