2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Seung-Woo Kim <sw0312.kim@samsung.com>
5 * Inki Dae <inki.dae@samsung.com>
6 * Joonyoung Shim <jy0922.shim@samsung.com>
8 * Based on drivers/media/video/s5p-tv/mixer_reg.c
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
19 #include "regs-mixer.h"
22 #include <linux/kernel.h>
23 #include <linux/spinlock.h>
24 #include <linux/wait.h>
25 #include <linux/i2c.h>
26 #include <linux/platform_device.h>
27 #include <linux/interrupt.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/clk.h>
32 #include <linux/regulator/consumer.h>
34 #include <linux/component.h>
36 #include <drm/exynos_drm.h>
38 #include "exynos_drm_drv.h"
39 #include "exynos_drm_crtc.h"
40 #include "exynos_drm_iommu.h"
41 #include "exynos_mixer.h"
43 #define MIXER_WIN_NR 3
44 #define MIXER_DEFAULT_WIN 0
46 struct hdmi_win_data {
48 dma_addr_t chroma_dma_addr;
49 uint32_t pixel_format;
53 unsigned int crtc_width;
54 unsigned int crtc_height;
57 unsigned int fb_width;
58 unsigned int fb_height;
59 unsigned int src_width;
60 unsigned int src_height;
61 unsigned int mode_width;
62 unsigned int mode_height;
63 unsigned int scan_flags;
68 struct mixer_resources {
70 void __iomem *mixer_regs;
71 void __iomem *vp_regs;
76 struct clk *sclk_mixer;
77 struct clk *sclk_hdmi;
78 struct clk *mout_mixer;
81 enum mixer_version_id {
87 struct mixer_context {
88 struct platform_device *pdev;
90 struct drm_device *drm_dev;
91 struct exynos_drm_crtc *crtc;
99 struct mutex mixer_mutex;
100 struct mixer_resources mixer_res;
101 struct hdmi_win_data win_data[MIXER_WIN_NR];
102 enum mixer_version_id mxr_ver;
103 wait_queue_head_t wait_vsync_queue;
104 atomic_t wait_vsync_event;
107 struct mixer_drv_data {
108 enum mixer_version_id version;
113 static const u8 filter_y_horiz_tap8[] = {
114 0, -1, -1, -1, -1, -1, -1, -1,
115 -1, -1, -1, -1, -1, 0, 0, 0,
116 0, 2, 4, 5, 6, 6, 6, 6,
117 6, 5, 5, 4, 3, 2, 1, 1,
118 0, -6, -12, -16, -18, -20, -21, -20,
119 -20, -18, -16, -13, -10, -8, -5, -2,
120 127, 126, 125, 121, 114, 107, 99, 89,
121 79, 68, 57, 46, 35, 25, 16, 8,
124 static const u8 filter_y_vert_tap4[] = {
125 0, -3, -6, -8, -8, -8, -8, -7,
126 -6, -5, -4, -3, -2, -1, -1, 0,
127 127, 126, 124, 118, 111, 102, 92, 81,
128 70, 59, 48, 37, 27, 19, 11, 5,
129 0, 5, 11, 19, 27, 37, 48, 59,
130 70, 81, 92, 102, 111, 118, 124, 126,
131 0, 0, -1, -1, -2, -3, -4, -5,
132 -6, -7, -8, -8, -8, -8, -6, -3,
135 static const u8 filter_cr_horiz_tap4[] = {
136 0, -3, -6, -8, -8, -8, -8, -7,
137 -6, -5, -4, -3, -2, -1, -1, 0,
138 127, 126, 124, 118, 111, 102, 92, 81,
139 70, 59, 48, 37, 27, 19, 11, 5,
142 static inline u32 vp_reg_read(struct mixer_resources *res, u32 reg_id)
144 return readl(res->vp_regs + reg_id);
147 static inline void vp_reg_write(struct mixer_resources *res, u32 reg_id,
150 writel(val, res->vp_regs + reg_id);
153 static inline void vp_reg_writemask(struct mixer_resources *res, u32 reg_id,
156 u32 old = vp_reg_read(res, reg_id);
158 val = (val & mask) | (old & ~mask);
159 writel(val, res->vp_regs + reg_id);
162 static inline u32 mixer_reg_read(struct mixer_resources *res, u32 reg_id)
164 return readl(res->mixer_regs + reg_id);
167 static inline void mixer_reg_write(struct mixer_resources *res, u32 reg_id,
170 writel(val, res->mixer_regs + reg_id);
173 static inline void mixer_reg_writemask(struct mixer_resources *res,
174 u32 reg_id, u32 val, u32 mask)
176 u32 old = mixer_reg_read(res, reg_id);
178 val = (val & mask) | (old & ~mask);
179 writel(val, res->mixer_regs + reg_id);
182 static void mixer_regs_dump(struct mixer_context *ctx)
184 #define DUMPREG(reg_id) \
186 DRM_DEBUG_KMS(#reg_id " = %08x\n", \
187 (u32)readl(ctx->mixer_res.mixer_regs + reg_id)); \
193 DUMPREG(MXR_INT_STATUS);
195 DUMPREG(MXR_LAYER_CFG);
196 DUMPREG(MXR_VIDEO_CFG);
198 DUMPREG(MXR_GRAPHIC0_CFG);
199 DUMPREG(MXR_GRAPHIC0_BASE);
200 DUMPREG(MXR_GRAPHIC0_SPAN);
201 DUMPREG(MXR_GRAPHIC0_WH);
202 DUMPREG(MXR_GRAPHIC0_SXY);
203 DUMPREG(MXR_GRAPHIC0_DXY);
205 DUMPREG(MXR_GRAPHIC1_CFG);
206 DUMPREG(MXR_GRAPHIC1_BASE);
207 DUMPREG(MXR_GRAPHIC1_SPAN);
208 DUMPREG(MXR_GRAPHIC1_WH);
209 DUMPREG(MXR_GRAPHIC1_SXY);
210 DUMPREG(MXR_GRAPHIC1_DXY);
214 static void vp_regs_dump(struct mixer_context *ctx)
216 #define DUMPREG(reg_id) \
218 DRM_DEBUG_KMS(#reg_id " = %08x\n", \
219 (u32) readl(ctx->mixer_res.vp_regs + reg_id)); \
224 DUMPREG(VP_SHADOW_UPDATE);
225 DUMPREG(VP_FIELD_ID);
227 DUMPREG(VP_IMG_SIZE_Y);
228 DUMPREG(VP_IMG_SIZE_C);
229 DUMPREG(VP_PER_RATE_CTRL);
230 DUMPREG(VP_TOP_Y_PTR);
231 DUMPREG(VP_BOT_Y_PTR);
232 DUMPREG(VP_TOP_C_PTR);
233 DUMPREG(VP_BOT_C_PTR);
234 DUMPREG(VP_ENDIAN_MODE);
235 DUMPREG(VP_SRC_H_POSITION);
236 DUMPREG(VP_SRC_V_POSITION);
237 DUMPREG(VP_SRC_WIDTH);
238 DUMPREG(VP_SRC_HEIGHT);
239 DUMPREG(VP_DST_H_POSITION);
240 DUMPREG(VP_DST_V_POSITION);
241 DUMPREG(VP_DST_WIDTH);
242 DUMPREG(VP_DST_HEIGHT);
249 static inline void vp_filter_set(struct mixer_resources *res,
250 int reg_id, const u8 *data, unsigned int size)
252 /* assure 4-byte align */
254 for (; size; size -= 4, reg_id += 4, data += 4) {
255 u32 val = (data[0] << 24) | (data[1] << 16) |
256 (data[2] << 8) | data[3];
257 vp_reg_write(res, reg_id, val);
261 static void vp_default_filter(struct mixer_resources *res)
263 vp_filter_set(res, VP_POLY8_Y0_LL,
264 filter_y_horiz_tap8, sizeof(filter_y_horiz_tap8));
265 vp_filter_set(res, VP_POLY4_Y0_LL,
266 filter_y_vert_tap4, sizeof(filter_y_vert_tap4));
267 vp_filter_set(res, VP_POLY4_C0_LL,
268 filter_cr_horiz_tap4, sizeof(filter_cr_horiz_tap4));
271 static void mixer_vsync_set_update(struct mixer_context *ctx, bool enable)
273 struct mixer_resources *res = &ctx->mixer_res;
275 /* block update on vsync */
276 mixer_reg_writemask(res, MXR_STATUS, enable ?
277 MXR_STATUS_SYNC_ENABLE : 0, MXR_STATUS_SYNC_ENABLE);
280 vp_reg_write(res, VP_SHADOW_UPDATE, enable ?
281 VP_SHADOW_UPDATE_ENABLE : 0);
284 static void mixer_cfg_scan(struct mixer_context *ctx, unsigned int height)
286 struct mixer_resources *res = &ctx->mixer_res;
289 /* choosing between interlace and progressive mode */
290 val = (ctx->interlace ? MXR_CFG_SCAN_INTERLACE :
291 MXR_CFG_SCAN_PROGRASSIVE);
293 if (ctx->mxr_ver != MXR_VER_128_0_0_184) {
294 /* choosing between proper HD and SD mode */
296 val |= MXR_CFG_SCAN_NTSC | MXR_CFG_SCAN_SD;
297 else if (height <= 576)
298 val |= MXR_CFG_SCAN_PAL | MXR_CFG_SCAN_SD;
299 else if (height <= 720)
300 val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
301 else if (height <= 1080)
302 val |= MXR_CFG_SCAN_HD_1080 | MXR_CFG_SCAN_HD;
304 val |= MXR_CFG_SCAN_HD_720 | MXR_CFG_SCAN_HD;
307 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_SCAN_MASK);
310 static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height)
312 struct mixer_resources *res = &ctx->mixer_res;
316 val = MXR_CFG_RGB601_0_255;
317 } else if (height == 576) {
318 val = MXR_CFG_RGB601_0_255;
319 } else if (height == 720) {
320 val = MXR_CFG_RGB709_16_235;
321 mixer_reg_write(res, MXR_CM_COEFF_Y,
322 (1 << 30) | (94 << 20) | (314 << 10) |
324 mixer_reg_write(res, MXR_CM_COEFF_CB,
325 (972 << 20) | (851 << 10) | (225 << 0));
326 mixer_reg_write(res, MXR_CM_COEFF_CR,
327 (225 << 20) | (820 << 10) | (1004 << 0));
328 } else if (height == 1080) {
329 val = MXR_CFG_RGB709_16_235;
330 mixer_reg_write(res, MXR_CM_COEFF_Y,
331 (1 << 30) | (94 << 20) | (314 << 10) |
333 mixer_reg_write(res, MXR_CM_COEFF_CB,
334 (972 << 20) | (851 << 10) | (225 << 0));
335 mixer_reg_write(res, MXR_CM_COEFF_CR,
336 (225 << 20) | (820 << 10) | (1004 << 0));
338 val = MXR_CFG_RGB709_16_235;
339 mixer_reg_write(res, MXR_CM_COEFF_Y,
340 (1 << 30) | (94 << 20) | (314 << 10) |
342 mixer_reg_write(res, MXR_CM_COEFF_CB,
343 (972 << 20) | (851 << 10) | (225 << 0));
344 mixer_reg_write(res, MXR_CM_COEFF_CR,
345 (225 << 20) | (820 << 10) | (1004 << 0));
348 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_RGB_FMT_MASK);
351 static void mixer_cfg_layer(struct mixer_context *ctx, int win, bool enable)
353 struct mixer_resources *res = &ctx->mixer_res;
354 u32 val = enable ? ~0 : 0;
358 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE);
361 mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE);
364 if (ctx->vp_enabled) {
365 vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON);
366 mixer_reg_writemask(res, MXR_CFG, val,
369 /* control blending of graphic layer 0 */
370 mixer_reg_writemask(res, MXR_GRAPHIC_CFG(0), val,
371 MXR_GRP_CFG_BLEND_PRE_MUL |
372 MXR_GRP_CFG_PIXEL_BLEND_EN);
378 static void mixer_run(struct mixer_context *ctx)
380 struct mixer_resources *res = &ctx->mixer_res;
382 mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_REG_RUN);
384 mixer_regs_dump(ctx);
387 static void mixer_stop(struct mixer_context *ctx)
389 struct mixer_resources *res = &ctx->mixer_res;
392 mixer_reg_writemask(res, MXR_STATUS, 0, MXR_STATUS_REG_RUN);
394 while (!(mixer_reg_read(res, MXR_STATUS) & MXR_STATUS_REG_IDLE) &&
396 usleep_range(10000, 12000);
398 mixer_regs_dump(ctx);
401 static void vp_video_buffer(struct mixer_context *ctx, int win)
403 struct mixer_resources *res = &ctx->mixer_res;
405 struct hdmi_win_data *win_data;
406 unsigned int x_ratio, y_ratio;
407 unsigned int buf_num = 1;
408 dma_addr_t luma_addr[2], chroma_addr[2];
409 bool tiled_mode = false;
410 bool crcb_mode = false;
413 win_data = &ctx->win_data[win];
415 switch (win_data->pixel_format) {
416 case DRM_FORMAT_NV12:
420 /* TODO: single buffer format NV12, NV21 */
422 /* ignore pixel format at disable time */
423 if (!win_data->dma_addr)
426 DRM_ERROR("pixel format for vp is wrong [%d].\n",
427 win_data->pixel_format);
431 /* scaling feature: (src << 16) / dst */
432 x_ratio = (win_data->src_width << 16) / win_data->crtc_width;
433 y_ratio = (win_data->src_height << 16) / win_data->crtc_height;
436 luma_addr[0] = win_data->dma_addr;
437 chroma_addr[0] = win_data->chroma_dma_addr;
439 luma_addr[0] = win_data->dma_addr;
440 chroma_addr[0] = win_data->dma_addr
441 + (win_data->fb_width * win_data->fb_height);
444 if (win_data->scan_flags & DRM_MODE_FLAG_INTERLACE) {
445 ctx->interlace = true;
447 luma_addr[1] = luma_addr[0] + 0x40;
448 chroma_addr[1] = chroma_addr[0] + 0x40;
450 luma_addr[1] = luma_addr[0] + win_data->fb_width;
451 chroma_addr[1] = chroma_addr[0] + win_data->fb_width;
454 ctx->interlace = false;
459 spin_lock_irqsave(&res->reg_slock, flags);
460 mixer_vsync_set_update(ctx, false);
462 /* interlace or progressive scan mode */
463 val = (ctx->interlace ? ~0 : 0);
464 vp_reg_writemask(res, VP_MODE, val, VP_MODE_LINE_SKIP);
467 val = (crcb_mode ? VP_MODE_NV21 : VP_MODE_NV12);
468 val |= (tiled_mode ? VP_MODE_MEM_TILED : VP_MODE_MEM_LINEAR);
469 vp_reg_writemask(res, VP_MODE, val, VP_MODE_FMT_MASK);
471 /* setting size of input image */
472 vp_reg_write(res, VP_IMG_SIZE_Y, VP_IMG_HSIZE(win_data->fb_width) |
473 VP_IMG_VSIZE(win_data->fb_height));
474 /* chroma height has to reduced by 2 to avoid chroma distorions */
475 vp_reg_write(res, VP_IMG_SIZE_C, VP_IMG_HSIZE(win_data->fb_width) |
476 VP_IMG_VSIZE(win_data->fb_height / 2));
478 vp_reg_write(res, VP_SRC_WIDTH, win_data->src_width);
479 vp_reg_write(res, VP_SRC_HEIGHT, win_data->src_height);
480 vp_reg_write(res, VP_SRC_H_POSITION,
481 VP_SRC_H_POSITION_VAL(win_data->fb_x));
482 vp_reg_write(res, VP_SRC_V_POSITION, win_data->fb_y);
484 vp_reg_write(res, VP_DST_WIDTH, win_data->crtc_width);
485 vp_reg_write(res, VP_DST_H_POSITION, win_data->crtc_x);
486 if (ctx->interlace) {
487 vp_reg_write(res, VP_DST_HEIGHT, win_data->crtc_height / 2);
488 vp_reg_write(res, VP_DST_V_POSITION, win_data->crtc_y / 2);
490 vp_reg_write(res, VP_DST_HEIGHT, win_data->crtc_height);
491 vp_reg_write(res, VP_DST_V_POSITION, win_data->crtc_y);
494 vp_reg_write(res, VP_H_RATIO, x_ratio);
495 vp_reg_write(res, VP_V_RATIO, y_ratio);
497 vp_reg_write(res, VP_ENDIAN_MODE, VP_ENDIAN_MODE_LITTLE);
499 /* set buffer address to vp */
500 vp_reg_write(res, VP_TOP_Y_PTR, luma_addr[0]);
501 vp_reg_write(res, VP_BOT_Y_PTR, luma_addr[1]);
502 vp_reg_write(res, VP_TOP_C_PTR, chroma_addr[0]);
503 vp_reg_write(res, VP_BOT_C_PTR, chroma_addr[1]);
505 mixer_cfg_scan(ctx, win_data->mode_height);
506 mixer_cfg_rgb_fmt(ctx, win_data->mode_height);
507 mixer_cfg_layer(ctx, win, true);
510 mixer_vsync_set_update(ctx, true);
511 spin_unlock_irqrestore(&res->reg_slock, flags);
516 static void mixer_layer_update(struct mixer_context *ctx)
518 struct mixer_resources *res = &ctx->mixer_res;
520 mixer_reg_writemask(res, MXR_CFG, ~0, MXR_CFG_LAYER_UPDATE);
523 static void mixer_graph_buffer(struct mixer_context *ctx, int win)
525 struct mixer_resources *res = &ctx->mixer_res;
527 struct hdmi_win_data *win_data;
528 unsigned int x_ratio, y_ratio;
529 unsigned int src_x_offset, src_y_offset, dst_x_offset, dst_y_offset;
534 win_data = &ctx->win_data[win];
541 switch (win_data->bpp) {
552 /* 2x scaling feature */
556 dst_x_offset = win_data->crtc_x;
557 dst_y_offset = win_data->crtc_y;
559 /* converting dma address base and source offset */
560 dma_addr = win_data->dma_addr
561 + (win_data->fb_x * win_data->bpp >> 3)
562 + (win_data->fb_y * win_data->fb_width * win_data->bpp >> 3);
566 if (win_data->scan_flags & DRM_MODE_FLAG_INTERLACE)
567 ctx->interlace = true;
569 ctx->interlace = false;
571 spin_lock_irqsave(&res->reg_slock, flags);
572 mixer_vsync_set_update(ctx, false);
575 mixer_reg_writemask(res, MXR_GRAPHIC_CFG(win),
576 MXR_GRP_CFG_FORMAT_VAL(fmt), MXR_GRP_CFG_FORMAT_MASK);
579 mixer_reg_write(res, MXR_GRAPHIC_SPAN(win), win_data->fb_width);
581 /* setup display size */
582 if (ctx->mxr_ver == MXR_VER_128_0_0_184 &&
583 win == MIXER_DEFAULT_WIN) {
584 val = MXR_MXR_RES_HEIGHT(win_data->mode_height);
585 val |= MXR_MXR_RES_WIDTH(win_data->mode_width);
586 mixer_reg_write(res, MXR_RESOLUTION, val);
589 val = MXR_GRP_WH_WIDTH(win_data->crtc_width);
590 val |= MXR_GRP_WH_HEIGHT(win_data->crtc_height);
591 val |= MXR_GRP_WH_H_SCALE(x_ratio);
592 val |= MXR_GRP_WH_V_SCALE(y_ratio);
593 mixer_reg_write(res, MXR_GRAPHIC_WH(win), val);
595 /* setup offsets in source image */
596 val = MXR_GRP_SXY_SX(src_x_offset);
597 val |= MXR_GRP_SXY_SY(src_y_offset);
598 mixer_reg_write(res, MXR_GRAPHIC_SXY(win), val);
600 /* setup offsets in display image */
601 val = MXR_GRP_DXY_DX(dst_x_offset);
602 val |= MXR_GRP_DXY_DY(dst_y_offset);
603 mixer_reg_write(res, MXR_GRAPHIC_DXY(win), val);
605 /* set buffer address to mixer */
606 mixer_reg_write(res, MXR_GRAPHIC_BASE(win), dma_addr);
608 mixer_cfg_scan(ctx, win_data->mode_height);
609 mixer_cfg_rgb_fmt(ctx, win_data->mode_height);
610 mixer_cfg_layer(ctx, win, true);
612 /* layer update mandatory for mixer 16.0.33.0 */
613 if (ctx->mxr_ver == MXR_VER_16_0_33_0 ||
614 ctx->mxr_ver == MXR_VER_128_0_0_184)
615 mixer_layer_update(ctx);
619 mixer_vsync_set_update(ctx, true);
620 spin_unlock_irqrestore(&res->reg_slock, flags);
623 static void vp_win_reset(struct mixer_context *ctx)
625 struct mixer_resources *res = &ctx->mixer_res;
628 vp_reg_write(res, VP_SRESET, VP_SRESET_PROCESSING);
629 for (tries = 100; tries; --tries) {
630 /* waiting until VP_SRESET_PROCESSING is 0 */
631 if (~vp_reg_read(res, VP_SRESET) & VP_SRESET_PROCESSING)
633 usleep_range(10000, 12000);
635 WARN(tries == 0, "failed to reset Video Processor\n");
638 static void mixer_win_reset(struct mixer_context *ctx)
640 struct mixer_resources *res = &ctx->mixer_res;
642 u32 val; /* value stored to register */
644 spin_lock_irqsave(&res->reg_slock, flags);
645 mixer_vsync_set_update(ctx, false);
647 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_DST_HDMI, MXR_CFG_DST_MASK);
649 /* set output in RGB888 mode */
650 mixer_reg_writemask(res, MXR_CFG, MXR_CFG_OUT_RGB888, MXR_CFG_OUT_MASK);
652 /* 16 beat burst in DMA */
653 mixer_reg_writemask(res, MXR_STATUS, MXR_STATUS_16_BURST,
654 MXR_STATUS_BURST_MASK);
656 /* setting default layer priority: layer1 > layer0 > video
657 * because typical usage scenario would be
659 * layer0 - framebuffer
660 * video - video overlay
662 val = MXR_LAYER_CFG_GRP1_VAL(3);
663 val |= MXR_LAYER_CFG_GRP0_VAL(2);
665 val |= MXR_LAYER_CFG_VP_VAL(1);
666 mixer_reg_write(res, MXR_LAYER_CFG, val);
668 /* setting background color */
669 mixer_reg_write(res, MXR_BG_COLOR0, 0x008080);
670 mixer_reg_write(res, MXR_BG_COLOR1, 0x008080);
671 mixer_reg_write(res, MXR_BG_COLOR2, 0x008080);
673 /* setting graphical layers */
674 val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
675 val |= MXR_GRP_CFG_WIN_BLEND_EN;
676 val |= MXR_GRP_CFG_ALPHA_VAL(0xff); /* non-transparent alpha */
678 /* Don't blend layer 0 onto the mixer background */
679 mixer_reg_write(res, MXR_GRAPHIC_CFG(0), val);
681 /* Blend layer 1 into layer 0 */
682 val |= MXR_GRP_CFG_BLEND_PRE_MUL;
683 val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
684 mixer_reg_write(res, MXR_GRAPHIC_CFG(1), val);
686 /* setting video layers */
687 val = MXR_GRP_CFG_ALPHA_VAL(0);
688 mixer_reg_write(res, MXR_VIDEO_CFG, val);
690 if (ctx->vp_enabled) {
691 /* configuration of Video Processor Registers */
693 vp_default_filter(res);
696 /* disable all layers */
697 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP0_ENABLE);
698 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_GRP1_ENABLE);
700 mixer_reg_writemask(res, MXR_CFG, 0, MXR_CFG_VP_ENABLE);
702 mixer_vsync_set_update(ctx, true);
703 spin_unlock_irqrestore(&res->reg_slock, flags);
706 static irqreturn_t mixer_irq_handler(int irq, void *arg)
708 struct mixer_context *ctx = arg;
709 struct mixer_resources *res = &ctx->mixer_res;
710 u32 val, base, shadow;
712 spin_lock(&res->reg_slock);
714 /* read interrupt status for handling and clearing flags for VSYNC */
715 val = mixer_reg_read(res, MXR_INT_STATUS);
718 if (val & MXR_INT_STATUS_VSYNC) {
719 /* interlace scan need to check shadow register */
720 if (ctx->interlace) {
721 base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
722 shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(0));
726 base = mixer_reg_read(res, MXR_GRAPHIC_BASE(1));
727 shadow = mixer_reg_read(res, MXR_GRAPHIC_BASE_S(1));
732 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
733 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
735 /* set wait vsync event to zero and wake up queue. */
736 if (atomic_read(&ctx->wait_vsync_event)) {
737 atomic_set(&ctx->wait_vsync_event, 0);
738 wake_up(&ctx->wait_vsync_queue);
743 /* clear interrupts */
744 if (~val & MXR_INT_EN_VSYNC) {
745 /* vsync interrupt use different bit for read and clear */
746 val &= ~MXR_INT_EN_VSYNC;
747 val |= MXR_INT_CLEAR_VSYNC;
749 mixer_reg_write(res, MXR_INT_STATUS, val);
751 spin_unlock(&res->reg_slock);
756 static int mixer_resources_init(struct mixer_context *mixer_ctx)
758 struct device *dev = &mixer_ctx->pdev->dev;
759 struct mixer_resources *mixer_res = &mixer_ctx->mixer_res;
760 struct resource *res;
763 spin_lock_init(&mixer_res->reg_slock);
765 mixer_res->mixer = devm_clk_get(dev, "mixer");
766 if (IS_ERR(mixer_res->mixer)) {
767 dev_err(dev, "failed to get clock 'mixer'\n");
771 mixer_res->hdmi = devm_clk_get(dev, "hdmi");
772 if (IS_ERR(mixer_res->hdmi)) {
773 dev_err(dev, "failed to get clock 'hdmi'\n");
774 return PTR_ERR(mixer_res->hdmi);
777 mixer_res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi");
778 if (IS_ERR(mixer_res->sclk_hdmi)) {
779 dev_err(dev, "failed to get clock 'sclk_hdmi'\n");
782 res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 0);
784 dev_err(dev, "get memory resource failed.\n");
788 mixer_res->mixer_regs = devm_ioremap(dev, res->start,
790 if (mixer_res->mixer_regs == NULL) {
791 dev_err(dev, "register mapping failed.\n");
795 res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_IRQ, 0);
797 dev_err(dev, "get interrupt resource failed.\n");
801 ret = devm_request_irq(dev, res->start, mixer_irq_handler,
802 0, "drm_mixer", mixer_ctx);
804 dev_err(dev, "request interrupt failed.\n");
807 mixer_res->irq = res->start;
812 static int vp_resources_init(struct mixer_context *mixer_ctx)
814 struct device *dev = &mixer_ctx->pdev->dev;
815 struct mixer_resources *mixer_res = &mixer_ctx->mixer_res;
816 struct resource *res;
818 mixer_res->vp = devm_clk_get(dev, "vp");
819 if (IS_ERR(mixer_res->vp)) {
820 dev_err(dev, "failed to get clock 'vp'\n");
824 if (mixer_ctx->has_sclk) {
825 mixer_res->sclk_mixer = devm_clk_get(dev, "sclk_mixer");
826 if (IS_ERR(mixer_res->sclk_mixer)) {
827 dev_err(dev, "failed to get clock 'sclk_mixer'\n");
830 mixer_res->mout_mixer = devm_clk_get(dev, "mout_mixer");
831 if (IS_ERR(mixer_res->mout_mixer)) {
832 dev_err(dev, "failed to get clock 'mout_mixer'\n");
836 if (mixer_res->sclk_hdmi && mixer_res->mout_mixer)
837 clk_set_parent(mixer_res->mout_mixer,
838 mixer_res->sclk_hdmi);
841 res = platform_get_resource(mixer_ctx->pdev, IORESOURCE_MEM, 1);
843 dev_err(dev, "get memory resource failed.\n");
847 mixer_res->vp_regs = devm_ioremap(dev, res->start,
849 if (mixer_res->vp_regs == NULL) {
850 dev_err(dev, "register mapping failed.\n");
857 static int mixer_initialize(struct mixer_context *mixer_ctx,
858 struct drm_device *drm_dev)
861 struct exynos_drm_private *priv;
862 priv = drm_dev->dev_private;
864 mixer_ctx->drm_dev = drm_dev;
865 mixer_ctx->pipe = priv->pipe++;
867 /* acquire resources: regs, irqs, clocks */
868 ret = mixer_resources_init(mixer_ctx);
870 DRM_ERROR("mixer_resources_init failed ret=%d\n", ret);
874 if (mixer_ctx->vp_enabled) {
875 /* acquire vp resources: regs, irqs, clocks */
876 ret = vp_resources_init(mixer_ctx);
878 DRM_ERROR("vp_resources_init failed ret=%d\n", ret);
883 if (!is_drm_iommu_supported(mixer_ctx->drm_dev))
886 return drm_iommu_attach_device(mixer_ctx->drm_dev, mixer_ctx->dev);
889 static void mixer_ctx_remove(struct mixer_context *mixer_ctx)
891 if (is_drm_iommu_supported(mixer_ctx->drm_dev))
892 drm_iommu_detach_device(mixer_ctx->drm_dev, mixer_ctx->dev);
895 static int mixer_enable_vblank(struct exynos_drm_crtc *crtc)
897 struct mixer_context *mixer_ctx = crtc->ctx;
898 struct mixer_resources *res = &mixer_ctx->mixer_res;
900 if (!mixer_ctx->powered) {
901 mixer_ctx->int_en |= MXR_INT_EN_VSYNC;
905 /* enable vsync interrupt */
906 mixer_reg_writemask(res, MXR_INT_EN, MXR_INT_EN_VSYNC,
912 static void mixer_disable_vblank(struct exynos_drm_crtc *crtc)
914 struct mixer_context *mixer_ctx = crtc->ctx;
915 struct mixer_resources *res = &mixer_ctx->mixer_res;
917 /* disable vsync interrupt */
918 mixer_reg_writemask(res, MXR_INT_EN, 0, MXR_INT_EN_VSYNC);
921 static void mixer_win_mode_set(struct exynos_drm_crtc *crtc,
922 struct exynos_drm_plane *plane)
924 struct mixer_context *mixer_ctx = crtc->ctx;
925 struct hdmi_win_data *win_data;
929 DRM_ERROR("plane is NULL\n");
933 DRM_DEBUG_KMS("set [%d]x[%d] at (%d,%d) to [%d]x[%d] at (%d,%d)\n",
934 plane->fb_width, plane->fb_height,
935 plane->fb_x, plane->fb_y,
936 plane->crtc_width, plane->crtc_height,
937 plane->crtc_x, plane->crtc_y);
940 if (win == DEFAULT_ZPOS)
941 win = MIXER_DEFAULT_WIN;
943 if (win < 0 || win >= MIXER_WIN_NR) {
944 DRM_ERROR("mixer window[%d] is wrong\n", win);
948 win_data = &mixer_ctx->win_data[win];
950 win_data->dma_addr = plane->dma_addr[0];
951 win_data->chroma_dma_addr = plane->dma_addr[1];
952 win_data->pixel_format = plane->pixel_format;
953 win_data->bpp = plane->bpp;
955 win_data->crtc_x = plane->crtc_x;
956 win_data->crtc_y = plane->crtc_y;
957 win_data->crtc_width = plane->crtc_width;
958 win_data->crtc_height = plane->crtc_height;
960 win_data->fb_x = plane->fb_x;
961 win_data->fb_y = plane->fb_y;
962 win_data->fb_width = plane->fb_width;
963 win_data->fb_height = plane->fb_height;
964 win_data->src_width = plane->src_width;
965 win_data->src_height = plane->src_height;
967 win_data->mode_width = plane->mode_width;
968 win_data->mode_height = plane->mode_height;
970 win_data->scan_flags = plane->scan_flag;
973 static void mixer_win_commit(struct exynos_drm_crtc *crtc, int zpos)
975 struct mixer_context *mixer_ctx = crtc->ctx;
976 int win = zpos == DEFAULT_ZPOS ? MIXER_DEFAULT_WIN : zpos;
978 DRM_DEBUG_KMS("win: %d\n", win);
980 mutex_lock(&mixer_ctx->mixer_mutex);
981 if (!mixer_ctx->powered) {
982 mutex_unlock(&mixer_ctx->mixer_mutex);
985 mutex_unlock(&mixer_ctx->mixer_mutex);
987 if (win > 1 && mixer_ctx->vp_enabled)
988 vp_video_buffer(mixer_ctx, win);
990 mixer_graph_buffer(mixer_ctx, win);
992 mixer_ctx->win_data[win].enabled = true;
995 static void mixer_win_disable(struct exynos_drm_crtc *crtc, int zpos)
997 struct mixer_context *mixer_ctx = crtc->ctx;
998 struct mixer_resources *res = &mixer_ctx->mixer_res;
999 int win = zpos == DEFAULT_ZPOS ? MIXER_DEFAULT_WIN : zpos;
1000 unsigned long flags;
1002 DRM_DEBUG_KMS("win: %d\n", win);
1004 mutex_lock(&mixer_ctx->mixer_mutex);
1005 if (!mixer_ctx->powered) {
1006 mutex_unlock(&mixer_ctx->mixer_mutex);
1007 mixer_ctx->win_data[win].resume = false;
1010 mutex_unlock(&mixer_ctx->mixer_mutex);
1012 spin_lock_irqsave(&res->reg_slock, flags);
1013 mixer_vsync_set_update(mixer_ctx, false);
1015 mixer_cfg_layer(mixer_ctx, win, false);
1017 mixer_vsync_set_update(mixer_ctx, true);
1018 spin_unlock_irqrestore(&res->reg_slock, flags);
1020 mixer_ctx->win_data[win].enabled = false;
1023 static void mixer_wait_for_vblank(struct exynos_drm_crtc *crtc)
1025 struct mixer_context *mixer_ctx = crtc->ctx;
1028 mutex_lock(&mixer_ctx->mixer_mutex);
1029 if (!mixer_ctx->powered) {
1030 mutex_unlock(&mixer_ctx->mixer_mutex);
1033 mutex_unlock(&mixer_ctx->mixer_mutex);
1035 err = drm_vblank_get(mixer_ctx->drm_dev, mixer_ctx->pipe);
1037 DRM_DEBUG_KMS("failed to acquire vblank counter\n");
1041 atomic_set(&mixer_ctx->wait_vsync_event, 1);
1044 * wait for MIXER to signal VSYNC interrupt or return after
1045 * timeout which is set to 50ms (refresh rate of 20).
1047 if (!wait_event_timeout(mixer_ctx->wait_vsync_queue,
1048 !atomic_read(&mixer_ctx->wait_vsync_event),
1050 DRM_DEBUG_KMS("vblank wait timed out.\n");
1052 drm_vblank_put(mixer_ctx->drm_dev, mixer_ctx->pipe);
1055 static void mixer_window_suspend(struct mixer_context *ctx)
1057 struct hdmi_win_data *win_data;
1060 for (i = 0; i < MIXER_WIN_NR; i++) {
1061 win_data = &ctx->win_data[i];
1062 win_data->resume = win_data->enabled;
1063 mixer_win_disable(ctx->crtc, i);
1065 mixer_wait_for_vblank(ctx->crtc);
1068 static void mixer_window_resume(struct mixer_context *ctx)
1070 struct hdmi_win_data *win_data;
1073 for (i = 0; i < MIXER_WIN_NR; i++) {
1074 win_data = &ctx->win_data[i];
1075 win_data->enabled = win_data->resume;
1076 win_data->resume = false;
1077 if (win_data->enabled)
1078 mixer_win_commit(ctx->crtc, i);
1082 static void mixer_poweron(struct mixer_context *ctx)
1084 struct mixer_resources *res = &ctx->mixer_res;
1086 mutex_lock(&ctx->mixer_mutex);
1088 mutex_unlock(&ctx->mixer_mutex);
1092 mutex_unlock(&ctx->mixer_mutex);
1094 pm_runtime_get_sync(ctx->dev);
1096 clk_prepare_enable(res->mixer);
1097 clk_prepare_enable(res->hdmi);
1098 if (ctx->vp_enabled) {
1099 clk_prepare_enable(res->vp);
1101 clk_prepare_enable(res->sclk_mixer);
1104 mutex_lock(&ctx->mixer_mutex);
1105 ctx->powered = true;
1106 mutex_unlock(&ctx->mixer_mutex);
1108 mixer_reg_writemask(res, MXR_STATUS, ~0, MXR_STATUS_SOFT_RESET);
1110 mixer_reg_write(res, MXR_INT_EN, ctx->int_en);
1111 mixer_win_reset(ctx);
1113 mixer_window_resume(ctx);
1116 static void mixer_poweroff(struct mixer_context *ctx)
1118 struct mixer_resources *res = &ctx->mixer_res;
1120 mutex_lock(&ctx->mixer_mutex);
1121 if (!ctx->powered) {
1122 mutex_unlock(&ctx->mixer_mutex);
1125 mutex_unlock(&ctx->mixer_mutex);
1128 mixer_window_suspend(ctx);
1130 ctx->int_en = mixer_reg_read(res, MXR_INT_EN);
1132 mutex_lock(&ctx->mixer_mutex);
1133 ctx->powered = false;
1134 mutex_unlock(&ctx->mixer_mutex);
1136 clk_disable_unprepare(res->hdmi);
1137 clk_disable_unprepare(res->mixer);
1138 if (ctx->vp_enabled) {
1139 clk_disable_unprepare(res->vp);
1141 clk_disable_unprepare(res->sclk_mixer);
1144 pm_runtime_put_sync(ctx->dev);
1147 static void mixer_dpms(struct exynos_drm_crtc *crtc, int mode)
1150 case DRM_MODE_DPMS_ON:
1151 mixer_poweron(crtc->ctx);
1153 case DRM_MODE_DPMS_STANDBY:
1154 case DRM_MODE_DPMS_SUSPEND:
1155 case DRM_MODE_DPMS_OFF:
1156 mixer_poweroff(crtc->ctx);
1159 DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
1164 /* Only valid for Mixer version 16.0.33.0 */
1165 int mixer_check_mode(struct drm_display_mode *mode)
1172 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d\n",
1173 mode->hdisplay, mode->vdisplay, mode->vrefresh,
1174 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1176 if ((w >= 464 && w <= 720 && h >= 261 && h <= 576) ||
1177 (w >= 1024 && w <= 1280 && h >= 576 && h <= 720) ||
1178 (w >= 1664 && w <= 1920 && h >= 936 && h <= 1080))
1184 static struct exynos_drm_crtc_ops mixer_crtc_ops = {
1186 .enable_vblank = mixer_enable_vblank,
1187 .disable_vblank = mixer_disable_vblank,
1188 .wait_for_vblank = mixer_wait_for_vblank,
1189 .win_mode_set = mixer_win_mode_set,
1190 .win_commit = mixer_win_commit,
1191 .win_disable = mixer_win_disable,
1194 static struct mixer_drv_data exynos5420_mxr_drv_data = {
1195 .version = MXR_VER_128_0_0_184,
1199 static struct mixer_drv_data exynos5250_mxr_drv_data = {
1200 .version = MXR_VER_16_0_33_0,
1204 static struct mixer_drv_data exynos4212_mxr_drv_data = {
1205 .version = MXR_VER_0_0_0_16,
1209 static struct mixer_drv_data exynos4210_mxr_drv_data = {
1210 .version = MXR_VER_0_0_0_16,
1215 static struct platform_device_id mixer_driver_types[] = {
1217 .name = "s5p-mixer",
1218 .driver_data = (unsigned long)&exynos4210_mxr_drv_data,
1220 .name = "exynos5-mixer",
1221 .driver_data = (unsigned long)&exynos5250_mxr_drv_data,
1227 static struct of_device_id mixer_match_types[] = {
1229 .compatible = "samsung,exynos4210-mixer",
1230 .data = &exynos4210_mxr_drv_data,
1232 .compatible = "samsung,exynos4212-mixer",
1233 .data = &exynos4212_mxr_drv_data,
1235 .compatible = "samsung,exynos5-mixer",
1236 .data = &exynos5250_mxr_drv_data,
1238 .compatible = "samsung,exynos5250-mixer",
1239 .data = &exynos5250_mxr_drv_data,
1241 .compatible = "samsung,exynos5420-mixer",
1242 .data = &exynos5420_mxr_drv_data,
1247 MODULE_DEVICE_TABLE(of, mixer_match_types);
1249 static int mixer_bind(struct device *dev, struct device *manager, void *data)
1251 struct mixer_context *ctx = dev_get_drvdata(dev);
1252 struct drm_device *drm_dev = data;
1255 ret = mixer_initialize(ctx, drm_dev);
1259 ctx->crtc = exynos_drm_crtc_create(drm_dev, ctx->pipe,
1260 EXYNOS_DISPLAY_TYPE_HDMI,
1261 &mixer_crtc_ops, ctx);
1262 if (IS_ERR(ctx->crtc)) {
1263 mixer_ctx_remove(ctx);
1264 ret = PTR_ERR(ctx->crtc);
1271 devm_kfree(dev, ctx);
1275 static void mixer_unbind(struct device *dev, struct device *master, void *data)
1277 struct mixer_context *ctx = dev_get_drvdata(dev);
1279 mixer_ctx_remove(ctx);
1282 static const struct component_ops mixer_component_ops = {
1284 .unbind = mixer_unbind,
1287 static int mixer_probe(struct platform_device *pdev)
1289 struct device *dev = &pdev->dev;
1290 struct mixer_drv_data *drv;
1291 struct mixer_context *ctx;
1294 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
1296 DRM_ERROR("failed to alloc mixer context.\n");
1300 mutex_init(&ctx->mixer_mutex);
1303 const struct of_device_id *match;
1305 match = of_match_node(mixer_match_types, dev->of_node);
1306 drv = (struct mixer_drv_data *)match->data;
1308 drv = (struct mixer_drv_data *)
1309 platform_get_device_id(pdev)->driver_data;
1314 ctx->vp_enabled = drv->is_vp_enabled;
1315 ctx->has_sclk = drv->has_sclk;
1316 ctx->mxr_ver = drv->version;
1317 init_waitqueue_head(&ctx->wait_vsync_queue);
1318 atomic_set(&ctx->wait_vsync_event, 0);
1320 platform_set_drvdata(pdev, ctx);
1322 ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC,
1323 EXYNOS_DISPLAY_TYPE_HDMI);
1327 ret = component_add(&pdev->dev, &mixer_component_ops);
1329 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1333 pm_runtime_enable(dev);
1338 static int mixer_remove(struct platform_device *pdev)
1340 pm_runtime_disable(&pdev->dev);
1342 component_del(&pdev->dev, &mixer_component_ops);
1343 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1348 struct platform_driver mixer_driver = {
1350 .name = "exynos-mixer",
1351 .owner = THIS_MODULE,
1352 .of_match_table = mixer_match_types,
1354 .probe = mixer_probe,
1355 .remove = mixer_remove,
1356 .id_table = mixer_driver_types,