2 * Copyright © 2006-2011 Intel Corporation
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * Eric Anholt <eric@anholt.net>
21 #include <linux/i2c.h>
22 #include <linux/pm_runtime.h>
25 #include "framebuffer.h"
27 #include "psb_intel_drv.h"
28 #include "psb_intel_reg.h"
29 #include "psb_intel_display.h"
31 #include "cdv_device.h"
34 struct cdv_intel_range_t {
38 struct cdv_intel_p2_t {
43 struct cdv_intel_clock_t {
55 #define INTEL_P2_NUM 2
57 struct cdv_intel_limit_t {
58 struct cdv_intel_range_t dot, vco, n, m, m1, m2, p, p1;
59 struct cdv_intel_p2_t p2;
62 #define CDV_LIMIT_SINGLE_LVDS_96 0
63 #define CDV_LIMIT_SINGLE_LVDS_100 1
64 #define CDV_LIMIT_DAC_HDMI_27 2
65 #define CDV_LIMIT_DAC_HDMI_96 3
67 static const struct cdv_intel_limit_t cdv_intel_limits[] = {
68 { /* CDV_SIGNLE_LVDS_96MHz */
69 .dot = {.min = 20000, .max = 115500},
70 .vco = {.min = 1800000, .max = 3600000},
71 .n = {.min = 2, .max = 6},
72 .m = {.min = 60, .max = 160},
73 .m1 = {.min = 0, .max = 0},
74 .m2 = {.min = 58, .max = 158},
75 .p = {.min = 28, .max = 140},
76 .p1 = {.min = 2, .max = 10},
77 .p2 = {.dot_limit = 200000,
78 .p2_slow = 14, .p2_fast = 14},
80 { /* CDV_SINGLE_LVDS_100MHz */
81 .dot = {.min = 20000, .max = 115500},
82 .vco = {.min = 1800000, .max = 3600000},
83 .n = {.min = 2, .max = 6},
84 .m = {.min = 60, .max = 160},
85 .m1 = {.min = 0, .max = 0},
86 .m2 = {.min = 58, .max = 158},
87 .p = {.min = 28, .max = 140},
88 .p1 = {.min = 2, .max = 10},
89 /* The single-channel range is 25-112Mhz, and dual-channel
90 * is 80-224Mhz. Prefer single channel as much as possible.
92 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
94 { /* CDV_DAC_HDMI_27MHz */
95 .dot = {.min = 20000, .max = 400000},
96 .vco = {.min = 1809000, .max = 3564000},
97 .n = {.min = 1, .max = 1},
98 .m = {.min = 67, .max = 132},
99 .m1 = {.min = 0, .max = 0},
100 .m2 = {.min = 65, .max = 130},
101 .p = {.min = 5, .max = 90},
102 .p1 = {.min = 1, .max = 9},
103 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
105 { /* CDV_DAC_HDMI_96MHz */
106 .dot = {.min = 20000, .max = 400000},
107 .vco = {.min = 1800000, .max = 3600000},
108 .n = {.min = 2, .max = 6},
109 .m = {.min = 60, .max = 160},
110 .m1 = {.min = 0, .max = 0},
111 .m2 = {.min = 58, .max = 158},
112 .p = {.min = 5, .max = 100},
113 .p1 = {.min = 1, .max = 10},
114 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
118 #define _wait_for(COND, MS, W) ({ \
119 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
122 if (time_after(jiffies, timeout__)) { \
123 ret__ = -ETIMEDOUT; \
126 if (W && !in_dbg_master()) \
132 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
135 static int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val)
139 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
141 DRM_ERROR("timeout waiting for SB to idle before read\n");
145 REG_WRITE(SB_ADDR, reg);
147 SET_FIELD(SB_OPCODE_READ, SB_OPCODE) |
148 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
149 SET_FIELD(0xf, SB_BYTE_ENABLE));
151 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
153 DRM_ERROR("timeout waiting for SB to idle after read\n");
157 *val = REG_READ(SB_DATA);
162 static int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val)
165 static bool dpio_debug = true;
169 if (cdv_sb_read(dev, reg, &temp) == 0)
170 DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp);
171 DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val);
174 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
176 DRM_ERROR("timeout waiting for SB to idle before write\n");
180 REG_WRITE(SB_ADDR, reg);
181 REG_WRITE(SB_DATA, val);
183 SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) |
184 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
185 SET_FIELD(0xf, SB_BYTE_ENABLE));
187 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
189 DRM_ERROR("timeout waiting for SB to idle after write\n");
194 if (cdv_sb_read(dev, reg, &temp) == 0)
195 DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp);
201 /* Reset the DPIO configuration register. The BIOS does this at every
204 static void cdv_sb_reset(struct drm_device *dev)
207 REG_WRITE(DPIO_CFG, 0);
209 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
212 /* Unlike most Intel display engines, on Cedarview the DPLL registers
213 * are behind this sideband bus. They must be programmed while the
214 * DPLL reference clock is on in the DPLL control register, but before
215 * the DPLL is enabled in the DPLL control register.
218 cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
219 struct cdv_intel_clock_t *clock)
221 struct psb_intel_crtc *psb_crtc =
222 to_psb_intel_crtc(crtc);
223 int pipe = psb_crtc->pipe;
226 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
231 if ((REG_READ(dpll_reg) & DPLL_SYNCLOCK_ENABLE) == 0) {
232 DRM_ERROR("Attempting to set DPLL with refclk disabled\n");
236 /* Follow the BIOS and write the REF/SFR Register. Hardcoded value */
237 ref_value = 0x68A701;
239 cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value);
241 /* We don't know what the other fields of these regs are, so
242 * leave them in place.
244 ret = cdv_sb_read(dev, SB_M(pipe), &m);
247 m &= ~SB_M_DIVIDER_MASK;
248 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT);
249 ret = cdv_sb_write(dev, SB_M(pipe), m);
253 ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco);
257 /* Follow the BIOS to program the N_DIVIDER REG */
260 n_vco &= ~(SB_N_VCO_SEL_MASK |
264 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT);
266 if (clock->vco < 2250000) {
267 n_vco |= (2 << SB_N_CB_TUNE_SHIFT);
268 n_vco |= (0 << SB_N_VCO_SEL_SHIFT);
269 } else if (clock->vco < 2750000) {
270 n_vco |= (1 << SB_N_CB_TUNE_SHIFT);
271 n_vco |= (1 << SB_N_VCO_SEL_SHIFT);
272 } else if (clock->vco < 3300000) {
273 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
274 n_vco |= (2 << SB_N_VCO_SEL_SHIFT);
276 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
277 n_vco |= (3 << SB_N_VCO_SEL_SHIFT);
280 ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco);
284 ret = cdv_sb_read(dev, SB_P(pipe), &p);
287 p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK);
288 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER);
291 p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER);
294 p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER);
297 p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER);
300 p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER);
303 DRM_ERROR("Bad P2 clock: %d\n", clock->p2);
306 ret = cdv_sb_write(dev, SB_P(pipe), p);
310 /* always Program the Lane Register for the Pipe A*/
312 /* Program the Lane0/1 for HDMI B */
313 u32 lane_reg, lane_value;
315 lane_reg = PSB_LANE0;
316 cdv_sb_read(dev, lane_reg, &lane_value);
317 lane_value &= ~(LANE_PLL_MASK);
318 lane_value |= LANE_PLL_ENABLE;
319 cdv_sb_write(dev, lane_reg, lane_value);
321 lane_reg = PSB_LANE1;
322 cdv_sb_read(dev, lane_reg, &lane_value);
323 lane_value &= ~(LANE_PLL_MASK);
324 lane_value |= LANE_PLL_ENABLE;
325 cdv_sb_write(dev, lane_reg, lane_value);
327 /* Program the Lane2/3 for HDMI C */
328 lane_reg = PSB_LANE2;
329 cdv_sb_read(dev, lane_reg, &lane_value);
330 lane_value &= ~(LANE_PLL_MASK);
331 lane_value |= LANE_PLL_ENABLE;
332 cdv_sb_write(dev, lane_reg, lane_value);
334 lane_reg = PSB_LANE3;
335 cdv_sb_read(dev, lane_reg, &lane_value);
336 lane_value &= ~(LANE_PLL_MASK);
337 lane_value |= LANE_PLL_ENABLE;
338 cdv_sb_write(dev, lane_reg, lane_value);
345 * Returns whether any encoder on the specified pipe is of the specified type
347 static bool cdv_intel_pipe_has_type(struct drm_crtc *crtc, int type)
349 struct drm_device *dev = crtc->dev;
350 struct drm_mode_config *mode_config = &dev->mode_config;
351 struct drm_connector *l_entry;
353 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
354 if (l_entry->encoder && l_entry->encoder->crtc == crtc) {
355 struct psb_intel_encoder *psb_intel_encoder =
356 psb_intel_attached_encoder(l_entry);
357 if (psb_intel_encoder->type == type)
364 static const struct cdv_intel_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
367 const struct cdv_intel_limit_t *limit;
368 if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
370 * Now only single-channel LVDS is supported on CDV. If it is
371 * incorrect, please add the dual-channel LVDS.
374 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96];
376 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100];
379 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_27];
381 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_96];
386 /* m1 is reserved as 0 in CDV, n is a ring counter */
387 static void cdv_intel_clock(struct drm_device *dev,
388 int refclk, struct cdv_intel_clock_t *clock)
390 clock->m = clock->m2 + 2;
391 clock->p = clock->p1 * clock->p2;
392 clock->vco = (refclk * clock->m) / clock->n;
393 clock->dot = clock->vco / clock->p;
397 #define INTELPllInvalid(s) { /* ErrorF (s) */; return false; }
398 static bool cdv_intel_PLL_is_valid(struct drm_crtc *crtc,
399 const struct cdv_intel_limit_t *limit,
400 struct cdv_intel_clock_t *clock)
402 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
403 INTELPllInvalid("p1 out of range\n");
404 if (clock->p < limit->p.min || limit->p.max < clock->p)
405 INTELPllInvalid("p out of range\n");
406 /* unnecessary to check the range of m(m1/M2)/n again */
407 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
408 INTELPllInvalid("vco out of range\n");
409 /* XXX: We may need to be checking "Dot clock"
410 * depending on the multiplier, connector, etc.,
411 * rather than just a single range.
413 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
414 INTELPllInvalid("dot out of range\n");
419 static bool cdv_intel_find_best_PLL(struct drm_crtc *crtc, int target,
421 struct cdv_intel_clock_t *best_clock)
423 struct drm_device *dev = crtc->dev;
424 struct cdv_intel_clock_t clock;
425 const struct cdv_intel_limit_t *limit = cdv_intel_limit(crtc, refclk);
429 if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
430 (REG_READ(LVDS) & LVDS_PORT_EN) != 0) {
432 * For LVDS, if the panel is on, just rely on its current
433 * settings for dual-channel. We haven't figured out how to
434 * reliably set up different single/dual channel state, if we
437 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
439 clock.p2 = limit->p2.p2_fast;
441 clock.p2 = limit->p2.p2_slow;
443 if (target < limit->p2.dot_limit)
444 clock.p2 = limit->p2.p2_slow;
446 clock.p2 = limit->p2.p2_fast;
449 memset(best_clock, 0, sizeof(*best_clock));
451 /* m1 is reserved as 0 in CDV, n is a ring counter.
452 So skip the m1 loop */
453 for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
454 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max;
456 for (clock.p1 = limit->p1.min;
457 clock.p1 <= limit->p1.max;
461 cdv_intel_clock(dev, refclk, &clock);
463 if (!cdv_intel_PLL_is_valid(crtc,
467 this_err = abs(clock.dot - target);
468 if (this_err < err) {
476 return err != target;
479 static int cdv_intel_pipe_set_base(struct drm_crtc *crtc,
480 int x, int y, struct drm_framebuffer *old_fb)
482 struct drm_device *dev = crtc->dev;
483 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
484 struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
485 int pipe = psb_intel_crtc->pipe;
486 unsigned long start, offset;
487 int dspbase = (pipe == 0 ? DSPABASE : DSPBBASE);
488 int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
489 int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
490 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
494 if (!gma_power_begin(dev, true))
499 dev_err(dev->dev, "No FB bound\n");
500 goto psb_intel_pipe_cleaner;
504 /* We are displaying this buffer, make sure it is actually loaded
506 ret = psb_gtt_pin(psbfb->gtt);
508 goto psb_intel_pipe_set_base_exit;
509 start = psbfb->gtt->offset;
510 offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
512 REG_WRITE(dspstride, crtc->fb->pitches[0]);
514 dspcntr = REG_READ(dspcntr_reg);
515 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
517 switch (crtc->fb->bits_per_pixel) {
519 dspcntr |= DISPPLANE_8BPP;
522 if (crtc->fb->depth == 15)
523 dspcntr |= DISPPLANE_15_16BPP;
525 dspcntr |= DISPPLANE_16BPP;
529 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
532 dev_err(dev->dev, "Unknown color depth\n");
534 goto psb_intel_pipe_set_base_exit;
536 REG_WRITE(dspcntr_reg, dspcntr);
539 "Writing base %08lX %08lX %d %d\n", start, offset, x, y);
541 REG_WRITE(dspbase, offset);
543 REG_WRITE(dspsurf, start);
546 psb_intel_pipe_cleaner:
547 /* If there was a previous display we can now unpin it */
549 psb_gtt_unpin(to_psb_fb(old_fb)->gtt);
551 psb_intel_pipe_set_base_exit:
557 * Sets the power management mode of the pipe and plane.
559 * This code should probably grow support for turning the cursor off and back
560 * on appropriately at the same time as we're turning the pipe off/on.
562 static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
564 struct drm_device *dev = crtc->dev;
565 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
566 int pipe = psb_intel_crtc->pipe;
567 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
568 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
569 int dspbase_reg = (pipe == 0) ? DSPABASE : DSPBBASE;
570 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
573 /* XXX: When our outputs are all unaware of DPMS modes other than off
574 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
577 case DRM_MODE_DPMS_ON:
578 case DRM_MODE_DPMS_STANDBY:
579 case DRM_MODE_DPMS_SUSPEND:
580 /* Enable the DPLL */
581 temp = REG_READ(dpll_reg);
582 if ((temp & DPLL_VCO_ENABLE) == 0) {
583 REG_WRITE(dpll_reg, temp);
585 /* Wait for the clocks to stabilize. */
587 REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
589 /* Wait for the clocks to stabilize. */
591 REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
593 /* Wait for the clocks to stabilize. */
597 /* Jim Bish - switch plan and pipe per scott */
598 /* Enable the plane */
599 temp = REG_READ(dspcntr_reg);
600 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
601 REG_WRITE(dspcntr_reg,
602 temp | DISPLAY_PLANE_ENABLE);
603 /* Flush the plane changes */
604 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
609 /* Enable the pipe */
610 temp = REG_READ(pipeconf_reg);
611 if ((temp & PIPEACONF_ENABLE) == 0)
612 REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
614 psb_intel_crtc_load_lut(crtc);
616 /* Give the overlay scaler a chance to enable
617 * if it's on this pipe */
618 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
620 case DRM_MODE_DPMS_OFF:
621 /* Give the overlay scaler a chance to disable
622 * if it's on this pipe */
623 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
625 /* Disable the VGA plane that we never use */
626 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
628 /* Jim Bish - changed pipe/plane here as well. */
630 /* Wait for vblank for the disable to take effect */
631 cdv_intel_wait_for_vblank(dev);
633 /* Next, disable display pipes */
634 temp = REG_READ(pipeconf_reg);
635 if ((temp & PIPEACONF_ENABLE) != 0) {
636 REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
637 REG_READ(pipeconf_reg);
640 /* Wait for vblank for the disable to take effect. */
641 cdv_intel_wait_for_vblank(dev);
645 /* Disable display plane */
646 temp = REG_READ(dspcntr_reg);
647 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
648 REG_WRITE(dspcntr_reg,
649 temp & ~DISPLAY_PLANE_ENABLE);
650 /* Flush the plane changes */
651 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
652 REG_READ(dspbase_reg);
655 temp = REG_READ(dpll_reg);
656 if ((temp & DPLL_VCO_ENABLE) != 0) {
657 REG_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
661 /* Wait for the clocks to turn off. */
665 /*Set FIFO Watermarks*/
666 REG_WRITE(DSPARB, 0x3F3E);
669 static void cdv_intel_crtc_prepare(struct drm_crtc *crtc)
671 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
672 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
675 static void cdv_intel_crtc_commit(struct drm_crtc *crtc)
677 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
678 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
681 static bool cdv_intel_crtc_mode_fixup(struct drm_crtc *crtc,
682 struct drm_display_mode *mode,
683 struct drm_display_mode *adjusted_mode)
690 * Return the pipe currently connected to the panel fitter,
691 * or -1 if the panel fitter is not present or not in use
693 static int cdv_intel_panel_fitter_pipe(struct drm_device *dev)
697 pfit_control = REG_READ(PFIT_CONTROL);
699 /* See if the panel fitter is in use */
700 if ((pfit_control & PFIT_ENABLE) == 0)
702 return (pfit_control >> 29) & 0x3;
705 static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
706 struct drm_display_mode *mode,
707 struct drm_display_mode *adjusted_mode,
709 struct drm_framebuffer *old_fb)
711 struct drm_device *dev = crtc->dev;
712 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
713 int pipe = psb_intel_crtc->pipe;
714 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
715 int dpll_md_reg = (psb_intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
716 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
717 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
718 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
719 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
720 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
721 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
722 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
723 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
724 int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
725 int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
726 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
728 struct cdv_intel_clock_t clock;
729 u32 dpll = 0, dspcntr, pipeconf;
731 bool is_crt = false, is_lvds = false, is_tv = false;
732 bool is_hdmi = false;
733 struct drm_mode_config *mode_config = &dev->mode_config;
734 struct drm_connector *connector;
736 list_for_each_entry(connector, &mode_config->connector_list, head) {
737 struct psb_intel_encoder *psb_intel_encoder =
738 psb_intel_attached_encoder(connector);
740 if (!connector->encoder
741 || connector->encoder->crtc != crtc)
744 switch (psb_intel_encoder->type) {
745 case INTEL_OUTPUT_LVDS:
748 case INTEL_OUTPUT_TVOUT:
751 case INTEL_OUTPUT_ANALOG:
754 case INTEL_OUTPUT_HDMI:
762 /* Hack selection about ref clk for CRT */
763 /* Select 27MHz as the reference clk for HDMI */
764 if (is_crt || is_hdmi)
767 drm_mode_debug_printmodeline(adjusted_mode);
769 ok = cdv_intel_find_best_PLL(crtc, adjusted_mode->clock, refclk,
772 dev_err(dev->dev, "Couldn't find PLL settings for mode!\n");
776 dpll = DPLL_VGA_MODE_DIS;
778 /* XXX: just matching BIOS for now */
779 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
782 dpll |= PLL_REF_INPUT_DREFCLK;
784 dpll |= DPLL_SYNCLOCK_ENABLE;
785 dpll |= DPLL_VGA_MODE_DIS;
787 dpll |= DPLLB_MODE_LVDS;
789 dpll |= DPLLB_MODE_DAC_SERIAL;
790 /* dpll |= (2 << 11); */
793 pipeconf = REG_READ(pipeconf_reg);
795 /* Set up the display plane register */
796 dspcntr = DISPPLANE_GAMMA_ENABLE;
799 dspcntr |= DISPPLANE_SEL_PIPE_A;
801 dspcntr |= DISPPLANE_SEL_PIPE_B;
803 dspcntr |= DISPLAY_PLANE_ENABLE;
804 pipeconf |= PIPEACONF_ENABLE;
806 REG_WRITE(dpll_reg, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
809 cdv_dpll_set_clock_cdv(dev, crtc, &clock);
814 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
815 * This is an exception to the general rule that mode_set doesn't turn
819 u32 lvds = REG_READ(LVDS);
822 LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP |
824 /* Set the B0-B3 data pairs corresponding to
825 * whether we're going to
826 * set the DPLLs for dual-channel mode or not.
829 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
831 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
833 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
834 * appropriately here, but we need to look more
835 * thoroughly into how panels behave in the two modes.
838 REG_WRITE(LVDS, lvds);
842 dpll |= DPLL_VCO_ENABLE;
844 /* Disable the panel fitter if it was on our pipe */
845 if (cdv_intel_panel_fitter_pipe(dev) == pipe)
846 REG_WRITE(PFIT_CONTROL, 0);
848 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
849 drm_mode_debug_printmodeline(mode);
852 (REG_READ(dpll_reg) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);
854 /* Wait for the clocks to stabilize. */
855 udelay(150); /* 42 usec w/o calibration, 110 with. rounded up. */
857 if (!(REG_READ(dpll_reg) & DPLL_LOCK)) {
858 dev_err(dev->dev, "Failed to get DPLL lock\n");
863 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
864 REG_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
867 REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
868 ((adjusted_mode->crtc_htotal - 1) << 16));
869 REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
870 ((adjusted_mode->crtc_hblank_end - 1) << 16));
871 REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
872 ((adjusted_mode->crtc_hsync_end - 1) << 16));
873 REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
874 ((adjusted_mode->crtc_vtotal - 1) << 16));
875 REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
876 ((adjusted_mode->crtc_vblank_end - 1) << 16));
877 REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
878 ((adjusted_mode->crtc_vsync_end - 1) << 16));
879 /* pipesrc and dspsize control the size that is scaled from,
880 * which should always be the user's requested size.
882 REG_WRITE(dspsize_reg,
883 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
884 REG_WRITE(dsppos_reg, 0);
885 REG_WRITE(pipesrc_reg,
886 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
887 REG_WRITE(pipeconf_reg, pipeconf);
888 REG_READ(pipeconf_reg);
890 cdv_intel_wait_for_vblank(dev);
892 REG_WRITE(dspcntr_reg, dspcntr);
894 /* Flush the plane changes */
896 struct drm_crtc_helper_funcs *crtc_funcs =
897 crtc->helper_private;
898 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
901 cdv_intel_wait_for_vblank(dev);
906 /** Loads the palette/gamma unit for the CRTC with the prepared values */
907 static void cdv_intel_crtc_load_lut(struct drm_crtc *crtc)
909 struct drm_device *dev = crtc->dev;
910 struct drm_psb_private *dev_priv =
911 (struct drm_psb_private *)dev->dev_private;
912 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
913 int palreg = PALETTE_A;
916 /* The clocks have to be on to load the palette. */
920 switch (psb_intel_crtc->pipe) {
930 dev_err(dev->dev, "Illegal Pipe Number.\n");
934 if (gma_power_begin(dev, false)) {
935 for (i = 0; i < 256; i++) {
936 REG_WRITE(palreg + 4 * i,
937 ((psb_intel_crtc->lut_r[i] +
938 psb_intel_crtc->lut_adj[i]) << 16) |
939 ((psb_intel_crtc->lut_g[i] +
940 psb_intel_crtc->lut_adj[i]) << 8) |
941 (psb_intel_crtc->lut_b[i] +
942 psb_intel_crtc->lut_adj[i]));
946 for (i = 0; i < 256; i++) {
947 dev_priv->regs.psb.save_palette_a[i] =
948 ((psb_intel_crtc->lut_r[i] +
949 psb_intel_crtc->lut_adj[i]) << 16) |
950 ((psb_intel_crtc->lut_g[i] +
951 psb_intel_crtc->lut_adj[i]) << 8) |
952 (psb_intel_crtc->lut_b[i] +
953 psb_intel_crtc->lut_adj[i]);
960 * Save HW states of giving crtc
962 static void cdv_intel_crtc_save(struct drm_crtc *crtc)
964 struct drm_device *dev = crtc->dev;
965 /* struct drm_psb_private *dev_priv =
966 (struct drm_psb_private *)dev->dev_private; */
967 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
968 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
969 int pipeA = (psb_intel_crtc->pipe == 0);
974 dev_dbg(dev->dev, "No CRTC state found\n");
978 crtc_state->saveDSPCNTR = REG_READ(pipeA ? DSPACNTR : DSPBCNTR);
979 crtc_state->savePIPECONF = REG_READ(pipeA ? PIPEACONF : PIPEBCONF);
980 crtc_state->savePIPESRC = REG_READ(pipeA ? PIPEASRC : PIPEBSRC);
981 crtc_state->saveFP0 = REG_READ(pipeA ? FPA0 : FPB0);
982 crtc_state->saveFP1 = REG_READ(pipeA ? FPA1 : FPB1);
983 crtc_state->saveDPLL = REG_READ(pipeA ? DPLL_A : DPLL_B);
984 crtc_state->saveHTOTAL = REG_READ(pipeA ? HTOTAL_A : HTOTAL_B);
985 crtc_state->saveHBLANK = REG_READ(pipeA ? HBLANK_A : HBLANK_B);
986 crtc_state->saveHSYNC = REG_READ(pipeA ? HSYNC_A : HSYNC_B);
987 crtc_state->saveVTOTAL = REG_READ(pipeA ? VTOTAL_A : VTOTAL_B);
988 crtc_state->saveVBLANK = REG_READ(pipeA ? VBLANK_A : VBLANK_B);
989 crtc_state->saveVSYNC = REG_READ(pipeA ? VSYNC_A : VSYNC_B);
990 crtc_state->saveDSPSTRIDE = REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE);
992 /*NOTE: DSPSIZE DSPPOS only for psb*/
993 crtc_state->saveDSPSIZE = REG_READ(pipeA ? DSPASIZE : DSPBSIZE);
994 crtc_state->saveDSPPOS = REG_READ(pipeA ? DSPAPOS : DSPBPOS);
996 crtc_state->saveDSPBASE = REG_READ(pipeA ? DSPABASE : DSPBBASE);
998 DRM_DEBUG("(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
999 crtc_state->saveDSPCNTR,
1000 crtc_state->savePIPECONF,
1001 crtc_state->savePIPESRC,
1002 crtc_state->saveFP0,
1003 crtc_state->saveFP1,
1004 crtc_state->saveDPLL,
1005 crtc_state->saveHTOTAL,
1006 crtc_state->saveHBLANK,
1007 crtc_state->saveHSYNC,
1008 crtc_state->saveVTOTAL,
1009 crtc_state->saveVBLANK,
1010 crtc_state->saveVSYNC,
1011 crtc_state->saveDSPSTRIDE,
1012 crtc_state->saveDSPSIZE,
1013 crtc_state->saveDSPPOS,
1014 crtc_state->saveDSPBASE
1017 paletteReg = pipeA ? PALETTE_A : PALETTE_B;
1018 for (i = 0; i < 256; ++i)
1019 crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2));
1023 * Restore HW states of giving crtc
1025 static void cdv_intel_crtc_restore(struct drm_crtc *crtc)
1027 struct drm_device *dev = crtc->dev;
1028 /* struct drm_psb_private * dev_priv =
1029 (struct drm_psb_private *)dev->dev_private; */
1030 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1031 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
1032 /* struct drm_crtc_helper_funcs * crtc_funcs = crtc->helper_private; */
1033 int pipeA = (psb_intel_crtc->pipe == 0);
1034 uint32_t paletteReg;
1038 dev_dbg(dev->dev, "No crtc state\n");
1043 "current:(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
1044 REG_READ(pipeA ? DSPACNTR : DSPBCNTR),
1045 REG_READ(pipeA ? PIPEACONF : PIPEBCONF),
1046 REG_READ(pipeA ? PIPEASRC : PIPEBSRC),
1047 REG_READ(pipeA ? FPA0 : FPB0),
1048 REG_READ(pipeA ? FPA1 : FPB1),
1049 REG_READ(pipeA ? DPLL_A : DPLL_B),
1050 REG_READ(pipeA ? HTOTAL_A : HTOTAL_B),
1051 REG_READ(pipeA ? HBLANK_A : HBLANK_B),
1052 REG_READ(pipeA ? HSYNC_A : HSYNC_B),
1053 REG_READ(pipeA ? VTOTAL_A : VTOTAL_B),
1054 REG_READ(pipeA ? VBLANK_A : VBLANK_B),
1055 REG_READ(pipeA ? VSYNC_A : VSYNC_B),
1056 REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE),
1057 REG_READ(pipeA ? DSPASIZE : DSPBSIZE),
1058 REG_READ(pipeA ? DSPAPOS : DSPBPOS),
1059 REG_READ(pipeA ? DSPABASE : DSPBBASE)
1063 "saved: (%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
1064 crtc_state->saveDSPCNTR,
1065 crtc_state->savePIPECONF,
1066 crtc_state->savePIPESRC,
1067 crtc_state->saveFP0,
1068 crtc_state->saveFP1,
1069 crtc_state->saveDPLL,
1070 crtc_state->saveHTOTAL,
1071 crtc_state->saveHBLANK,
1072 crtc_state->saveHSYNC,
1073 crtc_state->saveVTOTAL,
1074 crtc_state->saveVBLANK,
1075 crtc_state->saveVSYNC,
1076 crtc_state->saveDSPSTRIDE,
1077 crtc_state->saveDSPSIZE,
1078 crtc_state->saveDSPPOS,
1079 crtc_state->saveDSPBASE
1083 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
1084 REG_WRITE(pipeA ? DPLL_A : DPLL_B,
1085 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
1086 REG_READ(pipeA ? DPLL_A : DPLL_B);
1087 DRM_DEBUG("write dpll: %x\n",
1088 REG_READ(pipeA ? DPLL_A : DPLL_B));
1092 REG_WRITE(pipeA ? FPA0 : FPB0, crtc_state->saveFP0);
1093 REG_READ(pipeA ? FPA0 : FPB0);
1095 REG_WRITE(pipeA ? FPA1 : FPB1, crtc_state->saveFP1);
1096 REG_READ(pipeA ? FPA1 : FPB1);
1098 REG_WRITE(pipeA ? DPLL_A : DPLL_B, crtc_state->saveDPLL);
1099 REG_READ(pipeA ? DPLL_A : DPLL_B);
1102 REG_WRITE(pipeA ? HTOTAL_A : HTOTAL_B, crtc_state->saveHTOTAL);
1103 REG_WRITE(pipeA ? HBLANK_A : HBLANK_B, crtc_state->saveHBLANK);
1104 REG_WRITE(pipeA ? HSYNC_A : HSYNC_B, crtc_state->saveHSYNC);
1105 REG_WRITE(pipeA ? VTOTAL_A : VTOTAL_B, crtc_state->saveVTOTAL);
1106 REG_WRITE(pipeA ? VBLANK_A : VBLANK_B, crtc_state->saveVBLANK);
1107 REG_WRITE(pipeA ? VSYNC_A : VSYNC_B, crtc_state->saveVSYNC);
1108 REG_WRITE(pipeA ? DSPASTRIDE : DSPBSTRIDE, crtc_state->saveDSPSTRIDE);
1110 REG_WRITE(pipeA ? DSPASIZE : DSPBSIZE, crtc_state->saveDSPSIZE);
1111 REG_WRITE(pipeA ? DSPAPOS : DSPBPOS, crtc_state->saveDSPPOS);
1113 REG_WRITE(pipeA ? PIPEASRC : PIPEBSRC, crtc_state->savePIPESRC);
1114 REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE);
1115 REG_WRITE(pipeA ? PIPEACONF : PIPEBCONF, crtc_state->savePIPECONF);
1117 cdv_intel_wait_for_vblank(dev);
1119 REG_WRITE(pipeA ? DSPACNTR : DSPBCNTR, crtc_state->saveDSPCNTR);
1120 REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE);
1122 cdv_intel_wait_for_vblank(dev);
1124 paletteReg = pipeA ? PALETTE_A : PALETTE_B;
1125 for (i = 0; i < 256; ++i)
1126 REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]);
1129 static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc,
1130 struct drm_file *file_priv,
1132 uint32_t width, uint32_t height)
1134 struct drm_device *dev = crtc->dev;
1135 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1136 int pipe = psb_intel_crtc->pipe;
1137 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
1138 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
1141 struct gtt_range *gt;
1142 struct drm_gem_object *obj;
1145 /* if we want to turn of the cursor ignore width and height */
1147 /* turn off the cursor */
1148 temp = CURSOR_MODE_DISABLE;
1150 if (gma_power_begin(dev, false)) {
1151 REG_WRITE(control, temp);
1156 /* unpin the old GEM object */
1157 if (psb_intel_crtc->cursor_obj) {
1158 gt = container_of(psb_intel_crtc->cursor_obj,
1159 struct gtt_range, gem);
1161 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
1162 psb_intel_crtc->cursor_obj = NULL;
1168 /* Currently we only support 64x64 cursors */
1169 if (width != 64 || height != 64) {
1170 dev_dbg(dev->dev, "we currently only support 64x64 cursors\n");
1174 obj = drm_gem_object_lookup(dev, file_priv, handle);
1178 if (obj->size < width * height * 4) {
1179 dev_dbg(dev->dev, "buffer is to small\n");
1183 gt = container_of(obj, struct gtt_range, gem);
1185 /* Pin the memory into the GTT */
1186 ret = psb_gtt_pin(gt);
1188 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
1192 addr = gt->offset; /* Or resource.start ??? */
1194 psb_intel_crtc->cursor_addr = addr;
1197 /* set the pipe for the cursor */
1198 temp |= (pipe << 28);
1199 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
1201 if (gma_power_begin(dev, false)) {
1202 REG_WRITE(control, temp);
1203 REG_WRITE(base, addr);
1207 /* unpin the old GEM object */
1208 if (psb_intel_crtc->cursor_obj) {
1209 gt = container_of(psb_intel_crtc->cursor_obj,
1210 struct gtt_range, gem);
1212 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
1213 psb_intel_crtc->cursor_obj = obj;
1218 static int cdv_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1220 struct drm_device *dev = crtc->dev;
1221 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1222 int pipe = psb_intel_crtc->pipe;
1228 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
1232 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
1236 temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
1237 temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1239 adder = psb_intel_crtc->cursor_addr;
1241 if (gma_power_begin(dev, false)) {
1242 REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
1243 REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
1249 static void cdv_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
1250 u16 *green, u16 *blue, uint32_t start, uint32_t size)
1252 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1254 int end = (start + size > 256) ? 256 : start + size;
1256 for (i = start; i < end; i++) {
1257 psb_intel_crtc->lut_r[i] = red[i] >> 8;
1258 psb_intel_crtc->lut_g[i] = green[i] >> 8;
1259 psb_intel_crtc->lut_b[i] = blue[i] >> 8;
1262 cdv_intel_crtc_load_lut(crtc);
1265 static int cdv_crtc_set_config(struct drm_mode_set *set)
1268 struct drm_device *dev = set->crtc->dev;
1269 struct drm_psb_private *dev_priv = dev->dev_private;
1271 if (!dev_priv->rpm_enabled)
1272 return drm_crtc_helper_set_config(set);
1274 pm_runtime_forbid(&dev->pdev->dev);
1276 ret = drm_crtc_helper_set_config(set);
1278 pm_runtime_allow(&dev->pdev->dev);
1283 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
1285 /* FIXME: why are we using this, should it be cdv_ in this tree ? */
1287 static void i8xx_clock(int refclk, struct cdv_intel_clock_t *clock)
1289 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
1290 clock->p = clock->p1 * clock->p2;
1291 clock->vco = refclk * clock->m / (clock->n + 2);
1292 clock->dot = clock->vco / clock->p;
1295 /* Returns the clock of the currently programmed mode of the given pipe. */
1296 static int cdv_intel_crtc_clock_get(struct drm_device *dev,
1297 struct drm_crtc *crtc)
1299 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1300 int pipe = psb_intel_crtc->pipe;
1303 struct cdv_intel_clock_t clock;
1305 struct drm_psb_private *dev_priv = dev->dev_private;
1307 if (gma_power_begin(dev, false)) {
1308 dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B);
1309 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1310 fp = REG_READ((pipe == 0) ? FPA0 : FPB0);
1312 fp = REG_READ((pipe == 0) ? FPA1 : FPB1);
1313 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
1316 dpll = (pipe == 0) ?
1317 dev_priv->regs.psb.saveDPLL_A :
1318 dev_priv->regs.psb.saveDPLL_B;
1320 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1322 dev_priv->regs.psb.saveFPA0 :
1323 dev_priv->regs.psb.saveFPB0;
1326 dev_priv->regs.psb.saveFPA1 :
1327 dev_priv->regs.psb.saveFPB1;
1329 is_lvds = (pipe == 1) &&
1330 (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN);
1333 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
1334 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
1335 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
1340 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
1341 DPLL_FPA01_P1_POST_DIV_SHIFT);
1342 if (clock.p1 == 0) {
1344 dev_err(dev->dev, "PLL %d\n", dpll);
1348 if ((dpll & PLL_REF_INPUT_MASK) ==
1349 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
1350 /* XXX: might not be 66MHz */
1351 i8xx_clock(66000, &clock);
1353 i8xx_clock(48000, &clock);
1355 if (dpll & PLL_P1_DIVIDE_BY_TWO)
1360 DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
1361 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
1363 if (dpll & PLL_P2_DIVIDE_BY_4)
1368 i8xx_clock(48000, &clock);
1371 /* XXX: It would be nice to validate the clocks, but we can't reuse
1372 * i830PllIsValid() because it relies on the xf86_config connector
1373 * configuration being accurate, which it isn't necessarily.
1379 /** Returns the currently programmed mode of the given pipe. */
1380 struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
1381 struct drm_crtc *crtc)
1383 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1384 int pipe = psb_intel_crtc->pipe;
1385 struct drm_display_mode *mode;
1390 struct drm_psb_private *dev_priv = dev->dev_private;
1392 if (gma_power_begin(dev, false)) {
1393 htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
1394 hsync = REG_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
1395 vtot = REG_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
1396 vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
1399 htot = (pipe == 0) ?
1400 dev_priv->regs.psb.saveHTOTAL_A :
1401 dev_priv->regs.psb.saveHTOTAL_B;
1402 hsync = (pipe == 0) ?
1403 dev_priv->regs.psb.saveHSYNC_A :
1404 dev_priv->regs.psb.saveHSYNC_B;
1405 vtot = (pipe == 0) ?
1406 dev_priv->regs.psb.saveVTOTAL_A :
1407 dev_priv->regs.psb.saveVTOTAL_B;
1408 vsync = (pipe == 0) ?
1409 dev_priv->regs.psb.saveVSYNC_A :
1410 dev_priv->regs.psb.saveVSYNC_B;
1413 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
1417 mode->clock = cdv_intel_crtc_clock_get(dev, crtc);
1418 mode->hdisplay = (htot & 0xffff) + 1;
1419 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
1420 mode->hsync_start = (hsync & 0xffff) + 1;
1421 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
1422 mode->vdisplay = (vtot & 0xffff) + 1;
1423 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
1424 mode->vsync_start = (vsync & 0xffff) + 1;
1425 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
1427 drm_mode_set_name(mode);
1428 drm_mode_set_crtcinfo(mode, 0);
1433 static void cdv_intel_crtc_destroy(struct drm_crtc *crtc)
1435 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1437 kfree(psb_intel_crtc->crtc_state);
1438 drm_crtc_cleanup(crtc);
1439 kfree(psb_intel_crtc);
1442 const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
1443 .dpms = cdv_intel_crtc_dpms,
1444 .mode_fixup = cdv_intel_crtc_mode_fixup,
1445 .mode_set = cdv_intel_crtc_mode_set,
1446 .mode_set_base = cdv_intel_pipe_set_base,
1447 .prepare = cdv_intel_crtc_prepare,
1448 .commit = cdv_intel_crtc_commit,
1451 const struct drm_crtc_funcs cdv_intel_crtc_funcs = {
1452 .save = cdv_intel_crtc_save,
1453 .restore = cdv_intel_crtc_restore,
1454 .cursor_set = cdv_intel_crtc_cursor_set,
1455 .cursor_move = cdv_intel_crtc_cursor_move,
1456 .gamma_set = cdv_intel_crtc_gamma_set,
1457 .set_config = cdv_crtc_set_config,
1458 .destroy = cdv_intel_crtc_destroy,