1 /**************************************************************************
2 * Copyright (c) 2007-2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 **************************************************************************/
23 #include <linux/kref.h>
26 #include <drm/drm_global.h>
27 #include <drm/gma_drm.h>
29 #include "psb_intel_drv.h"
30 #include "gma_display.h"
31 #include "intel_bios.h"
38 #define DRIVER_AUTHOR "Alan Cox <alan@linux.intel.com> and others"
39 #define DRIVER_LICENSE "GPL"
41 #define DRIVER_NAME "gma500"
42 #define DRIVER_DESC "DRM driver for the Intel GMA500, GMA600, GMA3600, GMA3650"
43 #define DRIVER_DATE "20140314"
45 #define DRIVER_MAJOR 1
46 #define DRIVER_MINOR 0
47 #define DRIVER_PATCHLEVEL 0
49 /* Append new drm mode definition here, align with libdrm definition */
50 #define DRM_MODE_SCALE_NO_SCALE 2
53 CHIP_PSB_8108 = 0, /* Poulsbo */
54 CHIP_PSB_8109 = 1, /* Poulsbo */
55 CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */
56 CHIP_MFLD_0130 = 3, /* Medfield */
59 #define IS_PSB(dev) (((dev)->pdev->device & 0xfffe) == 0x8108)
60 #define IS_MRST(dev) (((dev)->pdev->device & 0xfff0) == 0x4100)
61 #define IS_MFLD(dev) (((dev)->pdev->device & 0xfff8) == 0x0130)
62 #define IS_CDV(dev) (((dev)->pdev->device & 0xfff0) == 0x0be0)
64 /* Hardware offsets */
65 #define PSB_VDC_OFFSET 0x00000000
66 #define PSB_VDC_SIZE 0x000080000
67 #define MRST_MMIO_SIZE 0x0000C0000
68 #define MDFLD_MMIO_SIZE 0x000100000
69 #define PSB_SGX_SIZE 0x8000
70 #define PSB_SGX_OFFSET 0x00040000
71 #define MRST_SGX_OFFSET 0x00080000
73 /* PCI resource identifiers */
74 #define PSB_MMIO_RESOURCE 0
75 #define PSB_AUX_RESOURCE 0
76 #define PSB_GATT_RESOURCE 2
77 #define PSB_GTT_RESOURCE 3
79 /* PCI configuration */
80 #define PSB_GMCH_CTRL 0x52
82 #define _PSB_GMCH_ENABLED 0x4
83 #define PSB_PGETBL_CTL 0x2020
84 #define _PSB_PGETBL_ENABLED 0x00000001
85 #define PSB_SGX_2D_SLAVE_PORT 0x4000
87 /* TODO: To get rid of */
88 #define PSB_TT_PRIV0_LIMIT (256*1024*1024)
89 #define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
91 /* SGX side MMU definitions (these can probably go) */
93 /* Flags for external memory type field */
94 #define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
95 #define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
96 #define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
99 #define PSB_PDE_MASK 0x003FFFFF
100 #define PSB_PDE_SHIFT 22
101 #define PSB_PTE_SHIFT 12
104 #define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
105 #define PSB_PTE_WO 0x0002 /* Write only */
106 #define PSB_PTE_RO 0x0004 /* Read only */
107 #define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
109 /* VDC registers and bits */
110 #define PSB_MSVDX_CLOCKGATING 0x2064
111 #define PSB_TOPAZ_CLOCKGATING 0x2068
112 #define PSB_HWSTAM 0x2098
113 #define PSB_INSTPM 0x20C0
114 #define PSB_INT_IDENTITY_R 0x20A4
115 #define _PSB_IRQ_ASLE (1<<0)
116 #define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
117 #define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
118 #define _PSB_DPST_PIPEB_FLAG (1<<4)
119 #define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
120 #define _PSB_VSYNC_PIPEB_FLAG (1<<5)
121 #define _PSB_DPST_PIPEA_FLAG (1<<6)
122 #define _PSB_PIPEA_EVENT_FLAG (1<<6)
123 #define _PSB_VSYNC_PIPEA_FLAG (1<<7)
124 #define _MDFLD_MIPIA_FLAG (1<<16)
125 #define _MDFLD_MIPIC_FLAG (1<<17)
126 #define _PSB_IRQ_DISP_HOTSYNC (1<<17)
127 #define _PSB_IRQ_SGX_FLAG (1<<18)
128 #define _PSB_IRQ_MSVDX_FLAG (1<<19)
129 #define _LNC_IRQ_TOPAZ_FLAG (1<<20)
131 #define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \
132 _PSB_VSYNC_PIPEB_FLAG)
134 /* This flag includes all the display IRQ bits excepts the vblank irqs. */
135 #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
136 _MDFLD_PIPEB_EVENT_FLAG | \
137 _PSB_PIPEA_EVENT_FLAG | \
138 _PSB_VSYNC_PIPEA_FLAG | \
139 _MDFLD_MIPIA_FLAG | \
141 #define PSB_INT_IDENTITY_R 0x20A4
142 #define PSB_INT_MASK_R 0x20A8
143 #define PSB_INT_ENABLE_R 0x20A0
145 #define _PSB_MMU_ER_MASK 0x0001FF00
146 #define _PSB_MMU_ER_HOST (1 << 16)
155 #define GPIO_CLOCK_DIR_MASK (1 << 0)
156 #define GPIO_CLOCK_DIR_IN (0 << 1)
157 #define GPIO_CLOCK_DIR_OUT (1 << 1)
158 #define GPIO_CLOCK_VAL_MASK (1 << 2)
159 #define GPIO_CLOCK_VAL_OUT (1 << 3)
160 #define GPIO_CLOCK_VAL_IN (1 << 4)
161 #define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
162 #define GPIO_DATA_DIR_MASK (1 << 8)
163 #define GPIO_DATA_DIR_IN (0 << 9)
164 #define GPIO_DATA_DIR_OUT (1 << 9)
165 #define GPIO_DATA_VAL_MASK (1 << 10)
166 #define GPIO_DATA_VAL_OUT (1 << 11)
167 #define GPIO_DATA_VAL_IN (1 << 12)
168 #define GPIO_DATA_PULLUP_DISABLE (1 << 13)
170 #define VCLK_DIVISOR_VGA0 0x6000
171 #define VCLK_DIVISOR_VGA1 0x6004
172 #define VCLK_POST_DIV 0x6010
174 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
175 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
176 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
177 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
178 #define PSB_COMM_USER_IRQ (1024 >> 2)
179 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
180 #define PSB_COMM_FW (2048 >> 2)
182 #define PSB_UIRQ_VISTEST 1
183 #define PSB_UIRQ_OOM_REPLY 2
184 #define PSB_UIRQ_FIRE_TA_REPLY 3
185 #define PSB_UIRQ_FIRE_RASTER_REPLY 4
187 #define PSB_2D_SIZE (256*1024*1024)
188 #define PSB_MAX_RELOC_PAGES 1024
190 #define PSB_LOW_REG_OFFS 0x0204
191 #define PSB_HIGH_REG_OFFS 0x0600
193 #define PSB_NUM_VBLANKS 2
196 #define PSB_2D_SIZE (256*1024*1024)
197 #define PSB_MAX_RELOC_PAGES 1024
199 #define PSB_LOW_REG_OFFS 0x0204
200 #define PSB_HIGH_REG_OFFS 0x0600
202 #define PSB_NUM_VBLANKS 2
203 #define PSB_WATCHDOG_DELAY (HZ * 2)
204 #define PSB_LID_DELAY (HZ / 10)
206 #define MDFLD_PNW_B0 0x04
207 #define MDFLD_PNW_C0 0x08
209 #define MDFLD_DSR_2D_3D_0 (1 << 0)
210 #define MDFLD_DSR_2D_3D_2 (1 << 1)
211 #define MDFLD_DSR_CURSOR_0 (1 << 2)
212 #define MDFLD_DSR_CURSOR_2 (1 << 3)
213 #define MDFLD_DSR_OVERLAY_0 (1 << 4)
214 #define MDFLD_DSR_OVERLAY_2 (1 << 5)
215 #define MDFLD_DSR_MIPI_CONTROL (1 << 6)
216 #define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
217 #define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
218 #define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
220 #define MDFLD_DSR_RR 45
221 #define MDFLD_DPU_ENABLE (1 << 31)
222 #define MDFLD_DSR_FULLSCREEN (1 << 30)
223 #define MDFLD_DSR_DELAY (HZ / MDFLD_DSR_RR)
225 #define PSB_PWR_STATE_ON 1
226 #define PSB_PWR_STATE_OFF 2
228 #define PSB_PMPOLICY_NOPM 0
229 #define PSB_PMPOLICY_CLOCKGATING 1
230 #define PSB_PMPOLICY_POWERDOWN 2
232 #define PSB_PMSTATE_POWERUP 0
233 #define PSB_PMSTATE_CLOCKGATED 1
234 #define PSB_PMSTATE_POWERDOWN 2
235 #define PSB_PCIx_MSI_ADDR_LOC 0x94
236 #define PSB_PCIx_MSI_DATA_LOC 0x98
238 /* Medfield crystal settings */
239 #define KSEL_CRYSTAL_19 1
240 #define KSEL_BYPASS_19 5
241 #define KSEL_BYPASS_25 6
242 #define KSEL_BYPASS_83_100 7
244 struct opregion_header;
245 struct opregion_acpi;
246 struct opregion_swsci;
247 struct opregion_asle;
249 struct psb_intel_opregion {
250 struct opregion_header *header;
251 struct opregion_acpi *acpi;
252 struct opregion_swsci *swsci;
253 struct opregion_asle *asle;
255 u32 __iomem *lid_state;
256 struct work_struct asle_work;
259 struct sdvo_device_mapping {
270 struct i2c_adapter adapter;
271 struct i2c_adapter *force_bit;
275 /* Register offset maps */
303 * Register save state. This is used to hold the context when the
304 * device is powered off. In the case of Oaktrail this can (but does not
305 * yet) include screen blank. Operations occuring during the save
306 * update the register cache instead.
309 /* Common status for pipes */
337 uint32_t saveVCLK_DIVISOR_VGA0;
338 uint32_t saveVCLK_DIVISOR_VGA1;
339 uint32_t saveVCLK_POST_DIV;
340 uint32_t saveVGACNTRL;
348 uint32_t savePP_CONTROL;
349 uint32_t savePP_CYCLE;
350 uint32_t savePFIT_CONTROL;
351 uint32_t saveCLOCKGATING;
353 uint32_t savePFIT_AUTO_RATIOS;
354 uint32_t savePFIT_PGM_RATIOS;
355 uint32_t savePP_ON_DELAYS;
356 uint32_t savePP_OFF_DELAYS;
357 uint32_t savePP_DIVISOR;
358 uint32_t saveBCLRPAT_A;
359 uint32_t saveBCLRPAT_B;
360 uint32_t savePERF_MODE;
367 uint32_t saveCHICKENBIT;
368 uint32_t saveDSPACURSOR_CTRL;
369 uint32_t saveDSPBCURSOR_CTRL;
370 uint32_t saveDSPACURSOR_BASE;
371 uint32_t saveDSPBCURSOR_BASE;
372 uint32_t saveDSPACURSOR_POS;
373 uint32_t saveDSPBCURSOR_POS;
374 uint32_t saveOV_OVADD;
375 uint32_t saveOV_OGAMC0;
376 uint32_t saveOV_OGAMC1;
377 uint32_t saveOV_OGAMC2;
378 uint32_t saveOV_OGAMC3;
379 uint32_t saveOV_OGAMC4;
380 uint32_t saveOV_OGAMC5;
381 uint32_t saveOVC_OVADD;
382 uint32_t saveOVC_OGAMC0;
383 uint32_t saveOVC_OGAMC1;
384 uint32_t saveOVC_OGAMC2;
385 uint32_t saveOVC_OGAMC3;
386 uint32_t saveOVC_OGAMC4;
387 uint32_t saveOVC_OGAMC5;
389 /* DPST register save */
390 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
391 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
392 uint32_t savePWM_CONTROL_LOGIC;
395 struct medfield_state {
399 uint32_t savePFIT_CONTROL;
400 uint32_t savePFIT_PGM_RATIOS;
401 uint32_t saveHDMIPHYMISCCTL;
402 uint32_t saveHDMIB_CONTROL;
406 uint32_t saveDSPCLK_GATE_D;
407 uint32_t saveRAMCLK_GATE_D;
409 uint32_t saveDSPFW[6];
411 uint32_t savePP_CONTROL;
412 uint32_t savePFIT_PGM_RATIOS;
414 uint32_t savePFIT_CONTROL;
415 uint32_t savePP_ON_DELAYS;
416 uint32_t savePP_OFF_DELAYS;
417 uint32_t savePP_CYCLE;
418 uint32_t saveVGACNTRL;
424 struct psb_save_area {
425 struct psb_pipe pipe[3];
429 struct psb_state psb;
430 struct medfield_state mdfld;
431 struct cdv_state cdv;
433 uint32_t saveBLC_PWM_CTL2;
434 uint32_t saveBLC_PWM_CTL;
439 #define PSB_NUM_PIPE 3
441 struct drm_psb_private {
442 struct drm_device *dev;
443 struct pci_dev *aux_pdev; /* Currently only used by mrst */
444 const struct psb_ops *ops;
445 const struct psb_offset *regmap;
447 struct child_device_config *child_dev;
452 /* GTT Memory manager */
453 struct psb_gtt_mm *gtt_mm;
454 struct page *scratch_page;
455 u32 __iomem *gtt_map;
456 uint32_t stolen_base;
457 u8 __iomem *vram_addr;
458 unsigned long vram_stolen_size;
460 u16 gmch_ctrl; /* Saved GTT setup */
463 struct mutex gtt_mutex;
464 struct resource *gtt_mem; /* Our PCI resource */
466 struct psb_mmu_driver *mmu;
467 struct psb_mmu_pd *pf_pd;
470 uint8_t __iomem *sgx_reg;
471 uint8_t __iomem *vdc_reg;
472 uint8_t __iomem *aux_reg; /* Auxillary vdc pipe regs */
473 uint32_t gatt_free_offset;
476 uint32_t vdc_irq_mask;
477 uint32_t pipestat[PSB_NUM_PIPE];
479 spinlock_t irqmask_lock;
487 struct psb_intel_mode_device mode_dev;
488 bool modeset; /* true if we have done the mode_device setup */
490 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
491 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
494 /* OSPM info (Power management base) (TODO: can go ?) */
499 u32 video_device_fuse;
501 /* PCI revision ID for B0:D2:F0 */
502 uint8_t platform_rev_id;
505 struct intel_gmbus *gmbus;
506 uint8_t __iomem *gmbus_reg;
510 /* FIXME: The mappings should be parsed from bios but for now we can
511 pretend there are no mappings available */
512 struct sdvo_device_mapping sdvo_mappings[2];
513 u32 hotplug_supported_mask;
514 struct drm_property *broadcast_rgb_property;
515 struct drm_property *force_audio_property;
518 int backlight_duty_cycle; /* restore backlight to this value */
519 bool panel_wants_dither;
520 struct drm_display_mode *panel_fixed_mode;
521 struct drm_display_mode *lfp_lvds_vbt_mode;
522 struct drm_display_mode *sdvo_lvds_vbt_mode;
524 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
525 struct psb_intel_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */
527 /* Feature bits from the VBIOS */
528 unsigned int int_tv_support:1;
529 unsigned int lvds_dither:1;
530 unsigned int lvds_vbt:1;
531 unsigned int int_crt_support:1;
532 unsigned int lvds_use_ssc:1;
536 u32 mipi_ctrl_display;
538 unsigned int core_freq;
539 uint32_t iLVDS_enable;
541 /* Runtime PM state */
546 struct oaktrail_gct_data gct_data;
548 /* Oaktrail HDMI state */
549 struct oaktrail_hdmi_dev *hdmi_priv;
552 struct psb_save_area regs;
558 /* Hotplug handling */
559 struct work_struct hotplug_work;
563 struct timer_list lid_timer;
564 struct psb_intel_opregion opregion;
572 * Used for modifying backlight from
573 * xrandr -- consider removing and using HAL instead
575 struct backlight_device *backlight_device;
576 struct drm_property *backlight_property;
577 bool backlight_enabled;
584 /* 2D acceleration */
587 /* Panel brightness */
589 int brightness_adjusted;
593 bool dpi_panel_on[3];
594 void *dsi_configs[2];
603 bool dplla_96mhz; /* DPLL data from the VBT */
614 struct edp_power_seq pps;
620 /* Operations for each board type */
623 unsigned int accel_2d:1;
624 int pipes; /* Number of output pipes */
625 int crtcs; /* Number of CRTCs */
626 int sgx_offset; /* Base offset of SGX device */
627 int hdmi_mask; /* Mask of HDMI CRTCs */
628 int lvds_mask; /* Mask of LVDS CRTCs */
629 int sdvo_mask; /* Mask of SDVO CRTCs */
630 int cursor_needs_phys; /* If cursor base reg need physical address */
633 struct drm_crtc_helper_funcs const *crtc_helper;
634 struct drm_crtc_funcs const *crtc_funcs;
635 const struct gma_clock_funcs *clock_funcs;
638 int (*chip_setup)(struct drm_device *dev);
639 void (*chip_teardown)(struct drm_device *dev);
640 /* Optional helper caller after modeset */
641 void (*errata)(struct drm_device *dev);
643 /* Display management hooks */
644 int (*output_init)(struct drm_device *dev);
645 int (*hotplug)(struct drm_device *dev);
646 void (*hotplug_enable)(struct drm_device *dev, bool on);
647 /* Power management hooks */
648 void (*init_pm)(struct drm_device *dev);
649 int (*save_regs)(struct drm_device *dev);
650 int (*restore_regs)(struct drm_device *dev);
651 int (*power_up)(struct drm_device *dev);
652 int (*power_down)(struct drm_device *dev);
653 void (*update_wm)(struct drm_device *dev, struct drm_crtc *crtc);
654 void (*disable_sr)(struct drm_device *dev);
656 void (*lvds_bl_power)(struct drm_device *dev, bool on);
657 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
659 int (*backlight_init)(struct drm_device *dev);
661 int i2c_bus; /* I2C bus identifier for Moorestown */
666 extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
667 extern int drm_pick_crtcs(struct drm_device *dev);
669 static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
671 return (struct drm_psb_private *) dev->dev_private;
675 extern irqreturn_t psb_irq_handler(int irq, void *arg);
676 extern int psb_irq_enable_dpst(struct drm_device *dev);
677 extern int psb_irq_disable_dpst(struct drm_device *dev);
678 extern void psb_irq_preinstall(struct drm_device *dev);
679 extern int psb_irq_postinstall(struct drm_device *dev);
680 extern void psb_irq_uninstall(struct drm_device *dev);
681 extern void psb_irq_turn_on_dpst(struct drm_device *dev);
682 extern void psb_irq_turn_off_dpst(struct drm_device *dev);
684 extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
685 extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
686 extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
687 extern int psb_enable_vblank(struct drm_device *dev, int crtc);
688 extern void psb_disable_vblank(struct drm_device *dev, int crtc);
690 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
693 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
695 extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
698 extern int psbfb_probed(struct drm_device *dev);
699 extern int psbfb_remove(struct drm_device *dev,
700 struct drm_framebuffer *fb);
702 extern void psbfb_copyarea(struct fb_info *info,
703 const struct fb_copyarea *region);
704 extern int psbfb_sync(struct fb_info *info);
705 extern void psb_spank(struct drm_psb_private *dev_priv);
708 extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
709 extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
710 extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
713 extern void psb_modeset_init(struct drm_device *dev);
714 extern void psb_modeset_cleanup(struct drm_device *dev);
715 extern int psb_fbdev_init(struct drm_device *dev);
718 int gma_backlight_init(struct drm_device *dev);
719 void gma_backlight_exit(struct drm_device *dev);
720 void gma_backlight_disable(struct drm_device *dev);
721 void gma_backlight_enable(struct drm_device *dev);
722 void gma_backlight_set(struct drm_device *dev, int v);
724 /* oaktrail_crtc.c */
725 extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
727 /* oaktrail_lvds.c */
728 extern void oaktrail_lvds_init(struct drm_device *dev,
729 struct psb_intel_mode_device *mode_dev);
731 /* psb_intel_display.c */
732 extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
733 extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
735 /* psb_intel_lvds.c */
736 extern const struct drm_connector_helper_funcs
737 psb_intel_lvds_connector_helper_funcs;
738 extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
741 extern void psb_gem_free_object(struct drm_gem_object *obj);
742 extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
743 struct drm_file *file);
744 extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
745 struct drm_mode_create_dumb *args);
746 extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
747 uint32_t handle, uint64_t *offset);
748 extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
749 extern int psb_gem_create_ioctl(struct drm_device *dev, void *data,
750 struct drm_file *file);
751 extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data,
752 struct drm_file *file);
755 extern const struct psb_ops psb_chip_ops;
757 /* oaktrail_device.c */
758 extern const struct psb_ops oaktrail_chip_ops;
761 extern const struct psb_ops mdfld_chip_ops;
764 extern const struct psb_ops cdv_chip_ops;
766 /* Debug print bits setting */
767 #define PSB_D_GENERAL (1 << 0)
768 #define PSB_D_INIT (1 << 1)
769 #define PSB_D_IRQ (1 << 2)
770 #define PSB_D_ENTRY (1 << 3)
771 /* debug the get H/V BP/FP count */
772 #define PSB_D_HV (1 << 4)
773 #define PSB_D_DBI_BF (1 << 5)
774 #define PSB_D_PM (1 << 6)
775 #define PSB_D_RENDER (1 << 7)
776 #define PSB_D_REG (1 << 8)
777 #define PSB_D_MSVDX (1 << 9)
778 #define PSB_D_TOPAZ (1 << 10)
780 extern int drm_idle_check_interval;
783 static inline u32 MRST_MSG_READ32(uint port, uint offset)
785 int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
786 uint32_t ret_val = 0;
787 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
788 pci_write_config_dword(pci_root, 0xD0, mcr);
789 pci_read_config_dword(pci_root, 0xD4, &ret_val);
790 pci_dev_put(pci_root);
793 static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
795 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
796 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
797 pci_write_config_dword(pci_root, 0xD4, value);
798 pci_write_config_dword(pci_root, 0xD0, mcr);
799 pci_dev_put(pci_root);
801 static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
803 int mcr = (0x10<<24) | (port << 16) | (offset << 8);
804 uint32_t ret_val = 0;
805 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
806 pci_write_config_dword(pci_root, 0xD0, mcr);
807 pci_read_config_dword(pci_root, 0xD4, &ret_val);
808 pci_dev_put(pci_root);
811 static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
813 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
814 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
815 pci_write_config_dword(pci_root, 0xD4, value);
816 pci_write_config_dword(pci_root, 0xD0, mcr);
817 pci_dev_put(pci_root);
820 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
822 struct drm_psb_private *dev_priv = dev->dev_private;
823 return ioread32(dev_priv->vdc_reg + reg);
826 static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg)
828 struct drm_psb_private *dev_priv = dev->dev_private;
829 return ioread32(dev_priv->aux_reg + reg);
832 #define REG_READ(reg) REGISTER_READ(dev, (reg))
833 #define REG_READ_AUX(reg) REGISTER_READ_AUX(dev, (reg))
835 /* Useful for post reads */
836 static inline uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev,
837 uint32_t reg, int aux)
842 val = REG_READ_AUX(reg);
849 #define REG_READ_WITH_AUX(reg, aux) REGISTER_READ_WITH_AUX(dev, (reg), (aux))
851 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
854 struct drm_psb_private *dev_priv = dev->dev_private;
855 iowrite32((val), dev_priv->vdc_reg + (reg));
858 static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg,
861 struct drm_psb_private *dev_priv = dev->dev_private;
862 iowrite32((val), dev_priv->aux_reg + (reg));
865 #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
866 #define REG_WRITE_AUX(reg, val) REGISTER_WRITE_AUX(dev, (reg), (val))
868 static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg,
869 uint32_t val, int aux)
872 REG_WRITE_AUX(reg, val);
877 #define REG_WRITE_WITH_AUX(reg, val, aux) REGISTER_WRITE_WITH_AUX(dev, (reg), (val), (aux))
879 static inline void REGISTER_WRITE16(struct drm_device *dev,
880 uint32_t reg, uint32_t val)
882 struct drm_psb_private *dev_priv = dev->dev_private;
883 iowrite16((val), dev_priv->vdc_reg + (reg));
886 #define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
888 static inline void REGISTER_WRITE8(struct drm_device *dev,
889 uint32_t reg, uint32_t val)
891 struct drm_psb_private *dev_priv = dev->dev_private;
892 iowrite8((val), dev_priv->vdc_reg + (reg));
895 #define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
897 #define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
898 #define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
900 /* #define TRAP_SGX_PM_FAULT 1 */
901 #ifdef TRAP_SGX_PM_FAULT
902 #define PSB_RSGX32(_offs) \
904 if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
906 "access sgx when it's off!! (READ) %s, %d\n", \
907 __FILE__, __LINE__); \
910 ioread32(dev_priv->sgx_reg + (_offs)); \
913 #define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
915 #define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
917 #define MSVDX_REG_DUMP 0
919 #define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
920 #define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))