1 /**************************************************************************
2 * Copyright (c) 2007-2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 **************************************************************************/
23 #include <linux/kref.h>
26 #include "drm_global.h"
30 #include "psb_intel_drv.h"
35 /* Append new drm mode definition here, align with libdrm definition */
36 #define DRM_MODE_SCALE_NO_SCALE 2
39 CHIP_PSB_8108 = 0, /* Poulsbo */
40 CHIP_PSB_8109 = 1, /* Poulsbo */
41 CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */
42 CHIP_MFLD_0130 = 3, /* Medfield */
45 #define IS_PSB(dev) (((dev)->pci_device & 0xfffe) == 0x8108)
46 #define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
47 #define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130)
53 #define DRIVER_NAME "gma500"
54 #define DRIVER_DESC "DRM driver for the Intel GMA500"
56 #define PSB_DRM_DRIVER_DATE "2011-06-06"
57 #define PSB_DRM_DRIVER_MAJOR 1
58 #define PSB_DRM_DRIVER_MINOR 0
59 #define PSB_DRM_DRIVER_PATCHLEVEL 0
64 #define PSB_VDC_OFFSET 0x00000000
65 #define PSB_VDC_SIZE 0x000080000
66 #define MRST_MMIO_SIZE 0x0000C0000
67 #define MDFLD_MMIO_SIZE 0x000100000
68 #define PSB_SGX_SIZE 0x8000
69 #define PSB_SGX_OFFSET 0x00040000
70 #define MRST_SGX_OFFSET 0x00080000
72 * PCI resource identifiers
74 #define PSB_MMIO_RESOURCE 0
75 #define PSB_GATT_RESOURCE 2
76 #define PSB_GTT_RESOURCE 3
80 #define PSB_GMCH_CTRL 0x52
82 #define _PSB_GMCH_ENABLED 0x4
83 #define PSB_PGETBL_CTL 0x2020
84 #define _PSB_PGETBL_ENABLED 0x00000001
85 #define PSB_SGX_2D_SLAVE_PORT 0x4000
88 #define PSB_TT_PRIV0_LIMIT (256*1024*1024)
89 #define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
92 * SGX side MMU definitions (these can probably go)
96 * Flags for external memory type field.
98 #define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
99 #define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
100 #define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
104 #define PSB_PDE_MASK 0x003FFFFF
105 #define PSB_PDE_SHIFT 22
106 #define PSB_PTE_SHIFT 12
110 #define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
111 #define PSB_PTE_WO 0x0002 /* Write only */
112 #define PSB_PTE_RO 0x0004 /* Read only */
113 #define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
116 * VDC registers and bits
118 #define PSB_MSVDX_CLOCKGATING 0x2064
119 #define PSB_TOPAZ_CLOCKGATING 0x2068
120 #define PSB_HWSTAM 0x2098
121 #define PSB_INSTPM 0x20C0
122 #define PSB_INT_IDENTITY_R 0x20A4
123 #define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
124 #define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
125 #define _PSB_DPST_PIPEB_FLAG (1<<4)
126 #define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
127 #define _PSB_VSYNC_PIPEB_FLAG (1<<5)
128 #define _PSB_DPST_PIPEA_FLAG (1<<6)
129 #define _PSB_PIPEA_EVENT_FLAG (1<<6)
130 #define _PSB_VSYNC_PIPEA_FLAG (1<<7)
131 #define _MDFLD_MIPIA_FLAG (1<<16)
132 #define _MDFLD_MIPIC_FLAG (1<<17)
133 #define _PSB_IRQ_SGX_FLAG (1<<18)
134 #define _PSB_IRQ_MSVDX_FLAG (1<<19)
135 #define _LNC_IRQ_TOPAZ_FLAG (1<<20)
137 /* This flag includes all the display IRQ bits excepts the vblank irqs. */
138 #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
139 _MDFLD_PIPEB_EVENT_FLAG | \
140 _PSB_PIPEA_EVENT_FLAG | \
141 _PSB_VSYNC_PIPEA_FLAG | \
142 _MDFLD_MIPIA_FLAG | \
144 #define PSB_INT_IDENTITY_R 0x20A4
145 #define PSB_INT_MASK_R 0x20A8
146 #define PSB_INT_ENABLE_R 0x20A0
148 #define _PSB_MMU_ER_MASK 0x0001FF00
149 #define _PSB_MMU_ER_HOST (1 << 16)
158 #define GPIO_CLOCK_DIR_MASK (1 << 0)
159 #define GPIO_CLOCK_DIR_IN (0 << 1)
160 #define GPIO_CLOCK_DIR_OUT (1 << 1)
161 #define GPIO_CLOCK_VAL_MASK (1 << 2)
162 #define GPIO_CLOCK_VAL_OUT (1 << 3)
163 #define GPIO_CLOCK_VAL_IN (1 << 4)
164 #define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
165 #define GPIO_DATA_DIR_MASK (1 << 8)
166 #define GPIO_DATA_DIR_IN (0 << 9)
167 #define GPIO_DATA_DIR_OUT (1 << 9)
168 #define GPIO_DATA_VAL_MASK (1 << 10)
169 #define GPIO_DATA_VAL_OUT (1 << 11)
170 #define GPIO_DATA_VAL_IN (1 << 12)
171 #define GPIO_DATA_PULLUP_DISABLE (1 << 13)
173 #define VCLK_DIVISOR_VGA0 0x6000
174 #define VCLK_DIVISOR_VGA1 0x6004
175 #define VCLK_POST_DIV 0x6010
177 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
178 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
179 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
180 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
181 #define PSB_COMM_USER_IRQ (1024 >> 2)
182 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
183 #define PSB_COMM_FW (2048 >> 2)
185 #define PSB_UIRQ_VISTEST 1
186 #define PSB_UIRQ_OOM_REPLY 2
187 #define PSB_UIRQ_FIRE_TA_REPLY 3
188 #define PSB_UIRQ_FIRE_RASTER_REPLY 4
190 #define PSB_2D_SIZE (256*1024*1024)
191 #define PSB_MAX_RELOC_PAGES 1024
193 #define PSB_LOW_REG_OFFS 0x0204
194 #define PSB_HIGH_REG_OFFS 0x0600
196 #define PSB_NUM_VBLANKS 2
199 #define PSB_2D_SIZE (256*1024*1024)
200 #define PSB_MAX_RELOC_PAGES 1024
202 #define PSB_LOW_REG_OFFS 0x0204
203 #define PSB_HIGH_REG_OFFS 0x0600
205 #define PSB_NUM_VBLANKS 2
206 #define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
207 #define PSB_LID_DELAY (DRM_HZ / 10)
209 #define MDFLD_PNW_B0 0x04
210 #define MDFLD_PNW_C0 0x08
212 #define MDFLD_DSR_2D_3D_0 (1 << 0)
213 #define MDFLD_DSR_2D_3D_2 (1 << 1)
214 #define MDFLD_DSR_CURSOR_0 (1 << 2)
215 #define MDFLD_DSR_CURSOR_2 (1 << 3)
216 #define MDFLD_DSR_OVERLAY_0 (1 << 4)
217 #define MDFLD_DSR_OVERLAY_2 (1 << 5)
218 #define MDFLD_DSR_MIPI_CONTROL (1 << 6)
219 #define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
220 #define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
221 #define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
223 #define MDFLD_DSR_RR 45
224 #define MDFLD_DPU_ENABLE (1 << 31)
225 #define MDFLD_DSR_FULLSCREEN (1 << 30)
226 #define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR)
228 #define PSB_PWR_STATE_ON 1
229 #define PSB_PWR_STATE_OFF 2
231 #define PSB_PMPOLICY_NOPM 0
232 #define PSB_PMPOLICY_CLOCKGATING 1
233 #define PSB_PMPOLICY_POWERDOWN 2
235 #define PSB_PMSTATE_POWERUP 0
236 #define PSB_PMSTATE_CLOCKGATED 1
237 #define PSB_PMSTATE_POWERDOWN 2
238 #define PSB_PCIx_MSI_ADDR_LOC 0x94
239 #define PSB_PCIx_MSI_DATA_LOC 0x98
241 /* Medfield crystal settings */
242 #define KSEL_CRYSTAL_19 1
243 #define KSEL_BYPASS_19 5
244 #define KSEL_BYPASS_25 6
245 #define KSEL_BYPASS_83_100 7
247 struct opregion_header;
248 struct opregion_acpi;
249 struct opregion_swsci;
250 struct opregion_asle;
252 struct psb_intel_opregion {
253 struct opregion_header *header;
254 struct opregion_acpi *acpi;
255 struct opregion_swsci *swsci;
256 struct opregion_asle *asle;
262 #define PSB_NUM_PIPE 3
264 struct drm_psb_private {
265 struct drm_device *dev;
266 const struct psb_ops *ops;
270 /* GTT Memory manager */
271 struct psb_gtt_mm *gtt_mm;
272 struct page *scratch_page;
274 uint32_t stolen_base;
276 unsigned long vram_stolen_size;
278 u16 gmch_ctrl; /* Saved GTT setup */
281 struct mutex gtt_mutex;
282 struct resource *gtt_mem; /* Our PCI resource */
284 struct psb_mmu_driver *mmu;
285 struct psb_mmu_pd *pf_pd;
293 uint32_t gatt_free_offset;
299 uint32_t vdc_irq_mask;
300 uint32_t pipestat[PSB_NUM_PIPE];
302 spinlock_t irqmask_lock;
315 struct psb_intel_mode_device mode_dev;
317 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
318 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
322 * OSPM info (Power management base) (can go ?)
331 u32 video_device_fuse;
333 /* PCI revision ID for B0:D2:F0 */
334 uint8_t platform_rev_id;
339 int backlight_duty_cycle; /* restore backlight to this value */
340 bool panel_wants_dither;
341 struct drm_display_mode *panel_fixed_mode;
342 struct drm_display_mode *lfp_lvds_vbt_mode;
343 struct drm_display_mode *sdvo_lvds_vbt_mode;
345 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
346 struct psb_intel_i2c_chan *lvds_i2c_bus;
348 /* Feature bits from the VBIOS */
349 unsigned int int_tv_support:1;
350 unsigned int lvds_dither:1;
351 unsigned int lvds_vbt:1;
352 unsigned int int_crt_support:1;
353 unsigned int lvds_use_ssc:1;
357 u32 mipi_ctrl_display;
359 unsigned int core_freq;
360 uint32_t iLVDS_enable;
362 /* Runtime PM state */
366 struct oaktrail_vbt vbt_data;
367 struct oaktrail_gct_data gct_data;
369 /* MIPI Panel type etc */
371 bool dual_mipi; /* dual display - DPI & DBI */
372 bool dpi_panel_on; /* The DPI panel power is on */
373 bool dpi_panel_on2; /* The DPI panel power is on */
374 bool dbi_panel_on; /* The DBI panel power is on */
375 bool dbi_panel_on2; /* The DBI panel power is on */
376 u32 dsr_fb_update; /* DSR FB update counter */
378 /* Moorestown HDMI state */
379 struct oaktrail_hdmi_dev *hdmi_priv;
381 /* Moorestown pipe config register value cache */
386 /* Moorestown plane control register value cache */
391 /* Moorestown MM backlight cache */
394 uint8_t saveBKLTBRTL;
399 uint32_t saveDSPACNTR;
400 uint32_t saveDSPBCNTR;
401 uint32_t savePIPEACONF;
402 uint32_t savePIPEBCONF;
403 uint32_t savePIPEASRC;
404 uint32_t savePIPEBSRC;
408 uint32_t saveDPLL_A_MD;
409 uint32_t saveHTOTAL_A;
410 uint32_t saveHBLANK_A;
411 uint32_t saveHSYNC_A;
412 uint32_t saveVTOTAL_A;
413 uint32_t saveVBLANK_A;
414 uint32_t saveVSYNC_A;
415 uint32_t saveDSPASTRIDE;
416 uint32_t saveDSPASIZE;
417 uint32_t saveDSPAPOS;
418 uint32_t saveDSPABASE;
419 uint32_t saveDSPASURF;
420 uint32_t saveDSPASTATUS;
424 uint32_t saveDPLL_B_MD;
425 uint32_t saveHTOTAL_B;
426 uint32_t saveHBLANK_B;
427 uint32_t saveHSYNC_B;
428 uint32_t saveVTOTAL_B;
429 uint32_t saveVBLANK_B;
430 uint32_t saveVSYNC_B;
431 uint32_t saveDSPBSTRIDE;
432 uint32_t saveDSPBSIZE;
433 uint32_t saveDSPBPOS;
434 uint32_t saveDSPBBASE;
435 uint32_t saveDSPBSURF;
436 uint32_t saveDSPBSTATUS;
437 uint32_t saveVCLK_DIVISOR_VGA0;
438 uint32_t saveVCLK_DIVISOR_VGA1;
439 uint32_t saveVCLK_POST_DIV;
440 uint32_t saveVGACNTRL;
448 uint32_t savePP_CONTROL;
449 uint32_t savePP_CYCLE;
450 uint32_t savePFIT_CONTROL;
451 uint32_t savePaletteA[256];
452 uint32_t savePaletteB[256];
453 uint32_t saveBLC_PWM_CTL2;
454 uint32_t saveBLC_PWM_CTL;
455 uint32_t saveCLOCKGATING;
457 uint32_t saveDSPATILEOFF;
458 uint32_t saveDSPBTILEOFF;
459 uint32_t saveDSPAADDR;
460 uint32_t saveDSPBADDR;
461 uint32_t savePFIT_AUTO_RATIOS;
462 uint32_t savePFIT_PGM_RATIOS;
463 uint32_t savePP_ON_DELAYS;
464 uint32_t savePP_OFF_DELAYS;
465 uint32_t savePP_DIVISOR;
468 uint32_t saveBCLRPAT_A;
469 uint32_t saveBCLRPAT_B;
470 uint32_t saveDSPALINOFF;
471 uint32_t saveDSPBLINOFF;
472 uint32_t savePERF_MODE;
479 uint32_t saveCHICKENBIT;
480 uint32_t saveDSPACURSOR_CTRL;
481 uint32_t saveDSPBCURSOR_CTRL;
482 uint32_t saveDSPACURSOR_BASE;
483 uint32_t saveDSPBCURSOR_BASE;
484 uint32_t saveDSPACURSOR_POS;
485 uint32_t saveDSPBCURSOR_POS;
486 uint32_t save_palette_a[256];
487 uint32_t save_palette_b[256];
488 uint32_t saveOV_OVADD;
489 uint32_t saveOV_OGAMC0;
490 uint32_t saveOV_OGAMC1;
491 uint32_t saveOV_OGAMC2;
492 uint32_t saveOV_OGAMC3;
493 uint32_t saveOV_OGAMC4;
494 uint32_t saveOV_OGAMC5;
495 uint32_t saveOVC_OVADD;
496 uint32_t saveOVC_OGAMC0;
497 uint32_t saveOVC_OGAMC1;
498 uint32_t saveOVC_OGAMC2;
499 uint32_t saveOVC_OGAMC3;
500 uint32_t saveOVC_OGAMC4;
501 uint32_t saveOVC_OGAMC5;
507 /* Medfield specific register save state */
508 uint32_t saveHDMIPHYMISCCTL;
509 uint32_t saveHDMIB_CONTROL;
510 uint32_t saveDSPCCNTR;
511 uint32_t savePIPECCONF;
512 uint32_t savePIPECSRC;
513 uint32_t saveHTOTAL_C;
514 uint32_t saveHBLANK_C;
515 uint32_t saveHSYNC_C;
516 uint32_t saveVTOTAL_C;
517 uint32_t saveVBLANK_C;
518 uint32_t saveVSYNC_C;
519 uint32_t saveDSPCSTRIDE;
520 uint32_t saveDSPCSIZE;
521 uint32_t saveDSPCPOS;
522 uint32_t saveDSPCSURF;
523 uint32_t saveDSPCSTATUS;
524 uint32_t saveDSPCLINOFF;
525 uint32_t saveDSPCTILEOFF;
526 uint32_t saveDSPCCURSOR_CTRL;
527 uint32_t saveDSPCCURSOR_BASE;
528 uint32_t saveDSPCCURSOR_POS;
529 uint32_t save_palette_c[256];
530 uint32_t saveOV_OVADD_C;
531 uint32_t saveOV_OGAMC0_C;
532 uint32_t saveOV_OGAMC1_C;
533 uint32_t saveOV_OGAMC2_C;
534 uint32_t saveOV_OGAMC3_C;
535 uint32_t saveOV_OGAMC4_C;
536 uint32_t saveOV_OGAMC5_C;
538 /* DSI register save */
539 uint32_t saveDEVICE_READY_REG;
540 uint32_t saveINTR_EN_REG;
541 uint32_t saveDSI_FUNC_PRG_REG;
542 uint32_t saveHS_TX_TIMEOUT_REG;
543 uint32_t saveLP_RX_TIMEOUT_REG;
544 uint32_t saveTURN_AROUND_TIMEOUT_REG;
545 uint32_t saveDEVICE_RESET_REG;
546 uint32_t saveDPI_RESOLUTION_REG;
547 uint32_t saveHORIZ_SYNC_PAD_COUNT_REG;
548 uint32_t saveHORIZ_BACK_PORCH_COUNT_REG;
549 uint32_t saveHORIZ_FRONT_PORCH_COUNT_REG;
550 uint32_t saveHORIZ_ACTIVE_AREA_COUNT_REG;
551 uint32_t saveVERT_SYNC_PAD_COUNT_REG;
552 uint32_t saveVERT_BACK_PORCH_COUNT_REG;
553 uint32_t saveVERT_FRONT_PORCH_COUNT_REG;
554 uint32_t saveHIGH_LOW_SWITCH_COUNT_REG;
555 uint32_t saveINIT_COUNT_REG;
556 uint32_t saveMAX_RET_PAK_REG;
557 uint32_t saveVIDEO_FMT_REG;
558 uint32_t saveEOT_DISABLE_REG;
559 uint32_t saveLP_BYTECLK_REG;
560 uint32_t saveHS_LS_DBI_ENABLE_REG;
561 uint32_t saveTXCLKESC_REG;
562 uint32_t saveDPHY_PARAM_REG;
563 uint32_t saveMIPI_CONTROL_REG;
567 /* DPST register save */
568 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
569 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
570 uint32_t savePWM_CONTROL_LOGIC;
577 void * dsi_configs[2];
582 struct timer_list lid_timer;
583 struct psb_intel_opregion opregion;
595 * Used for modifying backlight from
596 * xrandr -- consider removing and using HAL instead
598 struct backlight_device *backlight_device;
599 struct drm_property *backlight_property;
605 /* 2D acceleration */
606 struct mutex mutex_2d;
611 * Operations for each board type
616 unsigned int accel_2d:1;
617 int pipes; /* Number of output pipes */
618 int crtcs; /* Number of CRTCs */
619 int sgx_offset; /* Base offset of SGX device */
622 struct drm_crtc_helper_funcs const *crtc_helper;
623 struct drm_crtc_funcs const *crtc_funcs;
626 int (*chip_setup)(struct drm_device *dev);
627 void (*chip_teardown)(struct drm_device *dev);
629 /* Display management hooks */
630 int (*output_init)(struct drm_device *dev);
631 /* Power management hooks */
632 void (*init_pm)(struct drm_device *dev);
633 int (*save_regs)(struct drm_device *dev);
634 int (*restore_regs)(struct drm_device *dev);
635 int (*power_up)(struct drm_device *dev);
636 int (*power_down)(struct drm_device *dev);
638 void (*lvds_bl_power)(struct drm_device *dev, bool on);
639 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
641 int (*backlight_init)(struct drm_device *dev);
643 int i2c_bus; /* I2C bus identifier for Moorestown */
648 struct psb_mmu_driver;
650 extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
651 extern int drm_pick_crtcs(struct drm_device *dev);
653 static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
655 return (struct drm_psb_private *) dev->dev_private;
662 extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
665 struct drm_psb_private *dev_priv);
666 extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
667 extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
669 extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
670 uint32_t gtt_start, uint32_t gtt_pages);
671 extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
674 extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
675 extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
676 extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
677 unsigned long address,
679 extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
681 unsigned long address,
682 uint32_t num_pages, int type);
683 extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
687 * Enable / disable MMU for different requestors.
691 extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
692 extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
693 unsigned long address, uint32_t num_pages,
694 uint32_t desired_tile_stride,
695 uint32_t hw_tile_stride, int type);
696 extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
697 unsigned long address, uint32_t num_pages,
698 uint32_t desired_tile_stride,
699 uint32_t hw_tile_stride);
704 extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
705 extern int psb_irq_enable_dpst(struct drm_device *dev);
706 extern int psb_irq_disable_dpst(struct drm_device *dev);
707 extern void psb_irq_preinstall(struct drm_device *dev);
708 extern int psb_irq_postinstall(struct drm_device *dev);
709 extern void psb_irq_uninstall(struct drm_device *dev);
710 extern void psb_irq_turn_on_dpst(struct drm_device *dev);
711 extern void psb_irq_turn_off_dpst(struct drm_device *dev);
713 extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
714 extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
715 extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
716 extern int psb_enable_vblank(struct drm_device *dev, int crtc);
717 extern void psb_disable_vblank(struct drm_device *dev, int crtc);
719 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
722 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
724 extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
729 extern int gma_intel_opregion_init(struct drm_device *dev);
730 extern int gma_intel_opregion_exit(struct drm_device *dev);
735 extern int psbfb_probed(struct drm_device *dev);
736 extern int psbfb_remove(struct drm_device *dev,
737 struct drm_framebuffer *fb);
741 extern void psbfb_copyarea(struct fb_info *info,
742 const struct fb_copyarea *region);
743 extern int psbfb_sync(struct fb_info *info);
744 extern void psb_spank(struct drm_psb_private *dev_priv);
750 extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
751 extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
752 extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
755 extern void psb_modeset_init(struct drm_device *dev);
756 extern void psb_modeset_cleanup(struct drm_device *dev);
757 extern int psb_fbdev_init(struct drm_device *dev);
760 int gma_backlight_init(struct drm_device *dev);
761 void gma_backlight_exit(struct drm_device *dev);
763 /* oaktrail_crtc.c */
764 extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
766 /* oaktrail_lvds.c */
767 extern void oaktrail_lvds_init(struct drm_device *dev,
768 struct psb_intel_mode_device *mode_dev);
770 /* psb_intel_display.c */
771 extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
772 extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
774 /* psb_intel_lvds.c */
775 extern const struct drm_connector_helper_funcs
776 psb_intel_lvds_connector_helper_funcs;
777 extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
780 extern int psb_gem_init_object(struct drm_gem_object *obj);
781 extern void psb_gem_free_object(struct drm_gem_object *obj);
782 extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
783 struct drm_file *file);
784 extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
785 struct drm_mode_create_dumb *args);
786 extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
788 extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
789 uint32_t handle, uint64_t *offset);
790 extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
791 extern int psb_gem_create_ioctl(struct drm_device *dev, void *data,
792 struct drm_file *file);
793 extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data,
794 struct drm_file *file);
797 extern const struct psb_ops psb_chip_ops;
799 /* oaktrail_device.c */
800 extern const struct psb_ops oaktrail_chip_ops;
803 extern const struct psb_ops cdv_chip_ops;
806 * Debug print bits setting
808 #define PSB_D_GENERAL (1 << 0)
809 #define PSB_D_INIT (1 << 1)
810 #define PSB_D_IRQ (1 << 2)
811 #define PSB_D_ENTRY (1 << 3)
812 /* debug the get H/V BP/FP count */
813 #define PSB_D_HV (1 << 4)
814 #define PSB_D_DBI_BF (1 << 5)
815 #define PSB_D_PM (1 << 6)
816 #define PSB_D_RENDER (1 << 7)
817 #define PSB_D_REG (1 << 8)
818 #define PSB_D_MSVDX (1 << 9)
819 #define PSB_D_TOPAZ (1 << 10)
821 extern int drm_psb_no_fb;
822 extern int drm_idle_check_interval;
828 static inline u32 MRST_MSG_READ32(uint port, uint offset)
830 int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
831 uint32_t ret_val = 0;
832 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
833 pci_write_config_dword(pci_root, 0xD0, mcr);
834 pci_read_config_dword(pci_root, 0xD4, &ret_val);
835 pci_dev_put(pci_root);
838 static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
840 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
841 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
842 pci_write_config_dword(pci_root, 0xD4, value);
843 pci_write_config_dword(pci_root, 0xD0, mcr);
844 pci_dev_put(pci_root);
846 static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
848 int mcr = (0x10<<24) | (port << 16) | (offset << 8);
849 uint32_t ret_val = 0;
850 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
851 pci_write_config_dword(pci_root, 0xD0, mcr);
852 pci_read_config_dword(pci_root, 0xD4, &ret_val);
853 pci_dev_put(pci_root);
856 static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
858 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
859 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
860 pci_write_config_dword(pci_root, 0xD4, value);
861 pci_write_config_dword(pci_root, 0xD0, mcr);
862 pci_dev_put(pci_root);
865 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
867 struct drm_psb_private *dev_priv = dev->dev_private;
868 return ioread32(dev_priv->vdc_reg + reg);
871 #define REG_READ(reg) REGISTER_READ(dev, (reg))
873 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
876 struct drm_psb_private *dev_priv = dev->dev_private;
877 iowrite32((val), dev_priv->vdc_reg + (reg));
880 #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
882 static inline void REGISTER_WRITE16(struct drm_device *dev,
883 uint32_t reg, uint32_t val)
885 struct drm_psb_private *dev_priv = dev->dev_private;
886 iowrite16((val), dev_priv->vdc_reg + (reg));
889 #define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
891 static inline void REGISTER_WRITE8(struct drm_device *dev,
892 uint32_t reg, uint32_t val)
894 struct drm_psb_private *dev_priv = dev->dev_private;
895 iowrite8((val), dev_priv->vdc_reg + (reg));
898 #define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
900 #define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
901 #define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
903 /* #define TRAP_SGX_PM_FAULT 1 */
904 #ifdef TRAP_SGX_PM_FAULT
905 #define PSB_RSGX32(_offs) \
907 if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
909 "access sgx when it's off!! (READ) %s, %d\n", \
910 __FILE__, __LINE__); \
913 ioread32(dev_priv->sgx_reg + (_offs)); \
916 #define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
918 #define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
920 #define MSVDX_REG_DUMP 0
922 #define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
923 #define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))