drivers/gpu/drm/i915/i915_cmd_parser.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Brad Volkin <bradley.d.volkin@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29
  30 /**
  31  * DOC: i915 batch buffer command parser
  32  *
  33  * Motivation:
  34  * Certain OpenGL features (e.g. transform feedback, performance monitoring)
  35  * require userspace code to submit batches containing commands such as
  36  * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
  37  * generations of the hardware will noop these commands in "unsecure" batches
  38  * (which includes all userspace batches submitted via i915) even though the
  39  * commands may be safe and represent the intended programming model of the
  40  * device.
  41  *
  42  * The software command parser is similar in operation to the command parsing
  43  * done in hardware for unsecure batches. However, the software parser allows
  44  * some operations that would be noop'd by hardware, if the parser determines
  45  * the operation is safe, and submits the batch as "secure" to prevent hardware
  46  * parsing.
  47  *
  48  * Threats:
  49  * At a high level, the hardware (and software) checks attempt to prevent
  50  * granting userspace undue privileges. There are three categories of privilege.
  51  *
  52  * First, commands which are explicitly defined as privileged or which should
  53  * only be used by the kernel driver. The parser generally rejects such
  54  * commands, though it may allow some from the drm master process.
  55  *
  56  * Second, commands which access registers. To support correct/enhanced
  57  * userspace functionality, particularly certain OpenGL extensions, the parser
  58  * provides a whitelist of registers which userspace may safely access (for both
  59  * normal and drm master processes).
  60  *
  61  * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc).
  62  * The parser always rejects such commands.
  63  *
  64  * The majority of the problematic commands fall in the MI_* range, with only a
  65  * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW).
  66  *
  67  * Implementation:
  68  * Each ring maintains tables of commands and registers which the parser uses in
  69  * scanning batch buffers submitted to that ring.
  70  *
  71  * Since the set of commands that the parser must check for is significantly
  72  * smaller than the number of commands supported, the parser tables contain only
  73  * those commands required by the parser. This generally works because command
  74  * opcode ranges have standard command length encodings. So for commands that
  75  * the parser does not need to check, it can easily skip them. This is
  76  * implementated via a per-ring length decoding vfunc.
  77  *
  78  * Unfortunately, there are a number of commands that do not follow the standard
  79  * length encoding for their opcode range, primarily amongst the MI_* commands.
  80  * To handle this, the parser provides a way to define explicit "skip" entries
  81  * in the per-ring command tables.
  82  *
  83  * Other command table entries map fairly directly to high level categories
  84  * mentioned above: rejected, master-only, register whitelist. The parser
  85  * implements a number of checks, including the privileged memory checks, via a
  86  * general bitmasking mechanism.
  87  */
  88
  89 #define STD_MI_OPCODE_MASK  0xFF800000
  90 #define STD_3D_OPCODE_MASK  0xFFFF0000
  91 #define STD_2D_OPCODE_MASK  0xFFC00000
  92 #define STD_MFX_OPCODE_MASK 0xFFFF0000
  93
  94 #define CMD(op, opm, f, lm, fl, ...)                            \
  95         {                                                       \
  96                 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0),     \
  97                 .cmd = { (op), (opm) },                         \
  98                 .length = { (lm) },                             \
  99                 __VA_ARGS__                                     \
 100         }
 101
 102 /* Convenience macros to compress the tables */
 103 #define SMI STD_MI_OPCODE_MASK
 104 #define S3D STD_3D_OPCODE_MASK
 105 #define S2D STD_2D_OPCODE_MASK
 106 #define SMFX STD_MFX_OPCODE_MASK
 107 #define F true
 108 #define S CMD_DESC_SKIP
 109 #define R CMD_DESC_REJECT
 110 #define W CMD_DESC_REGISTER
 111 #define B CMD_DESC_BITMASK
 112 #define M CMD_DESC_MASTER
 113
 114 /*            Command                          Mask   Fixed Len   Action
 115               ---------------------------------------------------------- */
 116 static const struct drm_i915_cmd_descriptor common_cmds[] = {
 117         CMD(  MI_NOOP,                          SMI,    F,  1,      S  ),
 118         CMD(  MI_USER_INTERRUPT,                SMI,    F,  1,      S  ),
 119         CMD(  MI_WAIT_FOR_EVENT,                SMI,    F,  1,      M  ),
 120         CMD(  MI_ARB_CHECK,                     SMI,    F,  1,      S  ),
 121         CMD(  MI_REPORT_HEAD,                   SMI,    F,  1,      S  ),
 122         CMD(  MI_SUSPEND_FLUSH,                 SMI,    F,  1,      S  ),
 123         CMD(  MI_SEMAPHORE_MBOX,                SMI,   !F,  0xFF,   R  ),
 124         CMD(  MI_STORE_DWORD_INDEX,             SMI,   !F,  0xFF,   R  ),
 125         CMD(  MI_LOAD_REGISTER_IMM(1),          SMI,   !F,  0xFF,   W,
 126               .reg = { .offset = 1, .mask = 0x007FFFFC }               ),
 127         CMD(  MI_STORE_REGISTER_MEM(1),         SMI,   !F,  0xFF,   W,
 128               .reg = { .offset = 1, .mask = 0x007FFFFC }               ),
 129         CMD(  MI_LOAD_REGISTER_MEM,             SMI,   !F,  0xFF,   W,
 130               .reg = { .offset = 1, .mask = 0x007FFFFC }               ),
 131         CMD(  MI_BATCH_BUFFER_START,            SMI,   !F,  0xFF,   S  ),
 132 };
 133
 134 static const struct drm_i915_cmd_descriptor render_cmds[] = {
 135         CMD(  MI_FLUSH,                         SMI,    F,  1,      S  ),
 136         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 137         CMD(  MI_PREDICATE,                     SMI,    F,  1,      S  ),
 138         CMD(  MI_TOPOLOGY_FILTER,               SMI,    F,  1,      S  ),
 139         CMD(  MI_DISPLAY_FLIP,                  SMI,   !F,  0xFF,   R  ),
 140         CMD(  MI_SET_CONTEXT,                   SMI,   !F,  0xFF,   R  ),
 141         CMD(  MI_URB_CLEAR,                     SMI,   !F,  0xFF,   S  ),
 142         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0xFF,   R  ),
 143         CMD(  MI_CLFLUSH,                       SMI,   !F,  0x3FF,  S  ),
 144         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   S  ),
 145         CMD(  GFX_OP_3DSTATE_VF_STATISTICS,     S3D,    F,  1,      S  ),
 146         CMD(  PIPELINE_SELECT,                  S3D,    F,  1,      S  ),
 147         CMD(  MEDIA_VFE_STATE,                  S3D,   !F,  0xFFFF, B,
 148               .bits = {{
 149                         .offset = 2,
 150                         .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
 151                         .expected = 0,
 152               }},                                                      ),
 153         CMD(  GPGPU_OBJECT,                     S3D,   !F,  0xFF,   S  ),
 154         CMD(  GPGPU_WALKER,                     S3D,   !F,  0xFF,   S  ),
 155         CMD(  GFX_OP_3DSTATE_SO_DECL_LIST,      S3D,   !F,  0x1FF,  S  ),
 156         CMD(  GFX_OP_PIPE_CONTROL(5),           S3D,   !F,  0xFF,   B,
 157               .bits = {{
 158                         .offset = 1,
 159                         .mask = PIPE_CONTROL_MMIO_WRITE,
 160                         .expected = 0,
 161               }},                                                      ),
 162 };
 163
 164 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
 165         CMD(  MI_SET_PREDICATE,                 SMI,    F,  1,      S  ),
 166         CMD(  MI_RS_CONTROL,                    SMI,    F,  1,      S  ),
 167         CMD(  MI_URB_ATOMIC_ALLOC,              SMI,    F,  1,      S  ),
 168         CMD(  MI_RS_CONTEXT,                    SMI,    F,  1,      S  ),
 169         CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   M  ),
 170         CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   R  ),
 171         CMD(  MI_LOAD_REGISTER_REG,             SMI,   !F,  0xFF,   R  ),
 172         CMD(  MI_RS_STORE_DATA_IMM,             SMI,   !F,  0xFF,   S  ),
 173         CMD(  MI_LOAD_URB_MEM,                  SMI,   !F,  0xFF,   S  ),
 174         CMD(  MI_STORE_URB_MEM,                 SMI,   !F,  0xFF,   S  ),
 175         CMD(  GFX_OP_3DSTATE_DX9_CONSTANTF_VS,  S3D,   !F,  0x7FF,  S  ),
 176         CMD(  GFX_OP_3DSTATE_DX9_CONSTANTF_PS,  S3D,   !F,  0x7FF,  S  ),
 177
 178         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS,  S3D,   !F,  0x1FF,  S  ),
 179         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS,  S3D,   !F,  0x1FF,  S  ),
 180         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS,  S3D,   !F,  0x1FF,  S  ),
 181         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS,  S3D,   !F,  0x1FF,  S  ),
 182         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS,  S3D,   !F,  0x1FF,  S  ),
 183 };
 184
 185 static const struct drm_i915_cmd_descriptor video_cmds[] = {
 186         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 187         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   S  ),
 188         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 189         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   S  ),
 190         /*
 191          * MFX_WAIT doesn't fit the way we handle length for most commands.
 192          * It has a length field but it uses a non-standard length bias.
 193          * It is always 1 dword though, so just treat it as fixed length.
 194          */
 195         CMD(  MFX_WAIT,                         SMFX,   F,  1,      S  ),
 196 };
 197
 198 static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
 199         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 200         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   S  ),
 201         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 202         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   S  ),
 203 };
 204
 205 static const struct drm_i915_cmd_descriptor blt_cmds[] = {
 206         CMD(  MI_DISPLAY_FLIP,                  SMI,   !F,  0xFF,   R  ),
 207         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0x3FF,  S  ),
 208         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 209         CMD(  COLOR_BLT,                        S2D,   !F,  0x3F,   S  ),
 210         CMD(  SRC_COPY_BLT,                     S2D,   !F,  0x3F,   S  ),
 211 };
 212
 213 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = {
 214         CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   M  ),
 215         CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   R  ),
 216 };
 217
 218 #undef CMD
 219 #undef SMI
 220 #undef S3D
 221 #undef S2D
 222 #undef SMFX
 223 #undef F
 224 #undef S
 225 #undef R
 226 #undef W
 227 #undef B
 228 #undef M
 229
 230 static const struct drm_i915_cmd_table gen7_render_cmds[] = {
 231         { common_cmds, ARRAY_SIZE(common_cmds) },
 232         { render_cmds, ARRAY_SIZE(render_cmds) },
 233 };
 234
 235 static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = {
 236         { common_cmds, ARRAY_SIZE(common_cmds) },
 237         { render_cmds, ARRAY_SIZE(render_cmds) },
 238         { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },
 239 };
 240
 241 static const struct drm_i915_cmd_table gen7_video_cmds[] = {
 242         { common_cmds, ARRAY_SIZE(common_cmds) },
 243         { video_cmds, ARRAY_SIZE(video_cmds) },
 244 };
 245
 246 static const struct drm_i915_cmd_table hsw_vebox_cmds[] = {
 247         { common_cmds, ARRAY_SIZE(common_cmds) },
 248         { vecs_cmds, ARRAY_SIZE(vecs_cmds) },
 249 };
 250
 251 static const struct drm_i915_cmd_table gen7_blt_cmds[] = {
 252         { common_cmds, ARRAY_SIZE(common_cmds) },
 253         { blt_cmds, ARRAY_SIZE(blt_cmds) },
 254 };
 255
 256 static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = {
 257         { common_cmds, ARRAY_SIZE(common_cmds) },
 258         { blt_cmds, ARRAY_SIZE(blt_cmds) },
 259         { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
 260 };
 261
 262 /*
 263  * Register whitelists, sorted by increasing register offset.
 264  *
 265  * Some registers that userspace accesses are 64 bits. The register
 266  * access commands only allow 32-bit accesses. Hence, we have to include
 267  * entries for both halves of the 64-bit registers.
 268  */
 269
 270 /* Convenience macro for adding 64-bit registers */
 271 #define REG64(addr) (addr), (addr + sizeof(u32))
 272
 273 static const u32 gen7_render_regs[] = {
 274         REG64(HS_INVOCATION_COUNT),
 275         REG64(DS_INVOCATION_COUNT),
 276         REG64(IA_VERTICES_COUNT),
 277         REG64(IA_PRIMITIVES_COUNT),
 278         REG64(VS_INVOCATION_COUNT),
 279         REG64(GS_INVOCATION_COUNT),
 280         REG64(GS_PRIMITIVES_COUNT),
 281         REG64(CL_INVOCATION_COUNT),
 282         REG64(CL_PRIMITIVES_COUNT),
 283         REG64(PS_INVOCATION_COUNT),
 284         REG64(PS_DEPTH_COUNT),
 285         REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),
 286         REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),
 287         REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),
 288         REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)),
 289         GEN7_SO_WRITE_OFFSET(0),
 290         GEN7_SO_WRITE_OFFSET(1),
 291         GEN7_SO_WRITE_OFFSET(2),
 292         GEN7_SO_WRITE_OFFSET(3),
 293 };
 294
 295 static const u32 gen7_blt_regs[] = {
 296         BCS_SWCTRL,
 297 };
 298
 299 static const u32 ivb_master_regs[] = {
 300         FORCEWAKE_MT,
 301         DERRMR,
 302         GEN7_PIPE_DE_LOAD_SL(PIPE_A),
 303         GEN7_PIPE_DE_LOAD_SL(PIPE_B),
 304         GEN7_PIPE_DE_LOAD_SL(PIPE_C),
 305 };
 306
 307 static const u32 hsw_master_regs[] = {
 308         FORCEWAKE_MT,
 309         DERRMR,
 310 };
 311
 312 #undef REG64
 313
 314 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
 315 {
 316         u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
 317         u32 subclient =
 318                 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
 319
 320         if (client == INSTR_MI_CLIENT)
 321                 return 0x3F;
 322         else if (client == INSTR_RC_CLIENT) {
 323                 if (subclient == INSTR_MEDIA_SUBCLIENT)
 324                         return 0xFFFF;
 325                 else
 326                         return 0xFF;
 327         }
 328
 329         DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header);
 330         return 0;
 331 }
 332
 333 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
 334 {
 335         u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
 336         u32 subclient =
 337                 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
 338
 339         if (client == INSTR_MI_CLIENT)
 340                 return 0x3F;
 341         else if (client == INSTR_RC_CLIENT) {
 342                 if (subclient == INSTR_MEDIA_SUBCLIENT)
 343                         return 0xFFF;
 344                 else
 345                         return 0xFF;
 346         }
 347
 348         DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header);
 349         return 0;
 350 }
 351
 352 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
 353 {
 354         u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
 355
 356         if (client == INSTR_MI_CLIENT)
 357                 return 0x3F;
 358         else if (client == INSTR_BC_CLIENT)
 359                 return 0xFF;
 360
 361         DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
 362         return 0;
 363 }
 364
 365 static void validate_cmds_sorted(struct intel_ring_buffer *ring)
 366 {
 367         int i;
 368
 369         if (!ring->cmd_tables || ring->cmd_table_count == 0)
 370                 return;
 371
 372         for (i = 0; i < ring->cmd_table_count; i++) {
 373                 const struct drm_i915_cmd_table *table = &ring->cmd_tables[i];
 374                 u32 previous = 0;
 375                 int j;
 376
 377                 for (j = 0; j < table->count; j++) {
 378                         const struct drm_i915_cmd_descriptor *desc =
 379                                 &table->table[i];
 380                         u32 curr = desc->cmd.value & desc->cmd.mask;
 381
 382                         if (curr < previous)
 383                                 DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
 384                                           ring->id, i, j, curr, previous);
 385
 386                         previous = curr;
 387                 }
 388         }
 389 }
 390
 391 static void check_sorted(int ring_id, const u32 *reg_table, int reg_count)
 392 {
 393         int i;
 394         u32 previous = 0;
 395
 396         for (i = 0; i < reg_count; i++) {
 397                 u32 curr = reg_table[i];
 398
 399                 if (curr < previous)
 400                         DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n",
 401                                   ring_id, i, curr, previous);
 402
 403                 previous = curr;
 404         }
 405 }
 406
 407 static void validate_regs_sorted(struct intel_ring_buffer *ring)
 408 {
 409         check_sorted(ring->id, ring->reg_table, ring->reg_count);
 410         check_sorted(ring->id, ring->master_reg_table, ring->master_reg_count);
 411 }
 412
 413 /**
 414  * i915_cmd_parser_init_ring() - set cmd parser related fields for a ringbuffer
 415  * @ring: the ringbuffer to initialize
 416  *
 417  * Optionally initializes fields related to batch buffer command parsing in the
 418  * struct intel_ring_buffer based on whether the platform requires software
 419  * command parsing.
 420  */
 421 void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring)
 422 {
 423         if (!IS_GEN7(ring->dev))
 424                 return;
 425
 426         switch (ring->id) {
 427         case RCS:
 428                 if (IS_HASWELL(ring->dev)) {
 429                         ring->cmd_tables = hsw_render_ring_cmds;
 430                         ring->cmd_table_count =
 431                                 ARRAY_SIZE(hsw_render_ring_cmds);
 432                 } else {
 433                         ring->cmd_tables = gen7_render_cmds;
 434                         ring->cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
 435                 }
 436
 437                 ring->reg_table = gen7_render_regs;
 438                 ring->reg_count = ARRAY_SIZE(gen7_render_regs);
 439
 440                 if (IS_HASWELL(ring->dev)) {
 441                         ring->master_reg_table = hsw_master_regs;
 442                         ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
 443                 } else {
 444                         ring->master_reg_table = ivb_master_regs;
 445                         ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
 446                 }
 447
 448                 ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
 449                 break;
 450         case VCS:
 451                 ring->cmd_tables = gen7_video_cmds;
 452                 ring->cmd_table_count = ARRAY_SIZE(gen7_video_cmds);
 453                 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
 454                 break;
 455         case BCS:
 456                 if (IS_HASWELL(ring->dev)) {
 457                         ring->cmd_tables = hsw_blt_ring_cmds;
 458                         ring->cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
 459                 } else {
 460                         ring->cmd_tables = gen7_blt_cmds;
 461                         ring->cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
 462                 }
 463
 464                 ring->reg_table = gen7_blt_regs;
 465                 ring->reg_count = ARRAY_SIZE(gen7_blt_regs);
 466
 467                 if (IS_HASWELL(ring->dev)) {
 468                         ring->master_reg_table = hsw_master_regs;
 469                         ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
 470                 } else {
 471                         ring->master_reg_table = ivb_master_regs;
 472                         ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
 473                 }
 474
 475                 ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
 476                 break;
 477         case VECS:
 478                 ring->cmd_tables = hsw_vebox_cmds;
 479                 ring->cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds);
 480                 /* VECS can use the same length_mask function as VCS */
 481                 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
 482                 break;
 483         default:
 484                 DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n",
 485                           ring->id);
 486                 BUG();
 487         }
 488
 489         validate_cmds_sorted(ring);
 490         validate_regs_sorted(ring);
 491 }
 492
 493 static const struct drm_i915_cmd_descriptor*
 494 find_cmd_in_table(const struct drm_i915_cmd_table *table,
 495                   u32 cmd_header)
 496 {
 497         int i;
 498
 499         for (i = 0; i < table->count; i++) {
 500                 const struct drm_i915_cmd_descriptor *desc = &table->table[i];
 501                 u32 masked_cmd = desc->cmd.mask & cmd_header;
 502                 u32 masked_value = desc->cmd.value & desc->cmd.mask;
 503
 504                 if (masked_cmd == masked_value)
 505                         return desc;
 506         }
 507
 508         return NULL;
 509 }
 510
 511 /*
 512  * Returns a pointer to a descriptor for the command specified by cmd_header.
 513  *
 514  * The caller must supply space for a default descriptor via the default_desc
 515  * parameter. If no descriptor for the specified command exists in the ring's
 516  * command parser tables, this function fills in default_desc based on the
 517  * ring's default length encoding and returns default_desc.
 518  */
 519 static const struct drm_i915_cmd_descriptor*
 520 find_cmd(struct intel_ring_buffer *ring,
 521          u32 cmd_header,
 522          struct drm_i915_cmd_descriptor *default_desc)
 523 {
 524         u32 mask;
 525         int i;
 526
 527         for (i = 0; i < ring->cmd_table_count; i++) {
 528                 const struct drm_i915_cmd_descriptor *desc;
 529
 530                 desc = find_cmd_in_table(&ring->cmd_tables[i], cmd_header);
 531                 if (desc)
 532                         return desc;
 533         }
 534
 535         mask = ring->get_cmd_length_mask(cmd_header);
 536         if (!mask)
 537                 return NULL;
 538
 539         BUG_ON(!default_desc);
 540         default_desc->flags = CMD_DESC_SKIP;
 541         default_desc->length.mask = mask;
 542
 543         return default_desc;
 544 }
 545
 546 static bool valid_reg(const u32 *table, int count, u32 addr)
 547 {
 548         if (table && count != 0) {
 549                 int i;
 550
 551                 for (i = 0; i < count; i++) {
 552                         if (table[i] == addr)
 553                                 return true;
 554                 }
 555         }
 556
 557         return false;
 558 }
 559
 560 static u32 *vmap_batch(struct drm_i915_gem_object *obj)
 561 {
 562         int i;
 563         void *addr = NULL;
 564         struct sg_page_iter sg_iter;
 565         struct page **pages;
 566
 567         pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
 568         if (pages == NULL) {
 569                 DRM_DEBUG_DRIVER("Failed to get space for pages\n");
 570                 goto finish;
 571         }
 572
 573         i = 0;
 574         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
 575                 pages[i] = sg_page_iter_page(&sg_iter);
 576                 i++;
 577         }
 578
 579         addr = vmap(pages, i, 0, PAGE_KERNEL);
 580         if (addr == NULL) {
 581                 DRM_DEBUG_DRIVER("Failed to vmap pages\n");
 582                 goto finish;
 583         }
 584
 585 finish:
 586         if (pages)
 587                 drm_free_large(pages);
 588         return (u32*)addr;
 589 }
 590
 591 /**
 592  * i915_needs_cmd_parser() - should a given ring use software command parsing?
 593  * @ring: the ring in question
 594  *
 595  * Only certain platforms require software batch buffer command parsing, and
 596  * only when enabled via module paramter.
 597  *
 598  * Return: true if the ring requires software command parsing
 599  */
 600 bool i915_needs_cmd_parser(struct intel_ring_buffer *ring)
 601 {
 602         /* No command tables indicates a platform without parsing */
 603         if (!ring->cmd_tables)
 604                 return false;
 605
 606         return (i915.enable_cmd_parser == 1);
 607 }
 608
 609 #define LENGTH_BIAS 2
 610
 611 /**
 612  * i915_parse_cmds() - parse a submitted batch buffer for privilege violations
 613  * @ring: the ring on which the batch is to execute
 614  * @batch_obj: the batch buffer in question
 615  * @batch_start_offset: byte offset in the batch at which execution starts
 616  * @is_master: is the submitting process the drm master?
 617  *
 618  * Parses the specified batch buffer looking for privilege violations as
 619  * described in the overview.
 620  *
 621  * Return: non-zero if the parser finds violations or otherwise fails
 622  */
 623 int i915_parse_cmds(struct intel_ring_buffer *ring,
 624                     struct drm_i915_gem_object *batch_obj,
 625                     u32 batch_start_offset,
 626                     bool is_master)
 627 {
 628         int ret = 0;
 629         u32 *cmd, *batch_base, *batch_end;
 630         struct drm_i915_cmd_descriptor default_desc = { 0 };
 631         int needs_clflush = 0;
 632
 633         ret = i915_gem_obj_prepare_shmem_read(batch_obj, &needs_clflush);
 634         if (ret) {
 635                 DRM_DEBUG_DRIVER("CMD: failed to prep read\n");
 636                 return ret;
 637         }
 638
 639         batch_base = vmap_batch(batch_obj);
 640         if (!batch_base) {
 641                 DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n");
 642                 i915_gem_object_unpin_pages(batch_obj);
 643                 return -ENOMEM;
 644         }
 645
 646         if (needs_clflush)
 647                 drm_clflush_virt_range((char *)batch_base, batch_obj->base.size);
 648
 649         cmd = batch_base + (batch_start_offset / sizeof(*cmd));
 650         batch_end = cmd + (batch_obj->base.size / sizeof(*batch_end));
 651
 652         while (cmd < batch_end) {
 653                 const struct drm_i915_cmd_descriptor *desc;
 654                 u32 length;
 655
 656                 if (*cmd == MI_BATCH_BUFFER_END)
 657                         break;
 658
 659                 desc = find_cmd(ring, *cmd, &default_desc);
 660                 if (!desc) {
 661                         DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n",
 662                                          *cmd);
 663                         ret = -EINVAL;
 664                         break;
 665                 }
 666
 667                 if (desc->flags & CMD_DESC_FIXED)
 668                         length = desc->length.fixed;
 669                 else
 670                         length = ((*cmd & desc->length.mask) + LENGTH_BIAS);
 671
 672                 if ((batch_end - cmd) < length) {
 673                         DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%d batchlen=%td\n",
 674                                          *cmd,
 675                                          length,
 676                                          batch_end - cmd);
 677                         ret = -EINVAL;
 678                         break;
 679                 }
 680
 681                 if (desc->flags & CMD_DESC_REJECT) {
 682                         DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd);
 683                         ret = -EINVAL;
 684                         break;
 685                 }
 686
 687                 if ((desc->flags & CMD_DESC_MASTER) && !is_master) {
 688                         DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n",
 689                                          *cmd);
 690                         ret = -EINVAL;
 691                         break;
 692                 }
 693
 694                 if (desc->flags & CMD_DESC_REGISTER) {
 695                         u32 reg_addr = cmd[desc->reg.offset] & desc->reg.mask;
 696
 697                         if (!valid_reg(ring->reg_table,
 698                                        ring->reg_count, reg_addr)) {
 699                                 if (!is_master ||
 700                                     !valid_reg(ring->master_reg_table,
 701                                                ring->master_reg_count,
 702                                                reg_addr)) {
 703                                         DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n",
 704                                                          reg_addr,
 705                                                          *cmd,
 706                                                          ring->id);
 707                                         ret = -EINVAL;
 708                                         break;
 709                                 }
 710                         }
 711                 }
 712
 713                 if (desc->flags & CMD_DESC_BITMASK) {
 714                         int i;
 715
 716                         for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) {
 717                                 u32 dword;
 718
 719                                 if (desc->bits[i].mask == 0)
 720                                         break;
 721
 722                                 dword = cmd[desc->bits[i].offset] &
 723                                         desc->bits[i].mask;
 724
 725                                 if (dword != desc->bits[i].expected) {
 726                                         DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n",
 727                                                          *cmd,
 728                                                          desc->bits[i].mask,
 729                                                          desc->bits[i].expected,
 730                                                          dword, ring->id);
 731                                         ret = -EINVAL;
 732                                         break;
 733                                 }
 734                         }
 735
 736                         if (ret)
 737                                 break;
 738                 }
 739
 740                 cmd += length;
 741         }
 742
 743         if (cmd >= batch_end) {
 744                 DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
 745                 ret = -EINVAL;
 746         }
 747
 748         vunmap(batch_base);
 749
 750         i915_gem_object_unpin_pages(batch_obj);
 751
 752         return ret;
 753 }