drivers/gpu/drm/i915/i915_cmd_parser.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Brad Volkin <bradley.d.volkin@intel.com>
  25  *
  26  */
  27
  28 #include "i915_drv.h"
  29
  30 /**
  31  * DOC: batch buffer command parser
  32  *
  33  * Motivation:
  34  * Certain OpenGL features (e.g. transform feedback, performance monitoring)
  35  * require userspace code to submit batches containing commands such as
  36  * MI_LOAD_REGISTER_IMM to access various registers. Unfortunately, some
  37  * generations of the hardware will noop these commands in "unsecure" batches
  38  * (which includes all userspace batches submitted via i915) even though the
  39  * commands may be safe and represent the intended programming model of the
  40  * device.
  41  *
  42  * The software command parser is similar in operation to the command parsing
  43  * done in hardware for unsecure batches. However, the software parser allows
  44  * some operations that would be noop'd by hardware, if the parser determines
  45  * the operation is safe, and submits the batch as "secure" to prevent hardware
  46  * parsing.
  47  *
  48  * Threats:
  49  * At a high level, the hardware (and software) checks attempt to prevent
  50  * granting userspace undue privileges. There are three categories of privilege.
  51  *
  52  * First, commands which are explicitly defined as privileged or which should
  53  * only be used by the kernel driver. The parser generally rejects such
  54  * commands, though it may allow some from the drm master process.
  55  *
  56  * Second, commands which access registers. To support correct/enhanced
  57  * userspace functionality, particularly certain OpenGL extensions, the parser
  58  * provides a whitelist of registers which userspace may safely access (for both
  59  * normal and drm master processes).
  60  *
  61  * Third, commands which access privileged memory (i.e. GGTT, HWS page, etc).
  62  * The parser always rejects such commands.
  63  *
  64  * The majority of the problematic commands fall in the MI_* range, with only a
  65  * few specific commands on each ring (e.g. PIPE_CONTROL and MI_FLUSH_DW).
  66  *
  67  * Implementation:
  68  * Each ring maintains tables of commands and registers which the parser uses in
  69  * scanning batch buffers submitted to that ring.
  70  *
  71  * Since the set of commands that the parser must check for is significantly
  72  * smaller than the number of commands supported, the parser tables contain only
  73  * those commands required by the parser. This generally works because command
  74  * opcode ranges have standard command length encodings. So for commands that
  75  * the parser does not need to check, it can easily skip them. This is
  76  * implementated via a per-ring length decoding vfunc.
  77  *
  78  * Unfortunately, there are a number of commands that do not follow the standard
  79  * length encoding for their opcode range, primarily amongst the MI_* commands.
  80  * To handle this, the parser provides a way to define explicit "skip" entries
  81  * in the per-ring command tables.
  82  *
  83  * Other command table entries map fairly directly to high level categories
  84  * mentioned above: rejected, master-only, register whitelist. The parser
  85  * implements a number of checks, including the privileged memory checks, via a
  86  * general bitmasking mechanism.
  87  */
  88
  89 #define STD_MI_OPCODE_MASK  0xFF800000
  90 #define STD_3D_OPCODE_MASK  0xFFFF0000
  91 #define STD_2D_OPCODE_MASK  0xFFC00000
  92 #define STD_MFX_OPCODE_MASK 0xFFFF0000
  93
  94 #define CMD(op, opm, f, lm, fl, ...)                            \
  95         {                                                       \
  96                 .flags = (fl) | ((f) ? CMD_DESC_FIXED : 0),     \
  97                 .cmd = { (op), (opm) },                         \
  98                 .length = { (lm) },                             \
  99                 __VA_ARGS__                                     \
 100         }
 101
 102 /* Convenience macros to compress the tables */
 103 #define SMI STD_MI_OPCODE_MASK
 104 #define S3D STD_3D_OPCODE_MASK
 105 #define S2D STD_2D_OPCODE_MASK
 106 #define SMFX STD_MFX_OPCODE_MASK
 107 #define F true
 108 #define S CMD_DESC_SKIP
 109 #define R CMD_DESC_REJECT
 110 #define W CMD_DESC_REGISTER
 111 #define B CMD_DESC_BITMASK
 112 #define M CMD_DESC_MASTER
 113
 114 /*            Command                          Mask   Fixed Len   Action
 115               ---------------------------------------------------------- */
 116 static const struct drm_i915_cmd_descriptor common_cmds[] = {
 117         CMD(  MI_NOOP,                          SMI,    F,  1,      S  ),
 118         CMD(  MI_USER_INTERRUPT,                SMI,    F,  1,      R  ),
 119         CMD(  MI_WAIT_FOR_EVENT,                SMI,    F,  1,      M  ),
 120         CMD(  MI_ARB_CHECK,                     SMI,    F,  1,      S  ),
 121         CMD(  MI_REPORT_HEAD,                   SMI,    F,  1,      S  ),
 122         CMD(  MI_SUSPEND_FLUSH,                 SMI,    F,  1,      S  ),
 123         CMD(  MI_SEMAPHORE_MBOX,                SMI,   !F,  0xFF,   R  ),
 124         CMD(  MI_STORE_DWORD_INDEX,             SMI,   !F,  0xFF,   R  ),
 125         CMD(  MI_LOAD_REGISTER_IMM(1),          SMI,   !F,  0xFF,   W,
 126               .reg = { .offset = 1, .mask = 0x007FFFFC }               ),
 127         CMD(  MI_STORE_REGISTER_MEM(1),         SMI,   !F,  0xFF,   W | B,
 128               .reg = { .offset = 1, .mask = 0x007FFFFC },
 129               .bits = {{
 130                         .offset = 0,
 131                         .mask = MI_GLOBAL_GTT,
 132                         .expected = 0,
 133               }},                                                      ),
 134         CMD(  MI_LOAD_REGISTER_MEM,             SMI,   !F,  0xFF,   W | B,
 135               .reg = { .offset = 1, .mask = 0x007FFFFC },
 136               .bits = {{
 137                         .offset = 0,
 138                         .mask = MI_GLOBAL_GTT,
 139                         .expected = 0,
 140               }},                                                      ),
 141         /*
 142          * MI_BATCH_BUFFER_START requires some special handling. It's not
 143          * really a 'skip' action but it doesn't seem like it's worth adding
 144          * a new action. See i915_parse_cmds().
 145          */
 146         CMD(  MI_BATCH_BUFFER_START,            SMI,   !F,  0xFF,   S  ),
 147 };
 148
 149 static const struct drm_i915_cmd_descriptor render_cmds[] = {
 150         CMD(  MI_FLUSH,                         SMI,    F,  1,      S  ),
 151         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 152         CMD(  MI_PREDICATE,                     SMI,    F,  1,      S  ),
 153         CMD(  MI_TOPOLOGY_FILTER,               SMI,    F,  1,      S  ),
 154         CMD(  MI_DISPLAY_FLIP,                  SMI,   !F,  0xFF,   R  ),
 155         CMD(  MI_SET_CONTEXT,                   SMI,   !F,  0xFF,   R  ),
 156         CMD(  MI_URB_CLEAR,                     SMI,   !F,  0xFF,   S  ),
 157         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0x3F,   B,
 158               .bits = {{
 159                         .offset = 0,
 160                         .mask = MI_GLOBAL_GTT,
 161                         .expected = 0,
 162               }},                                                      ),
 163         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0xFF,   R  ),
 164         CMD(  MI_CLFLUSH,                       SMI,   !F,  0x3FF,  B,
 165               .bits = {{
 166                         .offset = 0,
 167                         .mask = MI_GLOBAL_GTT,
 168                         .expected = 0,
 169               }},                                                      ),
 170         CMD(  MI_REPORT_PERF_COUNT,             SMI,   !F,  0x3F,   B,
 171               .bits = {{
 172                         .offset = 1,
 173                         .mask = MI_REPORT_PERF_COUNT_GGTT,
 174                         .expected = 0,
 175               }},                                                      ),
 176         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
 177               .bits = {{
 178                         .offset = 0,
 179                         .mask = MI_GLOBAL_GTT,
 180                         .expected = 0,
 181               }},                                                      ),
 182         CMD(  GFX_OP_3DSTATE_VF_STATISTICS,     S3D,    F,  1,      S  ),
 183         CMD(  PIPELINE_SELECT,                  S3D,    F,  1,      S  ),
 184         CMD(  MEDIA_VFE_STATE,                  S3D,   !F,  0xFFFF, B,
 185               .bits = {{
 186                         .offset = 2,
 187                         .mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
 188                         .expected = 0,
 189               }},                                                      ),
 190         CMD(  GPGPU_OBJECT,                     S3D,   !F,  0xFF,   S  ),
 191         CMD(  GPGPU_WALKER,                     S3D,   !F,  0xFF,   S  ),
 192         CMD(  GFX_OP_3DSTATE_SO_DECL_LIST,      S3D,   !F,  0x1FF,  S  ),
 193         CMD(  GFX_OP_PIPE_CONTROL(5),           S3D,   !F,  0xFF,   B,
 194               .bits = {{
 195                         .offset = 1,
 196                         .mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),
 197                         .expected = 0,
 198               },
 199               {
 200                         .offset = 1,
 201                         .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |
 202                                  PIPE_CONTROL_STORE_DATA_INDEX),
 203                         .expected = 0,
 204                         .condition_offset = 1,
 205                         .condition_mask = PIPE_CONTROL_POST_SYNC_OP_MASK,
 206               }},                                                      ),
 207 };
 208
 209 static const struct drm_i915_cmd_descriptor hsw_render_cmds[] = {
 210         CMD(  MI_SET_PREDICATE,                 SMI,    F,  1,      S  ),
 211         CMD(  MI_RS_CONTROL,                    SMI,    F,  1,      S  ),
 212         CMD(  MI_URB_ATOMIC_ALLOC,              SMI,    F,  1,      S  ),
 213         CMD(  MI_RS_CONTEXT,                    SMI,    F,  1,      S  ),
 214         CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   M  ),
 215         CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   R  ),
 216         CMD(  MI_LOAD_REGISTER_REG,             SMI,   !F,  0xFF,   R  ),
 217         CMD(  MI_RS_STORE_DATA_IMM,             SMI,   !F,  0xFF,   S  ),
 218         CMD(  MI_LOAD_URB_MEM,                  SMI,   !F,  0xFF,   S  ),
 219         CMD(  MI_STORE_URB_MEM,                 SMI,   !F,  0xFF,   S  ),
 220         CMD(  GFX_OP_3DSTATE_DX9_CONSTANTF_VS,  S3D,   !F,  0x7FF,  S  ),
 221         CMD(  GFX_OP_3DSTATE_DX9_CONSTANTF_PS,  S3D,   !F,  0x7FF,  S  ),
 222
 223         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_VS,  S3D,   !F,  0x1FF,  S  ),
 224         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_GS,  S3D,   !F,  0x1FF,  S  ),
 225         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_HS,  S3D,   !F,  0x1FF,  S  ),
 226         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_DS,  S3D,   !F,  0x1FF,  S  ),
 227         CMD(  GFX_OP_3DSTATE_BINDING_TABLE_EDIT_PS,  S3D,   !F,  0x1FF,  S  ),
 228 };
 229
 230 static const struct drm_i915_cmd_descriptor video_cmds[] = {
 231         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 232         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   B,
 233               .bits = {{
 234                         .offset = 0,
 235                         .mask = MI_GLOBAL_GTT,
 236                         .expected = 0,
 237               }},                                                      ),
 238         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 239         CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,
 240               .bits = {{
 241                         .offset = 0,
 242                         .mask = MI_FLUSH_DW_NOTIFY,
 243                         .expected = 0,
 244               },
 245               {
 246                         .offset = 1,
 247                         .mask = MI_FLUSH_DW_USE_GTT,
 248                         .expected = 0,
 249                         .condition_offset = 0,
 250                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 251               },
 252               {
 253                         .offset = 0,
 254                         .mask = MI_FLUSH_DW_STORE_INDEX,
 255                         .expected = 0,
 256                         .condition_offset = 0,
 257                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 258               }},                                                      ),
 259         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
 260               .bits = {{
 261                         .offset = 0,
 262                         .mask = MI_GLOBAL_GTT,
 263                         .expected = 0,
 264               }},                                                      ),
 265         /*
 266          * MFX_WAIT doesn't fit the way we handle length for most commands.
 267          * It has a length field but it uses a non-standard length bias.
 268          * It is always 1 dword though, so just treat it as fixed length.
 269          */
 270         CMD(  MFX_WAIT,                         SMFX,   F,  1,      S  ),
 271 };
 272
 273 static const struct drm_i915_cmd_descriptor vecs_cmds[] = {
 274         CMD(  MI_ARB_ON_OFF,                    SMI,    F,  1,      R  ),
 275         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0xFF,   B,
 276               .bits = {{
 277                         .offset = 0,
 278                         .mask = MI_GLOBAL_GTT,
 279                         .expected = 0,
 280               }},                                                      ),
 281         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 282         CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,
 283               .bits = {{
 284                         .offset = 0,
 285                         .mask = MI_FLUSH_DW_NOTIFY,
 286                         .expected = 0,
 287               },
 288               {
 289                         .offset = 1,
 290                         .mask = MI_FLUSH_DW_USE_GTT,
 291                         .expected = 0,
 292                         .condition_offset = 0,
 293                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 294               },
 295               {
 296                         .offset = 0,
 297                         .mask = MI_FLUSH_DW_STORE_INDEX,
 298                         .expected = 0,
 299                         .condition_offset = 0,
 300                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 301               }},                                                      ),
 302         CMD(  MI_CONDITIONAL_BATCH_BUFFER_END,  SMI,   !F,  0xFF,   B,
 303               .bits = {{
 304                         .offset = 0,
 305                         .mask = MI_GLOBAL_GTT,
 306                         .expected = 0,
 307               }},                                                      ),
 308 };
 309
 310 static const struct drm_i915_cmd_descriptor blt_cmds[] = {
 311         CMD(  MI_DISPLAY_FLIP,                  SMI,   !F,  0xFF,   R  ),
 312         CMD(  MI_STORE_DWORD_IMM,               SMI,   !F,  0x3FF,  B,
 313               .bits = {{
 314                         .offset = 0,
 315                         .mask = MI_GLOBAL_GTT,
 316                         .expected = 0,
 317               }},                                                      ),
 318         CMD(  MI_UPDATE_GTT,                    SMI,   !F,  0x3F,   R  ),
 319         CMD(  MI_FLUSH_DW,                      SMI,   !F,  0x3F,   B,
 320               .bits = {{
 321                         .offset = 0,
 322                         .mask = MI_FLUSH_DW_NOTIFY,
 323                         .expected = 0,
 324               },
 325               {
 326                         .offset = 1,
 327                         .mask = MI_FLUSH_DW_USE_GTT,
 328                         .expected = 0,
 329                         .condition_offset = 0,
 330                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 331               },
 332               {
 333                         .offset = 0,
 334                         .mask = MI_FLUSH_DW_STORE_INDEX,
 335                         .expected = 0,
 336                         .condition_offset = 0,
 337                         .condition_mask = MI_FLUSH_DW_OP_MASK,
 338               }},                                                      ),
 339         CMD(  COLOR_BLT,                        S2D,   !F,  0x3F,   S  ),
 340         CMD(  SRC_COPY_BLT,                     S2D,   !F,  0x3F,   S  ),
 341 };
 342
 343 static const struct drm_i915_cmd_descriptor hsw_blt_cmds[] = {
 344         CMD(  MI_LOAD_SCAN_LINES_INCL,          SMI,   !F,  0x3F,   M  ),
 345         CMD(  MI_LOAD_SCAN_LINES_EXCL,          SMI,   !F,  0x3F,   R  ),
 346 };
 347
 348 #undef CMD
 349 #undef SMI
 350 #undef S3D
 351 #undef S2D
 352 #undef SMFX
 353 #undef F
 354 #undef S
 355 #undef R
 356 #undef W
 357 #undef B
 358 #undef M
 359
 360 static const struct drm_i915_cmd_table gen7_render_cmds[] = {
 361         { common_cmds, ARRAY_SIZE(common_cmds) },
 362         { render_cmds, ARRAY_SIZE(render_cmds) },
 363 };
 364
 365 static const struct drm_i915_cmd_table hsw_render_ring_cmds[] = {
 366         { common_cmds, ARRAY_SIZE(common_cmds) },
 367         { render_cmds, ARRAY_SIZE(render_cmds) },
 368         { hsw_render_cmds, ARRAY_SIZE(hsw_render_cmds) },
 369 };
 370
 371 static const struct drm_i915_cmd_table gen7_video_cmds[] = {
 372         { common_cmds, ARRAY_SIZE(common_cmds) },
 373         { video_cmds, ARRAY_SIZE(video_cmds) },
 374 };
 375
 376 static const struct drm_i915_cmd_table hsw_vebox_cmds[] = {
 377         { common_cmds, ARRAY_SIZE(common_cmds) },
 378         { vecs_cmds, ARRAY_SIZE(vecs_cmds) },
 379 };
 380
 381 static const struct drm_i915_cmd_table gen7_blt_cmds[] = {
 382         { common_cmds, ARRAY_SIZE(common_cmds) },
 383         { blt_cmds, ARRAY_SIZE(blt_cmds) },
 384 };
 385
 386 static const struct drm_i915_cmd_table hsw_blt_ring_cmds[] = {
 387         { common_cmds, ARRAY_SIZE(common_cmds) },
 388         { blt_cmds, ARRAY_SIZE(blt_cmds) },
 389         { hsw_blt_cmds, ARRAY_SIZE(hsw_blt_cmds) },
 390 };
 391
 392 /*
 393  * Register whitelists, sorted by increasing register offset.
 394  *
 395  * Some registers that userspace accesses are 64 bits. The register
 396  * access commands only allow 32-bit accesses. Hence, we have to include
 397  * entries for both halves of the 64-bit registers.
 398  */
 399
 400 /* Convenience macro for adding 64-bit registers */
 401 #define REG64(addr) (addr), (addr + sizeof(u32))
 402
 403 static const u32 gen7_render_regs[] = {
 404         REG64(HS_INVOCATION_COUNT),
 405         REG64(DS_INVOCATION_COUNT),
 406         REG64(IA_VERTICES_COUNT),
 407         REG64(IA_PRIMITIVES_COUNT),
 408         REG64(VS_INVOCATION_COUNT),
 409         REG64(GS_INVOCATION_COUNT),
 410         REG64(GS_PRIMITIVES_COUNT),
 411         REG64(CL_INVOCATION_COUNT),
 412         REG64(CL_PRIMITIVES_COUNT),
 413         REG64(PS_INVOCATION_COUNT),
 414         REG64(PS_DEPTH_COUNT),
 415         OACONTROL, /* Only allowed for LRI and SRM. See below. */
 416         GEN7_3DPRIM_END_OFFSET,
 417         GEN7_3DPRIM_START_VERTEX,
 418         GEN7_3DPRIM_VERTEX_COUNT,
 419         GEN7_3DPRIM_INSTANCE_COUNT,
 420         GEN7_3DPRIM_START_INSTANCE,
 421         GEN7_3DPRIM_BASE_VERTEX,
 422         REG64(GEN7_SO_NUM_PRIMS_WRITTEN(0)),
 423         REG64(GEN7_SO_NUM_PRIMS_WRITTEN(1)),
 424         REG64(GEN7_SO_NUM_PRIMS_WRITTEN(2)),
 425         REG64(GEN7_SO_NUM_PRIMS_WRITTEN(3)),
 426         REG64(GEN7_SO_PRIM_STORAGE_NEEDED(0)),
 427         REG64(GEN7_SO_PRIM_STORAGE_NEEDED(1)),
 428         REG64(GEN7_SO_PRIM_STORAGE_NEEDED(2)),
 429         REG64(GEN7_SO_PRIM_STORAGE_NEEDED(3)),
 430         GEN7_SO_WRITE_OFFSET(0),
 431         GEN7_SO_WRITE_OFFSET(1),
 432         GEN7_SO_WRITE_OFFSET(2),
 433         GEN7_SO_WRITE_OFFSET(3),
 434         GEN7_L3SQCREG1,
 435         GEN7_L3CNTLREG2,
 436         GEN7_L3CNTLREG3,
 437 };
 438
 439 static const u32 gen7_blt_regs[] = {
 440         BCS_SWCTRL,
 441 };
 442
 443 static const u32 ivb_master_regs[] = {
 444         FORCEWAKE_MT,
 445         DERRMR,
 446         GEN7_PIPE_DE_LOAD_SL(PIPE_A),
 447         GEN7_PIPE_DE_LOAD_SL(PIPE_B),
 448         GEN7_PIPE_DE_LOAD_SL(PIPE_C),
 449 };
 450
 451 static const u32 hsw_master_regs[] = {
 452         FORCEWAKE_MT,
 453         DERRMR,
 454 };
 455
 456 #undef REG64
 457
 458 static u32 gen7_render_get_cmd_length_mask(u32 cmd_header)
 459 {
 460         u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
 461         u32 subclient =
 462                 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
 463
 464         if (client == INSTR_MI_CLIENT)
 465                 return 0x3F;
 466         else if (client == INSTR_RC_CLIENT) {
 467                 if (subclient == INSTR_MEDIA_SUBCLIENT)
 468                         return 0xFFFF;
 469                 else
 470                         return 0xFF;
 471         }
 472
 473         DRM_DEBUG_DRIVER("CMD: Abnormal rcs cmd length! 0x%08X\n", cmd_header);
 474         return 0;
 475 }
 476
 477 static u32 gen7_bsd_get_cmd_length_mask(u32 cmd_header)
 478 {
 479         u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
 480         u32 subclient =
 481                 (cmd_header & INSTR_SUBCLIENT_MASK) >> INSTR_SUBCLIENT_SHIFT;
 482
 483         if (client == INSTR_MI_CLIENT)
 484                 return 0x3F;
 485         else if (client == INSTR_RC_CLIENT) {
 486                 if (subclient == INSTR_MEDIA_SUBCLIENT)
 487                         return 0xFFF;
 488                 else
 489                         return 0xFF;
 490         }
 491
 492         DRM_DEBUG_DRIVER("CMD: Abnormal bsd cmd length! 0x%08X\n", cmd_header);
 493         return 0;
 494 }
 495
 496 static u32 gen7_blt_get_cmd_length_mask(u32 cmd_header)
 497 {
 498         u32 client = (cmd_header & INSTR_CLIENT_MASK) >> INSTR_CLIENT_SHIFT;
 499
 500         if (client == INSTR_MI_CLIENT)
 501                 return 0x3F;
 502         else if (client == INSTR_BC_CLIENT)
 503                 return 0xFF;
 504
 505         DRM_DEBUG_DRIVER("CMD: Abnormal blt cmd length! 0x%08X\n", cmd_header);
 506         return 0;
 507 }
 508
 509 static bool validate_cmds_sorted(struct intel_engine_cs *ring,
 510                                  const struct drm_i915_cmd_table *cmd_tables,
 511                                  int cmd_table_count)
 512 {
 513         int i;
 514         bool ret = true;
 515
 516         if (!cmd_tables || cmd_table_count == 0)
 517                 return true;
 518
 519         for (i = 0; i < cmd_table_count; i++) {
 520                 const struct drm_i915_cmd_table *table = &cmd_tables[i];
 521                 u32 previous = 0;
 522                 int j;
 523
 524                 for (j = 0; j < table->count; j++) {
 525                         const struct drm_i915_cmd_descriptor *desc =
 526                                 &table->table[i];
 527                         u32 curr = desc->cmd.value & desc->cmd.mask;
 528
 529                         if (curr < previous) {
 530                                 DRM_ERROR("CMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X\n",
 531                                           ring->id, i, j, curr, previous);
 532                                 ret = false;
 533                         }
 534
 535                         previous = curr;
 536                 }
 537         }
 538
 539         return ret;
 540 }
 541
 542 static bool check_sorted(int ring_id, const u32 *reg_table, int reg_count)
 543 {
 544         int i;
 545         u32 previous = 0;
 546         bool ret = true;
 547
 548         for (i = 0; i < reg_count; i++) {
 549                 u32 curr = reg_table[i];
 550
 551                 if (curr < previous) {
 552                         DRM_ERROR("CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X\n",
 553                                   ring_id, i, curr, previous);
 554                         ret = false;
 555                 }
 556
 557                 previous = curr;
 558         }
 559
 560         return ret;
 561 }
 562
 563 static bool validate_regs_sorted(struct intel_engine_cs *ring)
 564 {
 565         return check_sorted(ring->id, ring->reg_table, ring->reg_count) &&
 566                 check_sorted(ring->id, ring->master_reg_table,
 567                              ring->master_reg_count);
 568 }
 569
 570 struct cmd_node {
 571         const struct drm_i915_cmd_descriptor *desc;
 572         struct hlist_node node;
 573 };
 574
 575 /*
 576  * Different command ranges have different numbers of bits for the opcode. For
 577  * example, MI commands use bits 31:23 while 3D commands use bits 31:16. The
 578  * problem is that, for example, MI commands use bits 22:16 for other fields
 579  * such as GGTT vs PPGTT bits. If we include those bits in the mask then when
 580  * we mask a command from a batch it could hash to the wrong bucket due to
 581  * non-opcode bits being set. But if we don't include those bits, some 3D
 582  * commands may hash to the same bucket due to not including opcode bits that
 583  * make the command unique. For now, we will risk hashing to the same bucket.
 584  *
 585  * If we attempt to generate a perfect hash, we should be able to look at bits
 586  * 31:29 of a command from a batch buffer and use the full mask for that
 587  * client. The existing INSTR_CLIENT_MASK/SHIFT defines can be used for this.
 588  */
 589 #define CMD_HASH_MASK STD_MI_OPCODE_MASK
 590
 591 static int init_hash_table(struct intel_engine_cs *ring,
 592                            const struct drm_i915_cmd_table *cmd_tables,
 593                            int cmd_table_count)
 594 {
 595         int i, j;
 596
 597         hash_init(ring->cmd_hash);
 598
 599         for (i = 0; i < cmd_table_count; i++) {
 600                 const struct drm_i915_cmd_table *table = &cmd_tables[i];
 601
 602                 for (j = 0; j < table->count; j++) {
 603                         const struct drm_i915_cmd_descriptor *desc =
 604                                 &table->table[j];
 605                         struct cmd_node *desc_node =
 606                                 kmalloc(sizeof(*desc_node), GFP_KERNEL);
 607
 608                         if (!desc_node)
 609                                 return -ENOMEM;
 610
 611                         desc_node->desc = desc;
 612                         hash_add(ring->cmd_hash, &desc_node->node,
 613                                  desc->cmd.value & CMD_HASH_MASK);
 614                 }
 615         }
 616
 617         return 0;
 618 }
 619
 620 static void fini_hash_table(struct intel_engine_cs *ring)
 621 {
 622         struct hlist_node *tmp;
 623         struct cmd_node *desc_node;
 624         int i;
 625
 626         hash_for_each_safe(ring->cmd_hash, i, tmp, desc_node, node) {
 627                 hash_del(&desc_node->node);
 628                 kfree(desc_node);
 629         }
 630 }
 631
 632 /**
 633  * i915_cmd_parser_init_ring() - set cmd parser related fields for a ringbuffer
 634  * @ring: the ringbuffer to initialize
 635  *
 636  * Optionally initializes fields related to batch buffer command parsing in the
 637  * struct intel_engine_cs based on whether the platform requires software
 638  * command parsing.
 639  *
 640  * Return: non-zero if initialization fails
 641  */
 642 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring)
 643 {
 644         const struct drm_i915_cmd_table *cmd_tables;
 645         int cmd_table_count;
 646         int ret;
 647
 648         if (!IS_GEN7(ring->dev))
 649                 return 0;
 650
 651         switch (ring->id) {
 652         case RCS:
 653                 if (IS_HASWELL(ring->dev)) {
 654                         cmd_tables = hsw_render_ring_cmds;
 655                         cmd_table_count =
 656                                 ARRAY_SIZE(hsw_render_ring_cmds);
 657                 } else {
 658                         cmd_tables = gen7_render_cmds;
 659                         cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
 660                 }
 661
 662                 ring->reg_table = gen7_render_regs;
 663                 ring->reg_count = ARRAY_SIZE(gen7_render_regs);
 664
 665                 if (IS_HASWELL(ring->dev)) {
 666                         ring->master_reg_table = hsw_master_regs;
 667                         ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
 668                 } else {
 669                         ring->master_reg_table = ivb_master_regs;
 670                         ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
 671                 }
 672
 673                 ring->get_cmd_length_mask = gen7_render_get_cmd_length_mask;
 674                 break;
 675         case VCS:
 676                 cmd_tables = gen7_video_cmds;
 677                 cmd_table_count = ARRAY_SIZE(gen7_video_cmds);
 678                 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
 679                 break;
 680         case BCS:
 681                 if (IS_HASWELL(ring->dev)) {
 682                         cmd_tables = hsw_blt_ring_cmds;
 683                         cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
 684                 } else {
 685                         cmd_tables = gen7_blt_cmds;
 686                         cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
 687                 }
 688
 689                 ring->reg_table = gen7_blt_regs;
 690                 ring->reg_count = ARRAY_SIZE(gen7_blt_regs);
 691
 692                 if (IS_HASWELL(ring->dev)) {
 693                         ring->master_reg_table = hsw_master_regs;
 694                         ring->master_reg_count = ARRAY_SIZE(hsw_master_regs);
 695                 } else {
 696                         ring->master_reg_table = ivb_master_regs;
 697                         ring->master_reg_count = ARRAY_SIZE(ivb_master_regs);
 698                 }
 699
 700                 ring->get_cmd_length_mask = gen7_blt_get_cmd_length_mask;
 701                 break;
 702         case VECS:
 703                 cmd_tables = hsw_vebox_cmds;
 704                 cmd_table_count = ARRAY_SIZE(hsw_vebox_cmds);
 705                 /* VECS can use the same length_mask function as VCS */
 706                 ring->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
 707                 break;
 708         default:
 709                 DRM_ERROR("CMD: cmd_parser_init with unknown ring: %d\n",
 710                           ring->id);
 711                 BUG();
 712         }
 713
 714         BUG_ON(!validate_cmds_sorted(ring, cmd_tables, cmd_table_count));
 715         BUG_ON(!validate_regs_sorted(ring));
 716
 717         if (hash_empty(ring->cmd_hash)) {
 718                 ret = init_hash_table(ring, cmd_tables, cmd_table_count);
 719                 if (ret) {
 720                         DRM_ERROR("CMD: cmd_parser_init failed!\n");
 721                         fini_hash_table(ring);
 722                         return ret;
 723                 }
 724         }
 725
 726         ring->needs_cmd_parser = true;
 727
 728         return 0;
 729 }
 730
 731 /**
 732  * i915_cmd_parser_fini_ring() - clean up cmd parser related fields
 733  * @ring: the ringbuffer to clean up
 734  *
 735  * Releases any resources related to command parsing that may have been
 736  * initialized for the specified ring.
 737  */
 738 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring)
 739 {
 740         if (!ring->needs_cmd_parser)
 741                 return;
 742
 743         fini_hash_table(ring);
 744 }
 745
 746 static const struct drm_i915_cmd_descriptor*
 747 find_cmd_in_table(struct intel_engine_cs *ring,
 748                   u32 cmd_header)
 749 {
 750         struct cmd_node *desc_node;
 751
 752         hash_for_each_possible(ring->cmd_hash, desc_node, node,
 753                                cmd_header & CMD_HASH_MASK) {
 754                 const struct drm_i915_cmd_descriptor *desc = desc_node->desc;
 755                 u32 masked_cmd = desc->cmd.mask & cmd_header;
 756                 u32 masked_value = desc->cmd.value & desc->cmd.mask;
 757
 758                 if (masked_cmd == masked_value)
 759                         return desc;
 760         }
 761
 762         return NULL;
 763 }
 764
 765 /*
 766  * Returns a pointer to a descriptor for the command specified by cmd_header.
 767  *
 768  * The caller must supply space for a default descriptor via the default_desc
 769  * parameter. If no descriptor for the specified command exists in the ring's
 770  * command parser tables, this function fills in default_desc based on the
 771  * ring's default length encoding and returns default_desc.
 772  */
 773 static const struct drm_i915_cmd_descriptor*
 774 find_cmd(struct intel_engine_cs *ring,
 775          u32 cmd_header,
 776          struct drm_i915_cmd_descriptor *default_desc)
 777 {
 778         const struct drm_i915_cmd_descriptor *desc;
 779         u32 mask;
 780
 781         desc = find_cmd_in_table(ring, cmd_header);
 782         if (desc)
 783                 return desc;
 784
 785         mask = ring->get_cmd_length_mask(cmd_header);
 786         if (!mask)
 787                 return NULL;
 788
 789         BUG_ON(!default_desc);
 790         default_desc->flags = CMD_DESC_SKIP;
 791         default_desc->length.mask = mask;
 792
 793         return default_desc;
 794 }
 795
 796 static bool valid_reg(const u32 *table, int count, u32 addr)
 797 {
 798         if (table && count != 0) {
 799                 int i;
 800
 801                 for (i = 0; i < count; i++) {
 802                         if (table[i] == addr)
 803                                 return true;
 804                 }
 805         }
 806
 807         return false;
 808 }
 809
 810 static u32 *vmap_batch(struct drm_i915_gem_object *obj)
 811 {
 812         int i;
 813         void *addr = NULL;
 814         struct sg_page_iter sg_iter;
 815         struct page **pages;
 816
 817         pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
 818         if (pages == NULL) {
 819                 DRM_DEBUG_DRIVER("Failed to get space for pages\n");
 820                 goto finish;
 821         }
 822
 823         i = 0;
 824         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
 825                 pages[i] = sg_page_iter_page(&sg_iter);
 826                 i++;
 827         }
 828
 829         addr = vmap(pages, i, 0, PAGE_KERNEL);
 830         if (addr == NULL) {
 831                 DRM_DEBUG_DRIVER("Failed to vmap pages\n");
 832                 goto finish;
 833         }
 834
 835 finish:
 836         if (pages)
 837                 drm_free_large(pages);
 838         return (u32*)addr;
 839 }
 840
 841 /**
 842  * i915_needs_cmd_parser() - should a given ring use software command parsing?
 843  * @ring: the ring in question
 844  *
 845  * Only certain platforms require software batch buffer command parsing, and
 846  * only when enabled via module paramter.
 847  *
 848  * Return: true if the ring requires software command parsing
 849  */
 850 bool i915_needs_cmd_parser(struct intel_engine_cs *ring)
 851 {
 852         if (!ring->needs_cmd_parser)
 853                 return false;
 854
 855         if (!USES_PPGTT(ring->dev))
 856                 return false;
 857
 858         return (i915.enable_cmd_parser == 1);
 859 }
 860
 861 static bool check_cmd(const struct intel_engine_cs *ring,
 862                       const struct drm_i915_cmd_descriptor *desc,
 863                       const u32 *cmd,
 864                       const bool is_master,
 865                       bool *oacontrol_set)
 866 {
 867         if (desc->flags & CMD_DESC_REJECT) {
 868                 DRM_DEBUG_DRIVER("CMD: Rejected command: 0x%08X\n", *cmd);
 869                 return false;
 870         }
 871
 872         if ((desc->flags & CMD_DESC_MASTER) && !is_master) {
 873                 DRM_DEBUG_DRIVER("CMD: Rejected master-only command: 0x%08X\n",
 874                                  *cmd);
 875                 return false;
 876         }
 877
 878         if (desc->flags & CMD_DESC_REGISTER) {
 879                 u32 reg_addr = cmd[desc->reg.offset] & desc->reg.mask;
 880
 881                 /*
 882                  * OACONTROL requires some special handling for writes. We
 883                  * want to make sure that any batch which enables OA also
 884                  * disables it before the end of the batch. The goal is to
 885                  * prevent one process from snooping on the perf data from
 886                  * another process. To do that, we need to check the value
 887                  * that will be written to the register. Hence, limit
 888                  * OACONTROL writes to only MI_LOAD_REGISTER_IMM commands.
 889                  */
 890                 if (reg_addr == OACONTROL) {
 891                         if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
 892                                 DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n");
 893                                 return false;
 894                         }
 895
 896                         if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1))
 897                                 *oacontrol_set = (cmd[2] != 0);
 898                 }
 899
 900                 if (!valid_reg(ring->reg_table,
 901                                ring->reg_count, reg_addr)) {
 902                         if (!is_master ||
 903                             !valid_reg(ring->master_reg_table,
 904                                        ring->master_reg_count,
 905                                        reg_addr)) {
 906                                 DRM_DEBUG_DRIVER("CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d)\n",
 907                                                  reg_addr,
 908                                                  *cmd,
 909                                                  ring->id);
 910                                 return false;
 911                         }
 912                 }
 913         }
 914
 915         if (desc->flags & CMD_DESC_BITMASK) {
 916                 int i;
 917
 918                 for (i = 0; i < MAX_CMD_DESC_BITMASKS; i++) {
 919                         u32 dword;
 920
 921                         if (desc->bits[i].mask == 0)
 922                                 break;
 923
 924                         if (desc->bits[i].condition_mask != 0) {
 925                                 u32 offset =
 926                                         desc->bits[i].condition_offset;
 927                                 u32 condition = cmd[offset] &
 928                                         desc->bits[i].condition_mask;
 929
 930                                 if (condition == 0)
 931                                         continue;
 932                         }
 933
 934                         dword = cmd[desc->bits[i].offset] &
 935                                 desc->bits[i].mask;
 936
 937                         if (dword != desc->bits[i].expected) {
 938                                 DRM_DEBUG_DRIVER("CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d)\n",
 939                                                  *cmd,
 940                                                  desc->bits[i].mask,
 941                                                  desc->bits[i].expected,
 942                                                  dword, ring->id);
 943                                 return false;
 944                         }
 945                 }
 946         }
 947
 948         return true;
 949 }
 950
 951 #define LENGTH_BIAS 2
 952
 953 /**
 954  * i915_parse_cmds() - parse a submitted batch buffer for privilege violations
 955  * @ring: the ring on which the batch is to execute
 956  * @batch_obj: the batch buffer in question
 957  * @batch_start_offset: byte offset in the batch at which execution starts
 958  * @is_master: is the submitting process the drm master?
 959  *
 960  * Parses the specified batch buffer looking for privilege violations as
 961  * described in the overview.
 962  *
 963  * Return: non-zero if the parser finds violations or otherwise fails; -EACCES
 964  * if the batch appears legal but should use hardware parsing
 965  */
 966 int i915_parse_cmds(struct intel_engine_cs *ring,
 967                     struct drm_i915_gem_object *batch_obj,
 968                     u32 batch_start_offset,
 969                     bool is_master)
 970 {
 971         int ret = 0;
 972         u32 *cmd, *batch_base, *batch_end;
 973         struct drm_i915_cmd_descriptor default_desc = { 0 };
 974         int needs_clflush = 0;
 975         bool oacontrol_set = false; /* OACONTROL tracking. See check_cmd() */
 976
 977         ret = i915_gem_obj_prepare_shmem_read(batch_obj, &needs_clflush);
 978         if (ret) {
 979                 DRM_DEBUG_DRIVER("CMD: failed to prep read\n");
 980                 return ret;
 981         }
 982
 983         batch_base = vmap_batch(batch_obj);
 984         if (!batch_base) {
 985                 DRM_DEBUG_DRIVER("CMD: Failed to vmap batch\n");
 986                 i915_gem_object_unpin_pages(batch_obj);
 987                 return -ENOMEM;
 988         }
 989
 990         if (needs_clflush)
 991                 drm_clflush_virt_range((char *)batch_base, batch_obj->base.size);
 992
 993         cmd = batch_base + (batch_start_offset / sizeof(*cmd));
 994         batch_end = cmd + (batch_obj->base.size / sizeof(*batch_end));
 995
 996         while (cmd < batch_end) {
 997                 const struct drm_i915_cmd_descriptor *desc;
 998                 u32 length;
 999
1000                 if (*cmd == MI_BATCH_BUFFER_END)
1001                         break;
1002
1003                 desc = find_cmd(ring, *cmd, &default_desc);
1004                 if (!desc) {
1005                         DRM_DEBUG_DRIVER("CMD: Unrecognized command: 0x%08X\n",
1006                                          *cmd);
1007                         ret = -EINVAL;
1008                         break;
1009                 }
1010
1011                 /*
1012                  * If the batch buffer contains a chained batch, return an
1013                  * error that tells the caller to abort and dispatch the
1014                  * workload as a non-secure batch.
1015                  */
1016                 if (desc->cmd.value == MI_BATCH_BUFFER_START) {
1017                         ret = -EACCES;
1018                         break;
1019                 }
1020
1021                 if (desc->flags & CMD_DESC_FIXED)
1022                         length = desc->length.fixed;
1023                 else
1024                         length = ((*cmd & desc->length.mask) + LENGTH_BIAS);
1025
1026                 if ((batch_end - cmd) < length) {
1027                         DRM_DEBUG_DRIVER("CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td\n",
1028                                          *cmd,
1029                                          length,
1030                                          batch_end - cmd);
1031                         ret = -EINVAL;
1032                         break;
1033                 }
1034
1035                 if (!check_cmd(ring, desc, cmd, is_master, &oacontrol_set)) {
1036                         ret = -EINVAL;
1037                         break;
1038                 }
1039
1040                 cmd += length;
1041         }
1042
1043         if (oacontrol_set) {
1044                 DRM_DEBUG_DRIVER("CMD: batch set OACONTROL but did not clear it\n");
1045                 ret = -EINVAL;
1046         }
1047
1048         if (cmd >= batch_end) {
1049                 DRM_DEBUG_DRIVER("CMD: Got to the end of the buffer w/o a BBE cmd!\n");
1050                 ret = -EINVAL;
1051         }
1052
1053         vunmap(batch_base);
1054
1055         i915_gem_object_unpin_pages(batch_obj);
1056
1057         return ret;
1058 }
1059
1060 /**
1061  * i915_cmd_parser_get_version() - get the cmd parser version number
1062  *
1063  * The cmd parser maintains a simple increasing integer version number suitable
1064  * for passing to userspace clients to determine what operations are permitted.
1065  *
1066  * Return: the current version number of the cmd parser
1067  */
1068 int i915_cmd_parser_get_version(void)
1069 {
1070         /*
1071          * Command parser version history
1072          *
1073          * 1. Initial version. Checks batches and reports violations, but leaves
1074          *    hardware parsing enabled (so does not allow new use cases).
1075          */
1076         return 1;
1077 }