2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 static const char *yesno(int v)
51 return v ? "yes" : "no";
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
57 drm_add_fake_info_node(struct drm_minor *minor,
61 struct drm_info_node *node;
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
71 node->info_ent = (void *) key;
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
80 static int i915_capabilities(struct seq_file *m, void *data)
82 struct drm_info_node *node = m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
86 seq_printf(m, "gen: %d\n", info->gen);
87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
99 if (i915_gem_obj_is_pinned(obj))
105 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
107 switch (obj->tiling_mode) {
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
115 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
121 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
123 struct i915_vma *vma;
126 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
129 get_tiling_flag(obj),
130 get_global_flag(obj),
131 obj->base.size / 1024,
132 obj->base.read_domains,
133 obj->base.write_domain,
134 i915_gem_request_get_seqno(obj->last_read_req),
135 i915_gem_request_get_seqno(obj->last_write_req),
136 i915_gem_request_get_seqno(obj->last_fenced_req),
137 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
138 obj->dirty ? " dirty" : "",
139 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
141 seq_printf(m, " (name: %d)", obj->base.name);
142 list_for_each_entry(vma, &obj->vma_list, vma_link)
143 if (vma->pin_count > 0)
145 seq_printf(m, " (pinned x %d)", pin_count);
146 if (obj->pin_display)
147 seq_printf(m, " (display)");
148 if (obj->fence_reg != I915_FENCE_REG_NONE)
149 seq_printf(m, " (fence: %d)", obj->fence_reg);
150 list_for_each_entry(vma, &obj->vma_list, vma_link) {
151 if (!i915_is_ggtt(vma->vm))
155 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
156 vma->node.start, vma->node.size);
159 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
160 if (obj->pin_mappable || obj->fault_mappable) {
162 if (obj->pin_mappable)
164 if (obj->fault_mappable)
167 seq_printf(m, " (%s mappable)", s);
169 if (obj->ring != NULL)
170 seq_printf(m, " (%s)", obj->ring->name);
171 if (obj->frontbuffer_bits)
172 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
175 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
177 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
178 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
182 static int i915_gem_object_list_info(struct seq_file *m, void *data)
184 struct drm_info_node *node = m->private;
185 uintptr_t list = (uintptr_t) node->info_ent->data;
186 struct list_head *head;
187 struct drm_device *dev = node->minor->dev;
188 struct drm_i915_private *dev_priv = dev->dev_private;
189 struct i915_address_space *vm = &dev_priv->gtt.base;
190 struct i915_vma *vma;
191 size_t total_obj_size, total_gtt_size;
194 ret = mutex_lock_interruptible(&dev->struct_mutex);
198 /* FIXME: the user of this interface might want more than just GGTT */
201 seq_puts(m, "Active:\n");
202 head = &vm->active_list;
205 seq_puts(m, "Inactive:\n");
206 head = &vm->inactive_list;
209 mutex_unlock(&dev->struct_mutex);
213 total_obj_size = total_gtt_size = count = 0;
214 list_for_each_entry(vma, head, mm_list) {
216 describe_obj(m, vma->obj);
218 total_obj_size += vma->obj->base.size;
219 total_gtt_size += vma->node.size;
222 mutex_unlock(&dev->struct_mutex);
224 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
225 count, total_obj_size, total_gtt_size);
229 static int obj_rank_by_stolen(void *priv,
230 struct list_head *A, struct list_head *B)
232 struct drm_i915_gem_object *a =
233 container_of(A, struct drm_i915_gem_object, obj_exec_link);
234 struct drm_i915_gem_object *b =
235 container_of(B, struct drm_i915_gem_object, obj_exec_link);
237 return a->stolen->start - b->stolen->start;
240 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
242 struct drm_info_node *node = m->private;
243 struct drm_device *dev = node->minor->dev;
244 struct drm_i915_private *dev_priv = dev->dev_private;
245 struct drm_i915_gem_object *obj;
246 size_t total_obj_size, total_gtt_size;
250 ret = mutex_lock_interruptible(&dev->struct_mutex);
254 total_obj_size = total_gtt_size = count = 0;
255 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
256 if (obj->stolen == NULL)
259 list_add(&obj->obj_exec_link, &stolen);
261 total_obj_size += obj->base.size;
262 total_gtt_size += i915_gem_obj_ggtt_size(obj);
265 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
266 if (obj->stolen == NULL)
269 list_add(&obj->obj_exec_link, &stolen);
271 total_obj_size += obj->base.size;
274 list_sort(NULL, &stolen, obj_rank_by_stolen);
275 seq_puts(m, "Stolen:\n");
276 while (!list_empty(&stolen)) {
277 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
279 describe_obj(m, obj);
281 list_del_init(&obj->obj_exec_link);
283 mutex_unlock(&dev->struct_mutex);
285 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
286 count, total_obj_size, total_gtt_size);
290 #define count_objects(list, member) do { \
291 list_for_each_entry(obj, list, member) { \
292 size += i915_gem_obj_ggtt_size(obj); \
294 if (obj->map_and_fenceable) { \
295 mappable_size += i915_gem_obj_ggtt_size(obj); \
302 struct drm_i915_file_private *file_priv;
304 size_t total, unbound;
305 size_t global, shared;
306 size_t active, inactive;
309 static int per_file_stats(int id, void *ptr, void *data)
311 struct drm_i915_gem_object *obj = ptr;
312 struct file_stats *stats = data;
313 struct i915_vma *vma;
316 stats->total += obj->base.size;
318 if (obj->base.name || obj->base.dma_buf)
319 stats->shared += obj->base.size;
321 if (USES_FULL_PPGTT(obj->base.dev)) {
322 list_for_each_entry(vma, &obj->vma_list, vma_link) {
323 struct i915_hw_ppgtt *ppgtt;
325 if (!drm_mm_node_allocated(&vma->node))
328 if (i915_is_ggtt(vma->vm)) {
329 stats->global += obj->base.size;
333 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
334 if (ppgtt->file_priv != stats->file_priv)
337 if (obj->ring) /* XXX per-vma statistic */
338 stats->active += obj->base.size;
340 stats->inactive += obj->base.size;
345 if (i915_gem_obj_ggtt_bound(obj)) {
346 stats->global += obj->base.size;
348 stats->active += obj->base.size;
350 stats->inactive += obj->base.size;
355 if (!list_empty(&obj->global_list))
356 stats->unbound += obj->base.size;
361 #define count_vmas(list, member) do { \
362 list_for_each_entry(vma, list, member) { \
363 size += i915_gem_obj_ggtt_size(vma->obj); \
365 if (vma->obj->map_and_fenceable) { \
366 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
372 static int i915_gem_object_info(struct seq_file *m, void* data)
374 struct drm_info_node *node = m->private;
375 struct drm_device *dev = node->minor->dev;
376 struct drm_i915_private *dev_priv = dev->dev_private;
377 u32 count, mappable_count, purgeable_count;
378 size_t size, mappable_size, purgeable_size;
379 struct drm_i915_gem_object *obj;
380 struct i915_address_space *vm = &dev_priv->gtt.base;
381 struct drm_file *file;
382 struct i915_vma *vma;
385 ret = mutex_lock_interruptible(&dev->struct_mutex);
389 seq_printf(m, "%u objects, %zu bytes\n",
390 dev_priv->mm.object_count,
391 dev_priv->mm.object_memory);
393 size = count = mappable_size = mappable_count = 0;
394 count_objects(&dev_priv->mm.bound_list, global_list);
395 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
396 count, mappable_count, size, mappable_size);
398 size = count = mappable_size = mappable_count = 0;
399 count_vmas(&vm->active_list, mm_list);
400 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
401 count, mappable_count, size, mappable_size);
403 size = count = mappable_size = mappable_count = 0;
404 count_vmas(&vm->inactive_list, mm_list);
405 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
406 count, mappable_count, size, mappable_size);
408 size = count = purgeable_size = purgeable_count = 0;
409 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
410 size += obj->base.size, ++count;
411 if (obj->madv == I915_MADV_DONTNEED)
412 purgeable_size += obj->base.size, ++purgeable_count;
414 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
416 size = count = mappable_size = mappable_count = 0;
417 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
418 if (obj->fault_mappable) {
419 size += i915_gem_obj_ggtt_size(obj);
422 if (obj->pin_mappable) {
423 mappable_size += i915_gem_obj_ggtt_size(obj);
426 if (obj->madv == I915_MADV_DONTNEED) {
427 purgeable_size += obj->base.size;
431 seq_printf(m, "%u purgeable objects, %zu bytes\n",
432 purgeable_count, purgeable_size);
433 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
434 mappable_count, mappable_size);
435 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
438 seq_printf(m, "%zu [%lu] gtt total\n",
439 dev_priv->gtt.base.total,
440 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
443 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
444 struct file_stats stats;
445 struct task_struct *task;
447 memset(&stats, 0, sizeof(stats));
448 stats.file_priv = file->driver_priv;
449 spin_lock(&file->table_lock);
450 idr_for_each(&file->object_idr, per_file_stats, &stats);
451 spin_unlock(&file->table_lock);
453 * Although we have a valid reference on file->pid, that does
454 * not guarantee that the task_struct who called get_pid() is
455 * still alive (e.g. get_pid(current) => fork() => exit()).
456 * Therefore, we need to protect this ->comm access using RCU.
459 task = pid_task(file->pid, PIDTYPE_PID);
460 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
461 task ? task->comm : "<unknown>",
472 mutex_unlock(&dev->struct_mutex);
477 static int i915_gem_gtt_info(struct seq_file *m, void *data)
479 struct drm_info_node *node = m->private;
480 struct drm_device *dev = node->minor->dev;
481 uintptr_t list = (uintptr_t) node->info_ent->data;
482 struct drm_i915_private *dev_priv = dev->dev_private;
483 struct drm_i915_gem_object *obj;
484 size_t total_obj_size, total_gtt_size;
487 ret = mutex_lock_interruptible(&dev->struct_mutex);
491 total_obj_size = total_gtt_size = count = 0;
492 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
493 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
497 describe_obj(m, obj);
499 total_obj_size += obj->base.size;
500 total_gtt_size += i915_gem_obj_ggtt_size(obj);
504 mutex_unlock(&dev->struct_mutex);
506 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
507 count, total_obj_size, total_gtt_size);
512 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
514 struct drm_info_node *node = m->private;
515 struct drm_device *dev = node->minor->dev;
516 struct drm_i915_private *dev_priv = dev->dev_private;
517 struct intel_crtc *crtc;
520 ret = mutex_lock_interruptible(&dev->struct_mutex);
524 for_each_intel_crtc(dev, crtc) {
525 const char pipe = pipe_name(crtc->pipe);
526 const char plane = plane_name(crtc->plane);
527 struct intel_unpin_work *work;
529 spin_lock_irq(&dev->event_lock);
530 work = crtc->unpin_work;
532 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
537 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
538 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
541 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
544 if (work->flip_queued_ring) {
545 seq_printf(m, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n",
546 work->flip_queued_ring->name,
547 work->flip_queued_seqno,
548 dev_priv->next_seqno,
549 work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
550 i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
551 work->flip_queued_seqno));
553 seq_printf(m, "Flip not associated with any ring\n");
554 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
555 work->flip_queued_vblank,
556 work->flip_ready_vblank,
557 drm_vblank_count(dev, crtc->pipe));
558 if (work->enable_stall_check)
559 seq_puts(m, "Stall check enabled, ");
561 seq_puts(m, "Stall check waiting for page flip ioctl, ");
562 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
564 if (INTEL_INFO(dev)->gen >= 4)
565 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
567 addr = I915_READ(DSPADDR(crtc->plane));
568 seq_printf(m, "Current scanout address 0x%08x\n", addr);
570 if (work->pending_flip_obj) {
571 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
572 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
575 spin_unlock_irq(&dev->event_lock);
578 mutex_unlock(&dev->struct_mutex);
583 static int i915_gem_request_info(struct seq_file *m, void *data)
585 struct drm_info_node *node = m->private;
586 struct drm_device *dev = node->minor->dev;
587 struct drm_i915_private *dev_priv = dev->dev_private;
588 struct intel_engine_cs *ring;
589 struct drm_i915_gem_request *gem_request;
592 ret = mutex_lock_interruptible(&dev->struct_mutex);
597 for_each_ring(ring, dev_priv, i) {
598 if (list_empty(&ring->request_list))
601 seq_printf(m, "%s requests:\n", ring->name);
602 list_for_each_entry(gem_request,
605 seq_printf(m, " %d @ %d\n",
607 (int) (jiffies - gem_request->emitted_jiffies));
611 mutex_unlock(&dev->struct_mutex);
614 seq_puts(m, "No requests\n");
619 static void i915_ring_seqno_info(struct seq_file *m,
620 struct intel_engine_cs *ring)
622 if (ring->get_seqno) {
623 seq_printf(m, "Current sequence (%s): %u\n",
624 ring->name, ring->get_seqno(ring, false));
628 static int i915_gem_seqno_info(struct seq_file *m, void *data)
630 struct drm_info_node *node = m->private;
631 struct drm_device *dev = node->minor->dev;
632 struct drm_i915_private *dev_priv = dev->dev_private;
633 struct intel_engine_cs *ring;
636 ret = mutex_lock_interruptible(&dev->struct_mutex);
639 intel_runtime_pm_get(dev_priv);
641 for_each_ring(ring, dev_priv, i)
642 i915_ring_seqno_info(m, ring);
644 intel_runtime_pm_put(dev_priv);
645 mutex_unlock(&dev->struct_mutex);
651 static int i915_interrupt_info(struct seq_file *m, void *data)
653 struct drm_info_node *node = m->private;
654 struct drm_device *dev = node->minor->dev;
655 struct drm_i915_private *dev_priv = dev->dev_private;
656 struct intel_engine_cs *ring;
659 ret = mutex_lock_interruptible(&dev->struct_mutex);
662 intel_runtime_pm_get(dev_priv);
664 if (IS_CHERRYVIEW(dev)) {
665 seq_printf(m, "Master Interrupt Control:\t%08x\n",
666 I915_READ(GEN8_MASTER_IRQ));
668 seq_printf(m, "Display IER:\t%08x\n",
670 seq_printf(m, "Display IIR:\t%08x\n",
672 seq_printf(m, "Display IIR_RW:\t%08x\n",
673 I915_READ(VLV_IIR_RW));
674 seq_printf(m, "Display IMR:\t%08x\n",
676 for_each_pipe(dev_priv, pipe)
677 seq_printf(m, "Pipe %c stat:\t%08x\n",
679 I915_READ(PIPESTAT(pipe)));
681 seq_printf(m, "Port hotplug:\t%08x\n",
682 I915_READ(PORT_HOTPLUG_EN));
683 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
684 I915_READ(VLV_DPFLIPSTAT));
685 seq_printf(m, "DPINVGTT:\t%08x\n",
686 I915_READ(DPINVGTT));
688 for (i = 0; i < 4; i++) {
689 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
690 i, I915_READ(GEN8_GT_IMR(i)));
691 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
692 i, I915_READ(GEN8_GT_IIR(i)));
693 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
694 i, I915_READ(GEN8_GT_IER(i)));
697 seq_printf(m, "PCU interrupt mask:\t%08x\n",
698 I915_READ(GEN8_PCU_IMR));
699 seq_printf(m, "PCU interrupt identity:\t%08x\n",
700 I915_READ(GEN8_PCU_IIR));
701 seq_printf(m, "PCU interrupt enable:\t%08x\n",
702 I915_READ(GEN8_PCU_IER));
703 } else if (INTEL_INFO(dev)->gen >= 8) {
704 seq_printf(m, "Master Interrupt Control:\t%08x\n",
705 I915_READ(GEN8_MASTER_IRQ));
707 for (i = 0; i < 4; i++) {
708 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
709 i, I915_READ(GEN8_GT_IMR(i)));
710 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
711 i, I915_READ(GEN8_GT_IIR(i)));
712 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
713 i, I915_READ(GEN8_GT_IER(i)));
716 for_each_pipe(dev_priv, pipe) {
717 if (!intel_display_power_is_enabled(dev_priv,
718 POWER_DOMAIN_PIPE(pipe))) {
719 seq_printf(m, "Pipe %c power disabled\n",
723 seq_printf(m, "Pipe %c IMR:\t%08x\n",
725 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
726 seq_printf(m, "Pipe %c IIR:\t%08x\n",
728 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
729 seq_printf(m, "Pipe %c IER:\t%08x\n",
731 I915_READ(GEN8_DE_PIPE_IER(pipe)));
734 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
735 I915_READ(GEN8_DE_PORT_IMR));
736 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
737 I915_READ(GEN8_DE_PORT_IIR));
738 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
739 I915_READ(GEN8_DE_PORT_IER));
741 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
742 I915_READ(GEN8_DE_MISC_IMR));
743 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
744 I915_READ(GEN8_DE_MISC_IIR));
745 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
746 I915_READ(GEN8_DE_MISC_IER));
748 seq_printf(m, "PCU interrupt mask:\t%08x\n",
749 I915_READ(GEN8_PCU_IMR));
750 seq_printf(m, "PCU interrupt identity:\t%08x\n",
751 I915_READ(GEN8_PCU_IIR));
752 seq_printf(m, "PCU interrupt enable:\t%08x\n",
753 I915_READ(GEN8_PCU_IER));
754 } else if (IS_VALLEYVIEW(dev)) {
755 seq_printf(m, "Display IER:\t%08x\n",
757 seq_printf(m, "Display IIR:\t%08x\n",
759 seq_printf(m, "Display IIR_RW:\t%08x\n",
760 I915_READ(VLV_IIR_RW));
761 seq_printf(m, "Display IMR:\t%08x\n",
763 for_each_pipe(dev_priv, pipe)
764 seq_printf(m, "Pipe %c stat:\t%08x\n",
766 I915_READ(PIPESTAT(pipe)));
768 seq_printf(m, "Master IER:\t%08x\n",
769 I915_READ(VLV_MASTER_IER));
771 seq_printf(m, "Render IER:\t%08x\n",
773 seq_printf(m, "Render IIR:\t%08x\n",
775 seq_printf(m, "Render IMR:\t%08x\n",
778 seq_printf(m, "PM IER:\t\t%08x\n",
779 I915_READ(GEN6_PMIER));
780 seq_printf(m, "PM IIR:\t\t%08x\n",
781 I915_READ(GEN6_PMIIR));
782 seq_printf(m, "PM IMR:\t\t%08x\n",
783 I915_READ(GEN6_PMIMR));
785 seq_printf(m, "Port hotplug:\t%08x\n",
786 I915_READ(PORT_HOTPLUG_EN));
787 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
788 I915_READ(VLV_DPFLIPSTAT));
789 seq_printf(m, "DPINVGTT:\t%08x\n",
790 I915_READ(DPINVGTT));
792 } else if (!HAS_PCH_SPLIT(dev)) {
793 seq_printf(m, "Interrupt enable: %08x\n",
795 seq_printf(m, "Interrupt identity: %08x\n",
797 seq_printf(m, "Interrupt mask: %08x\n",
799 for_each_pipe(dev_priv, pipe)
800 seq_printf(m, "Pipe %c stat: %08x\n",
802 I915_READ(PIPESTAT(pipe)));
804 seq_printf(m, "North Display Interrupt enable: %08x\n",
806 seq_printf(m, "North Display Interrupt identity: %08x\n",
808 seq_printf(m, "North Display Interrupt mask: %08x\n",
810 seq_printf(m, "South Display Interrupt enable: %08x\n",
812 seq_printf(m, "South Display Interrupt identity: %08x\n",
814 seq_printf(m, "South Display Interrupt mask: %08x\n",
816 seq_printf(m, "Graphics Interrupt enable: %08x\n",
818 seq_printf(m, "Graphics Interrupt identity: %08x\n",
820 seq_printf(m, "Graphics Interrupt mask: %08x\n",
823 for_each_ring(ring, dev_priv, i) {
824 if (INTEL_INFO(dev)->gen >= 6) {
826 "Graphics Interrupt mask (%s): %08x\n",
827 ring->name, I915_READ_IMR(ring));
829 i915_ring_seqno_info(m, ring);
831 intel_runtime_pm_put(dev_priv);
832 mutex_unlock(&dev->struct_mutex);
837 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
839 struct drm_info_node *node = m->private;
840 struct drm_device *dev = node->minor->dev;
841 struct drm_i915_private *dev_priv = dev->dev_private;
844 ret = mutex_lock_interruptible(&dev->struct_mutex);
848 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
849 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
850 for (i = 0; i < dev_priv->num_fence_regs; i++) {
851 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
853 seq_printf(m, "Fence %d, pin count = %d, object = ",
854 i, dev_priv->fence_regs[i].pin_count);
856 seq_puts(m, "unused");
858 describe_obj(m, obj);
862 mutex_unlock(&dev->struct_mutex);
866 static int i915_hws_info(struct seq_file *m, void *data)
868 struct drm_info_node *node = m->private;
869 struct drm_device *dev = node->minor->dev;
870 struct drm_i915_private *dev_priv = dev->dev_private;
871 struct intel_engine_cs *ring;
875 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
876 hws = ring->status_page.page_addr;
880 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
881 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
883 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
889 i915_error_state_write(struct file *filp,
890 const char __user *ubuf,
894 struct i915_error_state_file_priv *error_priv = filp->private_data;
895 struct drm_device *dev = error_priv->dev;
898 DRM_DEBUG_DRIVER("Resetting error state\n");
900 ret = mutex_lock_interruptible(&dev->struct_mutex);
904 i915_destroy_error_state(dev);
905 mutex_unlock(&dev->struct_mutex);
910 static int i915_error_state_open(struct inode *inode, struct file *file)
912 struct drm_device *dev = inode->i_private;
913 struct i915_error_state_file_priv *error_priv;
915 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
919 error_priv->dev = dev;
921 i915_error_state_get(dev, error_priv);
923 file->private_data = error_priv;
928 static int i915_error_state_release(struct inode *inode, struct file *file)
930 struct i915_error_state_file_priv *error_priv = file->private_data;
932 i915_error_state_put(error_priv);
938 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
939 size_t count, loff_t *pos)
941 struct i915_error_state_file_priv *error_priv = file->private_data;
942 struct drm_i915_error_state_buf error_str;
944 ssize_t ret_count = 0;
947 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
951 ret = i915_error_state_to_str(&error_str, error_priv);
955 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
962 *pos = error_str.start + ret_count;
964 i915_error_state_buf_release(&error_str);
965 return ret ?: ret_count;
968 static const struct file_operations i915_error_state_fops = {
969 .owner = THIS_MODULE,
970 .open = i915_error_state_open,
971 .read = i915_error_state_read,
972 .write = i915_error_state_write,
973 .llseek = default_llseek,
974 .release = i915_error_state_release,
978 i915_next_seqno_get(void *data, u64 *val)
980 struct drm_device *dev = data;
981 struct drm_i915_private *dev_priv = dev->dev_private;
984 ret = mutex_lock_interruptible(&dev->struct_mutex);
988 *val = dev_priv->next_seqno;
989 mutex_unlock(&dev->struct_mutex);
995 i915_next_seqno_set(void *data, u64 val)
997 struct drm_device *dev = data;
1000 ret = mutex_lock_interruptible(&dev->struct_mutex);
1004 ret = i915_gem_set_seqno(dev, val);
1005 mutex_unlock(&dev->struct_mutex);
1010 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1011 i915_next_seqno_get, i915_next_seqno_set,
1014 static int i915_frequency_info(struct seq_file *m, void *unused)
1016 struct drm_info_node *node = m->private;
1017 struct drm_device *dev = node->minor->dev;
1018 struct drm_i915_private *dev_priv = dev->dev_private;
1021 intel_runtime_pm_get(dev_priv);
1023 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1026 u16 rgvswctl = I915_READ16(MEMSWCTL);
1027 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1029 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1030 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1031 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1033 seq_printf(m, "Current P-state: %d\n",
1034 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1035 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1036 IS_BROADWELL(dev)) {
1037 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1038 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1039 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1040 u32 rpmodectl, rpinclimit, rpdeclimit;
1041 u32 rpstat, cagf, reqf;
1042 u32 rpupei, rpcurup, rpprevup;
1043 u32 rpdownei, rpcurdown, rpprevdown;
1044 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1047 /* RPSTAT1 is in the GT power well */
1048 ret = mutex_lock_interruptible(&dev->struct_mutex);
1052 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
1054 reqf = I915_READ(GEN6_RPNSWREQ);
1055 reqf &= ~GEN6_TURBO_DISABLE;
1056 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1060 reqf *= GT_FREQUENCY_MULTIPLIER;
1062 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1063 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1064 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1066 rpstat = I915_READ(GEN6_RPSTAT1);
1067 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1068 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1069 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1070 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1071 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1072 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1073 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1074 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1076 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1077 cagf *= GT_FREQUENCY_MULTIPLIER;
1079 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
1080 mutex_unlock(&dev->struct_mutex);
1082 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1083 pm_ier = I915_READ(GEN6_PMIER);
1084 pm_imr = I915_READ(GEN6_PMIMR);
1085 pm_isr = I915_READ(GEN6_PMISR);
1086 pm_iir = I915_READ(GEN6_PMIIR);
1087 pm_mask = I915_READ(GEN6_PMINTRMSK);
1089 pm_ier = I915_READ(GEN8_GT_IER(2));
1090 pm_imr = I915_READ(GEN8_GT_IMR(2));
1091 pm_isr = I915_READ(GEN8_GT_ISR(2));
1092 pm_iir = I915_READ(GEN8_GT_IIR(2));
1093 pm_mask = I915_READ(GEN6_PMINTRMSK);
1095 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1096 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1097 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1098 seq_printf(m, "Render p-state ratio: %d\n",
1099 (gt_perf_status & 0xff00) >> 8);
1100 seq_printf(m, "Render p-state VID: %d\n",
1101 gt_perf_status & 0xff);
1102 seq_printf(m, "Render p-state limit: %d\n",
1103 rp_state_limits & 0xff);
1104 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1105 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1106 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1107 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1108 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1109 seq_printf(m, "CAGF: %dMHz\n", cagf);
1110 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1111 GEN6_CURICONT_MASK);
1112 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1113 GEN6_CURBSYTAVG_MASK);
1114 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1115 GEN6_CURBSYTAVG_MASK);
1116 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1118 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1119 GEN6_CURBSYTAVG_MASK);
1120 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1121 GEN6_CURBSYTAVG_MASK);
1123 max_freq = (rp_state_cap & 0xff0000) >> 16;
1124 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1125 max_freq * GT_FREQUENCY_MULTIPLIER);
1127 max_freq = (rp_state_cap & 0xff00) >> 8;
1128 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1129 max_freq * GT_FREQUENCY_MULTIPLIER);
1131 max_freq = rp_state_cap & 0xff;
1132 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1133 max_freq * GT_FREQUENCY_MULTIPLIER);
1135 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1136 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
1137 } else if (IS_VALLEYVIEW(dev)) {
1140 mutex_lock(&dev_priv->rps.hw_lock);
1141 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1142 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1143 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1145 seq_printf(m, "max GPU freq: %d MHz\n",
1146 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1148 seq_printf(m, "min GPU freq: %d MHz\n",
1149 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1151 seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
1152 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1154 seq_printf(m, "current GPU freq: %d MHz\n",
1155 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1156 mutex_unlock(&dev_priv->rps.hw_lock);
1158 seq_puts(m, "no P-state info available\n");
1162 intel_runtime_pm_put(dev_priv);
1166 static int ironlake_drpc_info(struct seq_file *m)
1168 struct drm_info_node *node = m->private;
1169 struct drm_device *dev = node->minor->dev;
1170 struct drm_i915_private *dev_priv = dev->dev_private;
1171 u32 rgvmodectl, rstdbyctl;
1175 ret = mutex_lock_interruptible(&dev->struct_mutex);
1178 intel_runtime_pm_get(dev_priv);
1180 rgvmodectl = I915_READ(MEMMODECTL);
1181 rstdbyctl = I915_READ(RSTDBYCTL);
1182 crstandvid = I915_READ16(CRSTANDVID);
1184 intel_runtime_pm_put(dev_priv);
1185 mutex_unlock(&dev->struct_mutex);
1187 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1189 seq_printf(m, "Boost freq: %d\n",
1190 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1191 MEMMODE_BOOST_FREQ_SHIFT);
1192 seq_printf(m, "HW control enabled: %s\n",
1193 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1194 seq_printf(m, "SW control enabled: %s\n",
1195 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1196 seq_printf(m, "Gated voltage change: %s\n",
1197 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1198 seq_printf(m, "Starting frequency: P%d\n",
1199 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1200 seq_printf(m, "Max P-state: P%d\n",
1201 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1202 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1203 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1204 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1205 seq_printf(m, "Render standby enabled: %s\n",
1206 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1207 seq_puts(m, "Current RS state: ");
1208 switch (rstdbyctl & RSX_STATUS_MASK) {
1210 seq_puts(m, "on\n");
1212 case RSX_STATUS_RC1:
1213 seq_puts(m, "RC1\n");
1215 case RSX_STATUS_RC1E:
1216 seq_puts(m, "RC1E\n");
1218 case RSX_STATUS_RS1:
1219 seq_puts(m, "RS1\n");
1221 case RSX_STATUS_RS2:
1222 seq_puts(m, "RS2 (RC6)\n");
1224 case RSX_STATUS_RS3:
1225 seq_puts(m, "RC3 (RC6+)\n");
1228 seq_puts(m, "unknown\n");
1235 static int vlv_drpc_info(struct seq_file *m)
1238 struct drm_info_node *node = m->private;
1239 struct drm_device *dev = node->minor->dev;
1240 struct drm_i915_private *dev_priv = dev->dev_private;
1241 u32 rpmodectl1, rcctl1, pw_status;
1242 unsigned fw_rendercount = 0, fw_mediacount = 0;
1244 intel_runtime_pm_get(dev_priv);
1246 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1247 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1248 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1250 intel_runtime_pm_put(dev_priv);
1252 seq_printf(m, "Video Turbo Mode: %s\n",
1253 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1254 seq_printf(m, "Turbo enabled: %s\n",
1255 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1256 seq_printf(m, "HW control enabled: %s\n",
1257 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1258 seq_printf(m, "SW control enabled: %s\n",
1259 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1260 GEN6_RP_MEDIA_SW_MODE));
1261 seq_printf(m, "RC6 Enabled: %s\n",
1262 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1263 GEN6_RC_CTL_EI_MODE(1))));
1264 seq_printf(m, "Render Power Well: %s\n",
1265 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1266 seq_printf(m, "Media Power Well: %s\n",
1267 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1269 seq_printf(m, "Render RC6 residency since boot: %u\n",
1270 I915_READ(VLV_GT_RENDER_RC6));
1271 seq_printf(m, "Media RC6 residency since boot: %u\n",
1272 I915_READ(VLV_GT_MEDIA_RC6));
1274 spin_lock_irq(&dev_priv->uncore.lock);
1275 fw_rendercount = dev_priv->uncore.fw_rendercount;
1276 fw_mediacount = dev_priv->uncore.fw_mediacount;
1277 spin_unlock_irq(&dev_priv->uncore.lock);
1279 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1280 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1287 static int gen6_drpc_info(struct seq_file *m)
1290 struct drm_info_node *node = m->private;
1291 struct drm_device *dev = node->minor->dev;
1292 struct drm_i915_private *dev_priv = dev->dev_private;
1293 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1294 unsigned forcewake_count;
1297 ret = mutex_lock_interruptible(&dev->struct_mutex);
1300 intel_runtime_pm_get(dev_priv);
1302 spin_lock_irq(&dev_priv->uncore.lock);
1303 forcewake_count = dev_priv->uncore.forcewake_count;
1304 spin_unlock_irq(&dev_priv->uncore.lock);
1306 if (forcewake_count) {
1307 seq_puts(m, "RC information inaccurate because somebody "
1308 "holds a forcewake reference \n");
1310 /* NB: we cannot use forcewake, else we read the wrong values */
1311 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1313 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1316 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1317 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1319 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1320 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1321 mutex_unlock(&dev->struct_mutex);
1322 mutex_lock(&dev_priv->rps.hw_lock);
1323 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1324 mutex_unlock(&dev_priv->rps.hw_lock);
1326 intel_runtime_pm_put(dev_priv);
1328 seq_printf(m, "Video Turbo Mode: %s\n",
1329 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1330 seq_printf(m, "HW control enabled: %s\n",
1331 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1332 seq_printf(m, "SW control enabled: %s\n",
1333 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1334 GEN6_RP_MEDIA_SW_MODE));
1335 seq_printf(m, "RC1e Enabled: %s\n",
1336 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1337 seq_printf(m, "RC6 Enabled: %s\n",
1338 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1339 seq_printf(m, "Deep RC6 Enabled: %s\n",
1340 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1341 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1342 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1343 seq_puts(m, "Current RC state: ");
1344 switch (gt_core_status & GEN6_RCn_MASK) {
1346 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1347 seq_puts(m, "Core Power Down\n");
1349 seq_puts(m, "on\n");
1352 seq_puts(m, "RC3\n");
1355 seq_puts(m, "RC6\n");
1358 seq_puts(m, "RC7\n");
1361 seq_puts(m, "Unknown\n");
1365 seq_printf(m, "Core Power Down: %s\n",
1366 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1368 /* Not exactly sure what this is */
1369 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1370 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1371 seq_printf(m, "RC6 residency since boot: %u\n",
1372 I915_READ(GEN6_GT_GFX_RC6));
1373 seq_printf(m, "RC6+ residency since boot: %u\n",
1374 I915_READ(GEN6_GT_GFX_RC6p));
1375 seq_printf(m, "RC6++ residency since boot: %u\n",
1376 I915_READ(GEN6_GT_GFX_RC6pp));
1378 seq_printf(m, "RC6 voltage: %dmV\n",
1379 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1380 seq_printf(m, "RC6+ voltage: %dmV\n",
1381 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1382 seq_printf(m, "RC6++ voltage: %dmV\n",
1383 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1387 static int i915_drpc_info(struct seq_file *m, void *unused)
1389 struct drm_info_node *node = m->private;
1390 struct drm_device *dev = node->minor->dev;
1392 if (IS_VALLEYVIEW(dev))
1393 return vlv_drpc_info(m);
1394 else if (INTEL_INFO(dev)->gen >= 6)
1395 return gen6_drpc_info(m);
1397 return ironlake_drpc_info(m);
1400 static int i915_fbc_status(struct seq_file *m, void *unused)
1402 struct drm_info_node *node = m->private;
1403 struct drm_device *dev = node->minor->dev;
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1406 if (!HAS_FBC(dev)) {
1407 seq_puts(m, "FBC unsupported on this chipset\n");
1411 intel_runtime_pm_get(dev_priv);
1413 if (intel_fbc_enabled(dev)) {
1414 seq_puts(m, "FBC enabled\n");
1416 seq_puts(m, "FBC disabled: ");
1417 switch (dev_priv->fbc.no_fbc_reason) {
1419 seq_puts(m, "FBC actived, but currently disabled in hardware");
1421 case FBC_UNSUPPORTED:
1422 seq_puts(m, "unsupported by this chipset");
1425 seq_puts(m, "no outputs");
1427 case FBC_STOLEN_TOO_SMALL:
1428 seq_puts(m, "not enough stolen memory");
1430 case FBC_UNSUPPORTED_MODE:
1431 seq_puts(m, "mode not supported");
1433 case FBC_MODE_TOO_LARGE:
1434 seq_puts(m, "mode too large");
1437 seq_puts(m, "FBC unsupported on plane");
1440 seq_puts(m, "scanout buffer not tiled");
1442 case FBC_MULTIPLE_PIPES:
1443 seq_puts(m, "multiple pipes are enabled");
1445 case FBC_MODULE_PARAM:
1446 seq_puts(m, "disabled per module param (default off)");
1448 case FBC_CHIP_DEFAULT:
1449 seq_puts(m, "disabled per chip default");
1452 seq_puts(m, "unknown reason");
1457 intel_runtime_pm_put(dev_priv);
1462 static int i915_fbc_fc_get(void *data, u64 *val)
1464 struct drm_device *dev = data;
1465 struct drm_i915_private *dev_priv = dev->dev_private;
1467 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1470 drm_modeset_lock_all(dev);
1471 *val = dev_priv->fbc.false_color;
1472 drm_modeset_unlock_all(dev);
1477 static int i915_fbc_fc_set(void *data, u64 val)
1479 struct drm_device *dev = data;
1480 struct drm_i915_private *dev_priv = dev->dev_private;
1483 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1486 drm_modeset_lock_all(dev);
1488 reg = I915_READ(ILK_DPFC_CONTROL);
1489 dev_priv->fbc.false_color = val;
1491 I915_WRITE(ILK_DPFC_CONTROL, val ?
1492 (reg | FBC_CTL_FALSE_COLOR) :
1493 (reg & ~FBC_CTL_FALSE_COLOR));
1495 drm_modeset_unlock_all(dev);
1499 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1500 i915_fbc_fc_get, i915_fbc_fc_set,
1503 static int i915_ips_status(struct seq_file *m, void *unused)
1505 struct drm_info_node *node = m->private;
1506 struct drm_device *dev = node->minor->dev;
1507 struct drm_i915_private *dev_priv = dev->dev_private;
1509 if (!HAS_IPS(dev)) {
1510 seq_puts(m, "not supported\n");
1514 intel_runtime_pm_get(dev_priv);
1516 seq_printf(m, "Enabled by kernel parameter: %s\n",
1517 yesno(i915.enable_ips));
1519 if (INTEL_INFO(dev)->gen >= 8) {
1520 seq_puts(m, "Currently: unknown\n");
1522 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1523 seq_puts(m, "Currently: enabled\n");
1525 seq_puts(m, "Currently: disabled\n");
1528 intel_runtime_pm_put(dev_priv);
1533 static int i915_sr_status(struct seq_file *m, void *unused)
1535 struct drm_info_node *node = m->private;
1536 struct drm_device *dev = node->minor->dev;
1537 struct drm_i915_private *dev_priv = dev->dev_private;
1538 bool sr_enabled = false;
1540 intel_runtime_pm_get(dev_priv);
1542 if (HAS_PCH_SPLIT(dev))
1543 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1544 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1545 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1546 else if (IS_I915GM(dev))
1547 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1548 else if (IS_PINEVIEW(dev))
1549 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1551 intel_runtime_pm_put(dev_priv);
1553 seq_printf(m, "self-refresh: %s\n",
1554 sr_enabled ? "enabled" : "disabled");
1559 static int i915_emon_status(struct seq_file *m, void *unused)
1561 struct drm_info_node *node = m->private;
1562 struct drm_device *dev = node->minor->dev;
1563 struct drm_i915_private *dev_priv = dev->dev_private;
1564 unsigned long temp, chipset, gfx;
1570 ret = mutex_lock_interruptible(&dev->struct_mutex);
1574 temp = i915_mch_val(dev_priv);
1575 chipset = i915_chipset_val(dev_priv);
1576 gfx = i915_gfx_val(dev_priv);
1577 mutex_unlock(&dev->struct_mutex);
1579 seq_printf(m, "GMCH temp: %ld\n", temp);
1580 seq_printf(m, "Chipset power: %ld\n", chipset);
1581 seq_printf(m, "GFX power: %ld\n", gfx);
1582 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1587 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1589 struct drm_info_node *node = m->private;
1590 struct drm_device *dev = node->minor->dev;
1591 struct drm_i915_private *dev_priv = dev->dev_private;
1593 int gpu_freq, ia_freq;
1595 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1596 seq_puts(m, "unsupported on this chipset\n");
1600 intel_runtime_pm_get(dev_priv);
1602 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1604 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1608 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1610 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1611 gpu_freq <= dev_priv->rps.max_freq_softlimit;
1614 sandybridge_pcode_read(dev_priv,
1615 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1617 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1618 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1619 ((ia_freq >> 0) & 0xff) * 100,
1620 ((ia_freq >> 8) & 0xff) * 100);
1623 mutex_unlock(&dev_priv->rps.hw_lock);
1626 intel_runtime_pm_put(dev_priv);
1630 static int i915_opregion(struct seq_file *m, void *unused)
1632 struct drm_info_node *node = m->private;
1633 struct drm_device *dev = node->minor->dev;
1634 struct drm_i915_private *dev_priv = dev->dev_private;
1635 struct intel_opregion *opregion = &dev_priv->opregion;
1636 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1642 ret = mutex_lock_interruptible(&dev->struct_mutex);
1646 if (opregion->header) {
1647 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1648 seq_write(m, data, OPREGION_SIZE);
1651 mutex_unlock(&dev->struct_mutex);
1658 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1660 struct drm_info_node *node = m->private;
1661 struct drm_device *dev = node->minor->dev;
1662 struct intel_fbdev *ifbdev = NULL;
1663 struct intel_framebuffer *fb;
1665 #ifdef CONFIG_DRM_I915_FBDEV
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1668 ifbdev = dev_priv->fbdev;
1669 fb = to_intel_framebuffer(ifbdev->helper.fb);
1671 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1675 fb->base.bits_per_pixel,
1676 atomic_read(&fb->base.refcount.refcount));
1677 describe_obj(m, fb->obj);
1681 mutex_lock(&dev->mode_config.fb_lock);
1682 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1683 if (ifbdev && &fb->base == ifbdev->helper.fb)
1686 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1690 fb->base.bits_per_pixel,
1691 atomic_read(&fb->base.refcount.refcount));
1692 describe_obj(m, fb->obj);
1695 mutex_unlock(&dev->mode_config.fb_lock);
1700 static void describe_ctx_ringbuf(struct seq_file *m,
1701 struct intel_ringbuffer *ringbuf)
1703 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1704 ringbuf->space, ringbuf->head, ringbuf->tail,
1705 ringbuf->last_retired_head);
1708 static int i915_context_status(struct seq_file *m, void *unused)
1710 struct drm_info_node *node = m->private;
1711 struct drm_device *dev = node->minor->dev;
1712 struct drm_i915_private *dev_priv = dev->dev_private;
1713 struct intel_engine_cs *ring;
1714 struct intel_context *ctx;
1717 ret = mutex_lock_interruptible(&dev->struct_mutex);
1721 if (dev_priv->ips.pwrctx) {
1722 seq_puts(m, "power context ");
1723 describe_obj(m, dev_priv->ips.pwrctx);
1727 if (dev_priv->ips.renderctx) {
1728 seq_puts(m, "render context ");
1729 describe_obj(m, dev_priv->ips.renderctx);
1733 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1734 if (!i915.enable_execlists &&
1735 ctx->legacy_hw_ctx.rcs_state == NULL)
1738 seq_puts(m, "HW context ");
1739 describe_ctx(m, ctx);
1740 for_each_ring(ring, dev_priv, i) {
1741 if (ring->default_context == ctx)
1742 seq_printf(m, "(default context %s) ",
1746 if (i915.enable_execlists) {
1748 for_each_ring(ring, dev_priv, i) {
1749 struct drm_i915_gem_object *ctx_obj =
1750 ctx->engine[i].state;
1751 struct intel_ringbuffer *ringbuf =
1752 ctx->engine[i].ringbuf;
1754 seq_printf(m, "%s: ", ring->name);
1756 describe_obj(m, ctx_obj);
1758 describe_ctx_ringbuf(m, ringbuf);
1762 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1768 mutex_unlock(&dev->struct_mutex);
1773 static void i915_dump_lrc_obj(struct seq_file *m,
1774 struct intel_engine_cs *ring,
1775 struct drm_i915_gem_object *ctx_obj)
1778 uint32_t *reg_state;
1780 unsigned long ggtt_offset = 0;
1782 if (ctx_obj == NULL) {
1783 seq_printf(m, "Context on %s with no gem object\n",
1788 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1789 intel_execlists_ctx_id(ctx_obj));
1791 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1792 seq_puts(m, "\tNot bound in GGTT\n");
1794 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1796 if (i915_gem_object_get_pages(ctx_obj)) {
1797 seq_puts(m, "\tFailed to get pages for context object\n");
1801 page = i915_gem_object_get_page(ctx_obj, 1);
1802 if (!WARN_ON(page == NULL)) {
1803 reg_state = kmap_atomic(page);
1805 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1806 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1807 ggtt_offset + 4096 + (j * 4),
1808 reg_state[j], reg_state[j + 1],
1809 reg_state[j + 2], reg_state[j + 3]);
1811 kunmap_atomic(reg_state);
1817 static int i915_dump_lrc(struct seq_file *m, void *unused)
1819 struct drm_info_node *node = (struct drm_info_node *) m->private;
1820 struct drm_device *dev = node->minor->dev;
1821 struct drm_i915_private *dev_priv = dev->dev_private;
1822 struct intel_engine_cs *ring;
1823 struct intel_context *ctx;
1826 if (!i915.enable_execlists) {
1827 seq_printf(m, "Logical Ring Contexts are disabled\n");
1831 ret = mutex_lock_interruptible(&dev->struct_mutex);
1835 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1836 for_each_ring(ring, dev_priv, i) {
1837 if (ring->default_context != ctx)
1838 i915_dump_lrc_obj(m, ring,
1839 ctx->engine[i].state);
1843 mutex_unlock(&dev->struct_mutex);
1848 static int i915_execlists(struct seq_file *m, void *data)
1850 struct drm_info_node *node = (struct drm_info_node *)m->private;
1851 struct drm_device *dev = node->minor->dev;
1852 struct drm_i915_private *dev_priv = dev->dev_private;
1853 struct intel_engine_cs *ring;
1859 struct list_head *cursor;
1863 if (!i915.enable_execlists) {
1864 seq_puts(m, "Logical Ring Contexts are disabled\n");
1868 ret = mutex_lock_interruptible(&dev->struct_mutex);
1872 intel_runtime_pm_get(dev_priv);
1874 for_each_ring(ring, dev_priv, ring_id) {
1875 struct intel_ctx_submit_request *head_req = NULL;
1877 unsigned long flags;
1879 seq_printf(m, "%s\n", ring->name);
1881 status = I915_READ(RING_EXECLIST_STATUS(ring));
1882 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1883 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1886 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
1887 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
1889 read_pointer = ring->next_context_status_buffer;
1890 write_pointer = status_pointer & 0x07;
1891 if (read_pointer > write_pointer)
1893 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1894 read_pointer, write_pointer);
1896 for (i = 0; i < 6; i++) {
1897 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
1898 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
1900 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
1904 spin_lock_irqsave(&ring->execlist_lock, flags);
1905 list_for_each(cursor, &ring->execlist_queue)
1907 head_req = list_first_entry_or_null(&ring->execlist_queue,
1908 struct intel_ctx_submit_request, execlist_link);
1909 spin_unlock_irqrestore(&ring->execlist_lock, flags);
1911 seq_printf(m, "\t%d requests in queue\n", count);
1913 struct drm_i915_gem_object *ctx_obj;
1915 ctx_obj = head_req->ctx->engine[ring_id].state;
1916 seq_printf(m, "\tHead request id: %u\n",
1917 intel_execlists_ctx_id(ctx_obj));
1918 seq_printf(m, "\tHead request tail: %u\n",
1925 intel_runtime_pm_put(dev_priv);
1926 mutex_unlock(&dev->struct_mutex);
1931 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1933 struct drm_info_node *node = m->private;
1934 struct drm_device *dev = node->minor->dev;
1935 struct drm_i915_private *dev_priv = dev->dev_private;
1936 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
1938 spin_lock_irq(&dev_priv->uncore.lock);
1939 if (IS_VALLEYVIEW(dev)) {
1940 fw_rendercount = dev_priv->uncore.fw_rendercount;
1941 fw_mediacount = dev_priv->uncore.fw_mediacount;
1943 forcewake_count = dev_priv->uncore.forcewake_count;
1944 spin_unlock_irq(&dev_priv->uncore.lock);
1946 if (IS_VALLEYVIEW(dev)) {
1947 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1948 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1950 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1955 static const char *swizzle_string(unsigned swizzle)
1958 case I915_BIT_6_SWIZZLE_NONE:
1960 case I915_BIT_6_SWIZZLE_9:
1962 case I915_BIT_6_SWIZZLE_9_10:
1963 return "bit9/bit10";
1964 case I915_BIT_6_SWIZZLE_9_11:
1965 return "bit9/bit11";
1966 case I915_BIT_6_SWIZZLE_9_10_11:
1967 return "bit9/bit10/bit11";
1968 case I915_BIT_6_SWIZZLE_9_17:
1969 return "bit9/bit17";
1970 case I915_BIT_6_SWIZZLE_9_10_17:
1971 return "bit9/bit10/bit17";
1972 case I915_BIT_6_SWIZZLE_UNKNOWN:
1979 static int i915_swizzle_info(struct seq_file *m, void *data)
1981 struct drm_info_node *node = m->private;
1982 struct drm_device *dev = node->minor->dev;
1983 struct drm_i915_private *dev_priv = dev->dev_private;
1986 ret = mutex_lock_interruptible(&dev->struct_mutex);
1989 intel_runtime_pm_get(dev_priv);
1991 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1992 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1993 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1994 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1996 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1997 seq_printf(m, "DDC = 0x%08x\n",
1999 seq_printf(m, "DDC2 = 0x%08x\n",
2001 seq_printf(m, "C0DRB3 = 0x%04x\n",
2002 I915_READ16(C0DRB3));
2003 seq_printf(m, "C1DRB3 = 0x%04x\n",
2004 I915_READ16(C1DRB3));
2005 } else if (INTEL_INFO(dev)->gen >= 6) {
2006 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2007 I915_READ(MAD_DIMM_C0));
2008 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2009 I915_READ(MAD_DIMM_C1));
2010 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2011 I915_READ(MAD_DIMM_C2));
2012 seq_printf(m, "TILECTL = 0x%08x\n",
2013 I915_READ(TILECTL));
2014 if (INTEL_INFO(dev)->gen >= 8)
2015 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2016 I915_READ(GAMTARBMODE));
2018 seq_printf(m, "ARB_MODE = 0x%08x\n",
2019 I915_READ(ARB_MODE));
2020 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2021 I915_READ(DISP_ARB_CTL));
2024 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2025 seq_puts(m, "L-shaped memory detected\n");
2027 intel_runtime_pm_put(dev_priv);
2028 mutex_unlock(&dev->struct_mutex);
2033 static int per_file_ctx(int id, void *ptr, void *data)
2035 struct intel_context *ctx = ptr;
2036 struct seq_file *m = data;
2037 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2040 seq_printf(m, " no ppgtt for context %d\n",
2045 if (i915_gem_context_is_default(ctx))
2046 seq_puts(m, " default context:\n");
2048 seq_printf(m, " context %d:\n", ctx->user_handle);
2049 ppgtt->debug_dump(ppgtt, m);
2054 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2056 struct drm_i915_private *dev_priv = dev->dev_private;
2057 struct intel_engine_cs *ring;
2058 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2064 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
2065 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
2066 for_each_ring(ring, dev_priv, unused) {
2067 seq_printf(m, "%s\n", ring->name);
2068 for (i = 0; i < 4; i++) {
2069 u32 offset = 0x270 + i * 8;
2070 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2072 pdp |= I915_READ(ring->mmio_base + offset);
2073 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2078 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2080 struct drm_i915_private *dev_priv = dev->dev_private;
2081 struct intel_engine_cs *ring;
2082 struct drm_file *file;
2085 if (INTEL_INFO(dev)->gen == 6)
2086 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2088 for_each_ring(ring, dev_priv, i) {
2089 seq_printf(m, "%s\n", ring->name);
2090 if (INTEL_INFO(dev)->gen == 7)
2091 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2092 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2093 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2094 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2096 if (dev_priv->mm.aliasing_ppgtt) {
2097 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2099 seq_puts(m, "aliasing PPGTT:\n");
2100 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
2102 ppgtt->debug_dump(ppgtt, m);
2105 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2106 struct drm_i915_file_private *file_priv = file->driver_priv;
2108 seq_printf(m, "proc: %s\n",
2109 get_pid_task(file->pid, PIDTYPE_PID)->comm);
2110 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
2112 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2115 static int i915_ppgtt_info(struct seq_file *m, void *data)
2117 struct drm_info_node *node = m->private;
2118 struct drm_device *dev = node->minor->dev;
2119 struct drm_i915_private *dev_priv = dev->dev_private;
2121 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2124 intel_runtime_pm_get(dev_priv);
2126 if (INTEL_INFO(dev)->gen >= 8)
2127 gen8_ppgtt_info(m, dev);
2128 else if (INTEL_INFO(dev)->gen >= 6)
2129 gen6_ppgtt_info(m, dev);
2131 intel_runtime_pm_put(dev_priv);
2132 mutex_unlock(&dev->struct_mutex);
2137 static int i915_llc(struct seq_file *m, void *data)
2139 struct drm_info_node *node = m->private;
2140 struct drm_device *dev = node->minor->dev;
2141 struct drm_i915_private *dev_priv = dev->dev_private;
2143 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2144 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2145 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2150 static int i915_edp_psr_status(struct seq_file *m, void *data)
2152 struct drm_info_node *node = m->private;
2153 struct drm_device *dev = node->minor->dev;
2154 struct drm_i915_private *dev_priv = dev->dev_private;
2158 bool enabled = false;
2160 intel_runtime_pm_get(dev_priv);
2162 mutex_lock(&dev_priv->psr.lock);
2163 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2164 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2165 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2166 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2167 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2168 dev_priv->psr.busy_frontbuffer_bits);
2169 seq_printf(m, "Re-enable work scheduled: %s\n",
2170 yesno(work_busy(&dev_priv->psr.work.work)));
2174 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2176 for_each_pipe(dev_priv, pipe) {
2177 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2178 VLV_EDP_PSR_CURR_STATE_MASK;
2179 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2180 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2185 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2188 for_each_pipe(dev_priv, pipe) {
2189 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2190 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2191 seq_printf(m, " pipe %c", pipe_name(pipe));
2195 /* CHV PSR has no kind of performance counter */
2196 if (HAS_PSR(dev) && HAS_DDI(dev)) {
2197 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2198 EDP_PSR_PERF_CNT_MASK;
2200 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2202 mutex_unlock(&dev_priv->psr.lock);
2204 intel_runtime_pm_put(dev_priv);
2208 static int i915_sink_crc(struct seq_file *m, void *data)
2210 struct drm_info_node *node = m->private;
2211 struct drm_device *dev = node->minor->dev;
2212 struct intel_encoder *encoder;
2213 struct intel_connector *connector;
2214 struct intel_dp *intel_dp = NULL;
2218 drm_modeset_lock_all(dev);
2219 list_for_each_entry(connector, &dev->mode_config.connector_list,
2222 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2225 if (!connector->base.encoder)
2228 encoder = to_intel_encoder(connector->base.encoder);
2229 if (encoder->type != INTEL_OUTPUT_EDP)
2232 intel_dp = enc_to_intel_dp(&encoder->base);
2234 ret = intel_dp_sink_crc(intel_dp, crc);
2238 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2239 crc[0], crc[1], crc[2],
2240 crc[3], crc[4], crc[5]);
2245 drm_modeset_unlock_all(dev);
2249 static int i915_energy_uJ(struct seq_file *m, void *data)
2251 struct drm_info_node *node = m->private;
2252 struct drm_device *dev = node->minor->dev;
2253 struct drm_i915_private *dev_priv = dev->dev_private;
2257 if (INTEL_INFO(dev)->gen < 6)
2260 intel_runtime_pm_get(dev_priv);
2262 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2263 power = (power & 0x1f00) >> 8;
2264 units = 1000000 / (1 << power); /* convert to uJ */
2265 power = I915_READ(MCH_SECP_NRG_STTS);
2268 intel_runtime_pm_put(dev_priv);
2270 seq_printf(m, "%llu", (long long unsigned)power);
2275 static int i915_pc8_status(struct seq_file *m, void *unused)
2277 struct drm_info_node *node = m->private;
2278 struct drm_device *dev = node->minor->dev;
2279 struct drm_i915_private *dev_priv = dev->dev_private;
2281 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2282 seq_puts(m, "not supported\n");
2286 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2287 seq_printf(m, "IRQs disabled: %s\n",
2288 yesno(!intel_irqs_enabled(dev_priv)));
2293 static const char *power_domain_str(enum intel_display_power_domain domain)
2296 case POWER_DOMAIN_PIPE_A:
2298 case POWER_DOMAIN_PIPE_B:
2300 case POWER_DOMAIN_PIPE_C:
2302 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2303 return "PIPE_A_PANEL_FITTER";
2304 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2305 return "PIPE_B_PANEL_FITTER";
2306 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2307 return "PIPE_C_PANEL_FITTER";
2308 case POWER_DOMAIN_TRANSCODER_A:
2309 return "TRANSCODER_A";
2310 case POWER_DOMAIN_TRANSCODER_B:
2311 return "TRANSCODER_B";
2312 case POWER_DOMAIN_TRANSCODER_C:
2313 return "TRANSCODER_C";
2314 case POWER_DOMAIN_TRANSCODER_EDP:
2315 return "TRANSCODER_EDP";
2316 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2317 return "PORT_DDI_A_2_LANES";
2318 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2319 return "PORT_DDI_A_4_LANES";
2320 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2321 return "PORT_DDI_B_2_LANES";
2322 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2323 return "PORT_DDI_B_4_LANES";
2324 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2325 return "PORT_DDI_C_2_LANES";
2326 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2327 return "PORT_DDI_C_4_LANES";
2328 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2329 return "PORT_DDI_D_2_LANES";
2330 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2331 return "PORT_DDI_D_4_LANES";
2332 case POWER_DOMAIN_PORT_DSI:
2334 case POWER_DOMAIN_PORT_CRT:
2336 case POWER_DOMAIN_PORT_OTHER:
2337 return "PORT_OTHER";
2338 case POWER_DOMAIN_VGA:
2340 case POWER_DOMAIN_AUDIO:
2342 case POWER_DOMAIN_PLLS:
2344 case POWER_DOMAIN_INIT:
2352 static int i915_power_domain_info(struct seq_file *m, void *unused)
2354 struct drm_info_node *node = m->private;
2355 struct drm_device *dev = node->minor->dev;
2356 struct drm_i915_private *dev_priv = dev->dev_private;
2357 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2360 mutex_lock(&power_domains->lock);
2362 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2363 for (i = 0; i < power_domains->power_well_count; i++) {
2364 struct i915_power_well *power_well;
2365 enum intel_display_power_domain power_domain;
2367 power_well = &power_domains->power_wells[i];
2368 seq_printf(m, "%-25s %d\n", power_well->name,
2371 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2373 if (!(BIT(power_domain) & power_well->domains))
2376 seq_printf(m, " %-23s %d\n",
2377 power_domain_str(power_domain),
2378 power_domains->domain_use_count[power_domain]);
2382 mutex_unlock(&power_domains->lock);
2387 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2388 struct drm_display_mode *mode)
2392 for (i = 0; i < tabs; i++)
2395 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2396 mode->base.id, mode->name,
2397 mode->vrefresh, mode->clock,
2398 mode->hdisplay, mode->hsync_start,
2399 mode->hsync_end, mode->htotal,
2400 mode->vdisplay, mode->vsync_start,
2401 mode->vsync_end, mode->vtotal,
2402 mode->type, mode->flags);
2405 static void intel_encoder_info(struct seq_file *m,
2406 struct intel_crtc *intel_crtc,
2407 struct intel_encoder *intel_encoder)
2409 struct drm_info_node *node = m->private;
2410 struct drm_device *dev = node->minor->dev;
2411 struct drm_crtc *crtc = &intel_crtc->base;
2412 struct intel_connector *intel_connector;
2413 struct drm_encoder *encoder;
2415 encoder = &intel_encoder->base;
2416 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2417 encoder->base.id, encoder->name);
2418 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2419 struct drm_connector *connector = &intel_connector->base;
2420 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2423 drm_get_connector_status_name(connector->status));
2424 if (connector->status == connector_status_connected) {
2425 struct drm_display_mode *mode = &crtc->mode;
2426 seq_printf(m, ", mode:\n");
2427 intel_seq_print_mode(m, 2, mode);
2434 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2436 struct drm_info_node *node = m->private;
2437 struct drm_device *dev = node->minor->dev;
2438 struct drm_crtc *crtc = &intel_crtc->base;
2439 struct intel_encoder *intel_encoder;
2441 if (crtc->primary->fb)
2442 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2443 crtc->primary->fb->base.id, crtc->x, crtc->y,
2444 crtc->primary->fb->width, crtc->primary->fb->height);
2446 seq_puts(m, "\tprimary plane disabled\n");
2447 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2448 intel_encoder_info(m, intel_crtc, intel_encoder);
2451 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2453 struct drm_display_mode *mode = panel->fixed_mode;
2455 seq_printf(m, "\tfixed mode:\n");
2456 intel_seq_print_mode(m, 2, mode);
2459 static void intel_dp_info(struct seq_file *m,
2460 struct intel_connector *intel_connector)
2462 struct intel_encoder *intel_encoder = intel_connector->encoder;
2463 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2465 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2466 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2468 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2469 intel_panel_info(m, &intel_connector->panel);
2472 static void intel_hdmi_info(struct seq_file *m,
2473 struct intel_connector *intel_connector)
2475 struct intel_encoder *intel_encoder = intel_connector->encoder;
2476 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2478 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2482 static void intel_lvds_info(struct seq_file *m,
2483 struct intel_connector *intel_connector)
2485 intel_panel_info(m, &intel_connector->panel);
2488 static void intel_connector_info(struct seq_file *m,
2489 struct drm_connector *connector)
2491 struct intel_connector *intel_connector = to_intel_connector(connector);
2492 struct intel_encoder *intel_encoder = intel_connector->encoder;
2493 struct drm_display_mode *mode;
2495 seq_printf(m, "connector %d: type %s, status: %s\n",
2496 connector->base.id, connector->name,
2497 drm_get_connector_status_name(connector->status));
2498 if (connector->status == connector_status_connected) {
2499 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2500 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2501 connector->display_info.width_mm,
2502 connector->display_info.height_mm);
2503 seq_printf(m, "\tsubpixel order: %s\n",
2504 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2505 seq_printf(m, "\tCEA rev: %d\n",
2506 connector->display_info.cea_rev);
2508 if (intel_encoder) {
2509 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2510 intel_encoder->type == INTEL_OUTPUT_EDP)
2511 intel_dp_info(m, intel_connector);
2512 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2513 intel_hdmi_info(m, intel_connector);
2514 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2515 intel_lvds_info(m, intel_connector);
2518 seq_printf(m, "\tmodes:\n");
2519 list_for_each_entry(mode, &connector->modes, head)
2520 intel_seq_print_mode(m, 2, mode);
2523 static bool cursor_active(struct drm_device *dev, int pipe)
2525 struct drm_i915_private *dev_priv = dev->dev_private;
2528 if (IS_845G(dev) || IS_I865G(dev))
2529 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2531 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2536 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2538 struct drm_i915_private *dev_priv = dev->dev_private;
2541 pos = I915_READ(CURPOS(pipe));
2543 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2544 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2547 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2548 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2551 return cursor_active(dev, pipe);
2554 static int i915_display_info(struct seq_file *m, void *unused)
2556 struct drm_info_node *node = m->private;
2557 struct drm_device *dev = node->minor->dev;
2558 struct drm_i915_private *dev_priv = dev->dev_private;
2559 struct intel_crtc *crtc;
2560 struct drm_connector *connector;
2562 intel_runtime_pm_get(dev_priv);
2563 drm_modeset_lock_all(dev);
2564 seq_printf(m, "CRTC info\n");
2565 seq_printf(m, "---------\n");
2566 for_each_intel_crtc(dev, crtc) {
2570 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2571 crtc->base.base.id, pipe_name(crtc->pipe),
2572 yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h);
2574 intel_crtc_info(m, crtc);
2576 active = cursor_position(dev, crtc->pipe, &x, &y);
2577 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2578 yesno(crtc->cursor_base),
2579 x, y, crtc->cursor_width, crtc->cursor_height,
2580 crtc->cursor_addr, yesno(active));
2583 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2584 yesno(!crtc->cpu_fifo_underrun_disabled),
2585 yesno(!crtc->pch_fifo_underrun_disabled));
2588 seq_printf(m, "\n");
2589 seq_printf(m, "Connector info\n");
2590 seq_printf(m, "--------------\n");
2591 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2592 intel_connector_info(m, connector);
2594 drm_modeset_unlock_all(dev);
2595 intel_runtime_pm_put(dev_priv);
2600 static int i915_semaphore_status(struct seq_file *m, void *unused)
2602 struct drm_info_node *node = (struct drm_info_node *) m->private;
2603 struct drm_device *dev = node->minor->dev;
2604 struct drm_i915_private *dev_priv = dev->dev_private;
2605 struct intel_engine_cs *ring;
2606 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2609 if (!i915_semaphore_is_enabled(dev)) {
2610 seq_puts(m, "Semaphores are disabled\n");
2614 ret = mutex_lock_interruptible(&dev->struct_mutex);
2617 intel_runtime_pm_get(dev_priv);
2619 if (IS_BROADWELL(dev)) {
2623 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2625 seqno = (uint64_t *)kmap_atomic(page);
2626 for_each_ring(ring, dev_priv, i) {
2629 seq_printf(m, "%s\n", ring->name);
2631 seq_puts(m, " Last signal:");
2632 for (j = 0; j < num_rings; j++) {
2633 offset = i * I915_NUM_RINGS + j;
2634 seq_printf(m, "0x%08llx (0x%02llx) ",
2635 seqno[offset], offset * 8);
2639 seq_puts(m, " Last wait: ");
2640 for (j = 0; j < num_rings; j++) {
2641 offset = i + (j * I915_NUM_RINGS);
2642 seq_printf(m, "0x%08llx (0x%02llx) ",
2643 seqno[offset], offset * 8);
2648 kunmap_atomic(seqno);
2650 seq_puts(m, " Last signal:");
2651 for_each_ring(ring, dev_priv, i)
2652 for (j = 0; j < num_rings; j++)
2653 seq_printf(m, "0x%08x\n",
2654 I915_READ(ring->semaphore.mbox.signal[j]));
2658 seq_puts(m, "\nSync seqno:\n");
2659 for_each_ring(ring, dev_priv, i) {
2660 for (j = 0; j < num_rings; j++) {
2661 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2667 intel_runtime_pm_put(dev_priv);
2668 mutex_unlock(&dev->struct_mutex);
2672 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2674 struct drm_info_node *node = (struct drm_info_node *) m->private;
2675 struct drm_device *dev = node->minor->dev;
2676 struct drm_i915_private *dev_priv = dev->dev_private;
2679 drm_modeset_lock_all(dev);
2680 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2681 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2683 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2684 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2685 pll->config.crtc_mask, pll->active, yesno(pll->on));
2686 seq_printf(m, " tracked hardware state:\n");
2687 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2688 seq_printf(m, " dpll_md: 0x%08x\n",
2689 pll->config.hw_state.dpll_md);
2690 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2691 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2692 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
2694 drm_modeset_unlock_all(dev);
2699 static int i915_wa_registers(struct seq_file *m, void *unused)
2703 struct drm_info_node *node = (struct drm_info_node *) m->private;
2704 struct drm_device *dev = node->minor->dev;
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2707 ret = mutex_lock_interruptible(&dev->struct_mutex);
2711 intel_runtime_pm_get(dev_priv);
2713 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2714 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2715 u32 addr, mask, value, read;
2718 addr = dev_priv->workarounds.reg[i].addr;
2719 mask = dev_priv->workarounds.reg[i].mask;
2720 value = dev_priv->workarounds.reg[i].value;
2721 read = I915_READ(addr);
2722 ok = (value & mask) == (read & mask);
2723 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2724 addr, value, mask, read, ok ? "OK" : "FAIL");
2727 intel_runtime_pm_put(dev_priv);
2728 mutex_unlock(&dev->struct_mutex);
2733 static int i915_ddb_info(struct seq_file *m, void *unused)
2735 struct drm_info_node *node = m->private;
2736 struct drm_device *dev = node->minor->dev;
2737 struct drm_i915_private *dev_priv = dev->dev_private;
2738 struct skl_ddb_allocation *ddb;
2739 struct skl_ddb_entry *entry;
2743 drm_modeset_lock_all(dev);
2745 ddb = &dev_priv->wm.skl_hw.ddb;
2747 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2749 for_each_pipe(dev_priv, pipe) {
2750 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2752 for_each_plane(pipe, plane) {
2753 entry = &ddb->plane[pipe][plane];
2754 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2755 entry->start, entry->end,
2756 skl_ddb_entry_size(entry));
2759 entry = &ddb->cursor[pipe];
2760 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2761 entry->end, skl_ddb_entry_size(entry));
2764 drm_modeset_unlock_all(dev);
2769 struct pipe_crc_info {
2771 struct drm_device *dev;
2775 static int i915_dp_mst_info(struct seq_file *m, void *unused)
2777 struct drm_info_node *node = (struct drm_info_node *) m->private;
2778 struct drm_device *dev = node->minor->dev;
2779 struct drm_encoder *encoder;
2780 struct intel_encoder *intel_encoder;
2781 struct intel_digital_port *intel_dig_port;
2782 drm_modeset_lock_all(dev);
2783 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2784 intel_encoder = to_intel_encoder(encoder);
2785 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2787 intel_dig_port = enc_to_dig_port(encoder);
2788 if (!intel_dig_port->dp.can_mst)
2791 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2793 drm_modeset_unlock_all(dev);
2797 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2799 struct pipe_crc_info *info = inode->i_private;
2800 struct drm_i915_private *dev_priv = info->dev->dev_private;
2801 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2803 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2806 spin_lock_irq(&pipe_crc->lock);
2808 if (pipe_crc->opened) {
2809 spin_unlock_irq(&pipe_crc->lock);
2810 return -EBUSY; /* already open */
2813 pipe_crc->opened = true;
2814 filep->private_data = inode->i_private;
2816 spin_unlock_irq(&pipe_crc->lock);
2821 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2823 struct pipe_crc_info *info = inode->i_private;
2824 struct drm_i915_private *dev_priv = info->dev->dev_private;
2825 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2827 spin_lock_irq(&pipe_crc->lock);
2828 pipe_crc->opened = false;
2829 spin_unlock_irq(&pipe_crc->lock);
2834 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2835 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2836 /* account for \'0' */
2837 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2839 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2841 assert_spin_locked(&pipe_crc->lock);
2842 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2843 INTEL_PIPE_CRC_ENTRIES_NR);
2847 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2850 struct pipe_crc_info *info = filep->private_data;
2851 struct drm_device *dev = info->dev;
2852 struct drm_i915_private *dev_priv = dev->dev_private;
2853 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2854 char buf[PIPE_CRC_BUFFER_LEN];
2855 int head, tail, n_entries, n;
2859 * Don't allow user space to provide buffers not big enough to hold
2862 if (count < PIPE_CRC_LINE_LEN)
2865 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2868 /* nothing to read */
2869 spin_lock_irq(&pipe_crc->lock);
2870 while (pipe_crc_data_count(pipe_crc) == 0) {
2873 if (filep->f_flags & O_NONBLOCK) {
2874 spin_unlock_irq(&pipe_crc->lock);
2878 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2879 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2881 spin_unlock_irq(&pipe_crc->lock);
2886 /* We now have one or more entries to read */
2887 head = pipe_crc->head;
2888 tail = pipe_crc->tail;
2889 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2890 count / PIPE_CRC_LINE_LEN);
2891 spin_unlock_irq(&pipe_crc->lock);
2896 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
2899 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2900 "%8u %8x %8x %8x %8x %8x\n",
2901 entry->frame, entry->crc[0],
2902 entry->crc[1], entry->crc[2],
2903 entry->crc[3], entry->crc[4]);
2905 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2906 buf, PIPE_CRC_LINE_LEN);
2907 if (ret == PIPE_CRC_LINE_LEN)
2910 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2911 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2913 } while (--n_entries);
2915 spin_lock_irq(&pipe_crc->lock);
2916 pipe_crc->tail = tail;
2917 spin_unlock_irq(&pipe_crc->lock);
2922 static const struct file_operations i915_pipe_crc_fops = {
2923 .owner = THIS_MODULE,
2924 .open = i915_pipe_crc_open,
2925 .read = i915_pipe_crc_read,
2926 .release = i915_pipe_crc_release,
2929 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2931 .name = "i915_pipe_A_crc",
2935 .name = "i915_pipe_B_crc",
2939 .name = "i915_pipe_C_crc",
2944 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2947 struct drm_device *dev = minor->dev;
2949 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2952 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2953 &i915_pipe_crc_fops);
2957 return drm_add_fake_info_node(minor, ent, info);
2960 static const char * const pipe_crc_sources[] = {
2973 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2975 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2976 return pipe_crc_sources[source];
2979 static int display_crc_ctl_show(struct seq_file *m, void *data)
2981 struct drm_device *dev = m->private;
2982 struct drm_i915_private *dev_priv = dev->dev_private;
2985 for (i = 0; i < I915_MAX_PIPES; i++)
2986 seq_printf(m, "%c %s\n", pipe_name(i),
2987 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2992 static int display_crc_ctl_open(struct inode *inode, struct file *file)
2994 struct drm_device *dev = inode->i_private;
2996 return single_open(file, display_crc_ctl_show, dev);
2999 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3002 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3003 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3006 case INTEL_PIPE_CRC_SOURCE_PIPE:
3007 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3009 case INTEL_PIPE_CRC_SOURCE_NONE:
3019 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3020 enum intel_pipe_crc_source *source)
3022 struct intel_encoder *encoder;
3023 struct intel_crtc *crtc;
3024 struct intel_digital_port *dig_port;
3027 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3029 drm_modeset_lock_all(dev);
3030 for_each_intel_encoder(dev, encoder) {
3031 if (!encoder->base.crtc)
3034 crtc = to_intel_crtc(encoder->base.crtc);
3036 if (crtc->pipe != pipe)
3039 switch (encoder->type) {
3040 case INTEL_OUTPUT_TVOUT:
3041 *source = INTEL_PIPE_CRC_SOURCE_TV;
3043 case INTEL_OUTPUT_DISPLAYPORT:
3044 case INTEL_OUTPUT_EDP:
3045 dig_port = enc_to_dig_port(&encoder->base);
3046 switch (dig_port->port) {
3048 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3051 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3054 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3057 WARN(1, "nonexisting DP port %c\n",
3058 port_name(dig_port->port));
3066 drm_modeset_unlock_all(dev);
3071 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3073 enum intel_pipe_crc_source *source,
3076 struct drm_i915_private *dev_priv = dev->dev_private;
3077 bool need_stable_symbols = false;
3079 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3080 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3086 case INTEL_PIPE_CRC_SOURCE_PIPE:
3087 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3089 case INTEL_PIPE_CRC_SOURCE_DP_B:
3090 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3091 need_stable_symbols = true;
3093 case INTEL_PIPE_CRC_SOURCE_DP_C:
3094 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3095 need_stable_symbols = true;
3097 case INTEL_PIPE_CRC_SOURCE_NONE:
3105 * When the pipe CRC tap point is after the transcoders we need
3106 * to tweak symbol-level features to produce a deterministic series of
3107 * symbols for a given frame. We need to reset those features only once
3108 * a frame (instead of every nth symbol):
3109 * - DC-balance: used to ensure a better clock recovery from the data
3111 * - DisplayPort scrambling: used for EMI reduction
3113 if (need_stable_symbols) {
3114 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3116 tmp |= DC_BALANCE_RESET_VLV;
3118 tmp |= PIPE_A_SCRAMBLE_RESET;
3120 tmp |= PIPE_B_SCRAMBLE_RESET;
3122 I915_WRITE(PORT_DFT2_G4X, tmp);
3128 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3130 enum intel_pipe_crc_source *source,
3133 struct drm_i915_private *dev_priv = dev->dev_private;
3134 bool need_stable_symbols = false;
3136 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3137 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3143 case INTEL_PIPE_CRC_SOURCE_PIPE:
3144 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3146 case INTEL_PIPE_CRC_SOURCE_TV:
3147 if (!SUPPORTS_TV(dev))
3149 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3151 case INTEL_PIPE_CRC_SOURCE_DP_B:
3154 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3155 need_stable_symbols = true;
3157 case INTEL_PIPE_CRC_SOURCE_DP_C:
3160 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3161 need_stable_symbols = true;
3163 case INTEL_PIPE_CRC_SOURCE_DP_D:
3166 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3167 need_stable_symbols = true;
3169 case INTEL_PIPE_CRC_SOURCE_NONE:
3177 * When the pipe CRC tap point is after the transcoders we need
3178 * to tweak symbol-level features to produce a deterministic series of
3179 * symbols for a given frame. We need to reset those features only once
3180 * a frame (instead of every nth symbol):
3181 * - DC-balance: used to ensure a better clock recovery from the data
3183 * - DisplayPort scrambling: used for EMI reduction
3185 if (need_stable_symbols) {
3186 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3188 WARN_ON(!IS_G4X(dev));
3190 I915_WRITE(PORT_DFT_I9XX,
3191 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3194 tmp |= PIPE_A_SCRAMBLE_RESET;
3196 tmp |= PIPE_B_SCRAMBLE_RESET;
3198 I915_WRITE(PORT_DFT2_G4X, tmp);
3204 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3207 struct drm_i915_private *dev_priv = dev->dev_private;
3208 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3211 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3213 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3214 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3215 tmp &= ~DC_BALANCE_RESET_VLV;
3216 I915_WRITE(PORT_DFT2_G4X, tmp);
3220 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3223 struct drm_i915_private *dev_priv = dev->dev_private;
3224 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3227 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3229 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3230 I915_WRITE(PORT_DFT2_G4X, tmp);
3232 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3233 I915_WRITE(PORT_DFT_I9XX,
3234 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3238 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3241 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3242 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3245 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3246 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3248 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3249 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3251 case INTEL_PIPE_CRC_SOURCE_PIPE:
3252 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3254 case INTEL_PIPE_CRC_SOURCE_NONE:
3264 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3266 struct drm_i915_private *dev_priv = dev->dev_private;
3267 struct intel_crtc *crtc =
3268 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3270 drm_modeset_lock_all(dev);
3272 * If we use the eDP transcoder we need to make sure that we don't
3273 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3274 * relevant on hsw with pipe A when using the always-on power well
3277 if (crtc->config.cpu_transcoder == TRANSCODER_EDP &&
3278 !crtc->config.pch_pfit.enabled) {
3279 crtc->config.pch_pfit.force_thru = true;
3281 intel_display_power_get(dev_priv,
3282 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3284 dev_priv->display.crtc_disable(&crtc->base);
3285 dev_priv->display.crtc_enable(&crtc->base);
3287 drm_modeset_unlock_all(dev);
3290 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3292 struct drm_i915_private *dev_priv = dev->dev_private;
3293 struct intel_crtc *crtc =
3294 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3296 drm_modeset_lock_all(dev);
3298 * If we use the eDP transcoder we need to make sure that we don't
3299 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3300 * relevant on hsw with pipe A when using the always-on power well
3303 if (crtc->config.pch_pfit.force_thru) {
3304 crtc->config.pch_pfit.force_thru = false;
3306 dev_priv->display.crtc_disable(&crtc->base);
3307 dev_priv->display.crtc_enable(&crtc->base);
3309 intel_display_power_put(dev_priv,
3310 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3312 drm_modeset_unlock_all(dev);
3315 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3317 enum intel_pipe_crc_source *source,
3320 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3321 *source = INTEL_PIPE_CRC_SOURCE_PF;
3324 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3325 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3327 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3328 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3330 case INTEL_PIPE_CRC_SOURCE_PF:
3331 if (IS_HASWELL(dev) && pipe == PIPE_A)
3332 hsw_trans_edp_pipe_A_crc_wa(dev);
3334 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3336 case INTEL_PIPE_CRC_SOURCE_NONE:
3346 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3347 enum intel_pipe_crc_source source)
3349 struct drm_i915_private *dev_priv = dev->dev_private;
3350 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3351 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3353 u32 val = 0; /* shut up gcc */
3356 if (pipe_crc->source == source)
3359 /* forbid changing the source without going back to 'none' */
3360 if (pipe_crc->source && source)
3363 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3364 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3369 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3370 else if (INTEL_INFO(dev)->gen < 5)
3371 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3372 else if (IS_VALLEYVIEW(dev))
3373 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3374 else if (IS_GEN5(dev) || IS_GEN6(dev))
3375 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3377 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3382 /* none -> real source transition */
3384 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3385 pipe_name(pipe), pipe_crc_source_name(source));
3387 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
3388 INTEL_PIPE_CRC_ENTRIES_NR,
3390 if (!pipe_crc->entries)
3394 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3395 * enabled and disabled dynamically based on package C states,
3396 * user space can't make reliable use of the CRCs, so let's just
3397 * completely disable it.
3399 hsw_disable_ips(crtc);
3401 spin_lock_irq(&pipe_crc->lock);
3404 spin_unlock_irq(&pipe_crc->lock);
3407 pipe_crc->source = source;
3409 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3410 POSTING_READ(PIPE_CRC_CTL(pipe));
3412 /* real source -> none transition */
3413 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3414 struct intel_pipe_crc_entry *entries;
3415 struct intel_crtc *crtc =
3416 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3418 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3421 drm_modeset_lock(&crtc->base.mutex, NULL);
3423 intel_wait_for_vblank(dev, pipe);
3424 drm_modeset_unlock(&crtc->base.mutex);
3426 spin_lock_irq(&pipe_crc->lock);
3427 entries = pipe_crc->entries;
3428 pipe_crc->entries = NULL;
3429 spin_unlock_irq(&pipe_crc->lock);
3434 g4x_undo_pipe_scramble_reset(dev, pipe);
3435 else if (IS_VALLEYVIEW(dev))
3436 vlv_undo_pipe_scramble_reset(dev, pipe);
3437 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3438 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3440 hsw_enable_ips(crtc);
3447 * Parse pipe CRC command strings:
3448 * command: wsp* object wsp+ name wsp+ source wsp*
3451 * source: (none | plane1 | plane2 | pf)
3452 * wsp: (#0x20 | #0x9 | #0xA)+
3455 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3456 * "pipe A none" -> Stop CRC
3458 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3465 /* skip leading white space */
3466 buf = skip_spaces(buf);
3468 break; /* end of buffer */
3470 /* find end of word */
3471 for (end = buf; *end && !isspace(*end); end++)
3474 if (n_words == max_words) {
3475 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3477 return -EINVAL; /* ran out of words[] before bytes */
3482 words[n_words++] = buf;
3489 enum intel_pipe_crc_object {
3490 PIPE_CRC_OBJECT_PIPE,
3493 static const char * const pipe_crc_objects[] = {
3498 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3502 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3503 if (!strcmp(buf, pipe_crc_objects[i])) {
3511 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3513 const char name = buf[0];
3515 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3524 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3528 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3529 if (!strcmp(buf, pipe_crc_sources[i])) {
3537 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3541 char *words[N_WORDS];
3543 enum intel_pipe_crc_object object;
3544 enum intel_pipe_crc_source source;
3546 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3547 if (n_words != N_WORDS) {
3548 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3553 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3554 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3558 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3559 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3563 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3564 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3568 return pipe_crc_set_source(dev, pipe, source);
3571 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3572 size_t len, loff_t *offp)
3574 struct seq_file *m = file->private_data;
3575 struct drm_device *dev = m->private;
3582 if (len > PAGE_SIZE - 1) {
3583 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3588 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3592 if (copy_from_user(tmpbuf, ubuf, len)) {
3598 ret = display_crc_ctl_parse(dev, tmpbuf, len);
3609 static const struct file_operations i915_display_crc_ctl_fops = {
3610 .owner = THIS_MODULE,
3611 .open = display_crc_ctl_open,
3613 .llseek = seq_lseek,
3614 .release = single_release,
3615 .write = display_crc_ctl_write
3618 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3620 struct drm_device *dev = m->private;
3621 int num_levels = ilk_wm_max_level(dev) + 1;
3624 drm_modeset_lock_all(dev);
3626 for (level = 0; level < num_levels; level++) {
3627 unsigned int latency = wm[level];
3630 * - WM1+ latency values in 0.5us units
3631 * - latencies are in us on gen9
3633 if (INTEL_INFO(dev)->gen >= 9)
3638 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3639 level, wm[level], latency / 10, latency % 10);
3642 drm_modeset_unlock_all(dev);
3645 static int pri_wm_latency_show(struct seq_file *m, void *data)
3647 struct drm_device *dev = m->private;
3648 struct drm_i915_private *dev_priv = dev->dev_private;
3649 const uint16_t *latencies;
3651 if (INTEL_INFO(dev)->gen >= 9)
3652 latencies = dev_priv->wm.skl_latency;
3654 latencies = to_i915(dev)->wm.pri_latency;
3656 wm_latency_show(m, latencies);
3661 static int spr_wm_latency_show(struct seq_file *m, void *data)
3663 struct drm_device *dev = m->private;
3664 struct drm_i915_private *dev_priv = dev->dev_private;
3665 const uint16_t *latencies;
3667 if (INTEL_INFO(dev)->gen >= 9)
3668 latencies = dev_priv->wm.skl_latency;
3670 latencies = to_i915(dev)->wm.spr_latency;
3672 wm_latency_show(m, latencies);
3677 static int cur_wm_latency_show(struct seq_file *m, void *data)
3679 struct drm_device *dev = m->private;
3680 struct drm_i915_private *dev_priv = dev->dev_private;
3681 const uint16_t *latencies;
3683 if (INTEL_INFO(dev)->gen >= 9)
3684 latencies = dev_priv->wm.skl_latency;
3686 latencies = to_i915(dev)->wm.cur_latency;
3688 wm_latency_show(m, latencies);
3693 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3695 struct drm_device *dev = inode->i_private;
3697 if (HAS_GMCH_DISPLAY(dev))
3700 return single_open(file, pri_wm_latency_show, dev);
3703 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3705 struct drm_device *dev = inode->i_private;
3707 if (HAS_GMCH_DISPLAY(dev))
3710 return single_open(file, spr_wm_latency_show, dev);
3713 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3715 struct drm_device *dev = inode->i_private;
3717 if (HAS_GMCH_DISPLAY(dev))
3720 return single_open(file, cur_wm_latency_show, dev);
3723 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3724 size_t len, loff_t *offp, uint16_t wm[8])
3726 struct seq_file *m = file->private_data;
3727 struct drm_device *dev = m->private;
3728 uint16_t new[8] = { 0 };
3729 int num_levels = ilk_wm_max_level(dev) + 1;
3734 if (len >= sizeof(tmp))
3737 if (copy_from_user(tmp, ubuf, len))
3742 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3743 &new[0], &new[1], &new[2], &new[3],
3744 &new[4], &new[5], &new[6], &new[7]);
3745 if (ret != num_levels)
3748 drm_modeset_lock_all(dev);
3750 for (level = 0; level < num_levels; level++)
3751 wm[level] = new[level];
3753 drm_modeset_unlock_all(dev);
3759 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3760 size_t len, loff_t *offp)
3762 struct seq_file *m = file->private_data;
3763 struct drm_device *dev = m->private;
3764 struct drm_i915_private *dev_priv = dev->dev_private;
3765 uint16_t *latencies;
3767 if (INTEL_INFO(dev)->gen >= 9)
3768 latencies = dev_priv->wm.skl_latency;
3770 latencies = to_i915(dev)->wm.pri_latency;
3772 return wm_latency_write(file, ubuf, len, offp, latencies);
3775 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3776 size_t len, loff_t *offp)
3778 struct seq_file *m = file->private_data;
3779 struct drm_device *dev = m->private;
3780 struct drm_i915_private *dev_priv = dev->dev_private;
3781 uint16_t *latencies;
3783 if (INTEL_INFO(dev)->gen >= 9)
3784 latencies = dev_priv->wm.skl_latency;
3786 latencies = to_i915(dev)->wm.spr_latency;
3788 return wm_latency_write(file, ubuf, len, offp, latencies);
3791 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3792 size_t len, loff_t *offp)
3794 struct seq_file *m = file->private_data;
3795 struct drm_device *dev = m->private;
3796 struct drm_i915_private *dev_priv = dev->dev_private;
3797 uint16_t *latencies;
3799 if (INTEL_INFO(dev)->gen >= 9)
3800 latencies = dev_priv->wm.skl_latency;
3802 latencies = to_i915(dev)->wm.cur_latency;
3804 return wm_latency_write(file, ubuf, len, offp, latencies);
3807 static const struct file_operations i915_pri_wm_latency_fops = {
3808 .owner = THIS_MODULE,
3809 .open = pri_wm_latency_open,
3811 .llseek = seq_lseek,
3812 .release = single_release,
3813 .write = pri_wm_latency_write
3816 static const struct file_operations i915_spr_wm_latency_fops = {
3817 .owner = THIS_MODULE,
3818 .open = spr_wm_latency_open,
3820 .llseek = seq_lseek,
3821 .release = single_release,
3822 .write = spr_wm_latency_write
3825 static const struct file_operations i915_cur_wm_latency_fops = {
3826 .owner = THIS_MODULE,
3827 .open = cur_wm_latency_open,
3829 .llseek = seq_lseek,
3830 .release = single_release,
3831 .write = cur_wm_latency_write
3835 i915_wedged_get(void *data, u64 *val)
3837 struct drm_device *dev = data;
3838 struct drm_i915_private *dev_priv = dev->dev_private;
3840 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
3846 i915_wedged_set(void *data, u64 val)
3848 struct drm_device *dev = data;
3849 struct drm_i915_private *dev_priv = dev->dev_private;
3851 intel_runtime_pm_get(dev_priv);
3853 i915_handle_error(dev, val,
3854 "Manually setting wedged to %llu", val);
3856 intel_runtime_pm_put(dev_priv);
3861 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3862 i915_wedged_get, i915_wedged_set,
3866 i915_ring_stop_get(void *data, u64 *val)
3868 struct drm_device *dev = data;
3869 struct drm_i915_private *dev_priv = dev->dev_private;
3871 *val = dev_priv->gpu_error.stop_rings;
3877 i915_ring_stop_set(void *data, u64 val)
3879 struct drm_device *dev = data;
3880 struct drm_i915_private *dev_priv = dev->dev_private;
3883 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
3885 ret = mutex_lock_interruptible(&dev->struct_mutex);
3889 dev_priv->gpu_error.stop_rings = val;
3890 mutex_unlock(&dev->struct_mutex);
3895 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3896 i915_ring_stop_get, i915_ring_stop_set,
3900 i915_ring_missed_irq_get(void *data, u64 *val)
3902 struct drm_device *dev = data;
3903 struct drm_i915_private *dev_priv = dev->dev_private;
3905 *val = dev_priv->gpu_error.missed_irq_rings;
3910 i915_ring_missed_irq_set(void *data, u64 val)
3912 struct drm_device *dev = data;
3913 struct drm_i915_private *dev_priv = dev->dev_private;
3916 /* Lock against concurrent debugfs callers */
3917 ret = mutex_lock_interruptible(&dev->struct_mutex);
3920 dev_priv->gpu_error.missed_irq_rings = val;
3921 mutex_unlock(&dev->struct_mutex);
3926 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3927 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3931 i915_ring_test_irq_get(void *data, u64 *val)
3933 struct drm_device *dev = data;
3934 struct drm_i915_private *dev_priv = dev->dev_private;
3936 *val = dev_priv->gpu_error.test_irq_rings;
3942 i915_ring_test_irq_set(void *data, u64 val)
3944 struct drm_device *dev = data;
3945 struct drm_i915_private *dev_priv = dev->dev_private;
3948 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3950 /* Lock against concurrent debugfs callers */
3951 ret = mutex_lock_interruptible(&dev->struct_mutex);
3955 dev_priv->gpu_error.test_irq_rings = val;
3956 mutex_unlock(&dev->struct_mutex);
3961 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3962 i915_ring_test_irq_get, i915_ring_test_irq_set,
3965 #define DROP_UNBOUND 0x1
3966 #define DROP_BOUND 0x2
3967 #define DROP_RETIRE 0x4
3968 #define DROP_ACTIVE 0x8
3969 #define DROP_ALL (DROP_UNBOUND | \
3974 i915_drop_caches_get(void *data, u64 *val)
3982 i915_drop_caches_set(void *data, u64 val)
3984 struct drm_device *dev = data;
3985 struct drm_i915_private *dev_priv = dev->dev_private;
3988 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
3990 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3991 * on ioctls on -EAGAIN. */
3992 ret = mutex_lock_interruptible(&dev->struct_mutex);
3996 if (val & DROP_ACTIVE) {
3997 ret = i915_gpu_idle(dev);
4002 if (val & (DROP_RETIRE | DROP_ACTIVE))
4003 i915_gem_retire_requests(dev);
4005 if (val & DROP_BOUND)
4006 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4008 if (val & DROP_UNBOUND)
4009 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4012 mutex_unlock(&dev->struct_mutex);
4017 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4018 i915_drop_caches_get, i915_drop_caches_set,
4022 i915_max_freq_get(void *data, u64 *val)
4024 struct drm_device *dev = data;
4025 struct drm_i915_private *dev_priv = dev->dev_private;
4028 if (INTEL_INFO(dev)->gen < 6)
4031 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4033 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4037 if (IS_VALLEYVIEW(dev))
4038 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4040 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4041 mutex_unlock(&dev_priv->rps.hw_lock);
4047 i915_max_freq_set(void *data, u64 val)
4049 struct drm_device *dev = data;
4050 struct drm_i915_private *dev_priv = dev->dev_private;
4051 u32 rp_state_cap, hw_max, hw_min;
4054 if (INTEL_INFO(dev)->gen < 6)
4057 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4059 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4061 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4066 * Turbo will still be enabled, but won't go above the set value.
4068 if (IS_VALLEYVIEW(dev)) {
4069 val = vlv_freq_opcode(dev_priv, val);
4071 hw_max = dev_priv->rps.max_freq;
4072 hw_min = dev_priv->rps.min_freq;
4074 do_div(val, GT_FREQUENCY_MULTIPLIER);
4076 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4077 hw_max = dev_priv->rps.max_freq;
4078 hw_min = (rp_state_cap >> 16) & 0xff;
4081 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4082 mutex_unlock(&dev_priv->rps.hw_lock);
4086 dev_priv->rps.max_freq_softlimit = val;
4088 if (IS_VALLEYVIEW(dev))
4089 valleyview_set_rps(dev, val);
4091 gen6_set_rps(dev, val);
4093 mutex_unlock(&dev_priv->rps.hw_lock);
4098 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4099 i915_max_freq_get, i915_max_freq_set,
4103 i915_min_freq_get(void *data, u64 *val)
4105 struct drm_device *dev = data;
4106 struct drm_i915_private *dev_priv = dev->dev_private;
4109 if (INTEL_INFO(dev)->gen < 6)
4112 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4114 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4118 if (IS_VALLEYVIEW(dev))
4119 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4121 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4122 mutex_unlock(&dev_priv->rps.hw_lock);
4128 i915_min_freq_set(void *data, u64 val)
4130 struct drm_device *dev = data;
4131 struct drm_i915_private *dev_priv = dev->dev_private;
4132 u32 rp_state_cap, hw_max, hw_min;
4135 if (INTEL_INFO(dev)->gen < 6)
4138 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4140 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4142 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4147 * Turbo will still be enabled, but won't go below the set value.
4149 if (IS_VALLEYVIEW(dev)) {
4150 val = vlv_freq_opcode(dev_priv, val);
4152 hw_max = dev_priv->rps.max_freq;
4153 hw_min = dev_priv->rps.min_freq;
4155 do_div(val, GT_FREQUENCY_MULTIPLIER);
4157 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4158 hw_max = dev_priv->rps.max_freq;
4159 hw_min = (rp_state_cap >> 16) & 0xff;
4162 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4163 mutex_unlock(&dev_priv->rps.hw_lock);
4167 dev_priv->rps.min_freq_softlimit = val;
4169 if (IS_VALLEYVIEW(dev))
4170 valleyview_set_rps(dev, val);
4172 gen6_set_rps(dev, val);
4174 mutex_unlock(&dev_priv->rps.hw_lock);
4179 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4180 i915_min_freq_get, i915_min_freq_set,
4184 i915_cache_sharing_get(void *data, u64 *val)
4186 struct drm_device *dev = data;
4187 struct drm_i915_private *dev_priv = dev->dev_private;
4191 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4194 ret = mutex_lock_interruptible(&dev->struct_mutex);
4197 intel_runtime_pm_get(dev_priv);
4199 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4201 intel_runtime_pm_put(dev_priv);
4202 mutex_unlock(&dev_priv->dev->struct_mutex);
4204 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4210 i915_cache_sharing_set(void *data, u64 val)
4212 struct drm_device *dev = data;
4213 struct drm_i915_private *dev_priv = dev->dev_private;
4216 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4222 intel_runtime_pm_get(dev_priv);
4223 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4225 /* Update the cache sharing policy here as well */
4226 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4227 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4228 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4229 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4231 intel_runtime_pm_put(dev_priv);
4235 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4236 i915_cache_sharing_get, i915_cache_sharing_set,
4239 static int i915_forcewake_open(struct inode *inode, struct file *file)
4241 struct drm_device *dev = inode->i_private;
4242 struct drm_i915_private *dev_priv = dev->dev_private;
4244 if (INTEL_INFO(dev)->gen < 6)
4247 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4252 static int i915_forcewake_release(struct inode *inode, struct file *file)
4254 struct drm_device *dev = inode->i_private;
4255 struct drm_i915_private *dev_priv = dev->dev_private;
4257 if (INTEL_INFO(dev)->gen < 6)
4260 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4265 static const struct file_operations i915_forcewake_fops = {
4266 .owner = THIS_MODULE,
4267 .open = i915_forcewake_open,
4268 .release = i915_forcewake_release,
4271 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4273 struct drm_device *dev = minor->dev;
4276 ent = debugfs_create_file("i915_forcewake_user",
4279 &i915_forcewake_fops);
4283 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
4286 static int i915_debugfs_create(struct dentry *root,
4287 struct drm_minor *minor,
4289 const struct file_operations *fops)
4291 struct drm_device *dev = minor->dev;
4294 ent = debugfs_create_file(name,
4301 return drm_add_fake_info_node(minor, ent, fops);
4304 static const struct drm_info_list i915_debugfs_list[] = {
4305 {"i915_capabilities", i915_capabilities, 0},
4306 {"i915_gem_objects", i915_gem_object_info, 0},
4307 {"i915_gem_gtt", i915_gem_gtt_info, 0},
4308 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
4309 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
4310 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
4311 {"i915_gem_stolen", i915_gem_stolen_list_info },
4312 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
4313 {"i915_gem_request", i915_gem_request_info, 0},
4314 {"i915_gem_seqno", i915_gem_seqno_info, 0},
4315 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4316 {"i915_gem_interrupt", i915_interrupt_info, 0},
4317 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4318 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4319 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
4320 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
4321 {"i915_frequency_info", i915_frequency_info, 0},
4322 {"i915_drpc_info", i915_drpc_info, 0},
4323 {"i915_emon_status", i915_emon_status, 0},
4324 {"i915_ring_freq_table", i915_ring_freq_table, 0},
4325 {"i915_fbc_status", i915_fbc_status, 0},
4326 {"i915_ips_status", i915_ips_status, 0},
4327 {"i915_sr_status", i915_sr_status, 0},
4328 {"i915_opregion", i915_opregion, 0},
4329 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4330 {"i915_context_status", i915_context_status, 0},
4331 {"i915_dump_lrc", i915_dump_lrc, 0},
4332 {"i915_execlists", i915_execlists, 0},
4333 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
4334 {"i915_swizzle_info", i915_swizzle_info, 0},
4335 {"i915_ppgtt_info", i915_ppgtt_info, 0},
4336 {"i915_llc", i915_llc, 0},
4337 {"i915_edp_psr_status", i915_edp_psr_status, 0},
4338 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4339 {"i915_energy_uJ", i915_energy_uJ, 0},
4340 {"i915_pc8_status", i915_pc8_status, 0},
4341 {"i915_power_domain_info", i915_power_domain_info, 0},
4342 {"i915_display_info", i915_display_info, 0},
4343 {"i915_semaphore_status", i915_semaphore_status, 0},
4344 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4345 {"i915_dp_mst_info", i915_dp_mst_info, 0},
4346 {"i915_wa_registers", i915_wa_registers, 0},
4347 {"i915_ddb_info", i915_ddb_info, 0},
4349 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4351 static const struct i915_debugfs_files {
4353 const struct file_operations *fops;
4354 } i915_debugfs_files[] = {
4355 {"i915_wedged", &i915_wedged_fops},
4356 {"i915_max_freq", &i915_max_freq_fops},
4357 {"i915_min_freq", &i915_min_freq_fops},
4358 {"i915_cache_sharing", &i915_cache_sharing_fops},
4359 {"i915_ring_stop", &i915_ring_stop_fops},
4360 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4361 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4362 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4363 {"i915_error_state", &i915_error_state_fops},
4364 {"i915_next_seqno", &i915_next_seqno_fops},
4365 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4366 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4367 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4368 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4369 {"i915_fbc_false_color", &i915_fbc_fc_fops},
4372 void intel_display_crc_init(struct drm_device *dev)
4374 struct drm_i915_private *dev_priv = dev->dev_private;
4377 for_each_pipe(dev_priv, pipe) {
4378 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4380 pipe_crc->opened = false;
4381 spin_lock_init(&pipe_crc->lock);
4382 init_waitqueue_head(&pipe_crc->wq);
4386 int i915_debugfs_init(struct drm_minor *minor)
4390 ret = i915_forcewake_create(minor->debugfs_root, minor);
4394 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4395 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4400 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4401 ret = i915_debugfs_create(minor->debugfs_root, minor,
4402 i915_debugfs_files[i].name,
4403 i915_debugfs_files[i].fops);
4408 return drm_debugfs_create_files(i915_debugfs_list,
4409 I915_DEBUGFS_ENTRIES,
4410 minor->debugfs_root, minor);
4413 void i915_debugfs_cleanup(struct drm_minor *minor)
4417 drm_debugfs_remove_files(i915_debugfs_list,
4418 I915_DEBUGFS_ENTRIES, minor);
4420 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4423 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4424 struct drm_info_list *info_list =
4425 (struct drm_info_list *)&i915_pipe_crc_data[i];
4427 drm_debugfs_remove_files(info_list, 1, minor);
4430 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4431 struct drm_info_list *info_list =
4432 (struct drm_info_list *) i915_debugfs_files[i].fops;
4434 drm_debugfs_remove_files(info_list, 1, minor);