drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 static const char *yesno(int v)
  50 {
  51         return v ? "yes" : "no";
  52 }
  53
  54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  55  * allocated we need to hook into the minor for release. */
  56 static int
  57 drm_add_fake_info_node(struct drm_minor *minor,
  58                        struct dentry *ent,
  59                        const void *key)
  60 {
  61         struct drm_info_node *node;
  62
  63         node = kmalloc(sizeof(*node), GFP_KERNEL);
  64         if (node == NULL) {
  65                 debugfs_remove(ent);
  66                 return -ENOMEM;
  67         }
  68
  69         node->minor = minor;
  70         node->dent = ent;
  71         node->info_ent = (void *) key;
  72
  73         mutex_lock(&minor->debugfs_lock);
  74         list_add(&node->list, &minor->debugfs_list);
  75         mutex_unlock(&minor->debugfs_lock);
  76
  77         return 0;
  78 }
  79
  80 static int i915_capabilities(struct seq_file *m, void *data)
  81 {
  82         struct drm_info_node *node = m->private;
  83         struct drm_device *dev = node->minor->dev;
  84         const struct intel_device_info *info = INTEL_INFO(dev);
  85
  86         seq_printf(m, "gen: %d\n", info->gen);
  87         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  88 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  89 #define SEP_SEMICOLON ;
  90         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  91 #undef PRINT_FLAG
  92 #undef SEP_SEMICOLON
  93
  94         return 0;
  95 }
  96
  97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  98 {
  99         if (obj->user_pin_count > 0)
 100                 return "P";
 101         else if (i915_gem_obj_is_pinned(obj))
 102                 return "p";
 103         else
 104                 return " ";
 105 }
 106
 107 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 108 {
 109         switch (obj->tiling_mode) {
 110         default:
 111         case I915_TILING_NONE: return " ";
 112         case I915_TILING_X: return "X";
 113         case I915_TILING_Y: return "Y";
 114         }
 115 }
 116
 117 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 118 {
 119         return obj->has_global_gtt_mapping ? "g" : " ";
 120 }
 121
 122 static void
 123 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 124 {
 125         struct i915_vma *vma;
 126         int pin_count = 0;
 127
 128         seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
 129                    &obj->base,
 130                    get_pin_flag(obj),
 131                    get_tiling_flag(obj),
 132                    get_global_flag(obj),
 133                    obj->base.size / 1024,
 134                    obj->base.read_domains,
 135                    obj->base.write_domain,
 136                    obj->last_read_seqno,
 137                    obj->last_write_seqno,
 138                    obj->last_fenced_seqno,
 139                    i915_cache_level_str(obj->cache_level),
 140                    obj->dirty ? " dirty" : "",
 141                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 142         if (obj->base.name)
 143                 seq_printf(m, " (name: %d)", obj->base.name);
 144         list_for_each_entry(vma, &obj->vma_list, vma_link)
 145                 if (vma->pin_count > 0)
 146                         pin_count++;
 147                 seq_printf(m, " (pinned x %d)", pin_count);
 148         if (obj->pin_display)
 149                 seq_printf(m, " (display)");
 150         if (obj->fence_reg != I915_FENCE_REG_NONE)
 151                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 152         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 153                 if (!i915_is_ggtt(vma->vm))
 154                         seq_puts(m, " (pp");
 155                 else
 156                         seq_puts(m, " (g");
 157                 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
 158                            vma->node.start, vma->node.size);
 159         }
 160         if (obj->stolen)
 161                 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
 162         if (obj->pin_mappable || obj->fault_mappable) {
 163                 char s[3], *t = s;
 164                 if (obj->pin_mappable)
 165                         *t++ = 'p';
 166                 if (obj->fault_mappable)
 167                         *t++ = 'f';
 168                 *t = '\0';
 169                 seq_printf(m, " (%s mappable)", s);
 170         }
 171         if (obj->ring != NULL)
 172                 seq_printf(m, " (%s)", obj->ring->name);
 173         if (obj->frontbuffer_bits)
 174                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 175 }
 176
 177 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
 178 {
 179         seq_putc(m, ctx->is_initialized ? 'I' : 'i');
 180         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 181         seq_putc(m, ' ');
 182 }
 183
 184 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 185 {
 186         struct drm_info_node *node = m->private;
 187         uintptr_t list = (uintptr_t) node->info_ent->data;
 188         struct list_head *head;
 189         struct drm_device *dev = node->minor->dev;
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191         struct i915_address_space *vm = &dev_priv->gtt.base;
 192         struct i915_vma *vma;
 193         size_t total_obj_size, total_gtt_size;
 194         int count, ret;
 195
 196         ret = mutex_lock_interruptible(&dev->struct_mutex);
 197         if (ret)
 198                 return ret;
 199
 200         /* FIXME: the user of this interface might want more than just GGTT */
 201         switch (list) {
 202         case ACTIVE_LIST:
 203                 seq_puts(m, "Active:\n");
 204                 head = &vm->active_list;
 205                 break;
 206         case INACTIVE_LIST:
 207                 seq_puts(m, "Inactive:\n");
 208                 head = &vm->inactive_list;
 209                 break;
 210         default:
 211                 mutex_unlock(&dev->struct_mutex);
 212                 return -EINVAL;
 213         }
 214
 215         total_obj_size = total_gtt_size = count = 0;
 216         list_for_each_entry(vma, head, mm_list) {
 217                 seq_printf(m, "   ");
 218                 describe_obj(m, vma->obj);
 219                 seq_printf(m, "\n");
 220                 total_obj_size += vma->obj->base.size;
 221                 total_gtt_size += vma->node.size;
 222                 count++;
 223         }
 224         mutex_unlock(&dev->struct_mutex);
 225
 226         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 227                    count, total_obj_size, total_gtt_size);
 228         return 0;
 229 }
 230
 231 static int obj_rank_by_stolen(void *priv,
 232                               struct list_head *A, struct list_head *B)
 233 {
 234         struct drm_i915_gem_object *a =
 235                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 236         struct drm_i915_gem_object *b =
 237                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 238
 239         return a->stolen->start - b->stolen->start;
 240 }
 241
 242 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 243 {
 244         struct drm_info_node *node = m->private;
 245         struct drm_device *dev = node->minor->dev;
 246         struct drm_i915_private *dev_priv = dev->dev_private;
 247         struct drm_i915_gem_object *obj;
 248         size_t total_obj_size, total_gtt_size;
 249         LIST_HEAD(stolen);
 250         int count, ret;
 251
 252         ret = mutex_lock_interruptible(&dev->struct_mutex);
 253         if (ret)
 254                 return ret;
 255
 256         total_obj_size = total_gtt_size = count = 0;
 257         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 258                 if (obj->stolen == NULL)
 259                         continue;
 260
 261                 list_add(&obj->obj_exec_link, &stolen);
 262
 263                 total_obj_size += obj->base.size;
 264                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 265                 count++;
 266         }
 267         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 268                 if (obj->stolen == NULL)
 269                         continue;
 270
 271                 list_add(&obj->obj_exec_link, &stolen);
 272
 273                 total_obj_size += obj->base.size;
 274                 count++;
 275         }
 276         list_sort(NULL, &stolen, obj_rank_by_stolen);
 277         seq_puts(m, "Stolen:\n");
 278         while (!list_empty(&stolen)) {
 279                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 280                 seq_puts(m, "   ");
 281                 describe_obj(m, obj);
 282                 seq_putc(m, '\n');
 283                 list_del_init(&obj->obj_exec_link);
 284         }
 285         mutex_unlock(&dev->struct_mutex);
 286
 287         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 288                    count, total_obj_size, total_gtt_size);
 289         return 0;
 290 }
 291
 292 #define count_objects(list, member) do { \
 293         list_for_each_entry(obj, list, member) { \
 294                 size += i915_gem_obj_ggtt_size(obj); \
 295                 ++count; \
 296                 if (obj->map_and_fenceable) { \
 297                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 298                         ++mappable_count; \
 299                 } \
 300         } \
 301 } while (0)
 302
 303 struct file_stats {
 304         struct drm_i915_file_private *file_priv;
 305         int count;
 306         size_t total, unbound;
 307         size_t global, shared;
 308         size_t active, inactive;
 309 };
 310
 311 static int per_file_stats(int id, void *ptr, void *data)
 312 {
 313         struct drm_i915_gem_object *obj = ptr;
 314         struct file_stats *stats = data;
 315         struct i915_vma *vma;
 316
 317         stats->count++;
 318         stats->total += obj->base.size;
 319
 320         if (obj->base.name || obj->base.dma_buf)
 321                 stats->shared += obj->base.size;
 322
 323         if (USES_FULL_PPGTT(obj->base.dev)) {
 324                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
 325                         struct i915_hw_ppgtt *ppgtt;
 326
 327                         if (!drm_mm_node_allocated(&vma->node))
 328                                 continue;
 329
 330                         if (i915_is_ggtt(vma->vm)) {
 331                                 stats->global += obj->base.size;
 332                                 continue;
 333                         }
 334
 335                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 336                         if (ppgtt->ctx && ppgtt->ctx->file_priv != stats->file_priv)
 337                                 continue;
 338
 339                         if (obj->ring) /* XXX per-vma statistic */
 340                                 stats->active += obj->base.size;
 341                         else
 342                                 stats->inactive += obj->base.size;
 343
 344                         return 0;
 345                 }
 346         } else {
 347                 if (i915_gem_obj_ggtt_bound(obj)) {
 348                         stats->global += obj->base.size;
 349                         if (obj->ring)
 350                                 stats->active += obj->base.size;
 351                         else
 352                                 stats->inactive += obj->base.size;
 353                         return 0;
 354                 }
 355         }
 356
 357         if (!list_empty(&obj->global_list))
 358                 stats->unbound += obj->base.size;
 359
 360         return 0;
 361 }
 362
 363 #define count_vmas(list, member) do { \
 364         list_for_each_entry(vma, list, member) { \
 365                 size += i915_gem_obj_ggtt_size(vma->obj); \
 366                 ++count; \
 367                 if (vma->obj->map_and_fenceable) { \
 368                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 369                         ++mappable_count; \
 370                 } \
 371         } \
 372 } while (0)
 373
 374 static int i915_gem_object_info(struct seq_file *m, void* data)
 375 {
 376         struct drm_info_node *node = m->private;
 377         struct drm_device *dev = node->minor->dev;
 378         struct drm_i915_private *dev_priv = dev->dev_private;
 379         u32 count, mappable_count, purgeable_count;
 380         size_t size, mappable_size, purgeable_size;
 381         struct drm_i915_gem_object *obj;
 382         struct i915_address_space *vm = &dev_priv->gtt.base;
 383         struct drm_file *file;
 384         struct i915_vma *vma;
 385         int ret;
 386
 387         ret = mutex_lock_interruptible(&dev->struct_mutex);
 388         if (ret)
 389                 return ret;
 390
 391         seq_printf(m, "%u objects, %zu bytes\n",
 392                    dev_priv->mm.object_count,
 393                    dev_priv->mm.object_memory);
 394
 395         size = count = mappable_size = mappable_count = 0;
 396         count_objects(&dev_priv->mm.bound_list, global_list);
 397         seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
 398                    count, mappable_count, size, mappable_size);
 399
 400         size = count = mappable_size = mappable_count = 0;
 401         count_vmas(&vm->active_list, mm_list);
 402         seq_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n",
 403                    count, mappable_count, size, mappable_size);
 404
 405         size = count = mappable_size = mappable_count = 0;
 406         count_vmas(&vm->inactive_list, mm_list);
 407         seq_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n",
 408                    count, mappable_count, size, mappable_size);
 409
 410         size = count = purgeable_size = purgeable_count = 0;
 411         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 412                 size += obj->base.size, ++count;
 413                 if (obj->madv == I915_MADV_DONTNEED)
 414                         purgeable_size += obj->base.size, ++purgeable_count;
 415         }
 416         seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
 417
 418         size = count = mappable_size = mappable_count = 0;
 419         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 420                 if (obj->fault_mappable) {
 421                         size += i915_gem_obj_ggtt_size(obj);
 422                         ++count;
 423                 }
 424                 if (obj->pin_mappable) {
 425                         mappable_size += i915_gem_obj_ggtt_size(obj);
 426                         ++mappable_count;
 427                 }
 428                 if (obj->madv == I915_MADV_DONTNEED) {
 429                         purgeable_size += obj->base.size;
 430                         ++purgeable_count;
 431                 }
 432         }
 433         seq_printf(m, "%u purgeable objects, %zu bytes\n",
 434                    purgeable_count, purgeable_size);
 435         seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
 436                    mappable_count, mappable_size);
 437         seq_printf(m, "%u fault mappable objects, %zu bytes\n",
 438                    count, size);
 439
 440         seq_printf(m, "%zu [%lu] gtt total\n",
 441                    dev_priv->gtt.base.total,
 442                    dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 443
 444         seq_putc(m, '\n');
 445         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 446                 struct file_stats stats;
 447                 struct task_struct *task;
 448
 449                 memset(&stats, 0, sizeof(stats));
 450                 stats.file_priv = file->driver_priv;
 451                 spin_lock(&file->table_lock);
 452                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 453                 spin_unlock(&file->table_lock);
 454                 /*
 455                  * Although we have a valid reference on file->pid, that does
 456                  * not guarantee that the task_struct who called get_pid() is
 457                  * still alive (e.g. get_pid(current) => fork() => exit()).
 458                  * Therefore, we need to protect this ->comm access using RCU.
 459                  */
 460                 rcu_read_lock();
 461                 task = pid_task(file->pid, PIDTYPE_PID);
 462                 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
 463                            task ? task->comm : "<unknown>",
 464                            stats.count,
 465                            stats.total,
 466                            stats.active,
 467                            stats.inactive,
 468                            stats.global,
 469                            stats.shared,
 470                            stats.unbound);
 471                 rcu_read_unlock();
 472         }
 473
 474         mutex_unlock(&dev->struct_mutex);
 475
 476         return 0;
 477 }
 478
 479 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 480 {
 481         struct drm_info_node *node = m->private;
 482         struct drm_device *dev = node->minor->dev;
 483         uintptr_t list = (uintptr_t) node->info_ent->data;
 484         struct drm_i915_private *dev_priv = dev->dev_private;
 485         struct drm_i915_gem_object *obj;
 486         size_t total_obj_size, total_gtt_size;
 487         int count, ret;
 488
 489         ret = mutex_lock_interruptible(&dev->struct_mutex);
 490         if (ret)
 491                 return ret;
 492
 493         total_obj_size = total_gtt_size = count = 0;
 494         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 495                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 496                         continue;
 497
 498                 seq_puts(m, "   ");
 499                 describe_obj(m, obj);
 500                 seq_putc(m, '\n');
 501                 total_obj_size += obj->base.size;
 502                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 503                 count++;
 504         }
 505
 506         mutex_unlock(&dev->struct_mutex);
 507
 508         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 509                    count, total_obj_size, total_gtt_size);
 510
 511         return 0;
 512 }
 513
 514 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 515 {
 516         struct drm_info_node *node = m->private;
 517         struct drm_device *dev = node->minor->dev;
 518         unsigned long flags;
 519         struct intel_crtc *crtc;
 520         int ret;
 521
 522         ret = mutex_lock_interruptible(&dev->struct_mutex);
 523         if (ret)
 524                 return ret;
 525
 526         for_each_intel_crtc(dev, crtc) {
 527                 const char pipe = pipe_name(crtc->pipe);
 528                 const char plane = plane_name(crtc->plane);
 529                 struct intel_unpin_work *work;
 530
 531                 spin_lock_irqsave(&dev->event_lock, flags);
 532                 work = crtc->unpin_work;
 533                 if (work == NULL) {
 534                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 535                                    pipe, plane);
 536                 } else {
 537                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 538                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 539                                            pipe, plane);
 540                         } else {
 541                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 542                                            pipe, plane);
 543                         }
 544                         if (work->enable_stall_check)
 545                                 seq_puts(m, "Stall check enabled, ");
 546                         else
 547                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 548                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 549
 550                         if (work->old_fb_obj) {
 551                                 struct drm_i915_gem_object *obj = work->old_fb_obj;
 552                                 if (obj)
 553                                         seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
 554                                                    i915_gem_obj_ggtt_offset(obj));
 555                         }
 556                         if (work->pending_flip_obj) {
 557                                 struct drm_i915_gem_object *obj = work->pending_flip_obj;
 558                                 if (obj)
 559                                         seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
 560                                                    i915_gem_obj_ggtt_offset(obj));
 561                         }
 562                 }
 563                 spin_unlock_irqrestore(&dev->event_lock, flags);
 564         }
 565
 566         mutex_unlock(&dev->struct_mutex);
 567
 568         return 0;
 569 }
 570
 571 static int i915_gem_request_info(struct seq_file *m, void *data)
 572 {
 573         struct drm_info_node *node = m->private;
 574         struct drm_device *dev = node->minor->dev;
 575         struct drm_i915_private *dev_priv = dev->dev_private;
 576         struct intel_engine_cs *ring;
 577         struct drm_i915_gem_request *gem_request;
 578         int ret, count, i;
 579
 580         ret = mutex_lock_interruptible(&dev->struct_mutex);
 581         if (ret)
 582                 return ret;
 583
 584         count = 0;
 585         for_each_ring(ring, dev_priv, i) {
 586                 if (list_empty(&ring->request_list))
 587                         continue;
 588
 589                 seq_printf(m, "%s requests:\n", ring->name);
 590                 list_for_each_entry(gem_request,
 591                                     &ring->request_list,
 592                                     list) {
 593                         seq_printf(m, "    %d @ %d\n",
 594                                    gem_request->seqno,
 595                                    (int) (jiffies - gem_request->emitted_jiffies));
 596                 }
 597                 count++;
 598         }
 599         mutex_unlock(&dev->struct_mutex);
 600
 601         if (count == 0)
 602                 seq_puts(m, "No requests\n");
 603
 604         return 0;
 605 }
 606
 607 static void i915_ring_seqno_info(struct seq_file *m,
 608                                  struct intel_engine_cs *ring)
 609 {
 610         if (ring->get_seqno) {
 611                 seq_printf(m, "Current sequence (%s): %u\n",
 612                            ring->name, ring->get_seqno(ring, false));
 613         }
 614 }
 615
 616 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 617 {
 618         struct drm_info_node *node = m->private;
 619         struct drm_device *dev = node->minor->dev;
 620         struct drm_i915_private *dev_priv = dev->dev_private;
 621         struct intel_engine_cs *ring;
 622         int ret, i;
 623
 624         ret = mutex_lock_interruptible(&dev->struct_mutex);
 625         if (ret)
 626                 return ret;
 627         intel_runtime_pm_get(dev_priv);
 628
 629         for_each_ring(ring, dev_priv, i)
 630                 i915_ring_seqno_info(m, ring);
 631
 632         intel_runtime_pm_put(dev_priv);
 633         mutex_unlock(&dev->struct_mutex);
 634
 635         return 0;
 636 }
 637
 638
 639 static int i915_interrupt_info(struct seq_file *m, void *data)
 640 {
 641         struct drm_info_node *node = m->private;
 642         struct drm_device *dev = node->minor->dev;
 643         struct drm_i915_private *dev_priv = dev->dev_private;
 644         struct intel_engine_cs *ring;
 645         int ret, i, pipe;
 646
 647         ret = mutex_lock_interruptible(&dev->struct_mutex);
 648         if (ret)
 649                 return ret;
 650         intel_runtime_pm_get(dev_priv);
 651
 652         if (IS_CHERRYVIEW(dev)) {
 653                 int i;
 654                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 655                            I915_READ(GEN8_MASTER_IRQ));
 656
 657                 seq_printf(m, "Display IER:\t%08x\n",
 658                            I915_READ(VLV_IER));
 659                 seq_printf(m, "Display IIR:\t%08x\n",
 660                            I915_READ(VLV_IIR));
 661                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 662                            I915_READ(VLV_IIR_RW));
 663                 seq_printf(m, "Display IMR:\t%08x\n",
 664                            I915_READ(VLV_IMR));
 665                 for_each_pipe(pipe)
 666                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 667                                    pipe_name(pipe),
 668                                    I915_READ(PIPESTAT(pipe)));
 669
 670                 seq_printf(m, "Port hotplug:\t%08x\n",
 671                            I915_READ(PORT_HOTPLUG_EN));
 672                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 673                            I915_READ(VLV_DPFLIPSTAT));
 674                 seq_printf(m, "DPINVGTT:\t%08x\n",
 675                            I915_READ(DPINVGTT));
 676
 677                 for (i = 0; i < 4; i++) {
 678                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 679                                    i, I915_READ(GEN8_GT_IMR(i)));
 680                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 681                                    i, I915_READ(GEN8_GT_IIR(i)));
 682                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 683                                    i, I915_READ(GEN8_GT_IER(i)));
 684                 }
 685
 686                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 687                            I915_READ(GEN8_PCU_IMR));
 688                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 689                            I915_READ(GEN8_PCU_IIR));
 690                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 691                            I915_READ(GEN8_PCU_IER));
 692         } else if (INTEL_INFO(dev)->gen >= 8) {
 693                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 694                            I915_READ(GEN8_MASTER_IRQ));
 695
 696                 for (i = 0; i < 4; i++) {
 697                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 698                                    i, I915_READ(GEN8_GT_IMR(i)));
 699                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 700                                    i, I915_READ(GEN8_GT_IIR(i)));
 701                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 702                                    i, I915_READ(GEN8_GT_IER(i)));
 703                 }
 704
 705                 for_each_pipe(pipe) {
 706                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 707                                    pipe_name(pipe),
 708                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 709                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 710                                    pipe_name(pipe),
 711                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 712                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 713                                    pipe_name(pipe),
 714                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 715                 }
 716
 717                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 718                            I915_READ(GEN8_DE_PORT_IMR));
 719                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 720                            I915_READ(GEN8_DE_PORT_IIR));
 721                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 722                            I915_READ(GEN8_DE_PORT_IER));
 723
 724                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 725                            I915_READ(GEN8_DE_MISC_IMR));
 726                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 727                            I915_READ(GEN8_DE_MISC_IIR));
 728                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 729                            I915_READ(GEN8_DE_MISC_IER));
 730
 731                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 732                            I915_READ(GEN8_PCU_IMR));
 733                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 734                            I915_READ(GEN8_PCU_IIR));
 735                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 736                            I915_READ(GEN8_PCU_IER));
 737         } else if (IS_VALLEYVIEW(dev)) {
 738                 seq_printf(m, "Display IER:\t%08x\n",
 739                            I915_READ(VLV_IER));
 740                 seq_printf(m, "Display IIR:\t%08x\n",
 741                            I915_READ(VLV_IIR));
 742                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 743                            I915_READ(VLV_IIR_RW));
 744                 seq_printf(m, "Display IMR:\t%08x\n",
 745                            I915_READ(VLV_IMR));
 746                 for_each_pipe(pipe)
 747                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 748                                    pipe_name(pipe),
 749                                    I915_READ(PIPESTAT(pipe)));
 750
 751                 seq_printf(m, "Master IER:\t%08x\n",
 752                            I915_READ(VLV_MASTER_IER));
 753
 754                 seq_printf(m, "Render IER:\t%08x\n",
 755                            I915_READ(GTIER));
 756                 seq_printf(m, "Render IIR:\t%08x\n",
 757                            I915_READ(GTIIR));
 758                 seq_printf(m, "Render IMR:\t%08x\n",
 759                            I915_READ(GTIMR));
 760
 761                 seq_printf(m, "PM IER:\t\t%08x\n",
 762                            I915_READ(GEN6_PMIER));
 763                 seq_printf(m, "PM IIR:\t\t%08x\n",
 764                            I915_READ(GEN6_PMIIR));
 765                 seq_printf(m, "PM IMR:\t\t%08x\n",
 766                            I915_READ(GEN6_PMIMR));
 767
 768                 seq_printf(m, "Port hotplug:\t%08x\n",
 769                            I915_READ(PORT_HOTPLUG_EN));
 770                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 771                            I915_READ(VLV_DPFLIPSTAT));
 772                 seq_printf(m, "DPINVGTT:\t%08x\n",
 773                            I915_READ(DPINVGTT));
 774
 775         } else if (!HAS_PCH_SPLIT(dev)) {
 776                 seq_printf(m, "Interrupt enable:    %08x\n",
 777                            I915_READ(IER));
 778                 seq_printf(m, "Interrupt identity:  %08x\n",
 779                            I915_READ(IIR));
 780                 seq_printf(m, "Interrupt mask:      %08x\n",
 781                            I915_READ(IMR));
 782                 for_each_pipe(pipe)
 783                         seq_printf(m, "Pipe %c stat:         %08x\n",
 784                                    pipe_name(pipe),
 785                                    I915_READ(PIPESTAT(pipe)));
 786         } else {
 787                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 788                            I915_READ(DEIER));
 789                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 790                            I915_READ(DEIIR));
 791                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 792                            I915_READ(DEIMR));
 793                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 794                            I915_READ(SDEIER));
 795                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 796                            I915_READ(SDEIIR));
 797                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 798                            I915_READ(SDEIMR));
 799                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 800                            I915_READ(GTIER));
 801                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 802                            I915_READ(GTIIR));
 803                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 804                            I915_READ(GTIMR));
 805         }
 806         for_each_ring(ring, dev_priv, i) {
 807                 if (INTEL_INFO(dev)->gen >= 6) {
 808                         seq_printf(m,
 809                                    "Graphics Interrupt mask (%s):       %08x\n",
 810                                    ring->name, I915_READ_IMR(ring));
 811                 }
 812                 i915_ring_seqno_info(m, ring);
 813         }
 814         intel_runtime_pm_put(dev_priv);
 815         mutex_unlock(&dev->struct_mutex);
 816
 817         return 0;
 818 }
 819
 820 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 821 {
 822         struct drm_info_node *node = m->private;
 823         struct drm_device *dev = node->minor->dev;
 824         struct drm_i915_private *dev_priv = dev->dev_private;
 825         int i, ret;
 826
 827         ret = mutex_lock_interruptible(&dev->struct_mutex);
 828         if (ret)
 829                 return ret;
 830
 831         seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 832         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 833         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 834                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 835
 836                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 837                            i, dev_priv->fence_regs[i].pin_count);
 838                 if (obj == NULL)
 839                         seq_puts(m, "unused");
 840                 else
 841                         describe_obj(m, obj);
 842                 seq_putc(m, '\n');
 843         }
 844
 845         mutex_unlock(&dev->struct_mutex);
 846         return 0;
 847 }
 848
 849 static int i915_hws_info(struct seq_file *m, void *data)
 850 {
 851         struct drm_info_node *node = m->private;
 852         struct drm_device *dev = node->minor->dev;
 853         struct drm_i915_private *dev_priv = dev->dev_private;
 854         struct intel_engine_cs *ring;
 855         const u32 *hws;
 856         int i;
 857
 858         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 859         hws = ring->status_page.page_addr;
 860         if (hws == NULL)
 861                 return 0;
 862
 863         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 864                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 865                            i * 4,
 866                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 867         }
 868         return 0;
 869 }
 870
 871 static ssize_t
 872 i915_error_state_write(struct file *filp,
 873                        const char __user *ubuf,
 874                        size_t cnt,
 875                        loff_t *ppos)
 876 {
 877         struct i915_error_state_file_priv *error_priv = filp->private_data;
 878         struct drm_device *dev = error_priv->dev;
 879         int ret;
 880
 881         DRM_DEBUG_DRIVER("Resetting error state\n");
 882
 883         ret = mutex_lock_interruptible(&dev->struct_mutex);
 884         if (ret)
 885                 return ret;
 886
 887         i915_destroy_error_state(dev);
 888         mutex_unlock(&dev->struct_mutex);
 889
 890         return cnt;
 891 }
 892
 893 static int i915_error_state_open(struct inode *inode, struct file *file)
 894 {
 895         struct drm_device *dev = inode->i_private;
 896         struct i915_error_state_file_priv *error_priv;
 897
 898         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 899         if (!error_priv)
 900                 return -ENOMEM;
 901
 902         error_priv->dev = dev;
 903
 904         i915_error_state_get(dev, error_priv);
 905
 906         file->private_data = error_priv;
 907
 908         return 0;
 909 }
 910
 911 static int i915_error_state_release(struct inode *inode, struct file *file)
 912 {
 913         struct i915_error_state_file_priv *error_priv = file->private_data;
 914
 915         i915_error_state_put(error_priv);
 916         kfree(error_priv);
 917
 918         return 0;
 919 }
 920
 921 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
 922                                      size_t count, loff_t *pos)
 923 {
 924         struct i915_error_state_file_priv *error_priv = file->private_data;
 925         struct drm_i915_error_state_buf error_str;
 926         loff_t tmp_pos = 0;
 927         ssize_t ret_count = 0;
 928         int ret;
 929
 930         ret = i915_error_state_buf_init(&error_str, count, *pos);
 931         if (ret)
 932                 return ret;
 933
 934         ret = i915_error_state_to_str(&error_str, error_priv);
 935         if (ret)
 936                 goto out;
 937
 938         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
 939                                             error_str.buf,
 940                                             error_str.bytes);
 941
 942         if (ret_count < 0)
 943                 ret = ret_count;
 944         else
 945                 *pos = error_str.start + ret_count;
 946 out:
 947         i915_error_state_buf_release(&error_str);
 948         return ret ?: ret_count;
 949 }
 950
 951 static const struct file_operations i915_error_state_fops = {
 952         .owner = THIS_MODULE,
 953         .open = i915_error_state_open,
 954         .read = i915_error_state_read,
 955         .write = i915_error_state_write,
 956         .llseek = default_llseek,
 957         .release = i915_error_state_release,
 958 };
 959
 960 static int
 961 i915_next_seqno_get(void *data, u64 *val)
 962 {
 963         struct drm_device *dev = data;
 964         struct drm_i915_private *dev_priv = dev->dev_private;
 965         int ret;
 966
 967         ret = mutex_lock_interruptible(&dev->struct_mutex);
 968         if (ret)
 969                 return ret;
 970
 971         *val = dev_priv->next_seqno;
 972         mutex_unlock(&dev->struct_mutex);
 973
 974         return 0;
 975 }
 976
 977 static int
 978 i915_next_seqno_set(void *data, u64 val)
 979 {
 980         struct drm_device *dev = data;
 981         int ret;
 982
 983         ret = mutex_lock_interruptible(&dev->struct_mutex);
 984         if (ret)
 985                 return ret;
 986
 987         ret = i915_gem_set_seqno(dev, val);
 988         mutex_unlock(&dev->struct_mutex);
 989
 990         return ret;
 991 }
 992
 993 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
 994                         i915_next_seqno_get, i915_next_seqno_set,
 995                         "0x%llx\n");
 996
 997 static int i915_rstdby_delays(struct seq_file *m, void *unused)
 998 {
 999         struct drm_info_node *node = m->private;
1000         struct drm_device *dev = node->minor->dev;
1001         struct drm_i915_private *dev_priv = dev->dev_private;
1002         u16 crstanddelay;
1003         int ret;
1004
1005         ret = mutex_lock_interruptible(&dev->struct_mutex);
1006         if (ret)
1007                 return ret;
1008         intel_runtime_pm_get(dev_priv);
1009
1010         crstanddelay = I915_READ16(CRSTANDVID);
1011
1012         intel_runtime_pm_put(dev_priv);
1013         mutex_unlock(&dev->struct_mutex);
1014
1015         seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
1016
1017         return 0;
1018 }
1019
1020 static int i915_frequency_info(struct seq_file *m, void *unused)
1021 {
1022         struct drm_info_node *node = m->private;
1023         struct drm_device *dev = node->minor->dev;
1024         struct drm_i915_private *dev_priv = dev->dev_private;
1025         int ret = 0;
1026
1027         intel_runtime_pm_get(dev_priv);
1028
1029         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1030
1031         if (IS_GEN5(dev)) {
1032                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1033                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1034
1035                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1036                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1037                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1038                            MEMSTAT_VID_SHIFT);
1039                 seq_printf(m, "Current P-state: %d\n",
1040                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1041         } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1042                    IS_BROADWELL(dev)) {
1043                 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1044                 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1045                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1046                 u32 rpmodectl, rpinclimit, rpdeclimit;
1047                 u32 rpstat, cagf, reqf;
1048                 u32 rpupei, rpcurup, rpprevup;
1049                 u32 rpdownei, rpcurdown, rpprevdown;
1050                 int max_freq;
1051
1052                 /* RPSTAT1 is in the GT power well */
1053                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1054                 if (ret)
1055                         goto out;
1056
1057                 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
1058
1059                 reqf = I915_READ(GEN6_RPNSWREQ);
1060                 reqf &= ~GEN6_TURBO_DISABLE;
1061                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1062                         reqf >>= 24;
1063                 else
1064                         reqf >>= 25;
1065                 reqf *= GT_FREQUENCY_MULTIPLIER;
1066
1067                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1068                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1069                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1070
1071                 rpstat = I915_READ(GEN6_RPSTAT1);
1072                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1073                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1074                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1075                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1076                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1077                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1078                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1079                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1080                 else
1081                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1082                 cagf *= GT_FREQUENCY_MULTIPLIER;
1083
1084                 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
1085                 mutex_unlock(&dev->struct_mutex);
1086
1087                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1088                            I915_READ(GEN6_PMIER),
1089                            I915_READ(GEN6_PMIMR),
1090                            I915_READ(GEN6_PMISR),
1091                            I915_READ(GEN6_PMIIR),
1092                            I915_READ(GEN6_PMINTRMSK));
1093                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1094                 seq_printf(m, "Render p-state ratio: %d\n",
1095                            (gt_perf_status & 0xff00) >> 8);
1096                 seq_printf(m, "Render p-state VID: %d\n",
1097                            gt_perf_status & 0xff);
1098                 seq_printf(m, "Render p-state limit: %d\n",
1099                            rp_state_limits & 0xff);
1100                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1101                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1102                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1103                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1104                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1105                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1106                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1107                            GEN6_CURICONT_MASK);
1108                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1109                            GEN6_CURBSYTAVG_MASK);
1110                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1111                            GEN6_CURBSYTAVG_MASK);
1112                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1113                            GEN6_CURIAVG_MASK);
1114                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1115                            GEN6_CURBSYTAVG_MASK);
1116                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1117                            GEN6_CURBSYTAVG_MASK);
1118
1119                 max_freq = (rp_state_cap & 0xff0000) >> 16;
1120                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1121                            max_freq * GT_FREQUENCY_MULTIPLIER);
1122
1123                 max_freq = (rp_state_cap & 0xff00) >> 8;
1124                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1125                            max_freq * GT_FREQUENCY_MULTIPLIER);
1126
1127                 max_freq = rp_state_cap & 0xff;
1128                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1129                            max_freq * GT_FREQUENCY_MULTIPLIER);
1130
1131                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1132                            dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
1133         } else if (IS_VALLEYVIEW(dev)) {
1134                 u32 freq_sts, val;
1135
1136                 mutex_lock(&dev_priv->rps.hw_lock);
1137                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1138                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1139                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1140
1141                 val = valleyview_rps_max_freq(dev_priv);
1142                 seq_printf(m, "max GPU freq: %d MHz\n",
1143                            vlv_gpu_freq(dev_priv, val));
1144
1145                 val = valleyview_rps_min_freq(dev_priv);
1146                 seq_printf(m, "min GPU freq: %d MHz\n",
1147                            vlv_gpu_freq(dev_priv, val));
1148
1149                 seq_printf(m, "current GPU freq: %d MHz\n",
1150                            vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1151                 mutex_unlock(&dev_priv->rps.hw_lock);
1152         } else {
1153                 seq_puts(m, "no P-state info available\n");
1154         }
1155
1156 out:
1157         intel_runtime_pm_put(dev_priv);
1158         return ret;
1159 }
1160
1161 static int i915_delayfreq_table(struct seq_file *m, void *unused)
1162 {
1163         struct drm_info_node *node = m->private;
1164         struct drm_device *dev = node->minor->dev;
1165         struct drm_i915_private *dev_priv = dev->dev_private;
1166         u32 delayfreq;
1167         int ret, i;
1168
1169         ret = mutex_lock_interruptible(&dev->struct_mutex);
1170         if (ret)
1171                 return ret;
1172         intel_runtime_pm_get(dev_priv);
1173
1174         for (i = 0; i < 16; i++) {
1175                 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
1176                 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1177                            (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
1178         }
1179
1180         intel_runtime_pm_put(dev_priv);
1181
1182         mutex_unlock(&dev->struct_mutex);
1183
1184         return 0;
1185 }
1186
1187 static inline int MAP_TO_MV(int map)
1188 {
1189         return 1250 - (map * 25);
1190 }
1191
1192 static int i915_inttoext_table(struct seq_file *m, void *unused)
1193 {
1194         struct drm_info_node *node = m->private;
1195         struct drm_device *dev = node->minor->dev;
1196         struct drm_i915_private *dev_priv = dev->dev_private;
1197         u32 inttoext;
1198         int ret, i;
1199
1200         ret = mutex_lock_interruptible(&dev->struct_mutex);
1201         if (ret)
1202                 return ret;
1203         intel_runtime_pm_get(dev_priv);
1204
1205         for (i = 1; i <= 32; i++) {
1206                 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1207                 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1208         }
1209
1210         intel_runtime_pm_put(dev_priv);
1211         mutex_unlock(&dev->struct_mutex);
1212
1213         return 0;
1214 }
1215
1216 static int ironlake_drpc_info(struct seq_file *m)
1217 {
1218         struct drm_info_node *node = m->private;
1219         struct drm_device *dev = node->minor->dev;
1220         struct drm_i915_private *dev_priv = dev->dev_private;
1221         u32 rgvmodectl, rstdbyctl;
1222         u16 crstandvid;
1223         int ret;
1224
1225         ret = mutex_lock_interruptible(&dev->struct_mutex);
1226         if (ret)
1227                 return ret;
1228         intel_runtime_pm_get(dev_priv);
1229
1230         rgvmodectl = I915_READ(MEMMODECTL);
1231         rstdbyctl = I915_READ(RSTDBYCTL);
1232         crstandvid = I915_READ16(CRSTANDVID);
1233
1234         intel_runtime_pm_put(dev_priv);
1235         mutex_unlock(&dev->struct_mutex);
1236
1237         seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1238                    "yes" : "no");
1239         seq_printf(m, "Boost freq: %d\n",
1240                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1241                    MEMMODE_BOOST_FREQ_SHIFT);
1242         seq_printf(m, "HW control enabled: %s\n",
1243                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1244         seq_printf(m, "SW control enabled: %s\n",
1245                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1246         seq_printf(m, "Gated voltage change: %s\n",
1247                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1248         seq_printf(m, "Starting frequency: P%d\n",
1249                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1250         seq_printf(m, "Max P-state: P%d\n",
1251                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1252         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1253         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1254         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1255         seq_printf(m, "Render standby enabled: %s\n",
1256                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1257         seq_puts(m, "Current RS state: ");
1258         switch (rstdbyctl & RSX_STATUS_MASK) {
1259         case RSX_STATUS_ON:
1260                 seq_puts(m, "on\n");
1261                 break;
1262         case RSX_STATUS_RC1:
1263                 seq_puts(m, "RC1\n");
1264                 break;
1265         case RSX_STATUS_RC1E:
1266                 seq_puts(m, "RC1E\n");
1267                 break;
1268         case RSX_STATUS_RS1:
1269                 seq_puts(m, "RS1\n");
1270                 break;
1271         case RSX_STATUS_RS2:
1272                 seq_puts(m, "RS2 (RC6)\n");
1273                 break;
1274         case RSX_STATUS_RS3:
1275                 seq_puts(m, "RC3 (RC6+)\n");
1276                 break;
1277         default:
1278                 seq_puts(m, "unknown\n");
1279                 break;
1280         }
1281
1282         return 0;
1283 }
1284
1285 static int vlv_drpc_info(struct seq_file *m)
1286 {
1287
1288         struct drm_info_node *node = m->private;
1289         struct drm_device *dev = node->minor->dev;
1290         struct drm_i915_private *dev_priv = dev->dev_private;
1291         u32 rpmodectl1, rcctl1;
1292         unsigned fw_rendercount = 0, fw_mediacount = 0;
1293
1294         intel_runtime_pm_get(dev_priv);
1295
1296         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1297         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1298
1299         intel_runtime_pm_put(dev_priv);
1300
1301         seq_printf(m, "Video Turbo Mode: %s\n",
1302                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1303         seq_printf(m, "Turbo enabled: %s\n",
1304                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1305         seq_printf(m, "HW control enabled: %s\n",
1306                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1307         seq_printf(m, "SW control enabled: %s\n",
1308                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1309                           GEN6_RP_MEDIA_SW_MODE));
1310         seq_printf(m, "RC6 Enabled: %s\n",
1311                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1312                                         GEN6_RC_CTL_EI_MODE(1))));
1313         seq_printf(m, "Render Power Well: %s\n",
1314                         (I915_READ(VLV_GTLC_PW_STATUS) &
1315                                 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1316         seq_printf(m, "Media Power Well: %s\n",
1317                         (I915_READ(VLV_GTLC_PW_STATUS) &
1318                                 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1319
1320         seq_printf(m, "Render RC6 residency since boot: %u\n",
1321                    I915_READ(VLV_GT_RENDER_RC6));
1322         seq_printf(m, "Media RC6 residency since boot: %u\n",
1323                    I915_READ(VLV_GT_MEDIA_RC6));
1324
1325         spin_lock_irq(&dev_priv->uncore.lock);
1326         fw_rendercount = dev_priv->uncore.fw_rendercount;
1327         fw_mediacount = dev_priv->uncore.fw_mediacount;
1328         spin_unlock_irq(&dev_priv->uncore.lock);
1329
1330         seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1331         seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1332
1333
1334         return 0;
1335 }
1336
1337
1338 static int gen6_drpc_info(struct seq_file *m)
1339 {
1340
1341         struct drm_info_node *node = m->private;
1342         struct drm_device *dev = node->minor->dev;
1343         struct drm_i915_private *dev_priv = dev->dev_private;
1344         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1345         unsigned forcewake_count;
1346         int count = 0, ret;
1347
1348         ret = mutex_lock_interruptible(&dev->struct_mutex);
1349         if (ret)
1350                 return ret;
1351         intel_runtime_pm_get(dev_priv);
1352
1353         spin_lock_irq(&dev_priv->uncore.lock);
1354         forcewake_count = dev_priv->uncore.forcewake_count;
1355         spin_unlock_irq(&dev_priv->uncore.lock);
1356
1357         if (forcewake_count) {
1358                 seq_puts(m, "RC information inaccurate because somebody "
1359                             "holds a forcewake reference \n");
1360         } else {
1361                 /* NB: we cannot use forcewake, else we read the wrong values */
1362                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1363                         udelay(10);
1364                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1365         }
1366
1367         gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1368         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1369
1370         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1371         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1372         mutex_unlock(&dev->struct_mutex);
1373         mutex_lock(&dev_priv->rps.hw_lock);
1374         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1375         mutex_unlock(&dev_priv->rps.hw_lock);
1376
1377         intel_runtime_pm_put(dev_priv);
1378
1379         seq_printf(m, "Video Turbo Mode: %s\n",
1380                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1381         seq_printf(m, "HW control enabled: %s\n",
1382                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1383         seq_printf(m, "SW control enabled: %s\n",
1384                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1385                           GEN6_RP_MEDIA_SW_MODE));
1386         seq_printf(m, "RC1e Enabled: %s\n",
1387                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1388         seq_printf(m, "RC6 Enabled: %s\n",
1389                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1390         seq_printf(m, "Deep RC6 Enabled: %s\n",
1391                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1392         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1393                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1394         seq_puts(m, "Current RC state: ");
1395         switch (gt_core_status & GEN6_RCn_MASK) {
1396         case GEN6_RC0:
1397                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1398                         seq_puts(m, "Core Power Down\n");
1399                 else
1400                         seq_puts(m, "on\n");
1401                 break;
1402         case GEN6_RC3:
1403                 seq_puts(m, "RC3\n");
1404                 break;
1405         case GEN6_RC6:
1406                 seq_puts(m, "RC6\n");
1407                 break;
1408         case GEN6_RC7:
1409                 seq_puts(m, "RC7\n");
1410                 break;
1411         default:
1412                 seq_puts(m, "Unknown\n");
1413                 break;
1414         }
1415
1416         seq_printf(m, "Core Power Down: %s\n",
1417                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1418
1419         /* Not exactly sure what this is */
1420         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1421                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1422         seq_printf(m, "RC6 residency since boot: %u\n",
1423                    I915_READ(GEN6_GT_GFX_RC6));
1424         seq_printf(m, "RC6+ residency since boot: %u\n",
1425                    I915_READ(GEN6_GT_GFX_RC6p));
1426         seq_printf(m, "RC6++ residency since boot: %u\n",
1427                    I915_READ(GEN6_GT_GFX_RC6pp));
1428
1429         seq_printf(m, "RC6   voltage: %dmV\n",
1430                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1431         seq_printf(m, "RC6+  voltage: %dmV\n",
1432                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1433         seq_printf(m, "RC6++ voltage: %dmV\n",
1434                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1435         return 0;
1436 }
1437
1438 static int i915_drpc_info(struct seq_file *m, void *unused)
1439 {
1440         struct drm_info_node *node = m->private;
1441         struct drm_device *dev = node->minor->dev;
1442
1443         if (IS_VALLEYVIEW(dev))
1444                 return vlv_drpc_info(m);
1445         else if (IS_GEN6(dev) || IS_GEN7(dev))
1446                 return gen6_drpc_info(m);
1447         else
1448                 return ironlake_drpc_info(m);
1449 }
1450
1451 static int i915_fbc_status(struct seq_file *m, void *unused)
1452 {
1453         struct drm_info_node *node = m->private;
1454         struct drm_device *dev = node->minor->dev;
1455         struct drm_i915_private *dev_priv = dev->dev_private;
1456
1457         if (!HAS_FBC(dev)) {
1458                 seq_puts(m, "FBC unsupported on this chipset\n");
1459                 return 0;
1460         }
1461
1462         intel_runtime_pm_get(dev_priv);
1463
1464         if (intel_fbc_enabled(dev)) {
1465                 seq_puts(m, "FBC enabled\n");
1466         } else {
1467                 seq_puts(m, "FBC disabled: ");
1468                 switch (dev_priv->fbc.no_fbc_reason) {
1469                 case FBC_OK:
1470                         seq_puts(m, "FBC actived, but currently disabled in hardware");
1471                         break;
1472                 case FBC_UNSUPPORTED:
1473                         seq_puts(m, "unsupported by this chipset");
1474                         break;
1475                 case FBC_NO_OUTPUT:
1476                         seq_puts(m, "no outputs");
1477                         break;
1478                 case FBC_STOLEN_TOO_SMALL:
1479                         seq_puts(m, "not enough stolen memory");
1480                         break;
1481                 case FBC_UNSUPPORTED_MODE:
1482                         seq_puts(m, "mode not supported");
1483                         break;
1484                 case FBC_MODE_TOO_LARGE:
1485                         seq_puts(m, "mode too large");
1486                         break;
1487                 case FBC_BAD_PLANE:
1488                         seq_puts(m, "FBC unsupported on plane");
1489                         break;
1490                 case FBC_NOT_TILED:
1491                         seq_puts(m, "scanout buffer not tiled");
1492                         break;
1493                 case FBC_MULTIPLE_PIPES:
1494                         seq_puts(m, "multiple pipes are enabled");
1495                         break;
1496                 case FBC_MODULE_PARAM:
1497                         seq_puts(m, "disabled per module param (default off)");
1498                         break;
1499                 case FBC_CHIP_DEFAULT:
1500                         seq_puts(m, "disabled per chip default");
1501                         break;
1502                 default:
1503                         seq_puts(m, "unknown reason");
1504                 }
1505                 seq_putc(m, '\n');
1506         }
1507
1508         intel_runtime_pm_put(dev_priv);
1509
1510         return 0;
1511 }
1512
1513 static int i915_ips_status(struct seq_file *m, void *unused)
1514 {
1515         struct drm_info_node *node = m->private;
1516         struct drm_device *dev = node->minor->dev;
1517         struct drm_i915_private *dev_priv = dev->dev_private;
1518
1519         if (!HAS_IPS(dev)) {
1520                 seq_puts(m, "not supported\n");
1521                 return 0;
1522         }
1523
1524         intel_runtime_pm_get(dev_priv);
1525
1526         seq_printf(m, "Enabled by kernel parameter: %s\n",
1527                    yesno(i915.enable_ips));
1528
1529         if (INTEL_INFO(dev)->gen >= 8) {
1530                 seq_puts(m, "Currently: unknown\n");
1531         } else {
1532                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1533                         seq_puts(m, "Currently: enabled\n");
1534                 else
1535                         seq_puts(m, "Currently: disabled\n");
1536         }
1537
1538         intel_runtime_pm_put(dev_priv);
1539
1540         return 0;
1541 }
1542
1543 static int i915_sr_status(struct seq_file *m, void *unused)
1544 {
1545         struct drm_info_node *node = m->private;
1546         struct drm_device *dev = node->minor->dev;
1547         struct drm_i915_private *dev_priv = dev->dev_private;
1548         bool sr_enabled = false;
1549
1550         intel_runtime_pm_get(dev_priv);
1551
1552         if (HAS_PCH_SPLIT(dev))
1553                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1554         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1555                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1556         else if (IS_I915GM(dev))
1557                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1558         else if (IS_PINEVIEW(dev))
1559                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1560
1561         intel_runtime_pm_put(dev_priv);
1562
1563         seq_printf(m, "self-refresh: %s\n",
1564                    sr_enabled ? "enabled" : "disabled");
1565
1566         return 0;
1567 }
1568
1569 static int i915_emon_status(struct seq_file *m, void *unused)
1570 {
1571         struct drm_info_node *node = m->private;
1572         struct drm_device *dev = node->minor->dev;
1573         struct drm_i915_private *dev_priv = dev->dev_private;
1574         unsigned long temp, chipset, gfx;
1575         int ret;
1576
1577         if (!IS_GEN5(dev))
1578                 return -ENODEV;
1579
1580         ret = mutex_lock_interruptible(&dev->struct_mutex);
1581         if (ret)
1582                 return ret;
1583
1584         temp = i915_mch_val(dev_priv);
1585         chipset = i915_chipset_val(dev_priv);
1586         gfx = i915_gfx_val(dev_priv);
1587         mutex_unlock(&dev->struct_mutex);
1588
1589         seq_printf(m, "GMCH temp: %ld\n", temp);
1590         seq_printf(m, "Chipset power: %ld\n", chipset);
1591         seq_printf(m, "GFX power: %ld\n", gfx);
1592         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1593
1594         return 0;
1595 }
1596
1597 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1598 {
1599         struct drm_info_node *node = m->private;
1600         struct drm_device *dev = node->minor->dev;
1601         struct drm_i915_private *dev_priv = dev->dev_private;
1602         int ret = 0;
1603         int gpu_freq, ia_freq;
1604
1605         if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1606                 seq_puts(m, "unsupported on this chipset\n");
1607                 return 0;
1608         }
1609
1610         intel_runtime_pm_get(dev_priv);
1611
1612         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1613
1614         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1615         if (ret)
1616                 goto out;
1617
1618         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1619
1620         for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1621              gpu_freq <= dev_priv->rps.max_freq_softlimit;
1622              gpu_freq++) {
1623                 ia_freq = gpu_freq;
1624                 sandybridge_pcode_read(dev_priv,
1625                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1626                                        &ia_freq);
1627                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1628                            gpu_freq * GT_FREQUENCY_MULTIPLIER,
1629                            ((ia_freq >> 0) & 0xff) * 100,
1630                            ((ia_freq >> 8) & 0xff) * 100);
1631         }
1632
1633         mutex_unlock(&dev_priv->rps.hw_lock);
1634
1635 out:
1636         intel_runtime_pm_put(dev_priv);
1637         return ret;
1638 }
1639
1640 static int i915_gfxec(struct seq_file *m, void *unused)
1641 {
1642         struct drm_info_node *node = m->private;
1643         struct drm_device *dev = node->minor->dev;
1644         struct drm_i915_private *dev_priv = dev->dev_private;
1645         int ret;
1646
1647         ret = mutex_lock_interruptible(&dev->struct_mutex);
1648         if (ret)
1649                 return ret;
1650         intel_runtime_pm_get(dev_priv);
1651
1652         seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1653         intel_runtime_pm_put(dev_priv);
1654
1655         mutex_unlock(&dev->struct_mutex);
1656
1657         return 0;
1658 }
1659
1660 static int i915_opregion(struct seq_file *m, void *unused)
1661 {
1662         struct drm_info_node *node = m->private;
1663         struct drm_device *dev = node->minor->dev;
1664         struct drm_i915_private *dev_priv = dev->dev_private;
1665         struct intel_opregion *opregion = &dev_priv->opregion;
1666         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1667         int ret;
1668
1669         if (data == NULL)
1670                 return -ENOMEM;
1671
1672         ret = mutex_lock_interruptible(&dev->struct_mutex);
1673         if (ret)
1674                 goto out;
1675
1676         if (opregion->header) {
1677                 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1678                 seq_write(m, data, OPREGION_SIZE);
1679         }
1680
1681         mutex_unlock(&dev->struct_mutex);
1682
1683 out:
1684         kfree(data);
1685         return 0;
1686 }
1687
1688 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1689 {
1690         struct drm_info_node *node = m->private;
1691         struct drm_device *dev = node->minor->dev;
1692         struct intel_fbdev *ifbdev = NULL;
1693         struct intel_framebuffer *fb;
1694
1695 #ifdef CONFIG_DRM_I915_FBDEV
1696         struct drm_i915_private *dev_priv = dev->dev_private;
1697
1698         ifbdev = dev_priv->fbdev;
1699         fb = to_intel_framebuffer(ifbdev->helper.fb);
1700
1701         seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1702                    fb->base.width,
1703                    fb->base.height,
1704                    fb->base.depth,
1705                    fb->base.bits_per_pixel,
1706                    atomic_read(&fb->base.refcount.refcount));
1707         describe_obj(m, fb->obj);
1708         seq_putc(m, '\n');
1709 #endif
1710
1711         mutex_lock(&dev->mode_config.fb_lock);
1712         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1713                 if (ifbdev && &fb->base == ifbdev->helper.fb)
1714                         continue;
1715
1716                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1717                            fb->base.width,
1718                            fb->base.height,
1719                            fb->base.depth,
1720                            fb->base.bits_per_pixel,
1721                            atomic_read(&fb->base.refcount.refcount));
1722                 describe_obj(m, fb->obj);
1723                 seq_putc(m, '\n');
1724         }
1725         mutex_unlock(&dev->mode_config.fb_lock);
1726
1727         return 0;
1728 }
1729
1730 static int i915_context_status(struct seq_file *m, void *unused)
1731 {
1732         struct drm_info_node *node = m->private;
1733         struct drm_device *dev = node->minor->dev;
1734         struct drm_i915_private *dev_priv = dev->dev_private;
1735         struct intel_engine_cs *ring;
1736         struct intel_context *ctx;
1737         int ret, i;
1738
1739         ret = mutex_lock_interruptible(&dev->struct_mutex);
1740         if (ret)
1741                 return ret;
1742
1743         if (dev_priv->ips.pwrctx) {
1744                 seq_puts(m, "power context ");
1745                 describe_obj(m, dev_priv->ips.pwrctx);
1746                 seq_putc(m, '\n');
1747         }
1748
1749         if (dev_priv->ips.renderctx) {
1750                 seq_puts(m, "render context ");
1751                 describe_obj(m, dev_priv->ips.renderctx);
1752                 seq_putc(m, '\n');
1753         }
1754
1755         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1756                 if (ctx->obj == NULL)
1757                         continue;
1758
1759                 seq_puts(m, "HW context ");
1760                 describe_ctx(m, ctx);
1761                 for_each_ring(ring, dev_priv, i)
1762                         if (ring->default_context == ctx)
1763                                 seq_printf(m, "(default context %s) ", ring->name);
1764
1765                 describe_obj(m, ctx->obj);
1766                 seq_putc(m, '\n');
1767         }
1768
1769         mutex_unlock(&dev->struct_mutex);
1770
1771         return 0;
1772 }
1773
1774 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1775 {
1776         struct drm_info_node *node = m->private;
1777         struct drm_device *dev = node->minor->dev;
1778         struct drm_i915_private *dev_priv = dev->dev_private;
1779         unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
1780
1781         spin_lock_irq(&dev_priv->uncore.lock);
1782         if (IS_VALLEYVIEW(dev)) {
1783                 fw_rendercount = dev_priv->uncore.fw_rendercount;
1784                 fw_mediacount = dev_priv->uncore.fw_mediacount;
1785         } else
1786                 forcewake_count = dev_priv->uncore.forcewake_count;
1787         spin_unlock_irq(&dev_priv->uncore.lock);
1788
1789         if (IS_VALLEYVIEW(dev)) {
1790                 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1791                 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1792         } else
1793                 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1794
1795         return 0;
1796 }
1797
1798 static const char *swizzle_string(unsigned swizzle)
1799 {
1800         switch (swizzle) {
1801         case I915_BIT_6_SWIZZLE_NONE:
1802                 return "none";
1803         case I915_BIT_6_SWIZZLE_9:
1804                 return "bit9";
1805         case I915_BIT_6_SWIZZLE_9_10:
1806                 return "bit9/bit10";
1807         case I915_BIT_6_SWIZZLE_9_11:
1808                 return "bit9/bit11";
1809         case I915_BIT_6_SWIZZLE_9_10_11:
1810                 return "bit9/bit10/bit11";
1811         case I915_BIT_6_SWIZZLE_9_17:
1812                 return "bit9/bit17";
1813         case I915_BIT_6_SWIZZLE_9_10_17:
1814                 return "bit9/bit10/bit17";
1815         case I915_BIT_6_SWIZZLE_UNKNOWN:
1816                 return "unknown";
1817         }
1818
1819         return "bug";
1820 }
1821
1822 static int i915_swizzle_info(struct seq_file *m, void *data)
1823 {
1824         struct drm_info_node *node = m->private;
1825         struct drm_device *dev = node->minor->dev;
1826         struct drm_i915_private *dev_priv = dev->dev_private;
1827         int ret;
1828
1829         ret = mutex_lock_interruptible(&dev->struct_mutex);
1830         if (ret)
1831                 return ret;
1832         intel_runtime_pm_get(dev_priv);
1833
1834         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1835                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1836         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1837                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1838
1839         if (IS_GEN3(dev) || IS_GEN4(dev)) {
1840                 seq_printf(m, "DDC = 0x%08x\n",
1841                            I915_READ(DCC));
1842                 seq_printf(m, "C0DRB3 = 0x%04x\n",
1843                            I915_READ16(C0DRB3));
1844                 seq_printf(m, "C1DRB3 = 0x%04x\n",
1845                            I915_READ16(C1DRB3));
1846         } else if (INTEL_INFO(dev)->gen >= 6) {
1847                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1848                            I915_READ(MAD_DIMM_C0));
1849                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1850                            I915_READ(MAD_DIMM_C1));
1851                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1852                            I915_READ(MAD_DIMM_C2));
1853                 seq_printf(m, "TILECTL = 0x%08x\n",
1854                            I915_READ(TILECTL));
1855                 if (IS_GEN8(dev))
1856                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1857                                    I915_READ(GAMTARBMODE));
1858                 else
1859                         seq_printf(m, "ARB_MODE = 0x%08x\n",
1860                                    I915_READ(ARB_MODE));
1861                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1862                            I915_READ(DISP_ARB_CTL));
1863         }
1864         intel_runtime_pm_put(dev_priv);
1865         mutex_unlock(&dev->struct_mutex);
1866
1867         return 0;
1868 }
1869
1870 static int per_file_ctx(int id, void *ptr, void *data)
1871 {
1872         struct intel_context *ctx = ptr;
1873         struct seq_file *m = data;
1874         struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);
1875
1876         if (i915_gem_context_is_default(ctx))
1877                 seq_puts(m, "  default context:\n");
1878         else
1879                 seq_printf(m, "  context %d:\n", ctx->id);
1880         ppgtt->debug_dump(ppgtt, m);
1881
1882         return 0;
1883 }
1884
1885 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1886 {
1887         struct drm_i915_private *dev_priv = dev->dev_private;
1888         struct intel_engine_cs *ring;
1889         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1890         int unused, i;
1891
1892         if (!ppgtt)
1893                 return;
1894
1895         seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
1896         seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
1897         for_each_ring(ring, dev_priv, unused) {
1898                 seq_printf(m, "%s\n", ring->name);
1899                 for (i = 0; i < 4; i++) {
1900                         u32 offset = 0x270 + i * 8;
1901                         u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1902                         pdp <<= 32;
1903                         pdp |= I915_READ(ring->mmio_base + offset);
1904                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
1905                 }
1906         }
1907 }
1908
1909 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1910 {
1911         struct drm_i915_private *dev_priv = dev->dev_private;
1912         struct intel_engine_cs *ring;
1913         struct drm_file *file;
1914         int i;
1915
1916         if (INTEL_INFO(dev)->gen == 6)
1917                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1918
1919         for_each_ring(ring, dev_priv, i) {
1920                 seq_printf(m, "%s\n", ring->name);
1921                 if (INTEL_INFO(dev)->gen == 7)
1922                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1923                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1924                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1925                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1926         }
1927         if (dev_priv->mm.aliasing_ppgtt) {
1928                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1929
1930                 seq_puts(m, "aliasing PPGTT:\n");
1931                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1932
1933                 ppgtt->debug_dump(ppgtt, m);
1934         } else
1935                 return;
1936
1937         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
1938                 struct drm_i915_file_private *file_priv = file->driver_priv;
1939
1940                 seq_printf(m, "proc: %s\n",
1941                            get_pid_task(file->pid, PIDTYPE_PID)->comm);
1942                 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
1943         }
1944         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1945 }
1946
1947 static int i915_ppgtt_info(struct seq_file *m, void *data)
1948 {
1949         struct drm_info_node *node = m->private;
1950         struct drm_device *dev = node->minor->dev;
1951         struct drm_i915_private *dev_priv = dev->dev_private;
1952
1953         int ret = mutex_lock_interruptible(&dev->struct_mutex);
1954         if (ret)
1955                 return ret;
1956         intel_runtime_pm_get(dev_priv);
1957
1958         if (INTEL_INFO(dev)->gen >= 8)
1959                 gen8_ppgtt_info(m, dev);
1960         else if (INTEL_INFO(dev)->gen >= 6)
1961                 gen6_ppgtt_info(m, dev);
1962
1963         intel_runtime_pm_put(dev_priv);
1964         mutex_unlock(&dev->struct_mutex);
1965
1966         return 0;
1967 }
1968
1969 static int i915_llc(struct seq_file *m, void *data)
1970 {
1971         struct drm_info_node *node = m->private;
1972         struct drm_device *dev = node->minor->dev;
1973         struct drm_i915_private *dev_priv = dev->dev_private;
1974
1975         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1976         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1977         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1978
1979         return 0;
1980 }
1981
1982 static int i915_edp_psr_status(struct seq_file *m, void *data)
1983 {
1984         struct drm_info_node *node = m->private;
1985         struct drm_device *dev = node->minor->dev;
1986         struct drm_i915_private *dev_priv = dev->dev_private;
1987         u32 psrperf = 0;
1988         bool enabled = false;
1989
1990         intel_runtime_pm_get(dev_priv);
1991
1992         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1993         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
1994         seq_printf(m, "Enabled: %s\n", yesno(dev_priv->psr.enabled));
1995         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
1996
1997         enabled = HAS_PSR(dev) &&
1998                 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1999         seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
2000
2001         if (HAS_PSR(dev))
2002                 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2003                         EDP_PSR_PERF_CNT_MASK;
2004         seq_printf(m, "Performance_Counter: %u\n", psrperf);
2005
2006         intel_runtime_pm_put(dev_priv);
2007         return 0;
2008 }
2009
2010 static int i915_sink_crc(struct seq_file *m, void *data)
2011 {
2012         struct drm_info_node *node = m->private;
2013         struct drm_device *dev = node->minor->dev;
2014         struct intel_encoder *encoder;
2015         struct intel_connector *connector;
2016         struct intel_dp *intel_dp = NULL;
2017         int ret;
2018         u8 crc[6];
2019
2020         drm_modeset_lock_all(dev);
2021         list_for_each_entry(connector, &dev->mode_config.connector_list,
2022                             base.head) {
2023
2024                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2025                         continue;
2026
2027                 if (!connector->base.encoder)
2028                         continue;
2029
2030                 encoder = to_intel_encoder(connector->base.encoder);
2031                 if (encoder->type != INTEL_OUTPUT_EDP)
2032                         continue;
2033
2034                 intel_dp = enc_to_intel_dp(&encoder->base);
2035
2036                 ret = intel_dp_sink_crc(intel_dp, crc);
2037                 if (ret)
2038                         goto out;
2039
2040                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2041                            crc[0], crc[1], crc[2],
2042                            crc[3], crc[4], crc[5]);
2043                 goto out;
2044         }
2045         ret = -ENODEV;
2046 out:
2047         drm_modeset_unlock_all(dev);
2048         return ret;
2049 }
2050
2051 static int i915_energy_uJ(struct seq_file *m, void *data)
2052 {
2053         struct drm_info_node *node = m->private;
2054         struct drm_device *dev = node->minor->dev;
2055         struct drm_i915_private *dev_priv = dev->dev_private;
2056         u64 power;
2057         u32 units;
2058
2059         if (INTEL_INFO(dev)->gen < 6)
2060                 return -ENODEV;
2061
2062         intel_runtime_pm_get(dev_priv);
2063
2064         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2065         power = (power & 0x1f00) >> 8;
2066         units = 1000000 / (1 << power); /* convert to uJ */
2067         power = I915_READ(MCH_SECP_NRG_STTS);
2068         power *= units;
2069
2070         intel_runtime_pm_put(dev_priv);
2071
2072         seq_printf(m, "%llu", (long long unsigned)power);
2073
2074         return 0;
2075 }
2076
2077 static int i915_pc8_status(struct seq_file *m, void *unused)
2078 {
2079         struct drm_info_node *node = m->private;
2080         struct drm_device *dev = node->minor->dev;
2081         struct drm_i915_private *dev_priv = dev->dev_private;
2082
2083         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2084                 seq_puts(m, "not supported\n");
2085                 return 0;
2086         }
2087
2088         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2089         seq_printf(m, "IRQs disabled: %s\n",
2090                    yesno(dev_priv->pm.irqs_disabled));
2091
2092         return 0;
2093 }
2094
2095 static const char *power_domain_str(enum intel_display_power_domain domain)
2096 {
2097         switch (domain) {
2098         case POWER_DOMAIN_PIPE_A:
2099                 return "PIPE_A";
2100         case POWER_DOMAIN_PIPE_B:
2101                 return "PIPE_B";
2102         case POWER_DOMAIN_PIPE_C:
2103                 return "PIPE_C";
2104         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2105                 return "PIPE_A_PANEL_FITTER";
2106         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2107                 return "PIPE_B_PANEL_FITTER";
2108         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2109                 return "PIPE_C_PANEL_FITTER";
2110         case POWER_DOMAIN_TRANSCODER_A:
2111                 return "TRANSCODER_A";
2112         case POWER_DOMAIN_TRANSCODER_B:
2113                 return "TRANSCODER_B";
2114         case POWER_DOMAIN_TRANSCODER_C:
2115                 return "TRANSCODER_C";
2116         case POWER_DOMAIN_TRANSCODER_EDP:
2117                 return "TRANSCODER_EDP";
2118         case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2119                 return "PORT_DDI_A_2_LANES";
2120         case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2121                 return "PORT_DDI_A_4_LANES";
2122         case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2123                 return "PORT_DDI_B_2_LANES";
2124         case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2125                 return "PORT_DDI_B_4_LANES";
2126         case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2127                 return "PORT_DDI_C_2_LANES";
2128         case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2129                 return "PORT_DDI_C_4_LANES";
2130         case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2131                 return "PORT_DDI_D_2_LANES";
2132         case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2133                 return "PORT_DDI_D_4_LANES";
2134         case POWER_DOMAIN_PORT_DSI:
2135                 return "PORT_DSI";
2136         case POWER_DOMAIN_PORT_CRT:
2137                 return "PORT_CRT";
2138         case POWER_DOMAIN_PORT_OTHER:
2139                 return "PORT_OTHER";
2140         case POWER_DOMAIN_VGA:
2141                 return "VGA";
2142         case POWER_DOMAIN_AUDIO:
2143                 return "AUDIO";
2144         case POWER_DOMAIN_INIT:
2145                 return "INIT";
2146         default:
2147                 WARN_ON(1);
2148                 return "?";
2149         }
2150 }
2151
2152 static int i915_power_domain_info(struct seq_file *m, void *unused)
2153 {
2154         struct drm_info_node *node = m->private;
2155         struct drm_device *dev = node->minor->dev;
2156         struct drm_i915_private *dev_priv = dev->dev_private;
2157         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2158         int i;
2159
2160         mutex_lock(&power_domains->lock);
2161
2162         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2163         for (i = 0; i < power_domains->power_well_count; i++) {
2164                 struct i915_power_well *power_well;
2165                 enum intel_display_power_domain power_domain;
2166
2167                 power_well = &power_domains->power_wells[i];
2168                 seq_printf(m, "%-25s %d\n", power_well->name,
2169                            power_well->count);
2170
2171                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2172                      power_domain++) {
2173                         if (!(BIT(power_domain) & power_well->domains))
2174                                 continue;
2175
2176                         seq_printf(m, "  %-23s %d\n",
2177                                  power_domain_str(power_domain),
2178                                  power_domains->domain_use_count[power_domain]);
2179                 }
2180         }
2181
2182         mutex_unlock(&power_domains->lock);
2183
2184         return 0;
2185 }
2186
2187 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2188                                  struct drm_display_mode *mode)
2189 {
2190         int i;
2191
2192         for (i = 0; i < tabs; i++)
2193                 seq_putc(m, '\t');
2194
2195         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2196                    mode->base.id, mode->name,
2197                    mode->vrefresh, mode->clock,
2198                    mode->hdisplay, mode->hsync_start,
2199                    mode->hsync_end, mode->htotal,
2200                    mode->vdisplay, mode->vsync_start,
2201                    mode->vsync_end, mode->vtotal,
2202                    mode->type, mode->flags);
2203 }
2204
2205 static void intel_encoder_info(struct seq_file *m,
2206                                struct intel_crtc *intel_crtc,
2207                                struct intel_encoder *intel_encoder)
2208 {
2209         struct drm_info_node *node = m->private;
2210         struct drm_device *dev = node->minor->dev;
2211         struct drm_crtc *crtc = &intel_crtc->base;
2212         struct intel_connector *intel_connector;
2213         struct drm_encoder *encoder;
2214
2215         encoder = &intel_encoder->base;
2216         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2217                    encoder->base.id, encoder->name);
2218         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2219                 struct drm_connector *connector = &intel_connector->base;
2220                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2221                            connector->base.id,
2222                            connector->name,
2223                            drm_get_connector_status_name(connector->status));
2224                 if (connector->status == connector_status_connected) {
2225                         struct drm_display_mode *mode = &crtc->mode;
2226                         seq_printf(m, ", mode:\n");
2227                         intel_seq_print_mode(m, 2, mode);
2228                 } else {
2229                         seq_putc(m, '\n');
2230                 }
2231         }
2232 }
2233
2234 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2235 {
2236         struct drm_info_node *node = m->private;
2237         struct drm_device *dev = node->minor->dev;
2238         struct drm_crtc *crtc = &intel_crtc->base;
2239         struct intel_encoder *intel_encoder;
2240
2241         if (crtc->primary->fb)
2242                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2243                            crtc->primary->fb->base.id, crtc->x, crtc->y,
2244                            crtc->primary->fb->width, crtc->primary->fb->height);
2245         else
2246                 seq_puts(m, "\tprimary plane disabled\n");
2247         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2248                 intel_encoder_info(m, intel_crtc, intel_encoder);
2249 }
2250
2251 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2252 {
2253         struct drm_display_mode *mode = panel->fixed_mode;
2254
2255         seq_printf(m, "\tfixed mode:\n");
2256         intel_seq_print_mode(m, 2, mode);
2257 }
2258
2259 static void intel_dp_info(struct seq_file *m,
2260                           struct intel_connector *intel_connector)
2261 {
2262         struct intel_encoder *intel_encoder = intel_connector->encoder;
2263         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2264
2265         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2266         seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2267                    "no");
2268         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2269                 intel_panel_info(m, &intel_connector->panel);
2270 }
2271
2272 static void intel_hdmi_info(struct seq_file *m,
2273                             struct intel_connector *intel_connector)
2274 {
2275         struct intel_encoder *intel_encoder = intel_connector->encoder;
2276         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2277
2278         seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2279                    "no");
2280 }
2281
2282 static void intel_lvds_info(struct seq_file *m,
2283                             struct intel_connector *intel_connector)
2284 {
2285         intel_panel_info(m, &intel_connector->panel);
2286 }
2287
2288 static void intel_connector_info(struct seq_file *m,
2289                                  struct drm_connector *connector)
2290 {
2291         struct intel_connector *intel_connector = to_intel_connector(connector);
2292         struct intel_encoder *intel_encoder = intel_connector->encoder;
2293         struct drm_display_mode *mode;
2294
2295         seq_printf(m, "connector %d: type %s, status: %s\n",
2296                    connector->base.id, connector->name,
2297                    drm_get_connector_status_name(connector->status));
2298         if (connector->status == connector_status_connected) {
2299                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2300                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2301                            connector->display_info.width_mm,
2302                            connector->display_info.height_mm);
2303                 seq_printf(m, "\tsubpixel order: %s\n",
2304                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2305                 seq_printf(m, "\tCEA rev: %d\n",
2306                            connector->display_info.cea_rev);
2307         }
2308         if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2309             intel_encoder->type == INTEL_OUTPUT_EDP)
2310                 intel_dp_info(m, intel_connector);
2311         else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2312                 intel_hdmi_info(m, intel_connector);
2313         else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2314                 intel_lvds_info(m, intel_connector);
2315
2316         seq_printf(m, "\tmodes:\n");
2317         list_for_each_entry(mode, &connector->modes, head)
2318                 intel_seq_print_mode(m, 2, mode);
2319 }
2320
2321 static bool cursor_active(struct drm_device *dev, int pipe)
2322 {
2323         struct drm_i915_private *dev_priv = dev->dev_private;
2324         u32 state;
2325
2326         if (IS_845G(dev) || IS_I865G(dev))
2327                 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2328         else
2329                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2330
2331         return state;
2332 }
2333
2334 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2335 {
2336         struct drm_i915_private *dev_priv = dev->dev_private;
2337         u32 pos;
2338
2339         pos = I915_READ(CURPOS(pipe));
2340
2341         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2342         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2343                 *x = -*x;
2344
2345         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2346         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2347                 *y = -*y;
2348
2349         return cursor_active(dev, pipe);
2350 }
2351
2352 static int i915_display_info(struct seq_file *m, void *unused)
2353 {
2354         struct drm_info_node *node = m->private;
2355         struct drm_device *dev = node->minor->dev;
2356         struct drm_i915_private *dev_priv = dev->dev_private;
2357         struct intel_crtc *crtc;
2358         struct drm_connector *connector;
2359
2360         intel_runtime_pm_get(dev_priv);
2361         drm_modeset_lock_all(dev);
2362         seq_printf(m, "CRTC info\n");
2363         seq_printf(m, "---------\n");
2364         for_each_intel_crtc(dev, crtc) {
2365                 bool active;
2366                 int x, y;
2367
2368                 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2369                            crtc->base.base.id, pipe_name(crtc->pipe),
2370                            yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h);
2371                 if (crtc->active) {
2372                         intel_crtc_info(m, crtc);
2373
2374                         active = cursor_position(dev, crtc->pipe, &x, &y);
2375                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2376                                    yesno(crtc->cursor_base),
2377                                    x, y, crtc->cursor_width, crtc->cursor_height,
2378                                    crtc->cursor_addr, yesno(active));
2379                 }
2380
2381                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2382                            yesno(!crtc->cpu_fifo_underrun_disabled),
2383                            yesno(!crtc->pch_fifo_underrun_disabled));
2384         }
2385
2386         seq_printf(m, "\n");
2387         seq_printf(m, "Connector info\n");
2388         seq_printf(m, "--------------\n");
2389         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2390                 intel_connector_info(m, connector);
2391         }
2392         drm_modeset_unlock_all(dev);
2393         intel_runtime_pm_put(dev_priv);
2394
2395         return 0;
2396 }
2397
2398 struct pipe_crc_info {
2399         const char *name;
2400         struct drm_device *dev;
2401         enum pipe pipe;
2402 };
2403
2404 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2405 {
2406         struct pipe_crc_info *info = inode->i_private;
2407         struct drm_i915_private *dev_priv = info->dev->dev_private;
2408         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2409
2410         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2411                 return -ENODEV;
2412
2413         spin_lock_irq(&pipe_crc->lock);
2414
2415         if (pipe_crc->opened) {
2416                 spin_unlock_irq(&pipe_crc->lock);
2417                 return -EBUSY; /* already open */
2418         }
2419
2420         pipe_crc->opened = true;
2421         filep->private_data = inode->i_private;
2422
2423         spin_unlock_irq(&pipe_crc->lock);
2424
2425         return 0;
2426 }
2427
2428 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2429 {
2430         struct pipe_crc_info *info = inode->i_private;
2431         struct drm_i915_private *dev_priv = info->dev->dev_private;
2432         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2433
2434         spin_lock_irq(&pipe_crc->lock);
2435         pipe_crc->opened = false;
2436         spin_unlock_irq(&pipe_crc->lock);
2437
2438         return 0;
2439 }
2440
2441 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2442 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
2443 /* account for \'0' */
2444 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
2445
2446 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2447 {
2448         assert_spin_locked(&pipe_crc->lock);
2449         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2450                         INTEL_PIPE_CRC_ENTRIES_NR);
2451 }
2452
2453 static ssize_t
2454 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2455                    loff_t *pos)
2456 {
2457         struct pipe_crc_info *info = filep->private_data;
2458         struct drm_device *dev = info->dev;
2459         struct drm_i915_private *dev_priv = dev->dev_private;
2460         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2461         char buf[PIPE_CRC_BUFFER_LEN];
2462         int head, tail, n_entries, n;
2463         ssize_t bytes_read;
2464
2465         /*
2466          * Don't allow user space to provide buffers not big enough to hold
2467          * a line of data.
2468          */
2469         if (count < PIPE_CRC_LINE_LEN)
2470                 return -EINVAL;
2471
2472         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2473                 return 0;
2474
2475         /* nothing to read */
2476         spin_lock_irq(&pipe_crc->lock);
2477         while (pipe_crc_data_count(pipe_crc) == 0) {
2478                 int ret;
2479
2480                 if (filep->f_flags & O_NONBLOCK) {
2481                         spin_unlock_irq(&pipe_crc->lock);
2482                         return -EAGAIN;
2483                 }
2484
2485                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2486                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2487                 if (ret) {
2488                         spin_unlock_irq(&pipe_crc->lock);
2489                         return ret;
2490                 }
2491         }
2492
2493         /* We now have one or more entries to read */
2494         head = pipe_crc->head;
2495         tail = pipe_crc->tail;
2496         n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2497                         count / PIPE_CRC_LINE_LEN);
2498         spin_unlock_irq(&pipe_crc->lock);
2499
2500         bytes_read = 0;
2501         n = 0;
2502         do {
2503                 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
2504                 int ret;
2505
2506                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2507                                        "%8u %8x %8x %8x %8x %8x\n",
2508                                        entry->frame, entry->crc[0],
2509                                        entry->crc[1], entry->crc[2],
2510                                        entry->crc[3], entry->crc[4]);
2511
2512                 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2513                                    buf, PIPE_CRC_LINE_LEN);
2514                 if (ret == PIPE_CRC_LINE_LEN)
2515                         return -EFAULT;
2516
2517                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2518                 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2519                 n++;
2520         } while (--n_entries);
2521
2522         spin_lock_irq(&pipe_crc->lock);
2523         pipe_crc->tail = tail;
2524         spin_unlock_irq(&pipe_crc->lock);
2525
2526         return bytes_read;
2527 }
2528
2529 static const struct file_operations i915_pipe_crc_fops = {
2530         .owner = THIS_MODULE,
2531         .open = i915_pipe_crc_open,
2532         .read = i915_pipe_crc_read,
2533         .release = i915_pipe_crc_release,
2534 };
2535
2536 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2537         {
2538                 .name = "i915_pipe_A_crc",
2539                 .pipe = PIPE_A,
2540         },
2541         {
2542                 .name = "i915_pipe_B_crc",
2543                 .pipe = PIPE_B,
2544         },
2545         {
2546                 .name = "i915_pipe_C_crc",
2547                 .pipe = PIPE_C,
2548         },
2549 };
2550
2551 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2552                                 enum pipe pipe)
2553 {
2554         struct drm_device *dev = minor->dev;
2555         struct dentry *ent;
2556         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2557
2558         info->dev = dev;
2559         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2560                                   &i915_pipe_crc_fops);
2561         if (!ent)
2562                 return -ENOMEM;
2563
2564         return drm_add_fake_info_node(minor, ent, info);
2565 }
2566
2567 static const char * const pipe_crc_sources[] = {
2568         "none",
2569         "plane1",
2570         "plane2",
2571         "pf",
2572         "pipe",
2573         "TV",
2574         "DP-B",
2575         "DP-C",
2576         "DP-D",
2577         "auto",
2578 };
2579
2580 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2581 {
2582         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2583         return pipe_crc_sources[source];
2584 }
2585
2586 static int display_crc_ctl_show(struct seq_file *m, void *data)
2587 {
2588         struct drm_device *dev = m->private;
2589         struct drm_i915_private *dev_priv = dev->dev_private;
2590         int i;
2591
2592         for (i = 0; i < I915_MAX_PIPES; i++)
2593                 seq_printf(m, "%c %s\n", pipe_name(i),
2594                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2595
2596         return 0;
2597 }
2598
2599 static int display_crc_ctl_open(struct inode *inode, struct file *file)
2600 {
2601         struct drm_device *dev = inode->i_private;
2602
2603         return single_open(file, display_crc_ctl_show, dev);
2604 }
2605
2606 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2607                                  uint32_t *val)
2608 {
2609         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2610                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2611
2612         switch (*source) {
2613         case INTEL_PIPE_CRC_SOURCE_PIPE:
2614                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2615                 break;
2616         case INTEL_PIPE_CRC_SOURCE_NONE:
2617                 *val = 0;
2618                 break;
2619         default:
2620                 return -EINVAL;
2621         }
2622
2623         return 0;
2624 }
2625
2626 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2627                                      enum intel_pipe_crc_source *source)
2628 {
2629         struct intel_encoder *encoder;
2630         struct intel_crtc *crtc;
2631         struct intel_digital_port *dig_port;
2632         int ret = 0;
2633
2634         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2635
2636         drm_modeset_lock_all(dev);
2637         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2638                             base.head) {
2639                 if (!encoder->base.crtc)
2640                         continue;
2641
2642                 crtc = to_intel_crtc(encoder->base.crtc);
2643
2644                 if (crtc->pipe != pipe)
2645                         continue;
2646
2647                 switch (encoder->type) {
2648                 case INTEL_OUTPUT_TVOUT:
2649                         *source = INTEL_PIPE_CRC_SOURCE_TV;
2650                         break;
2651                 case INTEL_OUTPUT_DISPLAYPORT:
2652                 case INTEL_OUTPUT_EDP:
2653                         dig_port = enc_to_dig_port(&encoder->base);
2654                         switch (dig_port->port) {
2655                         case PORT_B:
2656                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2657                                 break;
2658                         case PORT_C:
2659                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2660                                 break;
2661                         case PORT_D:
2662                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2663                                 break;
2664                         default:
2665                                 WARN(1, "nonexisting DP port %c\n",
2666                                      port_name(dig_port->port));
2667                                 break;
2668                         }
2669                         break;
2670                 }
2671         }
2672         drm_modeset_unlock_all(dev);
2673
2674         return ret;
2675 }
2676
2677 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2678                                 enum pipe pipe,
2679                                 enum intel_pipe_crc_source *source,
2680                                 uint32_t *val)
2681 {
2682         struct drm_i915_private *dev_priv = dev->dev_private;
2683         bool need_stable_symbols = false;
2684
2685         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2686                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2687                 if (ret)
2688                         return ret;
2689         }
2690
2691         switch (*source) {
2692         case INTEL_PIPE_CRC_SOURCE_PIPE:
2693                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2694                 break;
2695         case INTEL_PIPE_CRC_SOURCE_DP_B:
2696                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
2697                 need_stable_symbols = true;
2698                 break;
2699         case INTEL_PIPE_CRC_SOURCE_DP_C:
2700                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
2701                 need_stable_symbols = true;
2702                 break;
2703         case INTEL_PIPE_CRC_SOURCE_NONE:
2704                 *val = 0;
2705                 break;
2706         default:
2707                 return -EINVAL;
2708         }
2709
2710         /*
2711          * When the pipe CRC tap point is after the transcoders we need
2712          * to tweak symbol-level features to produce a deterministic series of
2713          * symbols for a given frame. We need to reset those features only once
2714          * a frame (instead of every nth symbol):
2715          *   - DC-balance: used to ensure a better clock recovery from the data
2716          *     link (SDVO)
2717          *   - DisplayPort scrambling: used for EMI reduction
2718          */
2719         if (need_stable_symbols) {
2720                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2721
2722                 tmp |= DC_BALANCE_RESET_VLV;
2723                 if (pipe == PIPE_A)
2724                         tmp |= PIPE_A_SCRAMBLE_RESET;
2725                 else
2726                         tmp |= PIPE_B_SCRAMBLE_RESET;
2727
2728                 I915_WRITE(PORT_DFT2_G4X, tmp);
2729         }
2730
2731         return 0;
2732 }
2733
2734 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
2735                                  enum pipe pipe,
2736                                  enum intel_pipe_crc_source *source,
2737                                  uint32_t *val)
2738 {
2739         struct drm_i915_private *dev_priv = dev->dev_private;
2740         bool need_stable_symbols = false;
2741
2742         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2743                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2744                 if (ret)
2745                         return ret;
2746         }
2747
2748         switch (*source) {
2749         case INTEL_PIPE_CRC_SOURCE_PIPE:
2750                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2751                 break;
2752         case INTEL_PIPE_CRC_SOURCE_TV:
2753                 if (!SUPPORTS_TV(dev))
2754                         return -EINVAL;
2755                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2756                 break;
2757         case INTEL_PIPE_CRC_SOURCE_DP_B:
2758                 if (!IS_G4X(dev))
2759                         return -EINVAL;
2760                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
2761                 need_stable_symbols = true;
2762                 break;
2763         case INTEL_PIPE_CRC_SOURCE_DP_C:
2764                 if (!IS_G4X(dev))
2765                         return -EINVAL;
2766                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
2767                 need_stable_symbols = true;
2768                 break;
2769         case INTEL_PIPE_CRC_SOURCE_DP_D:
2770                 if (!IS_G4X(dev))
2771                         return -EINVAL;
2772                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
2773                 need_stable_symbols = true;
2774                 break;
2775         case INTEL_PIPE_CRC_SOURCE_NONE:
2776                 *val = 0;
2777                 break;
2778         default:
2779                 return -EINVAL;
2780         }
2781
2782         /*
2783          * When the pipe CRC tap point is after the transcoders we need
2784          * to tweak symbol-level features to produce a deterministic series of
2785          * symbols for a given frame. We need to reset those features only once
2786          * a frame (instead of every nth symbol):
2787          *   - DC-balance: used to ensure a better clock recovery from the data
2788          *     link (SDVO)
2789          *   - DisplayPort scrambling: used for EMI reduction
2790          */
2791         if (need_stable_symbols) {
2792                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2793
2794                 WARN_ON(!IS_G4X(dev));
2795
2796                 I915_WRITE(PORT_DFT_I9XX,
2797                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2798
2799                 if (pipe == PIPE_A)
2800                         tmp |= PIPE_A_SCRAMBLE_RESET;
2801                 else
2802                         tmp |= PIPE_B_SCRAMBLE_RESET;
2803
2804                 I915_WRITE(PORT_DFT2_G4X, tmp);
2805         }
2806
2807         return 0;
2808 }
2809
2810 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2811                                          enum pipe pipe)
2812 {
2813         struct drm_i915_private *dev_priv = dev->dev_private;
2814         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2815
2816         if (pipe == PIPE_A)
2817                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2818         else
2819                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2820         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2821                 tmp &= ~DC_BALANCE_RESET_VLV;
2822         I915_WRITE(PORT_DFT2_G4X, tmp);
2823
2824 }
2825
2826 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2827                                          enum pipe pipe)
2828 {
2829         struct drm_i915_private *dev_priv = dev->dev_private;
2830         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2831
2832         if (pipe == PIPE_A)
2833                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2834         else
2835                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2836         I915_WRITE(PORT_DFT2_G4X, tmp);
2837
2838         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2839                 I915_WRITE(PORT_DFT_I9XX,
2840                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2841         }
2842 }
2843
2844 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2845                                 uint32_t *val)
2846 {
2847         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2848                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2849
2850         switch (*source) {
2851         case INTEL_PIPE_CRC_SOURCE_PLANE1:
2852                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2853                 break;
2854         case INTEL_PIPE_CRC_SOURCE_PLANE2:
2855                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2856                 break;
2857         case INTEL_PIPE_CRC_SOURCE_PIPE:
2858                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2859                 break;
2860         case INTEL_PIPE_CRC_SOURCE_NONE:
2861                 *val = 0;
2862                 break;
2863         default:
2864                 return -EINVAL;
2865         }
2866
2867         return 0;
2868 }
2869
2870 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
2871 {
2872         struct drm_i915_private *dev_priv = dev->dev_private;
2873         struct intel_crtc *crtc =
2874                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
2875
2876         drm_modeset_lock_all(dev);
2877         /*
2878          * If we use the eDP transcoder we need to make sure that we don't
2879          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
2880          * relevant on hsw with pipe A when using the always-on power well
2881          * routing.
2882          */
2883         if (crtc->config.cpu_transcoder == TRANSCODER_EDP &&
2884             !crtc->config.pch_pfit.enabled) {
2885                 crtc->config.pch_pfit.force_thru = true;
2886
2887                 intel_display_power_get(dev_priv,
2888                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
2889
2890                 dev_priv->display.crtc_disable(&crtc->base);
2891                 dev_priv->display.crtc_enable(&crtc->base);
2892         }
2893         drm_modeset_unlock_all(dev);
2894 }
2895
2896 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
2897 {
2898         struct drm_i915_private *dev_priv = dev->dev_private;
2899         struct intel_crtc *crtc =
2900                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
2901
2902         drm_modeset_lock_all(dev);
2903         /*
2904          * If we use the eDP transcoder we need to make sure that we don't
2905          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
2906          * relevant on hsw with pipe A when using the always-on power well
2907          * routing.
2908          */
2909         if (crtc->config.pch_pfit.force_thru) {
2910                 crtc->config.pch_pfit.force_thru = false;
2911
2912                 dev_priv->display.crtc_disable(&crtc->base);
2913                 dev_priv->display.crtc_enable(&crtc->base);
2914
2915                 intel_display_power_put(dev_priv,
2916                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
2917         }
2918         drm_modeset_unlock_all(dev);
2919 }
2920
2921 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
2922                                 enum pipe pipe,
2923                                 enum intel_pipe_crc_source *source,
2924                                 uint32_t *val)
2925 {
2926         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2927                 *source = INTEL_PIPE_CRC_SOURCE_PF;
2928
2929         switch (*source) {
2930         case INTEL_PIPE_CRC_SOURCE_PLANE1:
2931                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2932                 break;
2933         case INTEL_PIPE_CRC_SOURCE_PLANE2:
2934                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2935                 break;
2936         case INTEL_PIPE_CRC_SOURCE_PF:
2937                 if (IS_HASWELL(dev) && pipe == PIPE_A)
2938                         hsw_trans_edp_pipe_A_crc_wa(dev);
2939
2940                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2941                 break;
2942         case INTEL_PIPE_CRC_SOURCE_NONE:
2943                 *val = 0;
2944                 break;
2945         default:
2946                 return -EINVAL;
2947         }
2948
2949         return 0;
2950 }
2951
2952 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2953                                enum intel_pipe_crc_source source)
2954 {
2955         struct drm_i915_private *dev_priv = dev->dev_private;
2956         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
2957         u32 val = 0; /* shut up gcc */
2958         int ret;
2959
2960         if (pipe_crc->source == source)
2961                 return 0;
2962
2963         /* forbid changing the source without going back to 'none' */
2964         if (pipe_crc->source && source)
2965                 return -EINVAL;
2966
2967         if (IS_GEN2(dev))
2968                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
2969         else if (INTEL_INFO(dev)->gen < 5)
2970                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
2971         else if (IS_VALLEYVIEW(dev))
2972                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
2973         else if (IS_GEN5(dev) || IS_GEN6(dev))
2974                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
2975         else
2976                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
2977
2978         if (ret != 0)
2979                 return ret;
2980
2981         /* none -> real source transition */
2982         if (source) {
2983                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2984                                  pipe_name(pipe), pipe_crc_source_name(source));
2985
2986                 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2987                                             INTEL_PIPE_CRC_ENTRIES_NR,
2988                                             GFP_KERNEL);
2989                 if (!pipe_crc->entries)
2990                         return -ENOMEM;
2991
2992                 spin_lock_irq(&pipe_crc->lock);
2993                 pipe_crc->head = 0;
2994                 pipe_crc->tail = 0;
2995                 spin_unlock_irq(&pipe_crc->lock);
2996         }
2997
2998         pipe_crc->source = source;
2999
3000         I915_WRITE(PIPE_CRC_CTL(pipe), val);
3001         POSTING_READ(PIPE_CRC_CTL(pipe));
3002
3003         /* real source -> none transition */
3004         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3005                 struct intel_pipe_crc_entry *entries;
3006                 struct intel_crtc *crtc =
3007                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3008
3009                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3010                                  pipe_name(pipe));
3011
3012                 drm_modeset_lock(&crtc->base.mutex, NULL);
3013                 if (crtc->active)
3014                         intel_wait_for_vblank(dev, pipe);
3015                 drm_modeset_unlock(&crtc->base.mutex);
3016
3017                 spin_lock_irq(&pipe_crc->lock);
3018                 entries = pipe_crc->entries;
3019                 pipe_crc->entries = NULL;
3020                 spin_unlock_irq(&pipe_crc->lock);
3021
3022                 kfree(entries);
3023
3024                 if (IS_G4X(dev))
3025                         g4x_undo_pipe_scramble_reset(dev, pipe);
3026                 else if (IS_VALLEYVIEW(dev))
3027                         vlv_undo_pipe_scramble_reset(dev, pipe);
3028                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3029                         hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3030         }
3031
3032         return 0;
3033 }
3034
3035 /*
3036  * Parse pipe CRC command strings:
3037  *   command: wsp* object wsp+ name wsp+ source wsp*
3038  *   object: 'pipe'
3039  *   name: (A | B | C)
3040  *   source: (none | plane1 | plane2 | pf)
3041  *   wsp: (#0x20 | #0x9 | #0xA)+
3042  *
3043  * eg.:
3044  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
3045  *  "pipe A none"    ->  Stop CRC
3046  */
3047 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3048 {
3049         int n_words = 0;
3050
3051         while (*buf) {
3052                 char *end;
3053
3054                 /* skip leading white space */
3055                 buf = skip_spaces(buf);
3056                 if (!*buf)
3057                         break;  /* end of buffer */
3058
3059                 /* find end of word */
3060                 for (end = buf; *end && !isspace(*end); end++)
3061                         ;
3062
3063                 if (n_words == max_words) {
3064                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3065                                          max_words);
3066                         return -EINVAL; /* ran out of words[] before bytes */
3067                 }
3068
3069                 if (*end)
3070                         *end++ = '\0';
3071                 words[n_words++] = buf;
3072                 buf = end;
3073         }
3074
3075         return n_words;
3076 }
3077
3078 enum intel_pipe_crc_object {
3079         PIPE_CRC_OBJECT_PIPE,
3080 };
3081
3082 static const char * const pipe_crc_objects[] = {
3083         "pipe",
3084 };
3085
3086 static int
3087 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3088 {
3089         int i;
3090
3091         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3092                 if (!strcmp(buf, pipe_crc_objects[i])) {
3093                         *o = i;
3094                         return 0;
3095                     }
3096
3097         return -EINVAL;
3098 }
3099
3100 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3101 {
3102         const char name = buf[0];
3103
3104         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3105                 return -EINVAL;
3106
3107         *pipe = name - 'A';
3108
3109         return 0;
3110 }
3111
3112 static int
3113 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3114 {
3115         int i;
3116
3117         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3118                 if (!strcmp(buf, pipe_crc_sources[i])) {
3119                         *s = i;
3120                         return 0;
3121                     }
3122
3123         return -EINVAL;
3124 }
3125
3126 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3127 {
3128 #define N_WORDS 3
3129         int n_words;
3130         char *words[N_WORDS];
3131         enum pipe pipe;
3132         enum intel_pipe_crc_object object;
3133         enum intel_pipe_crc_source source;
3134
3135         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3136         if (n_words != N_WORDS) {
3137                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3138                                  N_WORDS);
3139                 return -EINVAL;
3140         }
3141
3142         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3143                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3144                 return -EINVAL;
3145         }
3146
3147         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3148                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3149                 return -EINVAL;
3150         }
3151
3152         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3153                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3154                 return -EINVAL;
3155         }
3156
3157         return pipe_crc_set_source(dev, pipe, source);
3158 }
3159
3160 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3161                                      size_t len, loff_t *offp)
3162 {
3163         struct seq_file *m = file->private_data;
3164         struct drm_device *dev = m->private;
3165         char *tmpbuf;
3166         int ret;
3167
3168         if (len == 0)
3169                 return 0;
3170
3171         if (len > PAGE_SIZE - 1) {
3172                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3173                                  PAGE_SIZE);
3174                 return -E2BIG;
3175         }
3176
3177         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3178         if (!tmpbuf)
3179                 return -ENOMEM;
3180
3181         if (copy_from_user(tmpbuf, ubuf, len)) {
3182                 ret = -EFAULT;
3183                 goto out;
3184         }
3185         tmpbuf[len] = '\0';
3186
3187         ret = display_crc_ctl_parse(dev, tmpbuf, len);
3188
3189 out:
3190         kfree(tmpbuf);
3191         if (ret < 0)
3192                 return ret;
3193
3194         *offp += len;
3195         return len;
3196 }
3197
3198 static const struct file_operations i915_display_crc_ctl_fops = {
3199         .owner = THIS_MODULE,
3200         .open = display_crc_ctl_open,
3201         .read = seq_read,
3202         .llseek = seq_lseek,
3203         .release = single_release,
3204         .write = display_crc_ctl_write
3205 };
3206
3207 static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
3208 {
3209         struct drm_device *dev = m->private;
3210         int num_levels = ilk_wm_max_level(dev) + 1;
3211         int level;
3212
3213         drm_modeset_lock_all(dev);
3214
3215         for (level = 0; level < num_levels; level++) {
3216                 unsigned int latency = wm[level];
3217
3218                 /* WM1+ latency values in 0.5us units */
3219                 if (level > 0)
3220                         latency *= 5;
3221
3222                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3223                            level, wm[level],
3224                            latency / 10, latency % 10);
3225         }
3226
3227         drm_modeset_unlock_all(dev);
3228 }
3229
3230 static int pri_wm_latency_show(struct seq_file *m, void *data)
3231 {
3232         struct drm_device *dev = m->private;
3233
3234         wm_latency_show(m, to_i915(dev)->wm.pri_latency);
3235
3236         return 0;
3237 }
3238
3239 static int spr_wm_latency_show(struct seq_file *m, void *data)
3240 {
3241         struct drm_device *dev = m->private;
3242
3243         wm_latency_show(m, to_i915(dev)->wm.spr_latency);
3244
3245         return 0;
3246 }
3247
3248 static int cur_wm_latency_show(struct seq_file *m, void *data)
3249 {
3250         struct drm_device *dev = m->private;
3251
3252         wm_latency_show(m, to_i915(dev)->wm.cur_latency);
3253
3254         return 0;
3255 }
3256
3257 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3258 {
3259         struct drm_device *dev = inode->i_private;
3260
3261         if (!HAS_PCH_SPLIT(dev))
3262                 return -ENODEV;
3263
3264         return single_open(file, pri_wm_latency_show, dev);
3265 }
3266
3267 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3268 {
3269         struct drm_device *dev = inode->i_private;
3270
3271         if (!HAS_PCH_SPLIT(dev))
3272                 return -ENODEV;
3273
3274         return single_open(file, spr_wm_latency_show, dev);
3275 }
3276
3277 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3278 {
3279         struct drm_device *dev = inode->i_private;
3280
3281         if (!HAS_PCH_SPLIT(dev))
3282                 return -ENODEV;
3283
3284         return single_open(file, cur_wm_latency_show, dev);
3285 }
3286
3287 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3288                                 size_t len, loff_t *offp, uint16_t wm[5])
3289 {
3290         struct seq_file *m = file->private_data;
3291         struct drm_device *dev = m->private;
3292         uint16_t new[5] = { 0 };
3293         int num_levels = ilk_wm_max_level(dev) + 1;
3294         int level;
3295         int ret;
3296         char tmp[32];
3297
3298         if (len >= sizeof(tmp))
3299                 return -EINVAL;
3300
3301         if (copy_from_user(tmp, ubuf, len))
3302                 return -EFAULT;
3303
3304         tmp[len] = '\0';
3305
3306         ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3307         if (ret != num_levels)
3308                 return -EINVAL;
3309
3310         drm_modeset_lock_all(dev);
3311
3312         for (level = 0; level < num_levels; level++)
3313                 wm[level] = new[level];
3314
3315         drm_modeset_unlock_all(dev);
3316
3317         return len;
3318 }
3319
3320
3321 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3322                                     size_t len, loff_t *offp)
3323 {
3324         struct seq_file *m = file->private_data;
3325         struct drm_device *dev = m->private;
3326
3327         return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
3328 }
3329
3330 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3331                                     size_t len, loff_t *offp)
3332 {
3333         struct seq_file *m = file->private_data;
3334         struct drm_device *dev = m->private;
3335
3336         return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
3337 }
3338
3339 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3340                                     size_t len, loff_t *offp)
3341 {
3342         struct seq_file *m = file->private_data;
3343         struct drm_device *dev = m->private;
3344
3345         return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
3346 }
3347
3348 static const struct file_operations i915_pri_wm_latency_fops = {
3349         .owner = THIS_MODULE,
3350         .open = pri_wm_latency_open,
3351         .read = seq_read,
3352         .llseek = seq_lseek,
3353         .release = single_release,
3354         .write = pri_wm_latency_write
3355 };
3356
3357 static const struct file_operations i915_spr_wm_latency_fops = {
3358         .owner = THIS_MODULE,
3359         .open = spr_wm_latency_open,
3360         .read = seq_read,
3361         .llseek = seq_lseek,
3362         .release = single_release,
3363         .write = spr_wm_latency_write
3364 };
3365
3366 static const struct file_operations i915_cur_wm_latency_fops = {
3367         .owner = THIS_MODULE,
3368         .open = cur_wm_latency_open,
3369         .read = seq_read,
3370         .llseek = seq_lseek,
3371         .release = single_release,
3372         .write = cur_wm_latency_write
3373 };
3374
3375 static int
3376 i915_wedged_get(void *data, u64 *val)
3377 {
3378         struct drm_device *dev = data;
3379         struct drm_i915_private *dev_priv = dev->dev_private;
3380
3381         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
3382
3383         return 0;
3384 }
3385
3386 static int
3387 i915_wedged_set(void *data, u64 val)
3388 {
3389         struct drm_device *dev = data;
3390         struct drm_i915_private *dev_priv = dev->dev_private;
3391
3392         intel_runtime_pm_get(dev_priv);
3393
3394         i915_handle_error(dev, val,
3395                           "Manually setting wedged to %llu", val);
3396
3397         intel_runtime_pm_put(dev_priv);
3398
3399         return 0;
3400 }
3401
3402 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3403                         i915_wedged_get, i915_wedged_set,
3404                         "%llu\n");
3405
3406 static int
3407 i915_ring_stop_get(void *data, u64 *val)
3408 {
3409         struct drm_device *dev = data;
3410         struct drm_i915_private *dev_priv = dev->dev_private;
3411
3412         *val = dev_priv->gpu_error.stop_rings;
3413
3414         return 0;
3415 }
3416
3417 static int
3418 i915_ring_stop_set(void *data, u64 val)
3419 {
3420         struct drm_device *dev = data;
3421         struct drm_i915_private *dev_priv = dev->dev_private;
3422         int ret;
3423
3424         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
3425
3426         ret = mutex_lock_interruptible(&dev->struct_mutex);
3427         if (ret)
3428                 return ret;
3429
3430         dev_priv->gpu_error.stop_rings = val;
3431         mutex_unlock(&dev->struct_mutex);
3432
3433         return 0;
3434 }
3435
3436 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3437                         i915_ring_stop_get, i915_ring_stop_set,
3438                         "0x%08llx\n");
3439
3440 static int
3441 i915_ring_missed_irq_get(void *data, u64 *val)
3442 {
3443         struct drm_device *dev = data;
3444         struct drm_i915_private *dev_priv = dev->dev_private;
3445
3446         *val = dev_priv->gpu_error.missed_irq_rings;
3447         return 0;
3448 }
3449
3450 static int
3451 i915_ring_missed_irq_set(void *data, u64 val)
3452 {
3453         struct drm_device *dev = data;
3454         struct drm_i915_private *dev_priv = dev->dev_private;
3455         int ret;
3456
3457         /* Lock against concurrent debugfs callers */
3458         ret = mutex_lock_interruptible(&dev->struct_mutex);
3459         if (ret)
3460                 return ret;
3461         dev_priv->gpu_error.missed_irq_rings = val;
3462         mutex_unlock(&dev->struct_mutex);
3463
3464         return 0;
3465 }
3466
3467 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3468                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3469                         "0x%08llx\n");
3470
3471 static int
3472 i915_ring_test_irq_get(void *data, u64 *val)
3473 {
3474         struct drm_device *dev = data;
3475         struct drm_i915_private *dev_priv = dev->dev_private;
3476
3477         *val = dev_priv->gpu_error.test_irq_rings;
3478
3479         return 0;
3480 }
3481
3482 static int
3483 i915_ring_test_irq_set(void *data, u64 val)
3484 {
3485         struct drm_device *dev = data;
3486         struct drm_i915_private *dev_priv = dev->dev_private;
3487         int ret;
3488
3489         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3490
3491         /* Lock against concurrent debugfs callers */
3492         ret = mutex_lock_interruptible(&dev->struct_mutex);
3493         if (ret)
3494                 return ret;
3495
3496         dev_priv->gpu_error.test_irq_rings = val;
3497         mutex_unlock(&dev->struct_mutex);
3498
3499         return 0;
3500 }
3501
3502 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3503                         i915_ring_test_irq_get, i915_ring_test_irq_set,
3504                         "0x%08llx\n");
3505
3506 #define DROP_UNBOUND 0x1
3507 #define DROP_BOUND 0x2
3508 #define DROP_RETIRE 0x4
3509 #define DROP_ACTIVE 0x8
3510 #define DROP_ALL (DROP_UNBOUND | \
3511                   DROP_BOUND | \
3512                   DROP_RETIRE | \
3513                   DROP_ACTIVE)
3514 static int
3515 i915_drop_caches_get(void *data, u64 *val)
3516 {
3517         *val = DROP_ALL;
3518
3519         return 0;
3520 }
3521
3522 static int
3523 i915_drop_caches_set(void *data, u64 val)
3524 {
3525         struct drm_device *dev = data;
3526         struct drm_i915_private *dev_priv = dev->dev_private;
3527         struct drm_i915_gem_object *obj, *next;
3528         struct i915_address_space *vm;
3529         struct i915_vma *vma, *x;
3530         int ret;
3531
3532         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
3533
3534         /* No need to check and wait for gpu resets, only libdrm auto-restarts
3535          * on ioctls on -EAGAIN. */
3536         ret = mutex_lock_interruptible(&dev->struct_mutex);
3537         if (ret)
3538                 return ret;
3539
3540         if (val & DROP_ACTIVE) {
3541                 ret = i915_gpu_idle(dev);
3542                 if (ret)
3543                         goto unlock;
3544         }
3545
3546         if (val & (DROP_RETIRE | DROP_ACTIVE))
3547                 i915_gem_retire_requests(dev);
3548
3549         if (val & DROP_BOUND) {
3550                 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3551                         list_for_each_entry_safe(vma, x, &vm->inactive_list,
3552                                                  mm_list) {
3553                                 if (vma->pin_count)
3554                                         continue;
3555
3556                                 ret = i915_vma_unbind(vma);
3557                                 if (ret)
3558                                         goto unlock;
3559                         }
3560                 }
3561         }
3562
3563         if (val & DROP_UNBOUND) {
3564                 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
3565                                          global_list)
3566                         if (obj->pages_pin_count == 0) {
3567                                 ret = i915_gem_object_put_pages(obj);
3568                                 if (ret)
3569                                         goto unlock;
3570                         }
3571         }
3572
3573 unlock:
3574         mutex_unlock(&dev->struct_mutex);
3575
3576         return ret;
3577 }
3578
3579 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3580                         i915_drop_caches_get, i915_drop_caches_set,
3581                         "0x%08llx\n");
3582
3583 static int
3584 i915_max_freq_get(void *data, u64 *val)
3585 {
3586         struct drm_device *dev = data;
3587         struct drm_i915_private *dev_priv = dev->dev_private;
3588         int ret;
3589
3590         if (INTEL_INFO(dev)->gen < 6)
3591                 return -ENODEV;
3592
3593         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3594
3595         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3596         if (ret)
3597                 return ret;
3598
3599         if (IS_VALLEYVIEW(dev))
3600                 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
3601         else
3602                 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
3603         mutex_unlock(&dev_priv->rps.hw_lock);
3604
3605         return 0;
3606 }
3607
3608 static int
3609 i915_max_freq_set(void *data, u64 val)
3610 {
3611         struct drm_device *dev = data;
3612         struct drm_i915_private *dev_priv = dev->dev_private;
3613         u32 rp_state_cap, hw_max, hw_min;
3614         int ret;
3615
3616         if (INTEL_INFO(dev)->gen < 6)
3617                 return -ENODEV;
3618
3619         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3620
3621         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
3622
3623         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3624         if (ret)
3625                 return ret;
3626
3627         /*
3628          * Turbo will still be enabled, but won't go above the set value.
3629          */
3630         if (IS_VALLEYVIEW(dev)) {
3631                 val = vlv_freq_opcode(dev_priv, val);
3632
3633                 hw_max = valleyview_rps_max_freq(dev_priv);
3634                 hw_min = valleyview_rps_min_freq(dev_priv);
3635         } else {
3636                 do_div(val, GT_FREQUENCY_MULTIPLIER);
3637
3638                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3639                 hw_max = dev_priv->rps.max_freq;
3640                 hw_min = (rp_state_cap >> 16) & 0xff;
3641         }
3642
3643         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
3644                 mutex_unlock(&dev_priv->rps.hw_lock);
3645                 return -EINVAL;
3646         }
3647
3648         dev_priv->rps.max_freq_softlimit = val;
3649
3650         if (IS_VALLEYVIEW(dev))
3651                 valleyview_set_rps(dev, val);
3652         else
3653                 gen6_set_rps(dev, val);
3654
3655         mutex_unlock(&dev_priv->rps.hw_lock);
3656
3657         return 0;
3658 }
3659
3660 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3661                         i915_max_freq_get, i915_max_freq_set,
3662                         "%llu\n");
3663
3664 static int
3665 i915_min_freq_get(void *data, u64 *val)
3666 {
3667         struct drm_device *dev = data;
3668         struct drm_i915_private *dev_priv = dev->dev_private;
3669         int ret;
3670
3671         if (INTEL_INFO(dev)->gen < 6)
3672                 return -ENODEV;
3673
3674         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3675
3676         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3677         if (ret)
3678                 return ret;
3679
3680         if (IS_VALLEYVIEW(dev))
3681                 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
3682         else
3683                 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
3684         mutex_unlock(&dev_priv->rps.hw_lock);
3685
3686         return 0;
3687 }
3688
3689 static int
3690 i915_min_freq_set(void *data, u64 val)
3691 {
3692         struct drm_device *dev = data;
3693         struct drm_i915_private *dev_priv = dev->dev_private;
3694         u32 rp_state_cap, hw_max, hw_min;
3695         int ret;
3696
3697         if (INTEL_INFO(dev)->gen < 6)
3698                 return -ENODEV;
3699
3700         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3701
3702         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
3703
3704         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3705         if (ret)
3706                 return ret;
3707
3708         /*
3709          * Turbo will still be enabled, but won't go below the set value.
3710          */
3711         if (IS_VALLEYVIEW(dev)) {
3712                 val = vlv_freq_opcode(dev_priv, val);
3713
3714                 hw_max = valleyview_rps_max_freq(dev_priv);
3715                 hw_min = valleyview_rps_min_freq(dev_priv);
3716         } else {
3717                 do_div(val, GT_FREQUENCY_MULTIPLIER);
3718
3719                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3720                 hw_max = dev_priv->rps.max_freq;
3721                 hw_min = (rp_state_cap >> 16) & 0xff;
3722         }
3723
3724         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
3725                 mutex_unlock(&dev_priv->rps.hw_lock);
3726                 return -EINVAL;
3727         }
3728
3729         dev_priv->rps.min_freq_softlimit = val;
3730
3731         if (IS_VALLEYVIEW(dev))
3732                 valleyview_set_rps(dev, val);
3733         else
3734                 gen6_set_rps(dev, val);
3735
3736         mutex_unlock(&dev_priv->rps.hw_lock);
3737
3738         return 0;
3739 }
3740
3741 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3742                         i915_min_freq_get, i915_min_freq_set,
3743                         "%llu\n");
3744
3745 static int
3746 i915_cache_sharing_get(void *data, u64 *val)
3747 {
3748         struct drm_device *dev = data;
3749         struct drm_i915_private *dev_priv = dev->dev_private;
3750         u32 snpcr;
3751         int ret;
3752
3753         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3754                 return -ENODEV;
3755
3756         ret = mutex_lock_interruptible(&dev->struct_mutex);
3757         if (ret)
3758                 return ret;
3759         intel_runtime_pm_get(dev_priv);
3760
3761         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3762
3763         intel_runtime_pm_put(dev_priv);
3764         mutex_unlock(&dev_priv->dev->struct_mutex);
3765
3766         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
3767
3768         return 0;
3769 }
3770
3771 static int
3772 i915_cache_sharing_set(void *data, u64 val)
3773 {
3774         struct drm_device *dev = data;
3775         struct drm_i915_private *dev_priv = dev->dev_private;
3776         u32 snpcr;
3777
3778         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3779                 return -ENODEV;
3780
3781         if (val > 3)
3782                 return -EINVAL;
3783
3784         intel_runtime_pm_get(dev_priv);
3785         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
3786
3787         /* Update the cache sharing policy here as well */
3788         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3789         snpcr &= ~GEN6_MBC_SNPCR_MASK;
3790         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3791         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3792
3793         intel_runtime_pm_put(dev_priv);
3794         return 0;
3795 }
3796
3797 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3798                         i915_cache_sharing_get, i915_cache_sharing_set,
3799                         "%llu\n");
3800
3801 static int i915_forcewake_open(struct inode *inode, struct file *file)
3802 {
3803         struct drm_device *dev = inode->i_private;
3804         struct drm_i915_private *dev_priv = dev->dev_private;
3805
3806         if (INTEL_INFO(dev)->gen < 6)
3807                 return 0;
3808
3809         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3810
3811         return 0;
3812 }
3813
3814 static int i915_forcewake_release(struct inode *inode, struct file *file)
3815 {
3816         struct drm_device *dev = inode->i_private;
3817         struct drm_i915_private *dev_priv = dev->dev_private;
3818
3819         if (INTEL_INFO(dev)->gen < 6)
3820                 return 0;
3821
3822         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3823
3824         return 0;
3825 }
3826
3827 static const struct file_operations i915_forcewake_fops = {
3828         .owner = THIS_MODULE,
3829         .open = i915_forcewake_open,
3830         .release = i915_forcewake_release,
3831 };
3832
3833 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3834 {
3835         struct drm_device *dev = minor->dev;
3836         struct dentry *ent;
3837
3838         ent = debugfs_create_file("i915_forcewake_user",
3839                                   S_IRUSR,
3840                                   root, dev,
3841                                   &i915_forcewake_fops);
3842         if (!ent)
3843                 return -ENOMEM;
3844
3845         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
3846 }
3847
3848 static int i915_debugfs_create(struct dentry *root,
3849                                struct drm_minor *minor,
3850                                const char *name,
3851                                const struct file_operations *fops)
3852 {
3853         struct drm_device *dev = minor->dev;
3854         struct dentry *ent;
3855
3856         ent = debugfs_create_file(name,
3857                                   S_IRUGO | S_IWUSR,
3858                                   root, dev,
3859                                   fops);
3860         if (!ent)
3861                 return -ENOMEM;
3862
3863         return drm_add_fake_info_node(minor, ent, fops);
3864 }
3865
3866 static const struct drm_info_list i915_debugfs_list[] = {
3867         {"i915_capabilities", i915_capabilities, 0},
3868         {"i915_gem_objects", i915_gem_object_info, 0},
3869         {"i915_gem_gtt", i915_gem_gtt_info, 0},
3870         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
3871         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
3872         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
3873         {"i915_gem_stolen", i915_gem_stolen_list_info },
3874         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
3875         {"i915_gem_request", i915_gem_request_info, 0},
3876         {"i915_gem_seqno", i915_gem_seqno_info, 0},
3877         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
3878         {"i915_gem_interrupt", i915_interrupt_info, 0},
3879         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3880         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3881         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
3882         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
3883         {"i915_rstdby_delays", i915_rstdby_delays, 0},
3884         {"i915_frequency_info", i915_frequency_info, 0},
3885         {"i915_delayfreq_table", i915_delayfreq_table, 0},
3886         {"i915_inttoext_table", i915_inttoext_table, 0},
3887         {"i915_drpc_info", i915_drpc_info, 0},
3888         {"i915_emon_status", i915_emon_status, 0},
3889         {"i915_ring_freq_table", i915_ring_freq_table, 0},
3890         {"i915_gfxec", i915_gfxec, 0},
3891         {"i915_fbc_status", i915_fbc_status, 0},
3892         {"i915_ips_status", i915_ips_status, 0},
3893         {"i915_sr_status", i915_sr_status, 0},
3894         {"i915_opregion", i915_opregion, 0},
3895         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
3896         {"i915_context_status", i915_context_status, 0},
3897         {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
3898         {"i915_swizzle_info", i915_swizzle_info, 0},
3899         {"i915_ppgtt_info", i915_ppgtt_info, 0},
3900         {"i915_llc", i915_llc, 0},
3901         {"i915_edp_psr_status", i915_edp_psr_status, 0},
3902         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
3903         {"i915_energy_uJ", i915_energy_uJ, 0},
3904         {"i915_pc8_status", i915_pc8_status, 0},
3905         {"i915_power_domain_info", i915_power_domain_info, 0},
3906         {"i915_display_info", i915_display_info, 0},
3907 };
3908 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
3909
3910 static const struct i915_debugfs_files {
3911         const char *name;
3912         const struct file_operations *fops;
3913 } i915_debugfs_files[] = {
3914         {"i915_wedged", &i915_wedged_fops},
3915         {"i915_max_freq", &i915_max_freq_fops},
3916         {"i915_min_freq", &i915_min_freq_fops},
3917         {"i915_cache_sharing", &i915_cache_sharing_fops},
3918         {"i915_ring_stop", &i915_ring_stop_fops},
3919         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3920         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
3921         {"i915_gem_drop_caches", &i915_drop_caches_fops},
3922         {"i915_error_state", &i915_error_state_fops},
3923         {"i915_next_seqno", &i915_next_seqno_fops},
3924         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
3925         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
3926         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
3927         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
3928 };
3929
3930 void intel_display_crc_init(struct drm_device *dev)
3931 {
3932         struct drm_i915_private *dev_priv = dev->dev_private;
3933         enum pipe pipe;
3934
3935         for_each_pipe(pipe) {
3936                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3937
3938                 pipe_crc->opened = false;
3939                 spin_lock_init(&pipe_crc->lock);
3940                 init_waitqueue_head(&pipe_crc->wq);
3941         }
3942 }
3943
3944 int i915_debugfs_init(struct drm_minor *minor)
3945 {
3946         int ret, i;
3947
3948         ret = i915_forcewake_create(minor->debugfs_root, minor);
3949         if (ret)
3950                 return ret;
3951
3952         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3953                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3954                 if (ret)
3955                         return ret;
3956         }
3957
3958         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3959                 ret = i915_debugfs_create(minor->debugfs_root, minor,
3960                                           i915_debugfs_files[i].name,
3961                                           i915_debugfs_files[i].fops);
3962                 if (ret)
3963                         return ret;
3964         }
3965
3966         return drm_debugfs_create_files(i915_debugfs_list,
3967                                         I915_DEBUGFS_ENTRIES,
3968                                         minor->debugfs_root, minor);
3969 }
3970
3971 void i915_debugfs_cleanup(struct drm_minor *minor)
3972 {
3973         int i;
3974
3975         drm_debugfs_remove_files(i915_debugfs_list,
3976                                  I915_DEBUGFS_ENTRIES, minor);
3977
3978         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3979                                  1, minor);
3980
3981         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3982                 struct drm_info_list *info_list =
3983                         (struct drm_info_list *)&i915_pipe_crc_data[i];
3984
3985                 drm_debugfs_remove_files(info_list, 1, minor);
3986         }
3987
3988         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3989                 struct drm_info_list *info_list =
3990                         (struct drm_info_list *) i915_debugfs_files[i].fops;
3991
3992                 drm_debugfs_remove_files(info_list, 1, minor);
3993         }
3994 }