drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 static const char *yesno(int v)
  50 {
  51         return v ? "yes" : "no";
  52 }
  53
  54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  55  * allocated we need to hook into the minor for release. */
  56 static int
  57 drm_add_fake_info_node(struct drm_minor *minor,
  58                        struct dentry *ent,
  59                        const void *key)
  60 {
  61         struct drm_info_node *node;
  62
  63         node = kmalloc(sizeof(*node), GFP_KERNEL);
  64         if (node == NULL) {
  65                 debugfs_remove(ent);
  66                 return -ENOMEM;
  67         }
  68
  69         node->minor = minor;
  70         node->dent = ent;
  71         node->info_ent = (void *) key;
  72
  73         mutex_lock(&minor->debugfs_lock);
  74         list_add(&node->list, &minor->debugfs_list);
  75         mutex_unlock(&minor->debugfs_lock);
  76
  77         return 0;
  78 }
  79
  80 static int i915_capabilities(struct seq_file *m, void *data)
  81 {
  82         struct drm_info_node *node = m->private;
  83         struct drm_device *dev = node->minor->dev;
  84         const struct intel_device_info *info = INTEL_INFO(dev);
  85
  86         seq_printf(m, "gen: %d\n", info->gen);
  87         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  88 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  89 #define SEP_SEMICOLON ;
  90         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  91 #undef PRINT_FLAG
  92 #undef SEP_SEMICOLON
  93
  94         return 0;
  95 }
  96
  97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  98 {
  99         if (i915_gem_obj_is_pinned(obj))
 100                 return "p";
 101         else
 102                 return " ";
 103 }
 104
 105 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 106 {
 107         switch (obj->tiling_mode) {
 108         default:
 109         case I915_TILING_NONE: return " ";
 110         case I915_TILING_X: return "X";
 111         case I915_TILING_Y: return "Y";
 112         }
 113 }
 114
 115 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 116 {
 117         return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
 118 }
 119
 120 static void
 121 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 122 {
 123         struct i915_vma *vma;
 124         int pin_count = 0;
 125
 126         seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
 127                    &obj->base,
 128                    get_pin_flag(obj),
 129                    get_tiling_flag(obj),
 130                    get_global_flag(obj),
 131                    obj->base.size / 1024,
 132                    obj->base.read_domains,
 133                    obj->base.write_domain,
 134                    i915_gem_request_get_seqno(obj->last_read_req),
 135                    i915_gem_request_get_seqno(obj->last_write_req),
 136                    i915_gem_request_get_seqno(obj->last_fenced_req),
 137                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 138                    obj->dirty ? " dirty" : "",
 139                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 140         if (obj->base.name)
 141                 seq_printf(m, " (name: %d)", obj->base.name);
 142         list_for_each_entry(vma, &obj->vma_list, vma_link)
 143                 if (vma->pin_count > 0)
 144                         pin_count++;
 145                 seq_printf(m, " (pinned x %d)", pin_count);
 146         if (obj->pin_display)
 147                 seq_printf(m, " (display)");
 148         if (obj->fence_reg != I915_FENCE_REG_NONE)
 149                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 150         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 151                 if (!i915_is_ggtt(vma->vm))
 152                         seq_puts(m, " (pp");
 153                 else
 154                         seq_puts(m, " (g");
 155                 seq_printf(m, "gtt offset: %08lx, size: %08lx, type: %u)",
 156                            vma->node.start, vma->node.size,
 157                            vma->ggtt_view.type);
 158         }
 159         if (obj->stolen)
 160                 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
 161         if (obj->pin_mappable || obj->fault_mappable) {
 162                 char s[3], *t = s;
 163                 if (obj->pin_mappable)
 164                         *t++ = 'p';
 165                 if (obj->fault_mappable)
 166                         *t++ = 'f';
 167                 *t = '\0';
 168                 seq_printf(m, " (%s mappable)", s);
 169         }
 170         if (obj->last_read_req != NULL)
 171                 seq_printf(m, " (%s)",
 172                            i915_gem_request_get_ring(obj->last_read_req)->name);
 173         if (obj->frontbuffer_bits)
 174                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 175 }
 176
 177 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
 178 {
 179         seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
 180         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 181         seq_putc(m, ' ');
 182 }
 183
 184 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 185 {
 186         struct drm_info_node *node = m->private;
 187         uintptr_t list = (uintptr_t) node->info_ent->data;
 188         struct list_head *head;
 189         struct drm_device *dev = node->minor->dev;
 190         struct drm_i915_private *dev_priv = dev->dev_private;
 191         struct i915_address_space *vm = &dev_priv->gtt.base;
 192         struct i915_vma *vma;
 193         size_t total_obj_size, total_gtt_size;
 194         int count, ret;
 195
 196         ret = mutex_lock_interruptible(&dev->struct_mutex);
 197         if (ret)
 198                 return ret;
 199
 200         /* FIXME: the user of this interface might want more than just GGTT */
 201         switch (list) {
 202         case ACTIVE_LIST:
 203                 seq_puts(m, "Active:\n");
 204                 head = &vm->active_list;
 205                 break;
 206         case INACTIVE_LIST:
 207                 seq_puts(m, "Inactive:\n");
 208                 head = &vm->inactive_list;
 209                 break;
 210         default:
 211                 mutex_unlock(&dev->struct_mutex);
 212                 return -EINVAL;
 213         }
 214
 215         total_obj_size = total_gtt_size = count = 0;
 216         list_for_each_entry(vma, head, mm_list) {
 217                 seq_printf(m, "   ");
 218                 describe_obj(m, vma->obj);
 219                 seq_printf(m, "\n");
 220                 total_obj_size += vma->obj->base.size;
 221                 total_gtt_size += vma->node.size;
 222                 count++;
 223         }
 224         mutex_unlock(&dev->struct_mutex);
 225
 226         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 227                    count, total_obj_size, total_gtt_size);
 228         return 0;
 229 }
 230
 231 static int obj_rank_by_stolen(void *priv,
 232                               struct list_head *A, struct list_head *B)
 233 {
 234         struct drm_i915_gem_object *a =
 235                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 236         struct drm_i915_gem_object *b =
 237                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 238
 239         return a->stolen->start - b->stolen->start;
 240 }
 241
 242 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 243 {
 244         struct drm_info_node *node = m->private;
 245         struct drm_device *dev = node->minor->dev;
 246         struct drm_i915_private *dev_priv = dev->dev_private;
 247         struct drm_i915_gem_object *obj;
 248         size_t total_obj_size, total_gtt_size;
 249         LIST_HEAD(stolen);
 250         int count, ret;
 251
 252         ret = mutex_lock_interruptible(&dev->struct_mutex);
 253         if (ret)
 254                 return ret;
 255
 256         total_obj_size = total_gtt_size = count = 0;
 257         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 258                 if (obj->stolen == NULL)
 259                         continue;
 260
 261                 list_add(&obj->obj_exec_link, &stolen);
 262
 263                 total_obj_size += obj->base.size;
 264                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 265                 count++;
 266         }
 267         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 268                 if (obj->stolen == NULL)
 269                         continue;
 270
 271                 list_add(&obj->obj_exec_link, &stolen);
 272
 273                 total_obj_size += obj->base.size;
 274                 count++;
 275         }
 276         list_sort(NULL, &stolen, obj_rank_by_stolen);
 277         seq_puts(m, "Stolen:\n");
 278         while (!list_empty(&stolen)) {
 279                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 280                 seq_puts(m, "   ");
 281                 describe_obj(m, obj);
 282                 seq_putc(m, '\n');
 283                 list_del_init(&obj->obj_exec_link);
 284         }
 285         mutex_unlock(&dev->struct_mutex);
 286
 287         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 288                    count, total_obj_size, total_gtt_size);
 289         return 0;
 290 }
 291
 292 #define count_objects(list, member) do { \
 293         list_for_each_entry(obj, list, member) { \
 294                 size += i915_gem_obj_ggtt_size(obj); \
 295                 ++count; \
 296                 if (obj->map_and_fenceable) { \
 297                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 298                         ++mappable_count; \
 299                 } \
 300         } \
 301 } while (0)
 302
 303 struct file_stats {
 304         struct drm_i915_file_private *file_priv;
 305         int count;
 306         size_t total, unbound;
 307         size_t global, shared;
 308         size_t active, inactive;
 309 };
 310
 311 static int per_file_stats(int id, void *ptr, void *data)
 312 {
 313         struct drm_i915_gem_object *obj = ptr;
 314         struct file_stats *stats = data;
 315         struct i915_vma *vma;
 316
 317         stats->count++;
 318         stats->total += obj->base.size;
 319
 320         if (obj->base.name || obj->base.dma_buf)
 321                 stats->shared += obj->base.size;
 322
 323         if (USES_FULL_PPGTT(obj->base.dev)) {
 324                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
 325                         struct i915_hw_ppgtt *ppgtt;
 326
 327                         if (!drm_mm_node_allocated(&vma->node))
 328                                 continue;
 329
 330                         if (i915_is_ggtt(vma->vm)) {
 331                                 stats->global += obj->base.size;
 332                                 continue;
 333                         }
 334
 335                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 336                         if (ppgtt->file_priv != stats->file_priv)
 337                                 continue;
 338
 339                         if (obj->active) /* XXX per-vma statistic */
 340                                 stats->active += obj->base.size;
 341                         else
 342                                 stats->inactive += obj->base.size;
 343
 344                         return 0;
 345                 }
 346         } else {
 347                 if (i915_gem_obj_ggtt_bound(obj)) {
 348                         stats->global += obj->base.size;
 349                         if (obj->active)
 350                                 stats->active += obj->base.size;
 351                         else
 352                                 stats->inactive += obj->base.size;
 353                         return 0;
 354                 }
 355         }
 356
 357         if (!list_empty(&obj->global_list))
 358                 stats->unbound += obj->base.size;
 359
 360         return 0;
 361 }
 362
 363 #define print_file_stats(m, name, stats) \
 364         seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
 365                    name, \
 366                    stats.count, \
 367                    stats.total, \
 368                    stats.active, \
 369                    stats.inactive, \
 370                    stats.global, \
 371                    stats.shared, \
 372                    stats.unbound)
 373
 374 static void print_batch_pool_stats(struct seq_file *m,
 375                                    struct drm_i915_private *dev_priv)
 376 {
 377         struct drm_i915_gem_object *obj;
 378         struct file_stats stats;
 379
 380         memset(&stats, 0, sizeof(stats));
 381
 382         list_for_each_entry(obj,
 383                             &dev_priv->mm.batch_pool.cache_list,
 384                             batch_pool_list)
 385                 per_file_stats(0, obj, &stats);
 386
 387         print_file_stats(m, "batch pool", stats);
 388 }
 389
 390 #define count_vmas(list, member) do { \
 391         list_for_each_entry(vma, list, member) { \
 392                 size += i915_gem_obj_ggtt_size(vma->obj); \
 393                 ++count; \
 394                 if (vma->obj->map_and_fenceable) { \
 395                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 396                         ++mappable_count; \
 397                 } \
 398         } \
 399 } while (0)
 400
 401 static int i915_gem_object_info(struct seq_file *m, void* data)
 402 {
 403         struct drm_info_node *node = m->private;
 404         struct drm_device *dev = node->minor->dev;
 405         struct drm_i915_private *dev_priv = dev->dev_private;
 406         u32 count, mappable_count, purgeable_count;
 407         size_t size, mappable_size, purgeable_size;
 408         struct drm_i915_gem_object *obj;
 409         struct i915_address_space *vm = &dev_priv->gtt.base;
 410         struct drm_file *file;
 411         struct i915_vma *vma;
 412         int ret;
 413
 414         ret = mutex_lock_interruptible(&dev->struct_mutex);
 415         if (ret)
 416                 return ret;
 417
 418         seq_printf(m, "%u objects, %zu bytes\n",
 419                    dev_priv->mm.object_count,
 420                    dev_priv->mm.object_memory);
 421
 422         size = count = mappable_size = mappable_count = 0;
 423         count_objects(&dev_priv->mm.bound_list, global_list);
 424         seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
 425                    count, mappable_count, size, mappable_size);
 426
 427         size = count = mappable_size = mappable_count = 0;
 428         count_vmas(&vm->active_list, mm_list);
 429         seq_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n",
 430                    count, mappable_count, size, mappable_size);
 431
 432         size = count = mappable_size = mappable_count = 0;
 433         count_vmas(&vm->inactive_list, mm_list);
 434         seq_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n",
 435                    count, mappable_count, size, mappable_size);
 436
 437         size = count = purgeable_size = purgeable_count = 0;
 438         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 439                 size += obj->base.size, ++count;
 440                 if (obj->madv == I915_MADV_DONTNEED)
 441                         purgeable_size += obj->base.size, ++purgeable_count;
 442         }
 443         seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
 444
 445         size = count = mappable_size = mappable_count = 0;
 446         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 447                 if (obj->fault_mappable) {
 448                         size += i915_gem_obj_ggtt_size(obj);
 449                         ++count;
 450                 }
 451                 if (obj->pin_mappable) {
 452                         mappable_size += i915_gem_obj_ggtt_size(obj);
 453                         ++mappable_count;
 454                 }
 455                 if (obj->madv == I915_MADV_DONTNEED) {
 456                         purgeable_size += obj->base.size;
 457                         ++purgeable_count;
 458                 }
 459         }
 460         seq_printf(m, "%u purgeable objects, %zu bytes\n",
 461                    purgeable_count, purgeable_size);
 462         seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
 463                    mappable_count, mappable_size);
 464         seq_printf(m, "%u fault mappable objects, %zu bytes\n",
 465                    count, size);
 466
 467         seq_printf(m, "%zu [%lu] gtt total\n",
 468                    dev_priv->gtt.base.total,
 469                    dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 470
 471         seq_putc(m, '\n');
 472         print_batch_pool_stats(m, dev_priv);
 473
 474         seq_putc(m, '\n');
 475         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 476                 struct file_stats stats;
 477                 struct task_struct *task;
 478
 479                 memset(&stats, 0, sizeof(stats));
 480                 stats.file_priv = file->driver_priv;
 481                 spin_lock(&file->table_lock);
 482                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 483                 spin_unlock(&file->table_lock);
 484                 /*
 485                  * Although we have a valid reference on file->pid, that does
 486                  * not guarantee that the task_struct who called get_pid() is
 487                  * still alive (e.g. get_pid(current) => fork() => exit()).
 488                  * Therefore, we need to protect this ->comm access using RCU.
 489                  */
 490                 rcu_read_lock();
 491                 task = pid_task(file->pid, PIDTYPE_PID);
 492                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 493                 rcu_read_unlock();
 494         }
 495
 496         mutex_unlock(&dev->struct_mutex);
 497
 498         return 0;
 499 }
 500
 501 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 502 {
 503         struct drm_info_node *node = m->private;
 504         struct drm_device *dev = node->minor->dev;
 505         uintptr_t list = (uintptr_t) node->info_ent->data;
 506         struct drm_i915_private *dev_priv = dev->dev_private;
 507         struct drm_i915_gem_object *obj;
 508         size_t total_obj_size, total_gtt_size;
 509         int count, ret;
 510
 511         ret = mutex_lock_interruptible(&dev->struct_mutex);
 512         if (ret)
 513                 return ret;
 514
 515         total_obj_size = total_gtt_size = count = 0;
 516         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 517                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 518                         continue;
 519
 520                 seq_puts(m, "   ");
 521                 describe_obj(m, obj);
 522                 seq_putc(m, '\n');
 523                 total_obj_size += obj->base.size;
 524                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 525                 count++;
 526         }
 527
 528         mutex_unlock(&dev->struct_mutex);
 529
 530         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 531                    count, total_obj_size, total_gtt_size);
 532
 533         return 0;
 534 }
 535
 536 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 537 {
 538         struct drm_info_node *node = m->private;
 539         struct drm_device *dev = node->minor->dev;
 540         struct drm_i915_private *dev_priv = dev->dev_private;
 541         struct intel_crtc *crtc;
 542         int ret;
 543
 544         ret = mutex_lock_interruptible(&dev->struct_mutex);
 545         if (ret)
 546                 return ret;
 547
 548         for_each_intel_crtc(dev, crtc) {
 549                 const char pipe = pipe_name(crtc->pipe);
 550                 const char plane = plane_name(crtc->plane);
 551                 struct intel_unpin_work *work;
 552
 553                 spin_lock_irq(&dev->event_lock);
 554                 work = crtc->unpin_work;
 555                 if (work == NULL) {
 556                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 557                                    pipe, plane);
 558                 } else {
 559                         u32 addr;
 560
 561                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 562                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 563                                            pipe, plane);
 564                         } else {
 565                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 566                                            pipe, plane);
 567                         }
 568                         if (work->flip_queued_req) {
 569                                 struct intel_engine_cs *ring =
 570                                         i915_gem_request_get_ring(work->flip_queued_req);
 571
 572                                 seq_printf(m, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n",
 573                                            ring->name,
 574                                            i915_gem_request_get_seqno(work->flip_queued_req),
 575                                            dev_priv->next_seqno,
 576                                            ring->get_seqno(ring, true),
 577                                            i915_gem_request_completed(work->flip_queued_req, true));
 578                         } else
 579                                 seq_printf(m, "Flip not associated with any ring\n");
 580                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 581                                    work->flip_queued_vblank,
 582                                    work->flip_ready_vblank,
 583                                    drm_vblank_count(dev, crtc->pipe));
 584                         if (work->enable_stall_check)
 585                                 seq_puts(m, "Stall check enabled, ");
 586                         else
 587                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 588                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 589
 590                         if (INTEL_INFO(dev)->gen >= 4)
 591                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 592                         else
 593                                 addr = I915_READ(DSPADDR(crtc->plane));
 594                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 595
 596                         if (work->pending_flip_obj) {
 597                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 598                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 599                         }
 600                 }
 601                 spin_unlock_irq(&dev->event_lock);
 602         }
 603
 604         mutex_unlock(&dev->struct_mutex);
 605
 606         return 0;
 607 }
 608
 609 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 610 {
 611         struct drm_info_node *node = m->private;
 612         struct drm_device *dev = node->minor->dev;
 613         struct drm_i915_private *dev_priv = dev->dev_private;
 614         struct drm_i915_gem_object *obj;
 615         int count = 0;
 616         int ret;
 617
 618         ret = mutex_lock_interruptible(&dev->struct_mutex);
 619         if (ret)
 620                 return ret;
 621
 622         seq_puts(m, "cache:\n");
 623         list_for_each_entry(obj,
 624                             &dev_priv->mm.batch_pool.cache_list,
 625                             batch_pool_list) {
 626                 seq_puts(m, "   ");
 627                 describe_obj(m, obj);
 628                 seq_putc(m, '\n');
 629                 count++;
 630         }
 631
 632         seq_printf(m, "total: %d\n", count);
 633
 634         mutex_unlock(&dev->struct_mutex);
 635
 636         return 0;
 637 }
 638
 639 static int i915_gem_request_info(struct seq_file *m, void *data)
 640 {
 641         struct drm_info_node *node = m->private;
 642         struct drm_device *dev = node->minor->dev;
 643         struct drm_i915_private *dev_priv = dev->dev_private;
 644         struct intel_engine_cs *ring;
 645         struct drm_i915_gem_request *gem_request;
 646         int ret, count, i;
 647
 648         ret = mutex_lock_interruptible(&dev->struct_mutex);
 649         if (ret)
 650                 return ret;
 651
 652         count = 0;
 653         for_each_ring(ring, dev_priv, i) {
 654                 if (list_empty(&ring->request_list))
 655                         continue;
 656
 657                 seq_printf(m, "%s requests:\n", ring->name);
 658                 list_for_each_entry(gem_request,
 659                                     &ring->request_list,
 660                                     list) {
 661                         seq_printf(m, "    %d @ %d\n",
 662                                    gem_request->seqno,
 663                                    (int) (jiffies - gem_request->emitted_jiffies));
 664                 }
 665                 count++;
 666         }
 667         mutex_unlock(&dev->struct_mutex);
 668
 669         if (count == 0)
 670                 seq_puts(m, "No requests\n");
 671
 672         return 0;
 673 }
 674
 675 static void i915_ring_seqno_info(struct seq_file *m,
 676                                  struct intel_engine_cs *ring)
 677 {
 678         if (ring->get_seqno) {
 679                 seq_printf(m, "Current sequence (%s): %u\n",
 680                            ring->name, ring->get_seqno(ring, false));
 681         }
 682 }
 683
 684 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 685 {
 686         struct drm_info_node *node = m->private;
 687         struct drm_device *dev = node->minor->dev;
 688         struct drm_i915_private *dev_priv = dev->dev_private;
 689         struct intel_engine_cs *ring;
 690         int ret, i;
 691
 692         ret = mutex_lock_interruptible(&dev->struct_mutex);
 693         if (ret)
 694                 return ret;
 695         intel_runtime_pm_get(dev_priv);
 696
 697         for_each_ring(ring, dev_priv, i)
 698                 i915_ring_seqno_info(m, ring);
 699
 700         intel_runtime_pm_put(dev_priv);
 701         mutex_unlock(&dev->struct_mutex);
 702
 703         return 0;
 704 }
 705
 706
 707 static int i915_interrupt_info(struct seq_file *m, void *data)
 708 {
 709         struct drm_info_node *node = m->private;
 710         struct drm_device *dev = node->minor->dev;
 711         struct drm_i915_private *dev_priv = dev->dev_private;
 712         struct intel_engine_cs *ring;
 713         int ret, i, pipe;
 714
 715         ret = mutex_lock_interruptible(&dev->struct_mutex);
 716         if (ret)
 717                 return ret;
 718         intel_runtime_pm_get(dev_priv);
 719
 720         if (IS_CHERRYVIEW(dev)) {
 721                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 722                            I915_READ(GEN8_MASTER_IRQ));
 723
 724                 seq_printf(m, "Display IER:\t%08x\n",
 725                            I915_READ(VLV_IER));
 726                 seq_printf(m, "Display IIR:\t%08x\n",
 727                            I915_READ(VLV_IIR));
 728                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 729                            I915_READ(VLV_IIR_RW));
 730                 seq_printf(m, "Display IMR:\t%08x\n",
 731                            I915_READ(VLV_IMR));
 732                 for_each_pipe(dev_priv, pipe)
 733                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 734                                    pipe_name(pipe),
 735                                    I915_READ(PIPESTAT(pipe)));
 736
 737                 seq_printf(m, "Port hotplug:\t%08x\n",
 738                            I915_READ(PORT_HOTPLUG_EN));
 739                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 740                            I915_READ(VLV_DPFLIPSTAT));
 741                 seq_printf(m, "DPINVGTT:\t%08x\n",
 742                            I915_READ(DPINVGTT));
 743
 744                 for (i = 0; i < 4; i++) {
 745                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 746                                    i, I915_READ(GEN8_GT_IMR(i)));
 747                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 748                                    i, I915_READ(GEN8_GT_IIR(i)));
 749                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 750                                    i, I915_READ(GEN8_GT_IER(i)));
 751                 }
 752
 753                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 754                            I915_READ(GEN8_PCU_IMR));
 755                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 756                            I915_READ(GEN8_PCU_IIR));
 757                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 758                            I915_READ(GEN8_PCU_IER));
 759         } else if (INTEL_INFO(dev)->gen >= 8) {
 760                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 761                            I915_READ(GEN8_MASTER_IRQ));
 762
 763                 for (i = 0; i < 4; i++) {
 764                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 765                                    i, I915_READ(GEN8_GT_IMR(i)));
 766                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 767                                    i, I915_READ(GEN8_GT_IIR(i)));
 768                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 769                                    i, I915_READ(GEN8_GT_IER(i)));
 770                 }
 771
 772                 for_each_pipe(dev_priv, pipe) {
 773                         if (!intel_display_power_is_enabled(dev_priv,
 774                                                 POWER_DOMAIN_PIPE(pipe))) {
 775                                 seq_printf(m, "Pipe %c power disabled\n",
 776                                            pipe_name(pipe));
 777                                 continue;
 778                         }
 779                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 780                                    pipe_name(pipe),
 781                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 782                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 783                                    pipe_name(pipe),
 784                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 785                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 786                                    pipe_name(pipe),
 787                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 788                 }
 789
 790                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 791                            I915_READ(GEN8_DE_PORT_IMR));
 792                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 793                            I915_READ(GEN8_DE_PORT_IIR));
 794                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 795                            I915_READ(GEN8_DE_PORT_IER));
 796
 797                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 798                            I915_READ(GEN8_DE_MISC_IMR));
 799                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 800                            I915_READ(GEN8_DE_MISC_IIR));
 801                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 802                            I915_READ(GEN8_DE_MISC_IER));
 803
 804                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 805                            I915_READ(GEN8_PCU_IMR));
 806                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 807                            I915_READ(GEN8_PCU_IIR));
 808                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 809                            I915_READ(GEN8_PCU_IER));
 810         } else if (IS_VALLEYVIEW(dev)) {
 811                 seq_printf(m, "Display IER:\t%08x\n",
 812                            I915_READ(VLV_IER));
 813                 seq_printf(m, "Display IIR:\t%08x\n",
 814                            I915_READ(VLV_IIR));
 815                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 816                            I915_READ(VLV_IIR_RW));
 817                 seq_printf(m, "Display IMR:\t%08x\n",
 818                            I915_READ(VLV_IMR));
 819                 for_each_pipe(dev_priv, pipe)
 820                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 821                                    pipe_name(pipe),
 822                                    I915_READ(PIPESTAT(pipe)));
 823
 824                 seq_printf(m, "Master IER:\t%08x\n",
 825                            I915_READ(VLV_MASTER_IER));
 826
 827                 seq_printf(m, "Render IER:\t%08x\n",
 828                            I915_READ(GTIER));
 829                 seq_printf(m, "Render IIR:\t%08x\n",
 830                            I915_READ(GTIIR));
 831                 seq_printf(m, "Render IMR:\t%08x\n",
 832                            I915_READ(GTIMR));
 833
 834                 seq_printf(m, "PM IER:\t\t%08x\n",
 835                            I915_READ(GEN6_PMIER));
 836                 seq_printf(m, "PM IIR:\t\t%08x\n",
 837                            I915_READ(GEN6_PMIIR));
 838                 seq_printf(m, "PM IMR:\t\t%08x\n",
 839                            I915_READ(GEN6_PMIMR));
 840
 841                 seq_printf(m, "Port hotplug:\t%08x\n",
 842                            I915_READ(PORT_HOTPLUG_EN));
 843                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 844                            I915_READ(VLV_DPFLIPSTAT));
 845                 seq_printf(m, "DPINVGTT:\t%08x\n",
 846                            I915_READ(DPINVGTT));
 847
 848         } else if (!HAS_PCH_SPLIT(dev)) {
 849                 seq_printf(m, "Interrupt enable:    %08x\n",
 850                            I915_READ(IER));
 851                 seq_printf(m, "Interrupt identity:  %08x\n",
 852                            I915_READ(IIR));
 853                 seq_printf(m, "Interrupt mask:      %08x\n",
 854                            I915_READ(IMR));
 855                 for_each_pipe(dev_priv, pipe)
 856                         seq_printf(m, "Pipe %c stat:         %08x\n",
 857                                    pipe_name(pipe),
 858                                    I915_READ(PIPESTAT(pipe)));
 859         } else {
 860                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 861                            I915_READ(DEIER));
 862                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 863                            I915_READ(DEIIR));
 864                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 865                            I915_READ(DEIMR));
 866                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 867                            I915_READ(SDEIER));
 868                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 869                            I915_READ(SDEIIR));
 870                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 871                            I915_READ(SDEIMR));
 872                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 873                            I915_READ(GTIER));
 874                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 875                            I915_READ(GTIIR));
 876                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 877                            I915_READ(GTIMR));
 878         }
 879         for_each_ring(ring, dev_priv, i) {
 880                 if (INTEL_INFO(dev)->gen >= 6) {
 881                         seq_printf(m,
 882                                    "Graphics Interrupt mask (%s):       %08x\n",
 883                                    ring->name, I915_READ_IMR(ring));
 884                 }
 885                 i915_ring_seqno_info(m, ring);
 886         }
 887         intel_runtime_pm_put(dev_priv);
 888         mutex_unlock(&dev->struct_mutex);
 889
 890         return 0;
 891 }
 892
 893 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 894 {
 895         struct drm_info_node *node = m->private;
 896         struct drm_device *dev = node->minor->dev;
 897         struct drm_i915_private *dev_priv = dev->dev_private;
 898         int i, ret;
 899
 900         ret = mutex_lock_interruptible(&dev->struct_mutex);
 901         if (ret)
 902                 return ret;
 903
 904         seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 905         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 906         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 907                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 908
 909                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 910                            i, dev_priv->fence_regs[i].pin_count);
 911                 if (obj == NULL)
 912                         seq_puts(m, "unused");
 913                 else
 914                         describe_obj(m, obj);
 915                 seq_putc(m, '\n');
 916         }
 917
 918         mutex_unlock(&dev->struct_mutex);
 919         return 0;
 920 }
 921
 922 static int i915_hws_info(struct seq_file *m, void *data)
 923 {
 924         struct drm_info_node *node = m->private;
 925         struct drm_device *dev = node->minor->dev;
 926         struct drm_i915_private *dev_priv = dev->dev_private;
 927         struct intel_engine_cs *ring;
 928         const u32 *hws;
 929         int i;
 930
 931         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 932         hws = ring->status_page.page_addr;
 933         if (hws == NULL)
 934                 return 0;
 935
 936         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 937                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 938                            i * 4,
 939                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 940         }
 941         return 0;
 942 }
 943
 944 static ssize_t
 945 i915_error_state_write(struct file *filp,
 946                        const char __user *ubuf,
 947                        size_t cnt,
 948                        loff_t *ppos)
 949 {
 950         struct i915_error_state_file_priv *error_priv = filp->private_data;
 951         struct drm_device *dev = error_priv->dev;
 952         int ret;
 953
 954         DRM_DEBUG_DRIVER("Resetting error state\n");
 955
 956         ret = mutex_lock_interruptible(&dev->struct_mutex);
 957         if (ret)
 958                 return ret;
 959
 960         i915_destroy_error_state(dev);
 961         mutex_unlock(&dev->struct_mutex);
 962
 963         return cnt;
 964 }
 965
 966 static int i915_error_state_open(struct inode *inode, struct file *file)
 967 {
 968         struct drm_device *dev = inode->i_private;
 969         struct i915_error_state_file_priv *error_priv;
 970
 971         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 972         if (!error_priv)
 973                 return -ENOMEM;
 974
 975         error_priv->dev = dev;
 976
 977         i915_error_state_get(dev, error_priv);
 978
 979         file->private_data = error_priv;
 980
 981         return 0;
 982 }
 983
 984 static int i915_error_state_release(struct inode *inode, struct file *file)
 985 {
 986         struct i915_error_state_file_priv *error_priv = file->private_data;
 987
 988         i915_error_state_put(error_priv);
 989         kfree(error_priv);
 990
 991         return 0;
 992 }
 993
 994 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
 995                                      size_t count, loff_t *pos)
 996 {
 997         struct i915_error_state_file_priv *error_priv = file->private_data;
 998         struct drm_i915_error_state_buf error_str;
 999         loff_t tmp_pos = 0;
1000         ssize_t ret_count = 0;
1001         int ret;
1002
1003         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1004         if (ret)
1005                 return ret;
1006
1007         ret = i915_error_state_to_str(&error_str, error_priv);
1008         if (ret)
1009                 goto out;
1010
1011         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1012                                             error_str.buf,
1013                                             error_str.bytes);
1014
1015         if (ret_count < 0)
1016                 ret = ret_count;
1017         else
1018                 *pos = error_str.start + ret_count;
1019 out:
1020         i915_error_state_buf_release(&error_str);
1021         return ret ?: ret_count;
1022 }
1023
1024 static const struct file_operations i915_error_state_fops = {
1025         .owner = THIS_MODULE,
1026         .open = i915_error_state_open,
1027         .read = i915_error_state_read,
1028         .write = i915_error_state_write,
1029         .llseek = default_llseek,
1030         .release = i915_error_state_release,
1031 };
1032
1033 static int
1034 i915_next_seqno_get(void *data, u64 *val)
1035 {
1036         struct drm_device *dev = data;
1037         struct drm_i915_private *dev_priv = dev->dev_private;
1038         int ret;
1039
1040         ret = mutex_lock_interruptible(&dev->struct_mutex);
1041         if (ret)
1042                 return ret;
1043
1044         *val = dev_priv->next_seqno;
1045         mutex_unlock(&dev->struct_mutex);
1046
1047         return 0;
1048 }
1049
1050 static int
1051 i915_next_seqno_set(void *data, u64 val)
1052 {
1053         struct drm_device *dev = data;
1054         int ret;
1055
1056         ret = mutex_lock_interruptible(&dev->struct_mutex);
1057         if (ret)
1058                 return ret;
1059
1060         ret = i915_gem_set_seqno(dev, val);
1061         mutex_unlock(&dev->struct_mutex);
1062
1063         return ret;
1064 }
1065
1066 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1067                         i915_next_seqno_get, i915_next_seqno_set,
1068                         "0x%llx\n");
1069
1070 static int i915_frequency_info(struct seq_file *m, void *unused)
1071 {
1072         struct drm_info_node *node = m->private;
1073         struct drm_device *dev = node->minor->dev;
1074         struct drm_i915_private *dev_priv = dev->dev_private;
1075         int ret = 0;
1076
1077         intel_runtime_pm_get(dev_priv);
1078
1079         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1080
1081         if (IS_GEN5(dev)) {
1082                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1083                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1084
1085                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1086                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1087                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1088                            MEMSTAT_VID_SHIFT);
1089                 seq_printf(m, "Current P-state: %d\n",
1090                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1091         } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1092                    IS_BROADWELL(dev)) {
1093                 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1094                 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1095                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1096                 u32 rpmodectl, rpinclimit, rpdeclimit;
1097                 u32 rpstat, cagf, reqf;
1098                 u32 rpupei, rpcurup, rpprevup;
1099                 u32 rpdownei, rpcurdown, rpprevdown;
1100                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1101                 int max_freq;
1102
1103                 /* RPSTAT1 is in the GT power well */
1104                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1105                 if (ret)
1106                         goto out;
1107
1108                 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
1109
1110                 reqf = I915_READ(GEN6_RPNSWREQ);
1111                 reqf &= ~GEN6_TURBO_DISABLE;
1112                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1113                         reqf >>= 24;
1114                 else
1115                         reqf >>= 25;
1116                 reqf *= GT_FREQUENCY_MULTIPLIER;
1117
1118                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1119                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1120                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1121
1122                 rpstat = I915_READ(GEN6_RPSTAT1);
1123                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1124                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1125                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1126                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1127                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1128                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1129                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1130                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1131                 else
1132                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1133                 cagf *= GT_FREQUENCY_MULTIPLIER;
1134
1135                 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
1136                 mutex_unlock(&dev->struct_mutex);
1137
1138                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1139                         pm_ier = I915_READ(GEN6_PMIER);
1140                         pm_imr = I915_READ(GEN6_PMIMR);
1141                         pm_isr = I915_READ(GEN6_PMISR);
1142                         pm_iir = I915_READ(GEN6_PMIIR);
1143                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1144                 } else {
1145                         pm_ier = I915_READ(GEN8_GT_IER(2));
1146                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1147                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1148                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1149                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1150                 }
1151                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1152                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1153                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1154                 seq_printf(m, "Render p-state ratio: %d\n",
1155                            (gt_perf_status & 0xff00) >> 8);
1156                 seq_printf(m, "Render p-state VID: %d\n",
1157                            gt_perf_status & 0xff);
1158                 seq_printf(m, "Render p-state limit: %d\n",
1159                            rp_state_limits & 0xff);
1160                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1161                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1162                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1163                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1164                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1165                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1166                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1167                            GEN6_CURICONT_MASK);
1168                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1169                            GEN6_CURBSYTAVG_MASK);
1170                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1171                            GEN6_CURBSYTAVG_MASK);
1172                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1173                            GEN6_CURIAVG_MASK);
1174                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1175                            GEN6_CURBSYTAVG_MASK);
1176                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1177                            GEN6_CURBSYTAVG_MASK);
1178
1179                 max_freq = (rp_state_cap & 0xff0000) >> 16;
1180                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1181                            max_freq * GT_FREQUENCY_MULTIPLIER);
1182
1183                 max_freq = (rp_state_cap & 0xff00) >> 8;
1184                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1185                            max_freq * GT_FREQUENCY_MULTIPLIER);
1186
1187                 max_freq = rp_state_cap & 0xff;
1188                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1189                            max_freq * GT_FREQUENCY_MULTIPLIER);
1190
1191                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1192                            dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
1193         } else if (IS_VALLEYVIEW(dev)) {
1194                 u32 freq_sts;
1195
1196                 mutex_lock(&dev_priv->rps.hw_lock);
1197                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1198                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1199                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1200
1201                 seq_printf(m, "max GPU freq: %d MHz\n",
1202                            vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1203
1204                 seq_printf(m, "min GPU freq: %d MHz\n",
1205                            vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1206
1207                 seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
1208                            vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1209
1210                 seq_printf(m, "current GPU freq: %d MHz\n",
1211                            vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1212                 mutex_unlock(&dev_priv->rps.hw_lock);
1213         } else {
1214                 seq_puts(m, "no P-state info available\n");
1215         }
1216
1217 out:
1218         intel_runtime_pm_put(dev_priv);
1219         return ret;
1220 }
1221
1222 static int ironlake_drpc_info(struct seq_file *m)
1223 {
1224         struct drm_info_node *node = m->private;
1225         struct drm_device *dev = node->minor->dev;
1226         struct drm_i915_private *dev_priv = dev->dev_private;
1227         u32 rgvmodectl, rstdbyctl;
1228         u16 crstandvid;
1229         int ret;
1230
1231         ret = mutex_lock_interruptible(&dev->struct_mutex);
1232         if (ret)
1233                 return ret;
1234         intel_runtime_pm_get(dev_priv);
1235
1236         rgvmodectl = I915_READ(MEMMODECTL);
1237         rstdbyctl = I915_READ(RSTDBYCTL);
1238         crstandvid = I915_READ16(CRSTANDVID);
1239
1240         intel_runtime_pm_put(dev_priv);
1241         mutex_unlock(&dev->struct_mutex);
1242
1243         seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1244                    "yes" : "no");
1245         seq_printf(m, "Boost freq: %d\n",
1246                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1247                    MEMMODE_BOOST_FREQ_SHIFT);
1248         seq_printf(m, "HW control enabled: %s\n",
1249                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1250         seq_printf(m, "SW control enabled: %s\n",
1251                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1252         seq_printf(m, "Gated voltage change: %s\n",
1253                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1254         seq_printf(m, "Starting frequency: P%d\n",
1255                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1256         seq_printf(m, "Max P-state: P%d\n",
1257                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1258         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1259         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1260         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1261         seq_printf(m, "Render standby enabled: %s\n",
1262                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1263         seq_puts(m, "Current RS state: ");
1264         switch (rstdbyctl & RSX_STATUS_MASK) {
1265         case RSX_STATUS_ON:
1266                 seq_puts(m, "on\n");
1267                 break;
1268         case RSX_STATUS_RC1:
1269                 seq_puts(m, "RC1\n");
1270                 break;
1271         case RSX_STATUS_RC1E:
1272                 seq_puts(m, "RC1E\n");
1273                 break;
1274         case RSX_STATUS_RS1:
1275                 seq_puts(m, "RS1\n");
1276                 break;
1277         case RSX_STATUS_RS2:
1278                 seq_puts(m, "RS2 (RC6)\n");
1279                 break;
1280         case RSX_STATUS_RS3:
1281                 seq_puts(m, "RC3 (RC6+)\n");
1282                 break;
1283         default:
1284                 seq_puts(m, "unknown\n");
1285                 break;
1286         }
1287
1288         return 0;
1289 }
1290
1291 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1292 {
1293         struct drm_info_node *node = m->private;
1294         struct drm_device *dev = node->minor->dev;
1295         struct drm_i915_private *dev_priv = dev->dev_private;
1296         struct intel_uncore_forcewake_domain *fw_domain;
1297         int i;
1298
1299         spin_lock_irq(&dev_priv->uncore.lock);
1300         for_each_fw_domain(fw_domain, dev_priv, i) {
1301                 seq_printf(m, "%s.wake_count = %u\n",
1302                            intel_uncore_forcewake_domain_to_str(i),
1303                            fw_domain->wake_count);
1304         }
1305         spin_unlock_irq(&dev_priv->uncore.lock);
1306
1307         return 0;
1308 }
1309
1310 static int vlv_drpc_info(struct seq_file *m)
1311 {
1312         struct drm_info_node *node = m->private;
1313         struct drm_device *dev = node->minor->dev;
1314         struct drm_i915_private *dev_priv = dev->dev_private;
1315         u32 rpmodectl1, rcctl1, pw_status;
1316
1317         intel_runtime_pm_get(dev_priv);
1318
1319         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1320         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1321         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1322
1323         intel_runtime_pm_put(dev_priv);
1324
1325         seq_printf(m, "Video Turbo Mode: %s\n",
1326                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1327         seq_printf(m, "Turbo enabled: %s\n",
1328                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1329         seq_printf(m, "HW control enabled: %s\n",
1330                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1331         seq_printf(m, "SW control enabled: %s\n",
1332                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1333                           GEN6_RP_MEDIA_SW_MODE));
1334         seq_printf(m, "RC6 Enabled: %s\n",
1335                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1336                                         GEN6_RC_CTL_EI_MODE(1))));
1337         seq_printf(m, "Render Power Well: %s\n",
1338                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1339         seq_printf(m, "Media Power Well: %s\n",
1340                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1341
1342         seq_printf(m, "Render RC6 residency since boot: %u\n",
1343                    I915_READ(VLV_GT_RENDER_RC6));
1344         seq_printf(m, "Media RC6 residency since boot: %u\n",
1345                    I915_READ(VLV_GT_MEDIA_RC6));
1346
1347         return i915_gen6_forcewake_count_info(m, NULL);
1348 }
1349
1350 static int gen6_drpc_info(struct seq_file *m)
1351 {
1352         struct drm_info_node *node = m->private;
1353         struct drm_device *dev = node->minor->dev;
1354         struct drm_i915_private *dev_priv = dev->dev_private;
1355         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1356         unsigned forcewake_count;
1357         int count = 0, ret;
1358
1359         ret = mutex_lock_interruptible(&dev->struct_mutex);
1360         if (ret)
1361                 return ret;
1362         intel_runtime_pm_get(dev_priv);
1363
1364         spin_lock_irq(&dev_priv->uncore.lock);
1365         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1366         spin_unlock_irq(&dev_priv->uncore.lock);
1367
1368         if (forcewake_count) {
1369                 seq_puts(m, "RC information inaccurate because somebody "
1370                             "holds a forcewake reference \n");
1371         } else {
1372                 /* NB: we cannot use forcewake, else we read the wrong values */
1373                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1374                         udelay(10);
1375                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1376         }
1377
1378         gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1379         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1380
1381         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1382         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1383         mutex_unlock(&dev->struct_mutex);
1384         mutex_lock(&dev_priv->rps.hw_lock);
1385         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1386         mutex_unlock(&dev_priv->rps.hw_lock);
1387
1388         intel_runtime_pm_put(dev_priv);
1389
1390         seq_printf(m, "Video Turbo Mode: %s\n",
1391                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1392         seq_printf(m, "HW control enabled: %s\n",
1393                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1394         seq_printf(m, "SW control enabled: %s\n",
1395                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1396                           GEN6_RP_MEDIA_SW_MODE));
1397         seq_printf(m, "RC1e Enabled: %s\n",
1398                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1399         seq_printf(m, "RC6 Enabled: %s\n",
1400                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1401         seq_printf(m, "Deep RC6 Enabled: %s\n",
1402                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1403         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1404                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1405         seq_puts(m, "Current RC state: ");
1406         switch (gt_core_status & GEN6_RCn_MASK) {
1407         case GEN6_RC0:
1408                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1409                         seq_puts(m, "Core Power Down\n");
1410                 else
1411                         seq_puts(m, "on\n");
1412                 break;
1413         case GEN6_RC3:
1414                 seq_puts(m, "RC3\n");
1415                 break;
1416         case GEN6_RC6:
1417                 seq_puts(m, "RC6\n");
1418                 break;
1419         case GEN6_RC7:
1420                 seq_puts(m, "RC7\n");
1421                 break;
1422         default:
1423                 seq_puts(m, "Unknown\n");
1424                 break;
1425         }
1426
1427         seq_printf(m, "Core Power Down: %s\n",
1428                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1429
1430         /* Not exactly sure what this is */
1431         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1432                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1433         seq_printf(m, "RC6 residency since boot: %u\n",
1434                    I915_READ(GEN6_GT_GFX_RC6));
1435         seq_printf(m, "RC6+ residency since boot: %u\n",
1436                    I915_READ(GEN6_GT_GFX_RC6p));
1437         seq_printf(m, "RC6++ residency since boot: %u\n",
1438                    I915_READ(GEN6_GT_GFX_RC6pp));
1439
1440         seq_printf(m, "RC6   voltage: %dmV\n",
1441                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1442         seq_printf(m, "RC6+  voltage: %dmV\n",
1443                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1444         seq_printf(m, "RC6++ voltage: %dmV\n",
1445                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1446         return 0;
1447 }
1448
1449 static int i915_drpc_info(struct seq_file *m, void *unused)
1450 {
1451         struct drm_info_node *node = m->private;
1452         struct drm_device *dev = node->minor->dev;
1453
1454         if (IS_VALLEYVIEW(dev))
1455                 return vlv_drpc_info(m);
1456         else if (INTEL_INFO(dev)->gen >= 6)
1457                 return gen6_drpc_info(m);
1458         else
1459                 return ironlake_drpc_info(m);
1460 }
1461
1462 static int i915_fbc_status(struct seq_file *m, void *unused)
1463 {
1464         struct drm_info_node *node = m->private;
1465         struct drm_device *dev = node->minor->dev;
1466         struct drm_i915_private *dev_priv = dev->dev_private;
1467
1468         if (!HAS_FBC(dev)) {
1469                 seq_puts(m, "FBC unsupported on this chipset\n");
1470                 return 0;
1471         }
1472
1473         intel_runtime_pm_get(dev_priv);
1474
1475         if (intel_fbc_enabled(dev)) {
1476                 seq_puts(m, "FBC enabled\n");
1477         } else {
1478                 seq_puts(m, "FBC disabled: ");
1479                 switch (dev_priv->fbc.no_fbc_reason) {
1480                 case FBC_OK:
1481                         seq_puts(m, "FBC actived, but currently disabled in hardware");
1482                         break;
1483                 case FBC_UNSUPPORTED:
1484                         seq_puts(m, "unsupported by this chipset");
1485                         break;
1486                 case FBC_NO_OUTPUT:
1487                         seq_puts(m, "no outputs");
1488                         break;
1489                 case FBC_STOLEN_TOO_SMALL:
1490                         seq_puts(m, "not enough stolen memory");
1491                         break;
1492                 case FBC_UNSUPPORTED_MODE:
1493                         seq_puts(m, "mode not supported");
1494                         break;
1495                 case FBC_MODE_TOO_LARGE:
1496                         seq_puts(m, "mode too large");
1497                         break;
1498                 case FBC_BAD_PLANE:
1499                         seq_puts(m, "FBC unsupported on plane");
1500                         break;
1501                 case FBC_NOT_TILED:
1502                         seq_puts(m, "scanout buffer not tiled");
1503                         break;
1504                 case FBC_MULTIPLE_PIPES:
1505                         seq_puts(m, "multiple pipes are enabled");
1506                         break;
1507                 case FBC_MODULE_PARAM:
1508                         seq_puts(m, "disabled per module param (default off)");
1509                         break;
1510                 case FBC_CHIP_DEFAULT:
1511                         seq_puts(m, "disabled per chip default");
1512                         break;
1513                 default:
1514                         seq_puts(m, "unknown reason");
1515                 }
1516                 seq_putc(m, '\n');
1517         }
1518
1519         intel_runtime_pm_put(dev_priv);
1520
1521         return 0;
1522 }
1523
1524 static int i915_fbc_fc_get(void *data, u64 *val)
1525 {
1526         struct drm_device *dev = data;
1527         struct drm_i915_private *dev_priv = dev->dev_private;
1528
1529         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1530                 return -ENODEV;
1531
1532         drm_modeset_lock_all(dev);
1533         *val = dev_priv->fbc.false_color;
1534         drm_modeset_unlock_all(dev);
1535
1536         return 0;
1537 }
1538
1539 static int i915_fbc_fc_set(void *data, u64 val)
1540 {
1541         struct drm_device *dev = data;
1542         struct drm_i915_private *dev_priv = dev->dev_private;
1543         u32 reg;
1544
1545         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1546                 return -ENODEV;
1547
1548         drm_modeset_lock_all(dev);
1549
1550         reg = I915_READ(ILK_DPFC_CONTROL);
1551         dev_priv->fbc.false_color = val;
1552
1553         I915_WRITE(ILK_DPFC_CONTROL, val ?
1554                    (reg | FBC_CTL_FALSE_COLOR) :
1555                    (reg & ~FBC_CTL_FALSE_COLOR));
1556
1557         drm_modeset_unlock_all(dev);
1558         return 0;
1559 }
1560
1561 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1562                         i915_fbc_fc_get, i915_fbc_fc_set,
1563                         "%llu\n");
1564
1565 static int i915_ips_status(struct seq_file *m, void *unused)
1566 {
1567         struct drm_info_node *node = m->private;
1568         struct drm_device *dev = node->minor->dev;
1569         struct drm_i915_private *dev_priv = dev->dev_private;
1570
1571         if (!HAS_IPS(dev)) {
1572                 seq_puts(m, "not supported\n");
1573                 return 0;
1574         }
1575
1576         intel_runtime_pm_get(dev_priv);
1577
1578         seq_printf(m, "Enabled by kernel parameter: %s\n",
1579                    yesno(i915.enable_ips));
1580
1581         if (INTEL_INFO(dev)->gen >= 8) {
1582                 seq_puts(m, "Currently: unknown\n");
1583         } else {
1584                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1585                         seq_puts(m, "Currently: enabled\n");
1586                 else
1587                         seq_puts(m, "Currently: disabled\n");
1588         }
1589
1590         intel_runtime_pm_put(dev_priv);
1591
1592         return 0;
1593 }
1594
1595 static int i915_sr_status(struct seq_file *m, void *unused)
1596 {
1597         struct drm_info_node *node = m->private;
1598         struct drm_device *dev = node->minor->dev;
1599         struct drm_i915_private *dev_priv = dev->dev_private;
1600         bool sr_enabled = false;
1601
1602         intel_runtime_pm_get(dev_priv);
1603
1604         if (HAS_PCH_SPLIT(dev))
1605                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1606         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1607                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1608         else if (IS_I915GM(dev))
1609                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1610         else if (IS_PINEVIEW(dev))
1611                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1612
1613         intel_runtime_pm_put(dev_priv);
1614
1615         seq_printf(m, "self-refresh: %s\n",
1616                    sr_enabled ? "enabled" : "disabled");
1617
1618         return 0;
1619 }
1620
1621 static int i915_emon_status(struct seq_file *m, void *unused)
1622 {
1623         struct drm_info_node *node = m->private;
1624         struct drm_device *dev = node->minor->dev;
1625         struct drm_i915_private *dev_priv = dev->dev_private;
1626         unsigned long temp, chipset, gfx;
1627         int ret;
1628
1629         if (!IS_GEN5(dev))
1630                 return -ENODEV;
1631
1632         ret = mutex_lock_interruptible(&dev->struct_mutex);
1633         if (ret)
1634                 return ret;
1635
1636         temp = i915_mch_val(dev_priv);
1637         chipset = i915_chipset_val(dev_priv);
1638         gfx = i915_gfx_val(dev_priv);
1639         mutex_unlock(&dev->struct_mutex);
1640
1641         seq_printf(m, "GMCH temp: %ld\n", temp);
1642         seq_printf(m, "Chipset power: %ld\n", chipset);
1643         seq_printf(m, "GFX power: %ld\n", gfx);
1644         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1645
1646         return 0;
1647 }
1648
1649 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1650 {
1651         struct drm_info_node *node = m->private;
1652         struct drm_device *dev = node->minor->dev;
1653         struct drm_i915_private *dev_priv = dev->dev_private;
1654         int ret = 0;
1655         int gpu_freq, ia_freq;
1656
1657         if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1658                 seq_puts(m, "unsupported on this chipset\n");
1659                 return 0;
1660         }
1661
1662         intel_runtime_pm_get(dev_priv);
1663
1664         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1665
1666         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1667         if (ret)
1668                 goto out;
1669
1670         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1671
1672         for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1673              gpu_freq <= dev_priv->rps.max_freq_softlimit;
1674              gpu_freq++) {
1675                 ia_freq = gpu_freq;
1676                 sandybridge_pcode_read(dev_priv,
1677                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1678                                        &ia_freq);
1679                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1680                            gpu_freq * GT_FREQUENCY_MULTIPLIER,
1681                            ((ia_freq >> 0) & 0xff) * 100,
1682                            ((ia_freq >> 8) & 0xff) * 100);
1683         }
1684
1685         mutex_unlock(&dev_priv->rps.hw_lock);
1686
1687 out:
1688         intel_runtime_pm_put(dev_priv);
1689         return ret;
1690 }
1691
1692 static int i915_opregion(struct seq_file *m, void *unused)
1693 {
1694         struct drm_info_node *node = m->private;
1695         struct drm_device *dev = node->minor->dev;
1696         struct drm_i915_private *dev_priv = dev->dev_private;
1697         struct intel_opregion *opregion = &dev_priv->opregion;
1698         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1699         int ret;
1700
1701         if (data == NULL)
1702                 return -ENOMEM;
1703
1704         ret = mutex_lock_interruptible(&dev->struct_mutex);
1705         if (ret)
1706                 goto out;
1707
1708         if (opregion->header) {
1709                 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1710                 seq_write(m, data, OPREGION_SIZE);
1711         }
1712
1713         mutex_unlock(&dev->struct_mutex);
1714
1715 out:
1716         kfree(data);
1717         return 0;
1718 }
1719
1720 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1721 {
1722         struct drm_info_node *node = m->private;
1723         struct drm_device *dev = node->minor->dev;
1724         struct intel_fbdev *ifbdev = NULL;
1725         struct intel_framebuffer *fb;
1726
1727 #ifdef CONFIG_DRM_I915_FBDEV
1728         struct drm_i915_private *dev_priv = dev->dev_private;
1729
1730         ifbdev = dev_priv->fbdev;
1731         fb = to_intel_framebuffer(ifbdev->helper.fb);
1732
1733         seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1734                    fb->base.width,
1735                    fb->base.height,
1736                    fb->base.depth,
1737                    fb->base.bits_per_pixel,
1738                    atomic_read(&fb->base.refcount.refcount));
1739         describe_obj(m, fb->obj);
1740         seq_putc(m, '\n');
1741 #endif
1742
1743         mutex_lock(&dev->mode_config.fb_lock);
1744         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1745                 if (ifbdev && &fb->base == ifbdev->helper.fb)
1746                         continue;
1747
1748                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1749                            fb->base.width,
1750                            fb->base.height,
1751                            fb->base.depth,
1752                            fb->base.bits_per_pixel,
1753                            atomic_read(&fb->base.refcount.refcount));
1754                 describe_obj(m, fb->obj);
1755                 seq_putc(m, '\n');
1756         }
1757         mutex_unlock(&dev->mode_config.fb_lock);
1758
1759         return 0;
1760 }
1761
1762 static void describe_ctx_ringbuf(struct seq_file *m,
1763                                  struct intel_ringbuffer *ringbuf)
1764 {
1765         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1766                    ringbuf->space, ringbuf->head, ringbuf->tail,
1767                    ringbuf->last_retired_head);
1768 }
1769
1770 static int i915_context_status(struct seq_file *m, void *unused)
1771 {
1772         struct drm_info_node *node = m->private;
1773         struct drm_device *dev = node->minor->dev;
1774         struct drm_i915_private *dev_priv = dev->dev_private;
1775         struct intel_engine_cs *ring;
1776         struct intel_context *ctx;
1777         int ret, i;
1778
1779         ret = mutex_lock_interruptible(&dev->struct_mutex);
1780         if (ret)
1781                 return ret;
1782
1783         if (dev_priv->ips.pwrctx) {
1784                 seq_puts(m, "power context ");
1785                 describe_obj(m, dev_priv->ips.pwrctx);
1786                 seq_putc(m, '\n');
1787         }
1788
1789         if (dev_priv->ips.renderctx) {
1790                 seq_puts(m, "render context ");
1791                 describe_obj(m, dev_priv->ips.renderctx);
1792                 seq_putc(m, '\n');
1793         }
1794
1795         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1796                 if (!i915.enable_execlists &&
1797                     ctx->legacy_hw_ctx.rcs_state == NULL)
1798                         continue;
1799
1800                 seq_puts(m, "HW context ");
1801                 describe_ctx(m, ctx);
1802                 for_each_ring(ring, dev_priv, i) {
1803                         if (ring->default_context == ctx)
1804                                 seq_printf(m, "(default context %s) ",
1805                                            ring->name);
1806                 }
1807
1808                 if (i915.enable_execlists) {
1809                         seq_putc(m, '\n');
1810                         for_each_ring(ring, dev_priv, i) {
1811                                 struct drm_i915_gem_object *ctx_obj =
1812                                         ctx->engine[i].state;
1813                                 struct intel_ringbuffer *ringbuf =
1814                                         ctx->engine[i].ringbuf;
1815
1816                                 seq_printf(m, "%s: ", ring->name);
1817                                 if (ctx_obj)
1818                                         describe_obj(m, ctx_obj);
1819                                 if (ringbuf)
1820                                         describe_ctx_ringbuf(m, ringbuf);
1821                                 seq_putc(m, '\n');
1822                         }
1823                 } else {
1824                         describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1825                 }
1826
1827                 seq_putc(m, '\n');
1828         }
1829
1830         mutex_unlock(&dev->struct_mutex);
1831
1832         return 0;
1833 }
1834
1835 static void i915_dump_lrc_obj(struct seq_file *m,
1836                               struct intel_engine_cs *ring,
1837                               struct drm_i915_gem_object *ctx_obj)
1838 {
1839         struct page *page;
1840         uint32_t *reg_state;
1841         int j;
1842         unsigned long ggtt_offset = 0;
1843
1844         if (ctx_obj == NULL) {
1845                 seq_printf(m, "Context on %s with no gem object\n",
1846                            ring->name);
1847                 return;
1848         }
1849
1850         seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1851                    intel_execlists_ctx_id(ctx_obj));
1852
1853         if (!i915_gem_obj_ggtt_bound(ctx_obj))
1854                 seq_puts(m, "\tNot bound in GGTT\n");
1855         else
1856                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1857
1858         if (i915_gem_object_get_pages(ctx_obj)) {
1859                 seq_puts(m, "\tFailed to get pages for context object\n");
1860                 return;
1861         }
1862
1863         page = i915_gem_object_get_page(ctx_obj, 1);
1864         if (!WARN_ON(page == NULL)) {
1865                 reg_state = kmap_atomic(page);
1866
1867                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1868                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1869                                    ggtt_offset + 4096 + (j * 4),
1870                                    reg_state[j], reg_state[j + 1],
1871                                    reg_state[j + 2], reg_state[j + 3]);
1872                 }
1873                 kunmap_atomic(reg_state);
1874         }
1875
1876         seq_putc(m, '\n');
1877 }
1878
1879 static int i915_dump_lrc(struct seq_file *m, void *unused)
1880 {
1881         struct drm_info_node *node = (struct drm_info_node *) m->private;
1882         struct drm_device *dev = node->minor->dev;
1883         struct drm_i915_private *dev_priv = dev->dev_private;
1884         struct intel_engine_cs *ring;
1885         struct intel_context *ctx;
1886         int ret, i;
1887
1888         if (!i915.enable_execlists) {
1889                 seq_printf(m, "Logical Ring Contexts are disabled\n");
1890                 return 0;
1891         }
1892
1893         ret = mutex_lock_interruptible(&dev->struct_mutex);
1894         if (ret)
1895                 return ret;
1896
1897         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1898                 for_each_ring(ring, dev_priv, i) {
1899                         if (ring->default_context != ctx)
1900                                 i915_dump_lrc_obj(m, ring,
1901                                                   ctx->engine[i].state);
1902                 }
1903         }
1904
1905         mutex_unlock(&dev->struct_mutex);
1906
1907         return 0;
1908 }
1909
1910 static int i915_execlists(struct seq_file *m, void *data)
1911 {
1912         struct drm_info_node *node = (struct drm_info_node *)m->private;
1913         struct drm_device *dev = node->minor->dev;
1914         struct drm_i915_private *dev_priv = dev->dev_private;
1915         struct intel_engine_cs *ring;
1916         u32 status_pointer;
1917         u8 read_pointer;
1918         u8 write_pointer;
1919         u32 status;
1920         u32 ctx_id;
1921         struct list_head *cursor;
1922         int ring_id, i;
1923         int ret;
1924
1925         if (!i915.enable_execlists) {
1926                 seq_puts(m, "Logical Ring Contexts are disabled\n");
1927                 return 0;
1928         }
1929
1930         ret = mutex_lock_interruptible(&dev->struct_mutex);
1931         if (ret)
1932                 return ret;
1933
1934         intel_runtime_pm_get(dev_priv);
1935
1936         for_each_ring(ring, dev_priv, ring_id) {
1937                 struct drm_i915_gem_request *head_req = NULL;
1938                 int count = 0;
1939                 unsigned long flags;
1940
1941                 seq_printf(m, "%s\n", ring->name);
1942
1943                 status = I915_READ(RING_EXECLIST_STATUS(ring));
1944                 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1945                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1946                            status, ctx_id);
1947
1948                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
1949                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
1950
1951                 read_pointer = ring->next_context_status_buffer;
1952                 write_pointer = status_pointer & 0x07;
1953                 if (read_pointer > write_pointer)
1954                         write_pointer += 6;
1955                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1956                            read_pointer, write_pointer);
1957
1958                 for (i = 0; i < 6; i++) {
1959                         status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
1960                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
1961
1962                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
1963                                    i, status, ctx_id);
1964                 }
1965
1966                 spin_lock_irqsave(&ring->execlist_lock, flags);
1967                 list_for_each(cursor, &ring->execlist_queue)
1968                         count++;
1969                 head_req = list_first_entry_or_null(&ring->execlist_queue,
1970                                 struct drm_i915_gem_request, execlist_link);
1971                 spin_unlock_irqrestore(&ring->execlist_lock, flags);
1972
1973                 seq_printf(m, "\t%d requests in queue\n", count);
1974                 if (head_req) {
1975                         struct drm_i915_gem_object *ctx_obj;
1976
1977                         ctx_obj = head_req->ctx->engine[ring_id].state;
1978                         seq_printf(m, "\tHead request id: %u\n",
1979                                    intel_execlists_ctx_id(ctx_obj));
1980                         seq_printf(m, "\tHead request tail: %u\n",
1981                                    head_req->tail);
1982                 }
1983
1984                 seq_putc(m, '\n');
1985         }
1986
1987         intel_runtime_pm_put(dev_priv);
1988         mutex_unlock(&dev->struct_mutex);
1989
1990         return 0;
1991 }
1992
1993 static const char *swizzle_string(unsigned swizzle)
1994 {
1995         switch (swizzle) {
1996         case I915_BIT_6_SWIZZLE_NONE:
1997                 return "none";
1998         case I915_BIT_6_SWIZZLE_9:
1999                 return "bit9";
2000         case I915_BIT_6_SWIZZLE_9_10:
2001                 return "bit9/bit10";
2002         case I915_BIT_6_SWIZZLE_9_11:
2003                 return "bit9/bit11";
2004         case I915_BIT_6_SWIZZLE_9_10_11:
2005                 return "bit9/bit10/bit11";
2006         case I915_BIT_6_SWIZZLE_9_17:
2007                 return "bit9/bit17";
2008         case I915_BIT_6_SWIZZLE_9_10_17:
2009                 return "bit9/bit10/bit17";
2010         case I915_BIT_6_SWIZZLE_UNKNOWN:
2011                 return "unknown";
2012         }
2013
2014         return "bug";
2015 }
2016
2017 static int i915_swizzle_info(struct seq_file *m, void *data)
2018 {
2019         struct drm_info_node *node = m->private;
2020         struct drm_device *dev = node->minor->dev;
2021         struct drm_i915_private *dev_priv = dev->dev_private;
2022         int ret;
2023
2024         ret = mutex_lock_interruptible(&dev->struct_mutex);
2025         if (ret)
2026                 return ret;
2027         intel_runtime_pm_get(dev_priv);
2028
2029         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2030                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2031         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2032                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2033
2034         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2035                 seq_printf(m, "DDC = 0x%08x\n",
2036                            I915_READ(DCC));
2037                 seq_printf(m, "DDC2 = 0x%08x\n",
2038                            I915_READ(DCC2));
2039                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2040                            I915_READ16(C0DRB3));
2041                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2042                            I915_READ16(C1DRB3));
2043         } else if (INTEL_INFO(dev)->gen >= 6) {
2044                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2045                            I915_READ(MAD_DIMM_C0));
2046                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2047                            I915_READ(MAD_DIMM_C1));
2048                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2049                            I915_READ(MAD_DIMM_C2));
2050                 seq_printf(m, "TILECTL = 0x%08x\n",
2051                            I915_READ(TILECTL));
2052                 if (INTEL_INFO(dev)->gen >= 8)
2053                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2054                                    I915_READ(GAMTARBMODE));
2055                 else
2056                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2057                                    I915_READ(ARB_MODE));
2058                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2059                            I915_READ(DISP_ARB_CTL));
2060         }
2061
2062         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2063                 seq_puts(m, "L-shaped memory detected\n");
2064
2065         intel_runtime_pm_put(dev_priv);
2066         mutex_unlock(&dev->struct_mutex);
2067
2068         return 0;
2069 }
2070
2071 static int per_file_ctx(int id, void *ptr, void *data)
2072 {
2073         struct intel_context *ctx = ptr;
2074         struct seq_file *m = data;
2075         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2076
2077         if (!ppgtt) {
2078                 seq_printf(m, "  no ppgtt for context %d\n",
2079                            ctx->user_handle);
2080                 return 0;
2081         }
2082
2083         if (i915_gem_context_is_default(ctx))
2084                 seq_puts(m, "  default context:\n");
2085         else
2086                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2087         ppgtt->debug_dump(ppgtt, m);
2088
2089         return 0;
2090 }
2091
2092 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2093 {
2094         struct drm_i915_private *dev_priv = dev->dev_private;
2095         struct intel_engine_cs *ring;
2096         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2097         int unused, i;
2098
2099         if (!ppgtt)
2100                 return;
2101
2102         seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
2103         seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
2104         for_each_ring(ring, dev_priv, unused) {
2105                 seq_printf(m, "%s\n", ring->name);
2106                 for (i = 0; i < 4; i++) {
2107                         u32 offset = 0x270 + i * 8;
2108                         u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2109                         pdp <<= 32;
2110                         pdp |= I915_READ(ring->mmio_base + offset);
2111                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2112                 }
2113         }
2114 }
2115
2116 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2117 {
2118         struct drm_i915_private *dev_priv = dev->dev_private;
2119         struct intel_engine_cs *ring;
2120         struct drm_file *file;
2121         int i;
2122
2123         if (INTEL_INFO(dev)->gen == 6)
2124                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2125
2126         for_each_ring(ring, dev_priv, i) {
2127                 seq_printf(m, "%s\n", ring->name);
2128                 if (INTEL_INFO(dev)->gen == 7)
2129                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2130                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2131                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2132                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2133         }
2134         if (dev_priv->mm.aliasing_ppgtt) {
2135                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2136
2137                 seq_puts(m, "aliasing PPGTT:\n");
2138                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
2139
2140                 ppgtt->debug_dump(ppgtt, m);
2141         }
2142
2143         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2144                 struct drm_i915_file_private *file_priv = file->driver_priv;
2145
2146                 seq_printf(m, "proc: %s\n",
2147                            get_pid_task(file->pid, PIDTYPE_PID)->comm);
2148                 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
2149         }
2150         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2151 }
2152
2153 static int i915_ppgtt_info(struct seq_file *m, void *data)
2154 {
2155         struct drm_info_node *node = m->private;
2156         struct drm_device *dev = node->minor->dev;
2157         struct drm_i915_private *dev_priv = dev->dev_private;
2158
2159         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2160         if (ret)
2161                 return ret;
2162         intel_runtime_pm_get(dev_priv);
2163
2164         if (INTEL_INFO(dev)->gen >= 8)
2165                 gen8_ppgtt_info(m, dev);
2166         else if (INTEL_INFO(dev)->gen >= 6)
2167                 gen6_ppgtt_info(m, dev);
2168
2169         intel_runtime_pm_put(dev_priv);
2170         mutex_unlock(&dev->struct_mutex);
2171
2172         return 0;
2173 }
2174
2175 static int i915_llc(struct seq_file *m, void *data)
2176 {
2177         struct drm_info_node *node = m->private;
2178         struct drm_device *dev = node->minor->dev;
2179         struct drm_i915_private *dev_priv = dev->dev_private;
2180
2181         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2182         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2183         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2184
2185         return 0;
2186 }
2187
2188 static int i915_edp_psr_status(struct seq_file *m, void *data)
2189 {
2190         struct drm_info_node *node = m->private;
2191         struct drm_device *dev = node->minor->dev;
2192         struct drm_i915_private *dev_priv = dev->dev_private;
2193         u32 psrperf = 0;
2194         u32 stat[3];
2195         enum pipe pipe;
2196         bool enabled = false;
2197
2198         intel_runtime_pm_get(dev_priv);
2199
2200         mutex_lock(&dev_priv->psr.lock);
2201         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2202         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2203         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2204         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2205         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2206                    dev_priv->psr.busy_frontbuffer_bits);
2207         seq_printf(m, "Re-enable work scheduled: %s\n",
2208                    yesno(work_busy(&dev_priv->psr.work.work)));
2209
2210         if (HAS_PSR(dev)) {
2211                 if (HAS_DDI(dev))
2212                         enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2213                 else {
2214                         for_each_pipe(dev_priv, pipe) {
2215                                 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2216                                         VLV_EDP_PSR_CURR_STATE_MASK;
2217                                 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2218                                     (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2219                                         enabled = true;
2220                         }
2221                 }
2222         }
2223         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2224
2225         if (!HAS_DDI(dev))
2226                 for_each_pipe(dev_priv, pipe) {
2227                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2228                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2229                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2230                 }
2231         seq_puts(m, "\n");
2232
2233         seq_printf(m, "Link standby: %s\n",
2234                    yesno((bool)dev_priv->psr.link_standby));
2235
2236         /* CHV PSR has no kind of performance counter */
2237         if (HAS_PSR(dev) && HAS_DDI(dev)) {
2238                 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2239                         EDP_PSR_PERF_CNT_MASK;
2240
2241                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2242         }
2243         mutex_unlock(&dev_priv->psr.lock);
2244
2245         intel_runtime_pm_put(dev_priv);
2246         return 0;
2247 }
2248
2249 static int i915_sink_crc(struct seq_file *m, void *data)
2250 {
2251         struct drm_info_node *node = m->private;
2252         struct drm_device *dev = node->minor->dev;
2253         struct intel_encoder *encoder;
2254         struct intel_connector *connector;
2255         struct intel_dp *intel_dp = NULL;
2256         int ret;
2257         u8 crc[6];
2258
2259         drm_modeset_lock_all(dev);
2260         list_for_each_entry(connector, &dev->mode_config.connector_list,
2261                             base.head) {
2262
2263                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2264                         continue;
2265
2266                 if (!connector->base.encoder)
2267                         continue;
2268
2269                 encoder = to_intel_encoder(connector->base.encoder);
2270                 if (encoder->type != INTEL_OUTPUT_EDP)
2271                         continue;
2272
2273                 intel_dp = enc_to_intel_dp(&encoder->base);
2274
2275                 ret = intel_dp_sink_crc(intel_dp, crc);
2276                 if (ret)
2277                         goto out;
2278
2279                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2280                            crc[0], crc[1], crc[2],
2281                            crc[3], crc[4], crc[5]);
2282                 goto out;
2283         }
2284         ret = -ENODEV;
2285 out:
2286         drm_modeset_unlock_all(dev);
2287         return ret;
2288 }
2289
2290 static int i915_energy_uJ(struct seq_file *m, void *data)
2291 {
2292         struct drm_info_node *node = m->private;
2293         struct drm_device *dev = node->minor->dev;
2294         struct drm_i915_private *dev_priv = dev->dev_private;
2295         u64 power;
2296         u32 units;
2297
2298         if (INTEL_INFO(dev)->gen < 6)
2299                 return -ENODEV;
2300
2301         intel_runtime_pm_get(dev_priv);
2302
2303         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2304         power = (power & 0x1f00) >> 8;
2305         units = 1000000 / (1 << power); /* convert to uJ */
2306         power = I915_READ(MCH_SECP_NRG_STTS);
2307         power *= units;
2308
2309         intel_runtime_pm_put(dev_priv);
2310
2311         seq_printf(m, "%llu", (long long unsigned)power);
2312
2313         return 0;
2314 }
2315
2316 static int i915_pc8_status(struct seq_file *m, void *unused)
2317 {
2318         struct drm_info_node *node = m->private;
2319         struct drm_device *dev = node->minor->dev;
2320         struct drm_i915_private *dev_priv = dev->dev_private;
2321
2322         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2323                 seq_puts(m, "not supported\n");
2324                 return 0;
2325         }
2326
2327         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2328         seq_printf(m, "IRQs disabled: %s\n",
2329                    yesno(!intel_irqs_enabled(dev_priv)));
2330
2331         return 0;
2332 }
2333
2334 static const char *power_domain_str(enum intel_display_power_domain domain)
2335 {
2336         switch (domain) {
2337         case POWER_DOMAIN_PIPE_A:
2338                 return "PIPE_A";
2339         case POWER_DOMAIN_PIPE_B:
2340                 return "PIPE_B";
2341         case POWER_DOMAIN_PIPE_C:
2342                 return "PIPE_C";
2343         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2344                 return "PIPE_A_PANEL_FITTER";
2345         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2346                 return "PIPE_B_PANEL_FITTER";
2347         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2348                 return "PIPE_C_PANEL_FITTER";
2349         case POWER_DOMAIN_TRANSCODER_A:
2350                 return "TRANSCODER_A";
2351         case POWER_DOMAIN_TRANSCODER_B:
2352                 return "TRANSCODER_B";
2353         case POWER_DOMAIN_TRANSCODER_C:
2354                 return "TRANSCODER_C";
2355         case POWER_DOMAIN_TRANSCODER_EDP:
2356                 return "TRANSCODER_EDP";
2357         case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2358                 return "PORT_DDI_A_2_LANES";
2359         case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2360                 return "PORT_DDI_A_4_LANES";
2361         case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2362                 return "PORT_DDI_B_2_LANES";
2363         case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2364                 return "PORT_DDI_B_4_LANES";
2365         case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2366                 return "PORT_DDI_C_2_LANES";
2367         case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2368                 return "PORT_DDI_C_4_LANES";
2369         case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2370                 return "PORT_DDI_D_2_LANES";
2371         case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2372                 return "PORT_DDI_D_4_LANES";
2373         case POWER_DOMAIN_PORT_DSI:
2374                 return "PORT_DSI";
2375         case POWER_DOMAIN_PORT_CRT:
2376                 return "PORT_CRT";
2377         case POWER_DOMAIN_PORT_OTHER:
2378                 return "PORT_OTHER";
2379         case POWER_DOMAIN_VGA:
2380                 return "VGA";
2381         case POWER_DOMAIN_AUDIO:
2382                 return "AUDIO";
2383         case POWER_DOMAIN_PLLS:
2384                 return "PLLS";
2385         case POWER_DOMAIN_INIT:
2386                 return "INIT";
2387         default:
2388                 MISSING_CASE(domain);
2389                 return "?";
2390         }
2391 }
2392
2393 static int i915_power_domain_info(struct seq_file *m, void *unused)
2394 {
2395         struct drm_info_node *node = m->private;
2396         struct drm_device *dev = node->minor->dev;
2397         struct drm_i915_private *dev_priv = dev->dev_private;
2398         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2399         int i;
2400
2401         mutex_lock(&power_domains->lock);
2402
2403         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2404         for (i = 0; i < power_domains->power_well_count; i++) {
2405                 struct i915_power_well *power_well;
2406                 enum intel_display_power_domain power_domain;
2407
2408                 power_well = &power_domains->power_wells[i];
2409                 seq_printf(m, "%-25s %d\n", power_well->name,
2410                            power_well->count);
2411
2412                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2413                      power_domain++) {
2414                         if (!(BIT(power_domain) & power_well->domains))
2415                                 continue;
2416
2417                         seq_printf(m, "  %-23s %d\n",
2418                                  power_domain_str(power_domain),
2419                                  power_domains->domain_use_count[power_domain]);
2420                 }
2421         }
2422
2423         mutex_unlock(&power_domains->lock);
2424
2425         return 0;
2426 }
2427
2428 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2429                                  struct drm_display_mode *mode)
2430 {
2431         int i;
2432
2433         for (i = 0; i < tabs; i++)
2434                 seq_putc(m, '\t');
2435
2436         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2437                    mode->base.id, mode->name,
2438                    mode->vrefresh, mode->clock,
2439                    mode->hdisplay, mode->hsync_start,
2440                    mode->hsync_end, mode->htotal,
2441                    mode->vdisplay, mode->vsync_start,
2442                    mode->vsync_end, mode->vtotal,
2443                    mode->type, mode->flags);
2444 }
2445
2446 static void intel_encoder_info(struct seq_file *m,
2447                                struct intel_crtc *intel_crtc,
2448                                struct intel_encoder *intel_encoder)
2449 {
2450         struct drm_info_node *node = m->private;
2451         struct drm_device *dev = node->minor->dev;
2452         struct drm_crtc *crtc = &intel_crtc->base;
2453         struct intel_connector *intel_connector;
2454         struct drm_encoder *encoder;
2455
2456         encoder = &intel_encoder->base;
2457         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2458                    encoder->base.id, encoder->name);
2459         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2460                 struct drm_connector *connector = &intel_connector->base;
2461                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2462                            connector->base.id,
2463                            connector->name,
2464                            drm_get_connector_status_name(connector->status));
2465                 if (connector->status == connector_status_connected) {
2466                         struct drm_display_mode *mode = &crtc->mode;
2467                         seq_printf(m, ", mode:\n");
2468                         intel_seq_print_mode(m, 2, mode);
2469                 } else {
2470                         seq_putc(m, '\n');
2471                 }
2472         }
2473 }
2474
2475 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2476 {
2477         struct drm_info_node *node = m->private;
2478         struct drm_device *dev = node->minor->dev;
2479         struct drm_crtc *crtc = &intel_crtc->base;
2480         struct intel_encoder *intel_encoder;
2481
2482         if (crtc->primary->fb)
2483                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2484                            crtc->primary->fb->base.id, crtc->x, crtc->y,
2485                            crtc->primary->fb->width, crtc->primary->fb->height);
2486         else
2487                 seq_puts(m, "\tprimary plane disabled\n");
2488         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2489                 intel_encoder_info(m, intel_crtc, intel_encoder);
2490 }
2491
2492 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2493 {
2494         struct drm_display_mode *mode = panel->fixed_mode;
2495
2496         seq_printf(m, "\tfixed mode:\n");
2497         intel_seq_print_mode(m, 2, mode);
2498 }
2499
2500 static void intel_dp_info(struct seq_file *m,
2501                           struct intel_connector *intel_connector)
2502 {
2503         struct intel_encoder *intel_encoder = intel_connector->encoder;
2504         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2505
2506         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2507         seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2508                    "no");
2509         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2510                 intel_panel_info(m, &intel_connector->panel);
2511 }
2512
2513 static void intel_hdmi_info(struct seq_file *m,
2514                             struct intel_connector *intel_connector)
2515 {
2516         struct intel_encoder *intel_encoder = intel_connector->encoder;
2517         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2518
2519         seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2520                    "no");
2521 }
2522
2523 static void intel_lvds_info(struct seq_file *m,
2524                             struct intel_connector *intel_connector)
2525 {
2526         intel_panel_info(m, &intel_connector->panel);
2527 }
2528
2529 static void intel_connector_info(struct seq_file *m,
2530                                  struct drm_connector *connector)
2531 {
2532         struct intel_connector *intel_connector = to_intel_connector(connector);
2533         struct intel_encoder *intel_encoder = intel_connector->encoder;
2534         struct drm_display_mode *mode;
2535
2536         seq_printf(m, "connector %d: type %s, status: %s\n",
2537                    connector->base.id, connector->name,
2538                    drm_get_connector_status_name(connector->status));
2539         if (connector->status == connector_status_connected) {
2540                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2541                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2542                            connector->display_info.width_mm,
2543                            connector->display_info.height_mm);
2544                 seq_printf(m, "\tsubpixel order: %s\n",
2545                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2546                 seq_printf(m, "\tCEA rev: %d\n",
2547                            connector->display_info.cea_rev);
2548         }
2549         if (intel_encoder) {
2550                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2551                     intel_encoder->type == INTEL_OUTPUT_EDP)
2552                         intel_dp_info(m, intel_connector);
2553                 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2554                         intel_hdmi_info(m, intel_connector);
2555                 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2556                         intel_lvds_info(m, intel_connector);
2557         }
2558
2559         seq_printf(m, "\tmodes:\n");
2560         list_for_each_entry(mode, &connector->modes, head)
2561                 intel_seq_print_mode(m, 2, mode);
2562 }
2563
2564 static bool cursor_active(struct drm_device *dev, int pipe)
2565 {
2566         struct drm_i915_private *dev_priv = dev->dev_private;
2567         u32 state;
2568
2569         if (IS_845G(dev) || IS_I865G(dev))
2570                 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2571         else
2572                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2573
2574         return state;
2575 }
2576
2577 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2578 {
2579         struct drm_i915_private *dev_priv = dev->dev_private;
2580         u32 pos;
2581
2582         pos = I915_READ(CURPOS(pipe));
2583
2584         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2585         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2586                 *x = -*x;
2587
2588         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2589         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2590                 *y = -*y;
2591
2592         return cursor_active(dev, pipe);
2593 }
2594
2595 static int i915_display_info(struct seq_file *m, void *unused)
2596 {
2597         struct drm_info_node *node = m->private;
2598         struct drm_device *dev = node->minor->dev;
2599         struct drm_i915_private *dev_priv = dev->dev_private;
2600         struct intel_crtc *crtc;
2601         struct drm_connector *connector;
2602
2603         intel_runtime_pm_get(dev_priv);
2604         drm_modeset_lock_all(dev);
2605         seq_printf(m, "CRTC info\n");
2606         seq_printf(m, "---------\n");
2607         for_each_intel_crtc(dev, crtc) {
2608                 bool active;
2609                 int x, y;
2610
2611                 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2612                            crtc->base.base.id, pipe_name(crtc->pipe),
2613                            yesno(crtc->active), crtc->config->pipe_src_w,
2614                            crtc->config->pipe_src_h);
2615                 if (crtc->active) {
2616                         intel_crtc_info(m, crtc);
2617
2618                         active = cursor_position(dev, crtc->pipe, &x, &y);
2619                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2620                                    yesno(crtc->cursor_base),
2621                                    x, y, crtc->cursor_width, crtc->cursor_height,
2622                                    crtc->cursor_addr, yesno(active));
2623                 }
2624
2625                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2626                            yesno(!crtc->cpu_fifo_underrun_disabled),
2627                            yesno(!crtc->pch_fifo_underrun_disabled));
2628         }
2629
2630         seq_printf(m, "\n");
2631         seq_printf(m, "Connector info\n");
2632         seq_printf(m, "--------------\n");
2633         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2634                 intel_connector_info(m, connector);
2635         }
2636         drm_modeset_unlock_all(dev);
2637         intel_runtime_pm_put(dev_priv);
2638
2639         return 0;
2640 }
2641
2642 static int i915_semaphore_status(struct seq_file *m, void *unused)
2643 {
2644         struct drm_info_node *node = (struct drm_info_node *) m->private;
2645         struct drm_device *dev = node->minor->dev;
2646         struct drm_i915_private *dev_priv = dev->dev_private;
2647         struct intel_engine_cs *ring;
2648         int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2649         int i, j, ret;
2650
2651         if (!i915_semaphore_is_enabled(dev)) {
2652                 seq_puts(m, "Semaphores are disabled\n");
2653                 return 0;
2654         }
2655
2656         ret = mutex_lock_interruptible(&dev->struct_mutex);
2657         if (ret)
2658                 return ret;
2659         intel_runtime_pm_get(dev_priv);
2660
2661         if (IS_BROADWELL(dev)) {
2662                 struct page *page;
2663                 uint64_t *seqno;
2664
2665                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2666
2667                 seqno = (uint64_t *)kmap_atomic(page);
2668                 for_each_ring(ring, dev_priv, i) {
2669                         uint64_t offset;
2670
2671                         seq_printf(m, "%s\n", ring->name);
2672
2673                         seq_puts(m, "  Last signal:");
2674                         for (j = 0; j < num_rings; j++) {
2675                                 offset = i * I915_NUM_RINGS + j;
2676                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2677                                            seqno[offset], offset * 8);
2678                         }
2679                         seq_putc(m, '\n');
2680
2681                         seq_puts(m, "  Last wait:  ");
2682                         for (j = 0; j < num_rings; j++) {
2683                                 offset = i + (j * I915_NUM_RINGS);
2684                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2685                                            seqno[offset], offset * 8);
2686                         }
2687                         seq_putc(m, '\n');
2688
2689                 }
2690                 kunmap_atomic(seqno);
2691         } else {
2692                 seq_puts(m, "  Last signal:");
2693                 for_each_ring(ring, dev_priv, i)
2694                         for (j = 0; j < num_rings; j++)
2695                                 seq_printf(m, "0x%08x\n",
2696                                            I915_READ(ring->semaphore.mbox.signal[j]));
2697                 seq_putc(m, '\n');
2698         }
2699
2700         seq_puts(m, "\nSync seqno:\n");
2701         for_each_ring(ring, dev_priv, i) {
2702                 for (j = 0; j < num_rings; j++) {
2703                         seq_printf(m, "  0x%08x ", ring->semaphore.sync_seqno[j]);
2704                 }
2705                 seq_putc(m, '\n');
2706         }
2707         seq_putc(m, '\n');
2708
2709         intel_runtime_pm_put(dev_priv);
2710         mutex_unlock(&dev->struct_mutex);
2711         return 0;
2712 }
2713
2714 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2715 {
2716         struct drm_info_node *node = (struct drm_info_node *) m->private;
2717         struct drm_device *dev = node->minor->dev;
2718         struct drm_i915_private *dev_priv = dev->dev_private;
2719         int i;
2720
2721         drm_modeset_lock_all(dev);
2722         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2723                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2724
2725                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2726                 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2727                            pll->config.crtc_mask, pll->active, yesno(pll->on));
2728                 seq_printf(m, " tracked hardware state:\n");
2729                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
2730                 seq_printf(m, " dpll_md: 0x%08x\n",
2731                            pll->config.hw_state.dpll_md);
2732                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
2733                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
2734                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
2735         }
2736         drm_modeset_unlock_all(dev);
2737
2738         return 0;
2739 }
2740
2741 static int i915_wa_registers(struct seq_file *m, void *unused)
2742 {
2743         int i;
2744         int ret;
2745         struct drm_info_node *node = (struct drm_info_node *) m->private;
2746         struct drm_device *dev = node->minor->dev;
2747         struct drm_i915_private *dev_priv = dev->dev_private;
2748
2749         ret = mutex_lock_interruptible(&dev->struct_mutex);
2750         if (ret)
2751                 return ret;
2752
2753         intel_runtime_pm_get(dev_priv);
2754
2755         seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2756         for (i = 0; i < dev_priv->workarounds.count; ++i) {
2757                 u32 addr, mask, value, read;
2758                 bool ok;
2759
2760                 addr = dev_priv->workarounds.reg[i].addr;
2761                 mask = dev_priv->workarounds.reg[i].mask;
2762                 value = dev_priv->workarounds.reg[i].value;
2763                 read = I915_READ(addr);
2764                 ok = (value & mask) == (read & mask);
2765                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2766                            addr, value, mask, read, ok ? "OK" : "FAIL");
2767         }
2768
2769         intel_runtime_pm_put(dev_priv);
2770         mutex_unlock(&dev->struct_mutex);
2771
2772         return 0;
2773 }
2774
2775 static int i915_ddb_info(struct seq_file *m, void *unused)
2776 {
2777         struct drm_info_node *node = m->private;
2778         struct drm_device *dev = node->minor->dev;
2779         struct drm_i915_private *dev_priv = dev->dev_private;
2780         struct skl_ddb_allocation *ddb;
2781         struct skl_ddb_entry *entry;
2782         enum pipe pipe;
2783         int plane;
2784
2785         if (INTEL_INFO(dev)->gen < 9)
2786                 return 0;
2787
2788         drm_modeset_lock_all(dev);
2789
2790         ddb = &dev_priv->wm.skl_hw.ddb;
2791
2792         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2793
2794         for_each_pipe(dev_priv, pipe) {
2795                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2796
2797                 for_each_plane(pipe, plane) {
2798                         entry = &ddb->plane[pipe][plane];
2799                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
2800                                    entry->start, entry->end,
2801                                    skl_ddb_entry_size(entry));
2802                 }
2803
2804                 entry = &ddb->cursor[pipe];
2805                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
2806                            entry->end, skl_ddb_entry_size(entry));
2807         }
2808
2809         drm_modeset_unlock_all(dev);
2810
2811         return 0;
2812 }
2813
2814 struct pipe_crc_info {
2815         const char *name;
2816         struct drm_device *dev;
2817         enum pipe pipe;
2818 };
2819
2820 static int i915_dp_mst_info(struct seq_file *m, void *unused)
2821 {
2822         struct drm_info_node *node = (struct drm_info_node *) m->private;
2823         struct drm_device *dev = node->minor->dev;
2824         struct drm_encoder *encoder;
2825         struct intel_encoder *intel_encoder;
2826         struct intel_digital_port *intel_dig_port;
2827         drm_modeset_lock_all(dev);
2828         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2829                 intel_encoder = to_intel_encoder(encoder);
2830                 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2831                         continue;
2832                 intel_dig_port = enc_to_dig_port(encoder);
2833                 if (!intel_dig_port->dp.can_mst)
2834                         continue;
2835
2836                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2837         }
2838         drm_modeset_unlock_all(dev);
2839         return 0;
2840 }
2841
2842 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2843 {
2844         struct pipe_crc_info *info = inode->i_private;
2845         struct drm_i915_private *dev_priv = info->dev->dev_private;
2846         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2847
2848         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2849                 return -ENODEV;
2850
2851         spin_lock_irq(&pipe_crc->lock);
2852
2853         if (pipe_crc->opened) {
2854                 spin_unlock_irq(&pipe_crc->lock);
2855                 return -EBUSY; /* already open */
2856         }
2857
2858         pipe_crc->opened = true;
2859         filep->private_data = inode->i_private;
2860
2861         spin_unlock_irq(&pipe_crc->lock);
2862
2863         return 0;
2864 }
2865
2866 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2867 {
2868         struct pipe_crc_info *info = inode->i_private;
2869         struct drm_i915_private *dev_priv = info->dev->dev_private;
2870         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2871
2872         spin_lock_irq(&pipe_crc->lock);
2873         pipe_crc->opened = false;
2874         spin_unlock_irq(&pipe_crc->lock);
2875
2876         return 0;
2877 }
2878
2879 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2880 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
2881 /* account for \'0' */
2882 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
2883
2884 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2885 {
2886         assert_spin_locked(&pipe_crc->lock);
2887         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2888                         INTEL_PIPE_CRC_ENTRIES_NR);
2889 }
2890
2891 static ssize_t
2892 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2893                    loff_t *pos)
2894 {
2895         struct pipe_crc_info *info = filep->private_data;
2896         struct drm_device *dev = info->dev;
2897         struct drm_i915_private *dev_priv = dev->dev_private;
2898         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2899         char buf[PIPE_CRC_BUFFER_LEN];
2900         int n_entries;
2901         ssize_t bytes_read;
2902
2903         /*
2904          * Don't allow user space to provide buffers not big enough to hold
2905          * a line of data.
2906          */
2907         if (count < PIPE_CRC_LINE_LEN)
2908                 return -EINVAL;
2909
2910         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2911                 return 0;
2912
2913         /* nothing to read */
2914         spin_lock_irq(&pipe_crc->lock);
2915         while (pipe_crc_data_count(pipe_crc) == 0) {
2916                 int ret;
2917
2918                 if (filep->f_flags & O_NONBLOCK) {
2919                         spin_unlock_irq(&pipe_crc->lock);
2920                         return -EAGAIN;
2921                 }
2922
2923                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2924                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2925                 if (ret) {
2926                         spin_unlock_irq(&pipe_crc->lock);
2927                         return ret;
2928                 }
2929         }
2930
2931         /* We now have one or more entries to read */
2932         n_entries = count / PIPE_CRC_LINE_LEN;
2933
2934         bytes_read = 0;
2935         while (n_entries > 0) {
2936                 struct intel_pipe_crc_entry *entry =
2937                         &pipe_crc->entries[pipe_crc->tail];
2938                 int ret;
2939
2940                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2941                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
2942                         break;
2943
2944                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2945                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2946
2947                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2948                                        "%8u %8x %8x %8x %8x %8x\n",
2949                                        entry->frame, entry->crc[0],
2950                                        entry->crc[1], entry->crc[2],
2951                                        entry->crc[3], entry->crc[4]);
2952
2953                 spin_unlock_irq(&pipe_crc->lock);
2954
2955                 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
2956                 if (ret == PIPE_CRC_LINE_LEN)
2957                         return -EFAULT;
2958
2959                 user_buf += PIPE_CRC_LINE_LEN;
2960                 n_entries--;
2961
2962                 spin_lock_irq(&pipe_crc->lock);
2963         }
2964
2965         spin_unlock_irq(&pipe_crc->lock);
2966
2967         return bytes_read;
2968 }
2969
2970 static const struct file_operations i915_pipe_crc_fops = {
2971         .owner = THIS_MODULE,
2972         .open = i915_pipe_crc_open,
2973         .read = i915_pipe_crc_read,
2974         .release = i915_pipe_crc_release,
2975 };
2976
2977 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2978         {
2979                 .name = "i915_pipe_A_crc",
2980                 .pipe = PIPE_A,
2981         },
2982         {
2983                 .name = "i915_pipe_B_crc",
2984                 .pipe = PIPE_B,
2985         },
2986         {
2987                 .name = "i915_pipe_C_crc",
2988                 .pipe = PIPE_C,
2989         },
2990 };
2991
2992 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2993                                 enum pipe pipe)
2994 {
2995         struct drm_device *dev = minor->dev;
2996         struct dentry *ent;
2997         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2998
2999         info->dev = dev;
3000         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3001                                   &i915_pipe_crc_fops);
3002         if (!ent)
3003                 return -ENOMEM;
3004
3005         return drm_add_fake_info_node(minor, ent, info);
3006 }
3007
3008 static const char * const pipe_crc_sources[] = {
3009         "none",
3010         "plane1",
3011         "plane2",
3012         "pf",
3013         "pipe",
3014         "TV",
3015         "DP-B",
3016         "DP-C",
3017         "DP-D",
3018         "auto",
3019 };
3020
3021 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3022 {
3023         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3024         return pipe_crc_sources[source];
3025 }
3026
3027 static int display_crc_ctl_show(struct seq_file *m, void *data)
3028 {
3029         struct drm_device *dev = m->private;
3030         struct drm_i915_private *dev_priv = dev->dev_private;
3031         int i;
3032
3033         for (i = 0; i < I915_MAX_PIPES; i++)
3034                 seq_printf(m, "%c %s\n", pipe_name(i),
3035                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3036
3037         return 0;
3038 }
3039
3040 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3041 {
3042         struct drm_device *dev = inode->i_private;
3043
3044         return single_open(file, display_crc_ctl_show, dev);
3045 }
3046
3047 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3048                                  uint32_t *val)
3049 {
3050         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3051                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3052
3053         switch (*source) {
3054         case INTEL_PIPE_CRC_SOURCE_PIPE:
3055                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3056                 break;
3057         case INTEL_PIPE_CRC_SOURCE_NONE:
3058                 *val = 0;
3059                 break;
3060         default:
3061                 return -EINVAL;
3062         }
3063
3064         return 0;
3065 }
3066
3067 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3068                                      enum intel_pipe_crc_source *source)
3069 {
3070         struct intel_encoder *encoder;
3071         struct intel_crtc *crtc;
3072         struct intel_digital_port *dig_port;
3073         int ret = 0;
3074
3075         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3076
3077         drm_modeset_lock_all(dev);
3078         for_each_intel_encoder(dev, encoder) {
3079                 if (!encoder->base.crtc)
3080                         continue;
3081
3082                 crtc = to_intel_crtc(encoder->base.crtc);
3083
3084                 if (crtc->pipe != pipe)
3085                         continue;
3086
3087                 switch (encoder->type) {
3088                 case INTEL_OUTPUT_TVOUT:
3089                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3090                         break;
3091                 case INTEL_OUTPUT_DISPLAYPORT:
3092                 case INTEL_OUTPUT_EDP:
3093                         dig_port = enc_to_dig_port(&encoder->base);
3094                         switch (dig_port->port) {
3095                         case PORT_B:
3096                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3097                                 break;
3098                         case PORT_C:
3099                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3100                                 break;
3101                         case PORT_D:
3102                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3103                                 break;
3104                         default:
3105                                 WARN(1, "nonexisting DP port %c\n",
3106                                      port_name(dig_port->port));
3107                                 break;
3108                         }
3109                         break;
3110                 default:
3111                         break;
3112                 }
3113         }
3114         drm_modeset_unlock_all(dev);
3115
3116         return ret;
3117 }
3118
3119 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3120                                 enum pipe pipe,
3121                                 enum intel_pipe_crc_source *source,
3122                                 uint32_t *val)
3123 {
3124         struct drm_i915_private *dev_priv = dev->dev_private;
3125         bool need_stable_symbols = false;
3126
3127         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3128                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3129                 if (ret)
3130                         return ret;
3131         }
3132
3133         switch (*source) {
3134         case INTEL_PIPE_CRC_SOURCE_PIPE:
3135                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3136                 break;
3137         case INTEL_PIPE_CRC_SOURCE_DP_B:
3138                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3139                 need_stable_symbols = true;
3140                 break;
3141         case INTEL_PIPE_CRC_SOURCE_DP_C:
3142                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3143                 need_stable_symbols = true;
3144                 break;
3145         case INTEL_PIPE_CRC_SOURCE_DP_D:
3146                 if (!IS_CHERRYVIEW(dev))
3147                         return -EINVAL;
3148                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3149                 need_stable_symbols = true;
3150                 break;
3151         case INTEL_PIPE_CRC_SOURCE_NONE:
3152                 *val = 0;
3153                 break;
3154         default:
3155                 return -EINVAL;
3156         }
3157
3158         /*
3159          * When the pipe CRC tap point is after the transcoders we need
3160          * to tweak symbol-level features to produce a deterministic series of
3161          * symbols for a given frame. We need to reset those features only once
3162          * a frame (instead of every nth symbol):
3163          *   - DC-balance: used to ensure a better clock recovery from the data
3164          *     link (SDVO)
3165          *   - DisplayPort scrambling: used for EMI reduction
3166          */
3167         if (need_stable_symbols) {
3168                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3169
3170                 tmp |= DC_BALANCE_RESET_VLV;
3171                 switch (pipe) {
3172                 case PIPE_A:
3173                         tmp |= PIPE_A_SCRAMBLE_RESET;
3174                         break;
3175                 case PIPE_B:
3176                         tmp |= PIPE_B_SCRAMBLE_RESET;
3177                         break;
3178                 case PIPE_C:
3179                         tmp |= PIPE_C_SCRAMBLE_RESET;
3180                         break;
3181                 default:
3182                         return -EINVAL;
3183                 }
3184                 I915_WRITE(PORT_DFT2_G4X, tmp);
3185         }
3186
3187         return 0;
3188 }
3189
3190 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3191                                  enum pipe pipe,
3192                                  enum intel_pipe_crc_source *source,
3193                                  uint32_t *val)
3194 {
3195         struct drm_i915_private *dev_priv = dev->dev_private;
3196         bool need_stable_symbols = false;
3197
3198         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3199                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3200                 if (ret)
3201                         return ret;
3202         }
3203
3204         switch (*source) {
3205         case INTEL_PIPE_CRC_SOURCE_PIPE:
3206                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3207                 break;
3208         case INTEL_PIPE_CRC_SOURCE_TV:
3209                 if (!SUPPORTS_TV(dev))
3210                         return -EINVAL;
3211                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3212                 break;
3213         case INTEL_PIPE_CRC_SOURCE_DP_B:
3214                 if (!IS_G4X(dev))
3215                         return -EINVAL;
3216                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3217                 need_stable_symbols = true;
3218                 break;
3219         case INTEL_PIPE_CRC_SOURCE_DP_C:
3220                 if (!IS_G4X(dev))
3221                         return -EINVAL;
3222                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3223                 need_stable_symbols = true;
3224                 break;
3225         case INTEL_PIPE_CRC_SOURCE_DP_D:
3226                 if (!IS_G4X(dev))
3227                         return -EINVAL;
3228                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3229                 need_stable_symbols = true;
3230                 break;
3231         case INTEL_PIPE_CRC_SOURCE_NONE:
3232                 *val = 0;
3233                 break;
3234         default:
3235                 return -EINVAL;
3236         }
3237
3238         /*
3239          * When the pipe CRC tap point is after the transcoders we need
3240          * to tweak symbol-level features to produce a deterministic series of
3241          * symbols for a given frame. We need to reset those features only once
3242          * a frame (instead of every nth symbol):
3243          *   - DC-balance: used to ensure a better clock recovery from the data
3244          *     link (SDVO)
3245          *   - DisplayPort scrambling: used for EMI reduction
3246          */
3247         if (need_stable_symbols) {
3248                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3249
3250                 WARN_ON(!IS_G4X(dev));
3251
3252                 I915_WRITE(PORT_DFT_I9XX,
3253                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3254
3255                 if (pipe == PIPE_A)
3256                         tmp |= PIPE_A_SCRAMBLE_RESET;
3257                 else
3258                         tmp |= PIPE_B_SCRAMBLE_RESET;
3259
3260                 I915_WRITE(PORT_DFT2_G4X, tmp);
3261         }
3262
3263         return 0;
3264 }
3265
3266 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3267                                          enum pipe pipe)
3268 {
3269         struct drm_i915_private *dev_priv = dev->dev_private;
3270         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3271
3272         switch (pipe) {
3273         case PIPE_A:
3274                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3275                 break;
3276         case PIPE_B:
3277                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3278                 break;
3279         case PIPE_C:
3280                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3281                 break;
3282         default:
3283                 return;
3284         }
3285         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3286                 tmp &= ~DC_BALANCE_RESET_VLV;
3287         I915_WRITE(PORT_DFT2_G4X, tmp);
3288
3289 }
3290
3291 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3292                                          enum pipe pipe)
3293 {
3294         struct drm_i915_private *dev_priv = dev->dev_private;
3295         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3296
3297         if (pipe == PIPE_A)
3298                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3299         else
3300                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3301         I915_WRITE(PORT_DFT2_G4X, tmp);
3302
3303         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3304                 I915_WRITE(PORT_DFT_I9XX,
3305                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3306         }
3307 }
3308
3309 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3310                                 uint32_t *val)
3311 {
3312         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3313                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3314
3315         switch (*source) {
3316         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3317                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3318                 break;
3319         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3320                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3321                 break;
3322         case INTEL_PIPE_CRC_SOURCE_PIPE:
3323                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3324                 break;
3325         case INTEL_PIPE_CRC_SOURCE_NONE:
3326                 *val = 0;
3327                 break;
3328         default:
3329                 return -EINVAL;
3330         }
3331
3332         return 0;
3333 }
3334
3335 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3336 {
3337         struct drm_i915_private *dev_priv = dev->dev_private;
3338         struct intel_crtc *crtc =
3339                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3340
3341         drm_modeset_lock_all(dev);
3342         /*
3343          * If we use the eDP transcoder we need to make sure that we don't
3344          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3345          * relevant on hsw with pipe A when using the always-on power well
3346          * routing.
3347          */
3348         if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3349             !crtc->config->pch_pfit.enabled) {
3350                 crtc->config->pch_pfit.force_thru = true;
3351
3352                 intel_display_power_get(dev_priv,
3353                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3354
3355                 dev_priv->display.crtc_disable(&crtc->base);
3356                 dev_priv->display.crtc_enable(&crtc->base);
3357         }
3358         drm_modeset_unlock_all(dev);
3359 }
3360
3361 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3362 {
3363         struct drm_i915_private *dev_priv = dev->dev_private;
3364         struct intel_crtc *crtc =
3365                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3366
3367         drm_modeset_lock_all(dev);
3368         /*
3369          * If we use the eDP transcoder we need to make sure that we don't
3370          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3371          * relevant on hsw with pipe A when using the always-on power well
3372          * routing.
3373          */
3374         if (crtc->config->pch_pfit.force_thru) {
3375                 crtc->config->pch_pfit.force_thru = false;
3376
3377                 dev_priv->display.crtc_disable(&crtc->base);
3378                 dev_priv->display.crtc_enable(&crtc->base);
3379
3380                 intel_display_power_put(dev_priv,
3381                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3382         }
3383         drm_modeset_unlock_all(dev);
3384 }
3385
3386 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3387                                 enum pipe pipe,
3388                                 enum intel_pipe_crc_source *source,
3389                                 uint32_t *val)
3390 {
3391         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3392                 *source = INTEL_PIPE_CRC_SOURCE_PF;
3393
3394         switch (*source) {
3395         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3396                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3397                 break;
3398         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3399                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3400                 break;
3401         case INTEL_PIPE_CRC_SOURCE_PF:
3402                 if (IS_HASWELL(dev) && pipe == PIPE_A)
3403                         hsw_trans_edp_pipe_A_crc_wa(dev);
3404
3405                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3406                 break;
3407         case INTEL_PIPE_CRC_SOURCE_NONE:
3408                 *val = 0;
3409                 break;
3410         default:
3411                 return -EINVAL;
3412         }
3413
3414         return 0;
3415 }
3416
3417 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3418                                enum intel_pipe_crc_source source)
3419 {
3420         struct drm_i915_private *dev_priv = dev->dev_private;
3421         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3422         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3423                                                                         pipe));
3424         u32 val = 0; /* shut up gcc */
3425         int ret;
3426
3427         if (pipe_crc->source == source)
3428                 return 0;
3429
3430         /* forbid changing the source without going back to 'none' */
3431         if (pipe_crc->source && source)
3432                 return -EINVAL;
3433
3434         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3435                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3436                 return -EIO;
3437         }
3438
3439         if (IS_GEN2(dev))
3440                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3441         else if (INTEL_INFO(dev)->gen < 5)
3442                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3443         else if (IS_VALLEYVIEW(dev))
3444                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3445         else if (IS_GEN5(dev) || IS_GEN6(dev))
3446                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3447         else
3448                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3449
3450         if (ret != 0)
3451                 return ret;
3452
3453         /* none -> real source transition */
3454         if (source) {
3455                 struct intel_pipe_crc_entry *entries;
3456
3457                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3458                                  pipe_name(pipe), pipe_crc_source_name(source));
3459
3460                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3461                                   sizeof(pipe_crc->entries[0]),
3462                                   GFP_KERNEL);
3463                 if (!entries)
3464                         return -ENOMEM;
3465
3466                 /*
3467                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3468                  * enabled and disabled dynamically based on package C states,
3469                  * user space can't make reliable use of the CRCs, so let's just
3470                  * completely disable it.
3471                  */
3472                 hsw_disable_ips(crtc);
3473
3474                 spin_lock_irq(&pipe_crc->lock);
3475                 kfree(pipe_crc->entries);
3476                 pipe_crc->entries = entries;
3477                 pipe_crc->head = 0;
3478                 pipe_crc->tail = 0;
3479                 spin_unlock_irq(&pipe_crc->lock);
3480         }
3481
3482         pipe_crc->source = source;
3483
3484         I915_WRITE(PIPE_CRC_CTL(pipe), val);
3485         POSTING_READ(PIPE_CRC_CTL(pipe));
3486
3487         /* real source -> none transition */
3488         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3489                 struct intel_pipe_crc_entry *entries;
3490                 struct intel_crtc *crtc =
3491                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3492
3493                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3494                                  pipe_name(pipe));
3495
3496                 drm_modeset_lock(&crtc->base.mutex, NULL);
3497                 if (crtc->active)
3498                         intel_wait_for_vblank(dev, pipe);
3499                 drm_modeset_unlock(&crtc->base.mutex);
3500
3501                 spin_lock_irq(&pipe_crc->lock);
3502                 entries = pipe_crc->entries;
3503                 pipe_crc->entries = NULL;
3504                 pipe_crc->head = 0;
3505                 pipe_crc->tail = 0;
3506                 spin_unlock_irq(&pipe_crc->lock);
3507
3508                 kfree(entries);
3509
3510                 if (IS_G4X(dev))
3511                         g4x_undo_pipe_scramble_reset(dev, pipe);
3512                 else if (IS_VALLEYVIEW(dev))
3513                         vlv_undo_pipe_scramble_reset(dev, pipe);
3514                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3515                         hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3516
3517                 hsw_enable_ips(crtc);
3518         }
3519
3520         return 0;
3521 }
3522
3523 /*
3524  * Parse pipe CRC command strings:
3525  *   command: wsp* object wsp+ name wsp+ source wsp*
3526  *   object: 'pipe'
3527  *   name: (A | B | C)
3528  *   source: (none | plane1 | plane2 | pf)
3529  *   wsp: (#0x20 | #0x9 | #0xA)+
3530  *
3531  * eg.:
3532  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
3533  *  "pipe A none"    ->  Stop CRC
3534  */
3535 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3536 {
3537         int n_words = 0;
3538
3539         while (*buf) {
3540                 char *end;
3541
3542                 /* skip leading white space */
3543                 buf = skip_spaces(buf);
3544                 if (!*buf)
3545                         break;  /* end of buffer */
3546
3547                 /* find end of word */
3548                 for (end = buf; *end && !isspace(*end); end++)
3549                         ;
3550
3551                 if (n_words == max_words) {
3552                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3553                                          max_words);
3554                         return -EINVAL; /* ran out of words[] before bytes */
3555                 }
3556
3557                 if (*end)
3558                         *end++ = '\0';
3559                 words[n_words++] = buf;
3560                 buf = end;
3561         }
3562
3563         return n_words;
3564 }
3565
3566 enum intel_pipe_crc_object {
3567         PIPE_CRC_OBJECT_PIPE,
3568 };
3569
3570 static const char * const pipe_crc_objects[] = {
3571         "pipe",
3572 };
3573
3574 static int
3575 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3576 {
3577         int i;
3578
3579         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3580                 if (!strcmp(buf, pipe_crc_objects[i])) {
3581                         *o = i;
3582                         return 0;
3583                     }
3584
3585         return -EINVAL;
3586 }
3587
3588 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3589 {
3590         const char name = buf[0];
3591
3592         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3593                 return -EINVAL;
3594
3595         *pipe = name - 'A';
3596
3597         return 0;
3598 }
3599
3600 static int
3601 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3602 {
3603         int i;
3604
3605         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3606                 if (!strcmp(buf, pipe_crc_sources[i])) {
3607                         *s = i;
3608                         return 0;
3609                     }
3610
3611         return -EINVAL;
3612 }
3613
3614 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3615 {
3616 #define N_WORDS 3
3617         int n_words;
3618         char *words[N_WORDS];
3619         enum pipe pipe;
3620         enum intel_pipe_crc_object object;
3621         enum intel_pipe_crc_source source;
3622
3623         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3624         if (n_words != N_WORDS) {
3625                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3626                                  N_WORDS);
3627                 return -EINVAL;
3628         }
3629
3630         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3631                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3632                 return -EINVAL;
3633         }
3634
3635         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3636                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3637                 return -EINVAL;
3638         }
3639
3640         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3641                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3642                 return -EINVAL;
3643         }
3644
3645         return pipe_crc_set_source(dev, pipe, source);
3646 }
3647
3648 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3649                                      size_t len, loff_t *offp)
3650 {
3651         struct seq_file *m = file->private_data;
3652         struct drm_device *dev = m->private;
3653         char *tmpbuf;
3654         int ret;
3655
3656         if (len == 0)
3657                 return 0;
3658
3659         if (len > PAGE_SIZE - 1) {
3660                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3661                                  PAGE_SIZE);
3662                 return -E2BIG;
3663         }
3664
3665         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3666         if (!tmpbuf)
3667                 return -ENOMEM;
3668
3669         if (copy_from_user(tmpbuf, ubuf, len)) {
3670                 ret = -EFAULT;
3671                 goto out;
3672         }
3673         tmpbuf[len] = '\0';
3674
3675         ret = display_crc_ctl_parse(dev, tmpbuf, len);
3676
3677 out:
3678         kfree(tmpbuf);
3679         if (ret < 0)
3680                 return ret;
3681
3682         *offp += len;
3683         return len;
3684 }
3685
3686 static const struct file_operations i915_display_crc_ctl_fops = {
3687         .owner = THIS_MODULE,
3688         .open = display_crc_ctl_open,
3689         .read = seq_read,
3690         .llseek = seq_lseek,
3691         .release = single_release,
3692         .write = display_crc_ctl_write
3693 };
3694
3695 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3696 {
3697         struct drm_device *dev = m->private;
3698         int num_levels = ilk_wm_max_level(dev) + 1;
3699         int level;
3700
3701         drm_modeset_lock_all(dev);
3702
3703         for (level = 0; level < num_levels; level++) {
3704                 unsigned int latency = wm[level];
3705
3706                 /*
3707                  * - WM1+ latency values in 0.5us units
3708                  * - latencies are in us on gen9
3709                  */
3710                 if (INTEL_INFO(dev)->gen >= 9)
3711                         latency *= 10;
3712                 else if (level > 0)
3713                         latency *= 5;
3714
3715                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3716                            level, wm[level], latency / 10, latency % 10);
3717         }
3718
3719         drm_modeset_unlock_all(dev);
3720 }
3721
3722 static int pri_wm_latency_show(struct seq_file *m, void *data)
3723 {
3724         struct drm_device *dev = m->private;
3725         struct drm_i915_private *dev_priv = dev->dev_private;
3726         const uint16_t *latencies;
3727
3728         if (INTEL_INFO(dev)->gen >= 9)
3729                 latencies = dev_priv->wm.skl_latency;
3730         else
3731                 latencies = to_i915(dev)->wm.pri_latency;
3732
3733         wm_latency_show(m, latencies);
3734
3735         return 0;
3736 }
3737
3738 static int spr_wm_latency_show(struct seq_file *m, void *data)
3739 {
3740         struct drm_device *dev = m->private;
3741         struct drm_i915_private *dev_priv = dev->dev_private;
3742         const uint16_t *latencies;
3743
3744         if (INTEL_INFO(dev)->gen >= 9)
3745                 latencies = dev_priv->wm.skl_latency;
3746         else
3747                 latencies = to_i915(dev)->wm.spr_latency;
3748
3749         wm_latency_show(m, latencies);
3750
3751         return 0;
3752 }
3753
3754 static int cur_wm_latency_show(struct seq_file *m, void *data)
3755 {
3756         struct drm_device *dev = m->private;
3757         struct drm_i915_private *dev_priv = dev->dev_private;
3758         const uint16_t *latencies;
3759
3760         if (INTEL_INFO(dev)->gen >= 9)
3761                 latencies = dev_priv->wm.skl_latency;
3762         else
3763                 latencies = to_i915(dev)->wm.cur_latency;
3764
3765         wm_latency_show(m, latencies);
3766
3767         return 0;
3768 }
3769
3770 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3771 {
3772         struct drm_device *dev = inode->i_private;
3773
3774         if (HAS_GMCH_DISPLAY(dev))
3775                 return -ENODEV;
3776
3777         return single_open(file, pri_wm_latency_show, dev);
3778 }
3779
3780 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3781 {
3782         struct drm_device *dev = inode->i_private;
3783
3784         if (HAS_GMCH_DISPLAY(dev))
3785                 return -ENODEV;
3786
3787         return single_open(file, spr_wm_latency_show, dev);
3788 }
3789
3790 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3791 {
3792         struct drm_device *dev = inode->i_private;
3793
3794         if (HAS_GMCH_DISPLAY(dev))
3795                 return -ENODEV;
3796
3797         return single_open(file, cur_wm_latency_show, dev);
3798 }
3799
3800 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3801                                 size_t len, loff_t *offp, uint16_t wm[8])
3802 {
3803         struct seq_file *m = file->private_data;
3804         struct drm_device *dev = m->private;
3805         uint16_t new[8] = { 0 };
3806         int num_levels = ilk_wm_max_level(dev) + 1;
3807         int level;
3808         int ret;
3809         char tmp[32];
3810
3811         if (len >= sizeof(tmp))
3812                 return -EINVAL;
3813
3814         if (copy_from_user(tmp, ubuf, len))
3815                 return -EFAULT;
3816
3817         tmp[len] = '\0';
3818
3819         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3820                      &new[0], &new[1], &new[2], &new[3],
3821                      &new[4], &new[5], &new[6], &new[7]);
3822         if (ret != num_levels)
3823                 return -EINVAL;
3824
3825         drm_modeset_lock_all(dev);
3826
3827         for (level = 0; level < num_levels; level++)
3828                 wm[level] = new[level];
3829
3830         drm_modeset_unlock_all(dev);
3831
3832         return len;
3833 }
3834
3835
3836 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3837                                     size_t len, loff_t *offp)
3838 {
3839         struct seq_file *m = file->private_data;
3840         struct drm_device *dev = m->private;
3841         struct drm_i915_private *dev_priv = dev->dev_private;
3842         uint16_t *latencies;
3843
3844         if (INTEL_INFO(dev)->gen >= 9)
3845                 latencies = dev_priv->wm.skl_latency;
3846         else
3847                 latencies = to_i915(dev)->wm.pri_latency;
3848
3849         return wm_latency_write(file, ubuf, len, offp, latencies);
3850 }
3851
3852 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3853                                     size_t len, loff_t *offp)
3854 {
3855         struct seq_file *m = file->private_data;
3856         struct drm_device *dev = m->private;
3857         struct drm_i915_private *dev_priv = dev->dev_private;
3858         uint16_t *latencies;
3859
3860         if (INTEL_INFO(dev)->gen >= 9)
3861                 latencies = dev_priv->wm.skl_latency;
3862         else
3863                 latencies = to_i915(dev)->wm.spr_latency;
3864
3865         return wm_latency_write(file, ubuf, len, offp, latencies);
3866 }
3867
3868 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3869                                     size_t len, loff_t *offp)
3870 {
3871         struct seq_file *m = file->private_data;
3872         struct drm_device *dev = m->private;
3873         struct drm_i915_private *dev_priv = dev->dev_private;
3874         uint16_t *latencies;
3875
3876         if (INTEL_INFO(dev)->gen >= 9)
3877                 latencies = dev_priv->wm.skl_latency;
3878         else
3879                 latencies = to_i915(dev)->wm.cur_latency;
3880
3881         return wm_latency_write(file, ubuf, len, offp, latencies);
3882 }
3883
3884 static const struct file_operations i915_pri_wm_latency_fops = {
3885         .owner = THIS_MODULE,
3886         .open = pri_wm_latency_open,
3887         .read = seq_read,
3888         .llseek = seq_lseek,
3889         .release = single_release,
3890         .write = pri_wm_latency_write
3891 };
3892
3893 static const struct file_operations i915_spr_wm_latency_fops = {
3894         .owner = THIS_MODULE,
3895         .open = spr_wm_latency_open,
3896         .read = seq_read,
3897         .llseek = seq_lseek,
3898         .release = single_release,
3899         .write = spr_wm_latency_write
3900 };
3901
3902 static const struct file_operations i915_cur_wm_latency_fops = {
3903         .owner = THIS_MODULE,
3904         .open = cur_wm_latency_open,
3905         .read = seq_read,
3906         .llseek = seq_lseek,
3907         .release = single_release,
3908         .write = cur_wm_latency_write
3909 };
3910
3911 static int
3912 i915_wedged_get(void *data, u64 *val)
3913 {
3914         struct drm_device *dev = data;
3915         struct drm_i915_private *dev_priv = dev->dev_private;
3916
3917         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
3918
3919         return 0;
3920 }
3921
3922 static int
3923 i915_wedged_set(void *data, u64 val)
3924 {
3925         struct drm_device *dev = data;
3926         struct drm_i915_private *dev_priv = dev->dev_private;
3927
3928         intel_runtime_pm_get(dev_priv);
3929
3930         i915_handle_error(dev, val,
3931                           "Manually setting wedged to %llu", val);
3932
3933         intel_runtime_pm_put(dev_priv);
3934
3935         return 0;
3936 }
3937
3938 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3939                         i915_wedged_get, i915_wedged_set,
3940                         "%llu\n");
3941
3942 static int
3943 i915_ring_stop_get(void *data, u64 *val)
3944 {
3945         struct drm_device *dev = data;
3946         struct drm_i915_private *dev_priv = dev->dev_private;
3947
3948         *val = dev_priv->gpu_error.stop_rings;
3949
3950         return 0;
3951 }
3952
3953 static int
3954 i915_ring_stop_set(void *data, u64 val)
3955 {
3956         struct drm_device *dev = data;
3957         struct drm_i915_private *dev_priv = dev->dev_private;
3958         int ret;
3959
3960         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
3961
3962         ret = mutex_lock_interruptible(&dev->struct_mutex);
3963         if (ret)
3964                 return ret;
3965
3966         dev_priv->gpu_error.stop_rings = val;
3967         mutex_unlock(&dev->struct_mutex);
3968
3969         return 0;
3970 }
3971
3972 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3973                         i915_ring_stop_get, i915_ring_stop_set,
3974                         "0x%08llx\n");
3975
3976 static int
3977 i915_ring_missed_irq_get(void *data, u64 *val)
3978 {
3979         struct drm_device *dev = data;
3980         struct drm_i915_private *dev_priv = dev->dev_private;
3981
3982         *val = dev_priv->gpu_error.missed_irq_rings;
3983         return 0;
3984 }
3985
3986 static int
3987 i915_ring_missed_irq_set(void *data, u64 val)
3988 {
3989         struct drm_device *dev = data;
3990         struct drm_i915_private *dev_priv = dev->dev_private;
3991         int ret;
3992
3993         /* Lock against concurrent debugfs callers */
3994         ret = mutex_lock_interruptible(&dev->struct_mutex);
3995         if (ret)
3996                 return ret;
3997         dev_priv->gpu_error.missed_irq_rings = val;
3998         mutex_unlock(&dev->struct_mutex);
3999
4000         return 0;
4001 }
4002
4003 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4004                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4005                         "0x%08llx\n");
4006
4007 static int
4008 i915_ring_test_irq_get(void *data, u64 *val)
4009 {
4010         struct drm_device *dev = data;
4011         struct drm_i915_private *dev_priv = dev->dev_private;
4012
4013         *val = dev_priv->gpu_error.test_irq_rings;
4014
4015         return 0;
4016 }
4017
4018 static int
4019 i915_ring_test_irq_set(void *data, u64 val)
4020 {
4021         struct drm_device *dev = data;
4022         struct drm_i915_private *dev_priv = dev->dev_private;
4023         int ret;
4024
4025         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4026
4027         /* Lock against concurrent debugfs callers */
4028         ret = mutex_lock_interruptible(&dev->struct_mutex);
4029         if (ret)
4030                 return ret;
4031
4032         dev_priv->gpu_error.test_irq_rings = val;
4033         mutex_unlock(&dev->struct_mutex);
4034
4035         return 0;
4036 }
4037
4038 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4039                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4040                         "0x%08llx\n");
4041
4042 #define DROP_UNBOUND 0x1
4043 #define DROP_BOUND 0x2
4044 #define DROP_RETIRE 0x4
4045 #define DROP_ACTIVE 0x8
4046 #define DROP_ALL (DROP_UNBOUND | \
4047                   DROP_BOUND | \
4048                   DROP_RETIRE | \
4049                   DROP_ACTIVE)
4050 static int
4051 i915_drop_caches_get(void *data, u64 *val)
4052 {
4053         *val = DROP_ALL;
4054
4055         return 0;
4056 }
4057
4058 static int
4059 i915_drop_caches_set(void *data, u64 val)
4060 {
4061         struct drm_device *dev = data;
4062         struct drm_i915_private *dev_priv = dev->dev_private;
4063         int ret;
4064
4065         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4066
4067         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4068          * on ioctls on -EAGAIN. */
4069         ret = mutex_lock_interruptible(&dev->struct_mutex);
4070         if (ret)
4071                 return ret;
4072
4073         if (val & DROP_ACTIVE) {
4074                 ret = i915_gpu_idle(dev);
4075                 if (ret)
4076                         goto unlock;
4077         }
4078
4079         if (val & (DROP_RETIRE | DROP_ACTIVE))
4080                 i915_gem_retire_requests(dev);
4081
4082         if (val & DROP_BOUND)
4083                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4084
4085         if (val & DROP_UNBOUND)
4086                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4087
4088 unlock:
4089         mutex_unlock(&dev->struct_mutex);
4090
4091         return ret;
4092 }
4093
4094 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4095                         i915_drop_caches_get, i915_drop_caches_set,
4096                         "0x%08llx\n");
4097
4098 static int
4099 i915_max_freq_get(void *data, u64 *val)
4100 {
4101         struct drm_device *dev = data;
4102         struct drm_i915_private *dev_priv = dev->dev_private;
4103         int ret;
4104
4105         if (INTEL_INFO(dev)->gen < 6)
4106                 return -ENODEV;
4107
4108         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4109
4110         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4111         if (ret)
4112                 return ret;
4113
4114         if (IS_VALLEYVIEW(dev))
4115                 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4116         else
4117                 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4118         mutex_unlock(&dev_priv->rps.hw_lock);
4119
4120         return 0;
4121 }
4122
4123 static int
4124 i915_max_freq_set(void *data, u64 val)
4125 {
4126         struct drm_device *dev = data;
4127         struct drm_i915_private *dev_priv = dev->dev_private;
4128         u32 rp_state_cap, hw_max, hw_min;
4129         int ret;
4130
4131         if (INTEL_INFO(dev)->gen < 6)
4132                 return -ENODEV;
4133
4134         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4135
4136         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4137
4138         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4139         if (ret)
4140                 return ret;
4141
4142         /*
4143          * Turbo will still be enabled, but won't go above the set value.
4144          */
4145         if (IS_VALLEYVIEW(dev)) {
4146                 val = vlv_freq_opcode(dev_priv, val);
4147
4148                 hw_max = dev_priv->rps.max_freq;
4149                 hw_min = dev_priv->rps.min_freq;
4150         } else {
4151                 do_div(val, GT_FREQUENCY_MULTIPLIER);
4152
4153                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4154                 hw_max = dev_priv->rps.max_freq;
4155                 hw_min = (rp_state_cap >> 16) & 0xff;
4156         }
4157
4158         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4159                 mutex_unlock(&dev_priv->rps.hw_lock);
4160                 return -EINVAL;
4161         }
4162
4163         dev_priv->rps.max_freq_softlimit = val;
4164
4165         if (IS_VALLEYVIEW(dev))
4166                 valleyview_set_rps(dev, val);
4167         else
4168                 gen6_set_rps(dev, val);
4169
4170         mutex_unlock(&dev_priv->rps.hw_lock);
4171
4172         return 0;
4173 }
4174
4175 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4176                         i915_max_freq_get, i915_max_freq_set,
4177                         "%llu\n");
4178
4179 static int
4180 i915_min_freq_get(void *data, u64 *val)
4181 {
4182         struct drm_device *dev = data;
4183         struct drm_i915_private *dev_priv = dev->dev_private;
4184         int ret;
4185
4186         if (INTEL_INFO(dev)->gen < 6)
4187                 return -ENODEV;
4188
4189         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4190
4191         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4192         if (ret)
4193                 return ret;
4194
4195         if (IS_VALLEYVIEW(dev))
4196                 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4197         else
4198                 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4199         mutex_unlock(&dev_priv->rps.hw_lock);
4200
4201         return 0;
4202 }
4203
4204 static int
4205 i915_min_freq_set(void *data, u64 val)
4206 {
4207         struct drm_device *dev = data;
4208         struct drm_i915_private *dev_priv = dev->dev_private;
4209         u32 rp_state_cap, hw_max, hw_min;
4210         int ret;
4211
4212         if (INTEL_INFO(dev)->gen < 6)
4213                 return -ENODEV;
4214
4215         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4216
4217         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4218
4219         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4220         if (ret)
4221                 return ret;
4222
4223         /*
4224          * Turbo will still be enabled, but won't go below the set value.
4225          */
4226         if (IS_VALLEYVIEW(dev)) {
4227                 val = vlv_freq_opcode(dev_priv, val);
4228
4229                 hw_max = dev_priv->rps.max_freq;
4230                 hw_min = dev_priv->rps.min_freq;
4231         } else {
4232                 do_div(val, GT_FREQUENCY_MULTIPLIER);
4233
4234                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4235                 hw_max = dev_priv->rps.max_freq;
4236                 hw_min = (rp_state_cap >> 16) & 0xff;
4237         }
4238
4239         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4240                 mutex_unlock(&dev_priv->rps.hw_lock);
4241                 return -EINVAL;
4242         }
4243
4244         dev_priv->rps.min_freq_softlimit = val;
4245
4246         if (IS_VALLEYVIEW(dev))
4247                 valleyview_set_rps(dev, val);
4248         else
4249                 gen6_set_rps(dev, val);
4250
4251         mutex_unlock(&dev_priv->rps.hw_lock);
4252
4253         return 0;
4254 }
4255
4256 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4257                         i915_min_freq_get, i915_min_freq_set,
4258                         "%llu\n");
4259
4260 static int
4261 i915_cache_sharing_get(void *data, u64 *val)
4262 {
4263         struct drm_device *dev = data;
4264         struct drm_i915_private *dev_priv = dev->dev_private;
4265         u32 snpcr;
4266         int ret;
4267
4268         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4269                 return -ENODEV;
4270
4271         ret = mutex_lock_interruptible(&dev->struct_mutex);
4272         if (ret)
4273                 return ret;
4274         intel_runtime_pm_get(dev_priv);
4275
4276         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4277
4278         intel_runtime_pm_put(dev_priv);
4279         mutex_unlock(&dev_priv->dev->struct_mutex);
4280
4281         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4282
4283         return 0;
4284 }
4285
4286 static int
4287 i915_cache_sharing_set(void *data, u64 val)
4288 {
4289         struct drm_device *dev = data;
4290         struct drm_i915_private *dev_priv = dev->dev_private;
4291         u32 snpcr;
4292
4293         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4294                 return -ENODEV;
4295
4296         if (val > 3)
4297                 return -EINVAL;
4298
4299         intel_runtime_pm_get(dev_priv);
4300         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4301
4302         /* Update the cache sharing policy here as well */
4303         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4304         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4305         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4306         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4307
4308         intel_runtime_pm_put(dev_priv);
4309         return 0;
4310 }
4311
4312 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4313                         i915_cache_sharing_get, i915_cache_sharing_set,
4314                         "%llu\n");
4315
4316 static int i915_forcewake_open(struct inode *inode, struct file *file)
4317 {
4318         struct drm_device *dev = inode->i_private;
4319         struct drm_i915_private *dev_priv = dev->dev_private;
4320
4321         if (INTEL_INFO(dev)->gen < 6)
4322                 return 0;
4323
4324         intel_runtime_pm_get(dev_priv);
4325         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4326
4327         return 0;
4328 }
4329
4330 static int i915_forcewake_release(struct inode *inode, struct file *file)
4331 {
4332         struct drm_device *dev = inode->i_private;
4333         struct drm_i915_private *dev_priv = dev->dev_private;
4334
4335         if (INTEL_INFO(dev)->gen < 6)
4336                 return 0;
4337
4338         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4339         intel_runtime_pm_put(dev_priv);
4340
4341         return 0;
4342 }
4343
4344 static const struct file_operations i915_forcewake_fops = {
4345         .owner = THIS_MODULE,
4346         .open = i915_forcewake_open,
4347         .release = i915_forcewake_release,
4348 };
4349
4350 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4351 {
4352         struct drm_device *dev = minor->dev;
4353         struct dentry *ent;
4354
4355         ent = debugfs_create_file("i915_forcewake_user",
4356                                   S_IRUSR,
4357                                   root, dev,
4358                                   &i915_forcewake_fops);
4359         if (!ent)
4360                 return -ENOMEM;
4361
4362         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
4363 }
4364
4365 static int i915_debugfs_create(struct dentry *root,
4366                                struct drm_minor *minor,
4367                                const char *name,
4368                                const struct file_operations *fops)
4369 {
4370         struct drm_device *dev = minor->dev;
4371         struct dentry *ent;
4372
4373         ent = debugfs_create_file(name,
4374                                   S_IRUGO | S_IWUSR,
4375                                   root, dev,
4376                                   fops);
4377         if (!ent)
4378                 return -ENOMEM;
4379
4380         return drm_add_fake_info_node(minor, ent, fops);
4381 }
4382
4383 static const struct drm_info_list i915_debugfs_list[] = {
4384         {"i915_capabilities", i915_capabilities, 0},
4385         {"i915_gem_objects", i915_gem_object_info, 0},
4386         {"i915_gem_gtt", i915_gem_gtt_info, 0},
4387         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
4388         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
4389         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
4390         {"i915_gem_stolen", i915_gem_stolen_list_info },
4391         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
4392         {"i915_gem_request", i915_gem_request_info, 0},
4393         {"i915_gem_seqno", i915_gem_seqno_info, 0},
4394         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4395         {"i915_gem_interrupt", i915_interrupt_info, 0},
4396         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4397         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4398         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
4399         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
4400         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
4401         {"i915_frequency_info", i915_frequency_info, 0},
4402         {"i915_drpc_info", i915_drpc_info, 0},
4403         {"i915_emon_status", i915_emon_status, 0},
4404         {"i915_ring_freq_table", i915_ring_freq_table, 0},
4405         {"i915_fbc_status", i915_fbc_status, 0},
4406         {"i915_ips_status", i915_ips_status, 0},
4407         {"i915_sr_status", i915_sr_status, 0},
4408         {"i915_opregion", i915_opregion, 0},
4409         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4410         {"i915_context_status", i915_context_status, 0},
4411         {"i915_dump_lrc", i915_dump_lrc, 0},
4412         {"i915_execlists", i915_execlists, 0},
4413         {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
4414         {"i915_swizzle_info", i915_swizzle_info, 0},
4415         {"i915_ppgtt_info", i915_ppgtt_info, 0},
4416         {"i915_llc", i915_llc, 0},
4417         {"i915_edp_psr_status", i915_edp_psr_status, 0},
4418         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4419         {"i915_energy_uJ", i915_energy_uJ, 0},
4420         {"i915_pc8_status", i915_pc8_status, 0},
4421         {"i915_power_domain_info", i915_power_domain_info, 0},
4422         {"i915_display_info", i915_display_info, 0},
4423         {"i915_semaphore_status", i915_semaphore_status, 0},
4424         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4425         {"i915_dp_mst_info", i915_dp_mst_info, 0},
4426         {"i915_wa_registers", i915_wa_registers, 0},
4427         {"i915_ddb_info", i915_ddb_info, 0},
4428 };
4429 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4430
4431 static const struct i915_debugfs_files {
4432         const char *name;
4433         const struct file_operations *fops;
4434 } i915_debugfs_files[] = {
4435         {"i915_wedged", &i915_wedged_fops},
4436         {"i915_max_freq", &i915_max_freq_fops},
4437         {"i915_min_freq", &i915_min_freq_fops},
4438         {"i915_cache_sharing", &i915_cache_sharing_fops},
4439         {"i915_ring_stop", &i915_ring_stop_fops},
4440         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4441         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4442         {"i915_gem_drop_caches", &i915_drop_caches_fops},
4443         {"i915_error_state", &i915_error_state_fops},
4444         {"i915_next_seqno", &i915_next_seqno_fops},
4445         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4446         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4447         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4448         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4449         {"i915_fbc_false_color", &i915_fbc_fc_fops},
4450 };
4451
4452 void intel_display_crc_init(struct drm_device *dev)
4453 {
4454         struct drm_i915_private *dev_priv = dev->dev_private;
4455         enum pipe pipe;
4456
4457         for_each_pipe(dev_priv, pipe) {
4458                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4459
4460                 pipe_crc->opened = false;
4461                 spin_lock_init(&pipe_crc->lock);
4462                 init_waitqueue_head(&pipe_crc->wq);
4463         }
4464 }
4465
4466 int i915_debugfs_init(struct drm_minor *minor)
4467 {
4468         int ret, i;
4469
4470         ret = i915_forcewake_create(minor->debugfs_root, minor);
4471         if (ret)
4472                 return ret;
4473
4474         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4475                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4476                 if (ret)
4477                         return ret;
4478         }
4479
4480         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4481                 ret = i915_debugfs_create(minor->debugfs_root, minor,
4482                                           i915_debugfs_files[i].name,
4483                                           i915_debugfs_files[i].fops);
4484                 if (ret)
4485                         return ret;
4486         }
4487
4488         return drm_debugfs_create_files(i915_debugfs_list,
4489                                         I915_DEBUGFS_ENTRIES,
4490                                         minor->debugfs_root, minor);
4491 }
4492
4493 void i915_debugfs_cleanup(struct drm_minor *minor)
4494 {
4495         int i;
4496
4497         drm_debugfs_remove_files(i915_debugfs_list,
4498                                  I915_DEBUGFS_ENTRIES, minor);
4499
4500         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4501                                  1, minor);
4502
4503         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4504                 struct drm_info_list *info_list =
4505                         (struct drm_info_list *)&i915_pipe_crc_data[i];
4506
4507                 drm_debugfs_remove_files(info_list, 1, minor);
4508         }
4509
4510         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4511                 struct drm_info_list *info_list =
4512                         (struct drm_info_list *) i915_debugfs_files[i].fops;
4513
4514                 drm_debugfs_remove_files(info_list, 1, minor);
4515         }
4516 }