drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 static const char *yesno(int v)
  50 {
  51         return v ? "yes" : "no";
  52 }
  53
  54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  55  * allocated we need to hook into the minor for release. */
  56 static int
  57 drm_add_fake_info_node(struct drm_minor *minor,
  58                        struct dentry *ent,
  59                        const void *key)
  60 {
  61         struct drm_info_node *node;
  62
  63         node = kmalloc(sizeof(*node), GFP_KERNEL);
  64         if (node == NULL) {
  65                 debugfs_remove(ent);
  66                 return -ENOMEM;
  67         }
  68
  69         node->minor = minor;
  70         node->dent = ent;
  71         node->info_ent = (void *) key;
  72
  73         mutex_lock(&minor->debugfs_lock);
  74         list_add(&node->list, &minor->debugfs_list);
  75         mutex_unlock(&minor->debugfs_lock);
  76
  77         return 0;
  78 }
  79
  80 static int i915_capabilities(struct seq_file *m, void *data)
  81 {
  82         struct drm_info_node *node = m->private;
  83         struct drm_device *dev = node->minor->dev;
  84         const struct intel_device_info *info = INTEL_INFO(dev);
  85
  86         seq_printf(m, "gen: %d\n", info->gen);
  87         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  88 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  89 #define SEP_SEMICOLON ;
  90         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  91 #undef PRINT_FLAG
  92 #undef SEP_SEMICOLON
  93
  94         return 0;
  95 }
  96
  97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  98 {
  99         if (obj->pin_display)
 100                 return "p";
 101         else
 102                 return " ";
 103 }
 104
 105 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 106 {
 107         switch (obj->tiling_mode) {
 108         default:
 109         case I915_TILING_NONE: return " ";
 110         case I915_TILING_X: return "X";
 111         case I915_TILING_Y: return "Y";
 112         }
 113 }
 114
 115 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 116 {
 117         return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
 118 }
 119
 120 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 121 {
 122         u64 size = 0;
 123         struct i915_vma *vma;
 124
 125         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 126                 if (i915_is_ggtt(vma->vm) &&
 127                     drm_mm_node_allocated(&vma->node))
 128                         size += vma->node.size;
 129         }
 130
 131         return size;
 132 }
 133
 134 static void
 135 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 136 {
 137         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 138         struct intel_engine_cs *ring;
 139         struct i915_vma *vma;
 140         int pin_count = 0;
 141         int i;
 142
 143         seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
 144                    &obj->base,
 145                    obj->active ? "*" : " ",
 146                    get_pin_flag(obj),
 147                    get_tiling_flag(obj),
 148                    get_global_flag(obj),
 149                    obj->base.size / 1024,
 150                    obj->base.read_domains,
 151                    obj->base.write_domain);
 152         for_each_ring(ring, dev_priv, i)
 153                 seq_printf(m, "%x ",
 154                                 i915_gem_request_get_seqno(obj->last_read_req[i]));
 155         seq_printf(m, "] %x %x%s%s%s",
 156                    i915_gem_request_get_seqno(obj->last_write_req),
 157                    i915_gem_request_get_seqno(obj->last_fenced_req),
 158                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 159                    obj->dirty ? " dirty" : "",
 160                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 161         if (obj->base.name)
 162                 seq_printf(m, " (name: %d)", obj->base.name);
 163         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 164                 if (vma->pin_count > 0)
 165                         pin_count++;
 166         }
 167         seq_printf(m, " (pinned x %d)", pin_count);
 168         if (obj->pin_display)
 169                 seq_printf(m, " (display)");
 170         if (obj->fence_reg != I915_FENCE_REG_NONE)
 171                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 172         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 173                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 174                            i915_is_ggtt(vma->vm) ? "g" : "pp",
 175                            vma->node.start, vma->node.size);
 176                 if (i915_is_ggtt(vma->vm))
 177                         seq_printf(m, ", type: %u)", vma->ggtt_view.type);
 178                 else
 179                         seq_puts(m, ")");
 180         }
 181         if (obj->stolen)
 182                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 183         if (obj->pin_display || obj->fault_mappable) {
 184                 char s[3], *t = s;
 185                 if (obj->pin_display)
 186                         *t++ = 'p';
 187                 if (obj->fault_mappable)
 188                         *t++ = 'f';
 189                 *t = '\0';
 190                 seq_printf(m, " (%s mappable)", s);
 191         }
 192         if (obj->last_write_req != NULL)
 193                 seq_printf(m, " (%s)",
 194                            i915_gem_request_get_ring(obj->last_write_req)->name);
 195         if (obj->frontbuffer_bits)
 196                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 197 }
 198
 199 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
 200 {
 201         seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
 202         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 203         seq_putc(m, ' ');
 204 }
 205
 206 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 207 {
 208         struct drm_info_node *node = m->private;
 209         uintptr_t list = (uintptr_t) node->info_ent->data;
 210         struct list_head *head;
 211         struct drm_device *dev = node->minor->dev;
 212         struct drm_i915_private *dev_priv = dev->dev_private;
 213         struct i915_address_space *vm = &dev_priv->gtt.base;
 214         struct i915_vma *vma;
 215         u64 total_obj_size, total_gtt_size;
 216         int count, ret;
 217
 218         ret = mutex_lock_interruptible(&dev->struct_mutex);
 219         if (ret)
 220                 return ret;
 221
 222         /* FIXME: the user of this interface might want more than just GGTT */
 223         switch (list) {
 224         case ACTIVE_LIST:
 225                 seq_puts(m, "Active:\n");
 226                 head = &vm->active_list;
 227                 break;
 228         case INACTIVE_LIST:
 229                 seq_puts(m, "Inactive:\n");
 230                 head = &vm->inactive_list;
 231                 break;
 232         default:
 233                 mutex_unlock(&dev->struct_mutex);
 234                 return -EINVAL;
 235         }
 236
 237         total_obj_size = total_gtt_size = count = 0;
 238         list_for_each_entry(vma, head, mm_list) {
 239                 seq_printf(m, "   ");
 240                 describe_obj(m, vma->obj);
 241                 seq_printf(m, "\n");
 242                 total_obj_size += vma->obj->base.size;
 243                 total_gtt_size += vma->node.size;
 244                 count++;
 245         }
 246         mutex_unlock(&dev->struct_mutex);
 247
 248         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 249                    count, total_obj_size, total_gtt_size);
 250         return 0;
 251 }
 252
 253 static int obj_rank_by_stolen(void *priv,
 254                               struct list_head *A, struct list_head *B)
 255 {
 256         struct drm_i915_gem_object *a =
 257                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 258         struct drm_i915_gem_object *b =
 259                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 260
 261         return a->stolen->start - b->stolen->start;
 262 }
 263
 264 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 265 {
 266         struct drm_info_node *node = m->private;
 267         struct drm_device *dev = node->minor->dev;
 268         struct drm_i915_private *dev_priv = dev->dev_private;
 269         struct drm_i915_gem_object *obj;
 270         u64 total_obj_size, total_gtt_size;
 271         LIST_HEAD(stolen);
 272         int count, ret;
 273
 274         ret = mutex_lock_interruptible(&dev->struct_mutex);
 275         if (ret)
 276                 return ret;
 277
 278         total_obj_size = total_gtt_size = count = 0;
 279         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 280                 if (obj->stolen == NULL)
 281                         continue;
 282
 283                 list_add(&obj->obj_exec_link, &stolen);
 284
 285                 total_obj_size += obj->base.size;
 286                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 287                 count++;
 288         }
 289         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 290                 if (obj->stolen == NULL)
 291                         continue;
 292
 293                 list_add(&obj->obj_exec_link, &stolen);
 294
 295                 total_obj_size += obj->base.size;
 296                 count++;
 297         }
 298         list_sort(NULL, &stolen, obj_rank_by_stolen);
 299         seq_puts(m, "Stolen:\n");
 300         while (!list_empty(&stolen)) {
 301                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 302                 seq_puts(m, "   ");
 303                 describe_obj(m, obj);
 304                 seq_putc(m, '\n');
 305                 list_del_init(&obj->obj_exec_link);
 306         }
 307         mutex_unlock(&dev->struct_mutex);
 308
 309         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 310                    count, total_obj_size, total_gtt_size);
 311         return 0;
 312 }
 313
 314 #define count_objects(list, member) do { \
 315         list_for_each_entry(obj, list, member) { \
 316                 size += i915_gem_obj_total_ggtt_size(obj); \
 317                 ++count; \
 318                 if (obj->map_and_fenceable) { \
 319                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 320                         ++mappable_count; \
 321                 } \
 322         } \
 323 } while (0)
 324
 325 struct file_stats {
 326         struct drm_i915_file_private *file_priv;
 327         unsigned long count;
 328         u64 total, unbound;
 329         u64 global, shared;
 330         u64 active, inactive;
 331 };
 332
 333 static int per_file_stats(int id, void *ptr, void *data)
 334 {
 335         struct drm_i915_gem_object *obj = ptr;
 336         struct file_stats *stats = data;
 337         struct i915_vma *vma;
 338
 339         stats->count++;
 340         stats->total += obj->base.size;
 341
 342         if (obj->base.name || obj->base.dma_buf)
 343                 stats->shared += obj->base.size;
 344
 345         if (USES_FULL_PPGTT(obj->base.dev)) {
 346                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
 347                         struct i915_hw_ppgtt *ppgtt;
 348
 349                         if (!drm_mm_node_allocated(&vma->node))
 350                                 continue;
 351
 352                         if (i915_is_ggtt(vma->vm)) {
 353                                 stats->global += obj->base.size;
 354                                 continue;
 355                         }
 356
 357                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 358                         if (ppgtt->file_priv != stats->file_priv)
 359                                 continue;
 360
 361                         if (obj->active) /* XXX per-vma statistic */
 362                                 stats->active += obj->base.size;
 363                         else
 364                                 stats->inactive += obj->base.size;
 365
 366                         return 0;
 367                 }
 368         } else {
 369                 if (i915_gem_obj_ggtt_bound(obj)) {
 370                         stats->global += obj->base.size;
 371                         if (obj->active)
 372                                 stats->active += obj->base.size;
 373                         else
 374                                 stats->inactive += obj->base.size;
 375                         return 0;
 376                 }
 377         }
 378
 379         if (!list_empty(&obj->global_list))
 380                 stats->unbound += obj->base.size;
 381
 382         return 0;
 383 }
 384
 385 #define print_file_stats(m, name, stats) do { \
 386         if (stats.count) \
 387                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 388                            name, \
 389                            stats.count, \
 390                            stats.total, \
 391                            stats.active, \
 392                            stats.inactive, \
 393                            stats.global, \
 394                            stats.shared, \
 395                            stats.unbound); \
 396 } while (0)
 397
 398 static void print_batch_pool_stats(struct seq_file *m,
 399                                    struct drm_i915_private *dev_priv)
 400 {
 401         struct drm_i915_gem_object *obj;
 402         struct file_stats stats;
 403         struct intel_engine_cs *ring;
 404         int i, j;
 405
 406         memset(&stats, 0, sizeof(stats));
 407
 408         for_each_ring(ring, dev_priv, i) {
 409                 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
 410                         list_for_each_entry(obj,
 411                                             &ring->batch_pool.cache_list[j],
 412                                             batch_pool_link)
 413                                 per_file_stats(0, obj, &stats);
 414                 }
 415         }
 416
 417         print_file_stats(m, "[k]batch pool", stats);
 418 }
 419
 420 #define count_vmas(list, member) do { \
 421         list_for_each_entry(vma, list, member) { \
 422                 size += i915_gem_obj_total_ggtt_size(vma->obj); \
 423                 ++count; \
 424                 if (vma->obj->map_and_fenceable) { \
 425                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 426                         ++mappable_count; \
 427                 } \
 428         } \
 429 } while (0)
 430
 431 static int i915_gem_object_info(struct seq_file *m, void* data)
 432 {
 433         struct drm_info_node *node = m->private;
 434         struct drm_device *dev = node->minor->dev;
 435         struct drm_i915_private *dev_priv = dev->dev_private;
 436         u32 count, mappable_count, purgeable_count;
 437         u64 size, mappable_size, purgeable_size;
 438         struct drm_i915_gem_object *obj;
 439         struct i915_address_space *vm = &dev_priv->gtt.base;
 440         struct drm_file *file;
 441         struct i915_vma *vma;
 442         int ret;
 443
 444         ret = mutex_lock_interruptible(&dev->struct_mutex);
 445         if (ret)
 446                 return ret;
 447
 448         seq_printf(m, "%u objects, %zu bytes\n",
 449                    dev_priv->mm.object_count,
 450                    dev_priv->mm.object_memory);
 451
 452         size = count = mappable_size = mappable_count = 0;
 453         count_objects(&dev_priv->mm.bound_list, global_list);
 454         seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
 455                    count, mappable_count, size, mappable_size);
 456
 457         size = count = mappable_size = mappable_count = 0;
 458         count_vmas(&vm->active_list, mm_list);
 459         seq_printf(m, "  %u [%u] active objects, %llu [%llu] bytes\n",
 460                    count, mappable_count, size, mappable_size);
 461
 462         size = count = mappable_size = mappable_count = 0;
 463         count_vmas(&vm->inactive_list, mm_list);
 464         seq_printf(m, "  %u [%u] inactive objects, %llu [%llu] bytes\n",
 465                    count, mappable_count, size, mappable_size);
 466
 467         size = count = purgeable_size = purgeable_count = 0;
 468         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 469                 size += obj->base.size, ++count;
 470                 if (obj->madv == I915_MADV_DONTNEED)
 471                         purgeable_size += obj->base.size, ++purgeable_count;
 472         }
 473         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 474
 475         size = count = mappable_size = mappable_count = 0;
 476         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 477                 if (obj->fault_mappable) {
 478                         size += i915_gem_obj_ggtt_size(obj);
 479                         ++count;
 480                 }
 481                 if (obj->pin_display) {
 482                         mappable_size += i915_gem_obj_ggtt_size(obj);
 483                         ++mappable_count;
 484                 }
 485                 if (obj->madv == I915_MADV_DONTNEED) {
 486                         purgeable_size += obj->base.size;
 487                         ++purgeable_count;
 488                 }
 489         }
 490         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 491                    purgeable_count, purgeable_size);
 492         seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
 493                    mappable_count, mappable_size);
 494         seq_printf(m, "%u fault mappable objects, %llu bytes\n",
 495                    count, size);
 496
 497         seq_printf(m, "%llu [%llu] gtt total\n",
 498                    dev_priv->gtt.base.total,
 499                    (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 500
 501         seq_putc(m, '\n');
 502         print_batch_pool_stats(m, dev_priv);
 503         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 504                 struct file_stats stats;
 505                 struct task_struct *task;
 506
 507                 memset(&stats, 0, sizeof(stats));
 508                 stats.file_priv = file->driver_priv;
 509                 spin_lock(&file->table_lock);
 510                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 511                 spin_unlock(&file->table_lock);
 512                 /*
 513                  * Although we have a valid reference on file->pid, that does
 514                  * not guarantee that the task_struct who called get_pid() is
 515                  * still alive (e.g. get_pid(current) => fork() => exit()).
 516                  * Therefore, we need to protect this ->comm access using RCU.
 517                  */
 518                 rcu_read_lock();
 519                 task = pid_task(file->pid, PIDTYPE_PID);
 520                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 521                 rcu_read_unlock();
 522         }
 523
 524         mutex_unlock(&dev->struct_mutex);
 525
 526         return 0;
 527 }
 528
 529 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 530 {
 531         struct drm_info_node *node = m->private;
 532         struct drm_device *dev = node->minor->dev;
 533         uintptr_t list = (uintptr_t) node->info_ent->data;
 534         struct drm_i915_private *dev_priv = dev->dev_private;
 535         struct drm_i915_gem_object *obj;
 536         u64 total_obj_size, total_gtt_size;
 537         int count, ret;
 538
 539         ret = mutex_lock_interruptible(&dev->struct_mutex);
 540         if (ret)
 541                 return ret;
 542
 543         total_obj_size = total_gtt_size = count = 0;
 544         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 545                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 546                         continue;
 547
 548                 seq_puts(m, "   ");
 549                 describe_obj(m, obj);
 550                 seq_putc(m, '\n');
 551                 total_obj_size += obj->base.size;
 552                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 553                 count++;
 554         }
 555
 556         mutex_unlock(&dev->struct_mutex);
 557
 558         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 559                    count, total_obj_size, total_gtt_size);
 560
 561         return 0;
 562 }
 563
 564 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 565 {
 566         struct drm_info_node *node = m->private;
 567         struct drm_device *dev = node->minor->dev;
 568         struct drm_i915_private *dev_priv = dev->dev_private;
 569         struct intel_crtc *crtc;
 570         int ret;
 571
 572         ret = mutex_lock_interruptible(&dev->struct_mutex);
 573         if (ret)
 574                 return ret;
 575
 576         for_each_intel_crtc(dev, crtc) {
 577                 const char pipe = pipe_name(crtc->pipe);
 578                 const char plane = plane_name(crtc->plane);
 579                 struct intel_unpin_work *work;
 580
 581                 spin_lock_irq(&dev->event_lock);
 582                 work = crtc->unpin_work;
 583                 if (work == NULL) {
 584                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 585                                    pipe, plane);
 586                 } else {
 587                         u32 addr;
 588
 589                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 590                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 591                                            pipe, plane);
 592                         } else {
 593                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 594                                            pipe, plane);
 595                         }
 596                         if (work->flip_queued_req) {
 597                                 struct intel_engine_cs *ring =
 598                                         i915_gem_request_get_ring(work->flip_queued_req);
 599
 600                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 601                                            ring->name,
 602                                            i915_gem_request_get_seqno(work->flip_queued_req),
 603                                            dev_priv->next_seqno,
 604                                            ring->get_seqno(ring, true),
 605                                            i915_gem_request_completed(work->flip_queued_req, true));
 606                         } else
 607                                 seq_printf(m, "Flip not associated with any ring\n");
 608                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 609                                    work->flip_queued_vblank,
 610                                    work->flip_ready_vblank,
 611                                    drm_crtc_vblank_count(&crtc->base));
 612                         if (work->enable_stall_check)
 613                                 seq_puts(m, "Stall check enabled, ");
 614                         else
 615                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 616                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 617
 618                         if (INTEL_INFO(dev)->gen >= 4)
 619                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 620                         else
 621                                 addr = I915_READ(DSPADDR(crtc->plane));
 622                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 623
 624                         if (work->pending_flip_obj) {
 625                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 626                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 627                         }
 628                 }
 629                 spin_unlock_irq(&dev->event_lock);
 630         }
 631
 632         mutex_unlock(&dev->struct_mutex);
 633
 634         return 0;
 635 }
 636
 637 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 638 {
 639         struct drm_info_node *node = m->private;
 640         struct drm_device *dev = node->minor->dev;
 641         struct drm_i915_private *dev_priv = dev->dev_private;
 642         struct drm_i915_gem_object *obj;
 643         struct intel_engine_cs *ring;
 644         int total = 0;
 645         int ret, i, j;
 646
 647         ret = mutex_lock_interruptible(&dev->struct_mutex);
 648         if (ret)
 649                 return ret;
 650
 651         for_each_ring(ring, dev_priv, i) {
 652                 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
 653                         int count;
 654
 655                         count = 0;
 656                         list_for_each_entry(obj,
 657                                             &ring->batch_pool.cache_list[j],
 658                                             batch_pool_link)
 659                                 count++;
 660                         seq_printf(m, "%s cache[%d]: %d objects\n",
 661                                    ring->name, j, count);
 662
 663                         list_for_each_entry(obj,
 664                                             &ring->batch_pool.cache_list[j],
 665                                             batch_pool_link) {
 666                                 seq_puts(m, "   ");
 667                                 describe_obj(m, obj);
 668                                 seq_putc(m, '\n');
 669                         }
 670
 671                         total += count;
 672                 }
 673         }
 674
 675         seq_printf(m, "total: %d\n", total);
 676
 677         mutex_unlock(&dev->struct_mutex);
 678
 679         return 0;
 680 }
 681
 682 static int i915_gem_request_info(struct seq_file *m, void *data)
 683 {
 684         struct drm_info_node *node = m->private;
 685         struct drm_device *dev = node->minor->dev;
 686         struct drm_i915_private *dev_priv = dev->dev_private;
 687         struct intel_engine_cs *ring;
 688         struct drm_i915_gem_request *req;
 689         int ret, any, i;
 690
 691         ret = mutex_lock_interruptible(&dev->struct_mutex);
 692         if (ret)
 693                 return ret;
 694
 695         any = 0;
 696         for_each_ring(ring, dev_priv, i) {
 697                 int count;
 698
 699                 count = 0;
 700                 list_for_each_entry(req, &ring->request_list, list)
 701                         count++;
 702                 if (count == 0)
 703                         continue;
 704
 705                 seq_printf(m, "%s requests: %d\n", ring->name, count);
 706                 list_for_each_entry(req, &ring->request_list, list) {
 707                         struct task_struct *task;
 708
 709                         rcu_read_lock();
 710                         task = NULL;
 711                         if (req->pid)
 712                                 task = pid_task(req->pid, PIDTYPE_PID);
 713                         seq_printf(m, "    %x @ %d: %s [%d]\n",
 714                                    req->seqno,
 715                                    (int) (jiffies - req->emitted_jiffies),
 716                                    task ? task->comm : "<unknown>",
 717                                    task ? task->pid : -1);
 718                         rcu_read_unlock();
 719                 }
 720
 721                 any++;
 722         }
 723         mutex_unlock(&dev->struct_mutex);
 724
 725         if (any == 0)
 726                 seq_puts(m, "No requests\n");
 727
 728         return 0;
 729 }
 730
 731 static void i915_ring_seqno_info(struct seq_file *m,
 732                                  struct intel_engine_cs *ring)
 733 {
 734         if (ring->get_seqno) {
 735                 seq_printf(m, "Current sequence (%s): %x\n",
 736                            ring->name, ring->get_seqno(ring, false));
 737         }
 738 }
 739
 740 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 741 {
 742         struct drm_info_node *node = m->private;
 743         struct drm_device *dev = node->minor->dev;
 744         struct drm_i915_private *dev_priv = dev->dev_private;
 745         struct intel_engine_cs *ring;
 746         int ret, i;
 747
 748         ret = mutex_lock_interruptible(&dev->struct_mutex);
 749         if (ret)
 750                 return ret;
 751         intel_runtime_pm_get(dev_priv);
 752
 753         for_each_ring(ring, dev_priv, i)
 754                 i915_ring_seqno_info(m, ring);
 755
 756         intel_runtime_pm_put(dev_priv);
 757         mutex_unlock(&dev->struct_mutex);
 758
 759         return 0;
 760 }
 761
 762
 763 static int i915_interrupt_info(struct seq_file *m, void *data)
 764 {
 765         struct drm_info_node *node = m->private;
 766         struct drm_device *dev = node->minor->dev;
 767         struct drm_i915_private *dev_priv = dev->dev_private;
 768         struct intel_engine_cs *ring;
 769         int ret, i, pipe;
 770
 771         ret = mutex_lock_interruptible(&dev->struct_mutex);
 772         if (ret)
 773                 return ret;
 774         intel_runtime_pm_get(dev_priv);
 775
 776         if (IS_CHERRYVIEW(dev)) {
 777                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 778                            I915_READ(GEN8_MASTER_IRQ));
 779
 780                 seq_printf(m, "Display IER:\t%08x\n",
 781                            I915_READ(VLV_IER));
 782                 seq_printf(m, "Display IIR:\t%08x\n",
 783                            I915_READ(VLV_IIR));
 784                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 785                            I915_READ(VLV_IIR_RW));
 786                 seq_printf(m, "Display IMR:\t%08x\n",
 787                            I915_READ(VLV_IMR));
 788                 for_each_pipe(dev_priv, pipe)
 789                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 790                                    pipe_name(pipe),
 791                                    I915_READ(PIPESTAT(pipe)));
 792
 793                 seq_printf(m, "Port hotplug:\t%08x\n",
 794                            I915_READ(PORT_HOTPLUG_EN));
 795                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 796                            I915_READ(VLV_DPFLIPSTAT));
 797                 seq_printf(m, "DPINVGTT:\t%08x\n",
 798                            I915_READ(DPINVGTT));
 799
 800                 for (i = 0; i < 4; i++) {
 801                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 802                                    i, I915_READ(GEN8_GT_IMR(i)));
 803                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 804                                    i, I915_READ(GEN8_GT_IIR(i)));
 805                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 806                                    i, I915_READ(GEN8_GT_IER(i)));
 807                 }
 808
 809                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 810                            I915_READ(GEN8_PCU_IMR));
 811                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 812                            I915_READ(GEN8_PCU_IIR));
 813                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 814                            I915_READ(GEN8_PCU_IER));
 815         } else if (INTEL_INFO(dev)->gen >= 8) {
 816                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 817                            I915_READ(GEN8_MASTER_IRQ));
 818
 819                 for (i = 0; i < 4; i++) {
 820                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 821                                    i, I915_READ(GEN8_GT_IMR(i)));
 822                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 823                                    i, I915_READ(GEN8_GT_IIR(i)));
 824                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 825                                    i, I915_READ(GEN8_GT_IER(i)));
 826                 }
 827
 828                 for_each_pipe(dev_priv, pipe) {
 829                         if (!intel_display_power_is_enabled(dev_priv,
 830                                                 POWER_DOMAIN_PIPE(pipe))) {
 831                                 seq_printf(m, "Pipe %c power disabled\n",
 832                                            pipe_name(pipe));
 833                                 continue;
 834                         }
 835                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 836                                    pipe_name(pipe),
 837                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 838                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 839                                    pipe_name(pipe),
 840                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 841                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 842                                    pipe_name(pipe),
 843                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 844                 }
 845
 846                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 847                            I915_READ(GEN8_DE_PORT_IMR));
 848                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 849                            I915_READ(GEN8_DE_PORT_IIR));
 850                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 851                            I915_READ(GEN8_DE_PORT_IER));
 852
 853                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 854                            I915_READ(GEN8_DE_MISC_IMR));
 855                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 856                            I915_READ(GEN8_DE_MISC_IIR));
 857                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 858                            I915_READ(GEN8_DE_MISC_IER));
 859
 860                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 861                            I915_READ(GEN8_PCU_IMR));
 862                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 863                            I915_READ(GEN8_PCU_IIR));
 864                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 865                            I915_READ(GEN8_PCU_IER));
 866         } else if (IS_VALLEYVIEW(dev)) {
 867                 seq_printf(m, "Display IER:\t%08x\n",
 868                            I915_READ(VLV_IER));
 869                 seq_printf(m, "Display IIR:\t%08x\n",
 870                            I915_READ(VLV_IIR));
 871                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 872                            I915_READ(VLV_IIR_RW));
 873                 seq_printf(m, "Display IMR:\t%08x\n",
 874                            I915_READ(VLV_IMR));
 875                 for_each_pipe(dev_priv, pipe)
 876                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 877                                    pipe_name(pipe),
 878                                    I915_READ(PIPESTAT(pipe)));
 879
 880                 seq_printf(m, "Master IER:\t%08x\n",
 881                            I915_READ(VLV_MASTER_IER));
 882
 883                 seq_printf(m, "Render IER:\t%08x\n",
 884                            I915_READ(GTIER));
 885                 seq_printf(m, "Render IIR:\t%08x\n",
 886                            I915_READ(GTIIR));
 887                 seq_printf(m, "Render IMR:\t%08x\n",
 888                            I915_READ(GTIMR));
 889
 890                 seq_printf(m, "PM IER:\t\t%08x\n",
 891                            I915_READ(GEN6_PMIER));
 892                 seq_printf(m, "PM IIR:\t\t%08x\n",
 893                            I915_READ(GEN6_PMIIR));
 894                 seq_printf(m, "PM IMR:\t\t%08x\n",
 895                            I915_READ(GEN6_PMIMR));
 896
 897                 seq_printf(m, "Port hotplug:\t%08x\n",
 898                            I915_READ(PORT_HOTPLUG_EN));
 899                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 900                            I915_READ(VLV_DPFLIPSTAT));
 901                 seq_printf(m, "DPINVGTT:\t%08x\n",
 902                            I915_READ(DPINVGTT));
 903
 904         } else if (!HAS_PCH_SPLIT(dev)) {
 905                 seq_printf(m, "Interrupt enable:    %08x\n",
 906                            I915_READ(IER));
 907                 seq_printf(m, "Interrupt identity:  %08x\n",
 908                            I915_READ(IIR));
 909                 seq_printf(m, "Interrupt mask:      %08x\n",
 910                            I915_READ(IMR));
 911                 for_each_pipe(dev_priv, pipe)
 912                         seq_printf(m, "Pipe %c stat:         %08x\n",
 913                                    pipe_name(pipe),
 914                                    I915_READ(PIPESTAT(pipe)));
 915         } else {
 916                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 917                            I915_READ(DEIER));
 918                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 919                            I915_READ(DEIIR));
 920                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 921                            I915_READ(DEIMR));
 922                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 923                            I915_READ(SDEIER));
 924                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 925                            I915_READ(SDEIIR));
 926                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 927                            I915_READ(SDEIMR));
 928                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 929                            I915_READ(GTIER));
 930                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 931                            I915_READ(GTIIR));
 932                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 933                            I915_READ(GTIMR));
 934         }
 935         for_each_ring(ring, dev_priv, i) {
 936                 if (INTEL_INFO(dev)->gen >= 6) {
 937                         seq_printf(m,
 938                                    "Graphics Interrupt mask (%s):       %08x\n",
 939                                    ring->name, I915_READ_IMR(ring));
 940                 }
 941                 i915_ring_seqno_info(m, ring);
 942         }
 943         intel_runtime_pm_put(dev_priv);
 944         mutex_unlock(&dev->struct_mutex);
 945
 946         return 0;
 947 }
 948
 949 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 950 {
 951         struct drm_info_node *node = m->private;
 952         struct drm_device *dev = node->minor->dev;
 953         struct drm_i915_private *dev_priv = dev->dev_private;
 954         int i, ret;
 955
 956         ret = mutex_lock_interruptible(&dev->struct_mutex);
 957         if (ret)
 958                 return ret;
 959
 960         seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 961         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 962         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 963                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 964
 965                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 966                            i, dev_priv->fence_regs[i].pin_count);
 967                 if (obj == NULL)
 968                         seq_puts(m, "unused");
 969                 else
 970                         describe_obj(m, obj);
 971                 seq_putc(m, '\n');
 972         }
 973
 974         mutex_unlock(&dev->struct_mutex);
 975         return 0;
 976 }
 977
 978 static int i915_hws_info(struct seq_file *m, void *data)
 979 {
 980         struct drm_info_node *node = m->private;
 981         struct drm_device *dev = node->minor->dev;
 982         struct drm_i915_private *dev_priv = dev->dev_private;
 983         struct intel_engine_cs *ring;
 984         const u32 *hws;
 985         int i;
 986
 987         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 988         hws = ring->status_page.page_addr;
 989         if (hws == NULL)
 990                 return 0;
 991
 992         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 993                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 994                            i * 4,
 995                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 996         }
 997         return 0;
 998 }
 999
1000 static ssize_t
1001 i915_error_state_write(struct file *filp,
1002                        const char __user *ubuf,
1003                        size_t cnt,
1004                        loff_t *ppos)
1005 {
1006         struct i915_error_state_file_priv *error_priv = filp->private_data;
1007         struct drm_device *dev = error_priv->dev;
1008         int ret;
1009
1010         DRM_DEBUG_DRIVER("Resetting error state\n");
1011
1012         ret = mutex_lock_interruptible(&dev->struct_mutex);
1013         if (ret)
1014                 return ret;
1015
1016         i915_destroy_error_state(dev);
1017         mutex_unlock(&dev->struct_mutex);
1018
1019         return cnt;
1020 }
1021
1022 static int i915_error_state_open(struct inode *inode, struct file *file)
1023 {
1024         struct drm_device *dev = inode->i_private;
1025         struct i915_error_state_file_priv *error_priv;
1026
1027         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1028         if (!error_priv)
1029                 return -ENOMEM;
1030
1031         error_priv->dev = dev;
1032
1033         i915_error_state_get(dev, error_priv);
1034
1035         file->private_data = error_priv;
1036
1037         return 0;
1038 }
1039
1040 static int i915_error_state_release(struct inode *inode, struct file *file)
1041 {
1042         struct i915_error_state_file_priv *error_priv = file->private_data;
1043
1044         i915_error_state_put(error_priv);
1045         kfree(error_priv);
1046
1047         return 0;
1048 }
1049
1050 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1051                                      size_t count, loff_t *pos)
1052 {
1053         struct i915_error_state_file_priv *error_priv = file->private_data;
1054         struct drm_i915_error_state_buf error_str;
1055         loff_t tmp_pos = 0;
1056         ssize_t ret_count = 0;
1057         int ret;
1058
1059         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1060         if (ret)
1061                 return ret;
1062
1063         ret = i915_error_state_to_str(&error_str, error_priv);
1064         if (ret)
1065                 goto out;
1066
1067         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1068                                             error_str.buf,
1069                                             error_str.bytes);
1070
1071         if (ret_count < 0)
1072                 ret = ret_count;
1073         else
1074                 *pos = error_str.start + ret_count;
1075 out:
1076         i915_error_state_buf_release(&error_str);
1077         return ret ?: ret_count;
1078 }
1079
1080 static const struct file_operations i915_error_state_fops = {
1081         .owner = THIS_MODULE,
1082         .open = i915_error_state_open,
1083         .read = i915_error_state_read,
1084         .write = i915_error_state_write,
1085         .llseek = default_llseek,
1086         .release = i915_error_state_release,
1087 };
1088
1089 static int
1090 i915_next_seqno_get(void *data, u64 *val)
1091 {
1092         struct drm_device *dev = data;
1093         struct drm_i915_private *dev_priv = dev->dev_private;
1094         int ret;
1095
1096         ret = mutex_lock_interruptible(&dev->struct_mutex);
1097         if (ret)
1098                 return ret;
1099
1100         *val = dev_priv->next_seqno;
1101         mutex_unlock(&dev->struct_mutex);
1102
1103         return 0;
1104 }
1105
1106 static int
1107 i915_next_seqno_set(void *data, u64 val)
1108 {
1109         struct drm_device *dev = data;
1110         int ret;
1111
1112         ret = mutex_lock_interruptible(&dev->struct_mutex);
1113         if (ret)
1114                 return ret;
1115
1116         ret = i915_gem_set_seqno(dev, val);
1117         mutex_unlock(&dev->struct_mutex);
1118
1119         return ret;
1120 }
1121
1122 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1123                         i915_next_seqno_get, i915_next_seqno_set,
1124                         "0x%llx\n");
1125
1126 static int i915_frequency_info(struct seq_file *m, void *unused)
1127 {
1128         struct drm_info_node *node = m->private;
1129         struct drm_device *dev = node->minor->dev;
1130         struct drm_i915_private *dev_priv = dev->dev_private;
1131         int ret = 0;
1132
1133         intel_runtime_pm_get(dev_priv);
1134
1135         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1136
1137         if (IS_GEN5(dev)) {
1138                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1139                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1140
1141                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1142                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1143                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1144                            MEMSTAT_VID_SHIFT);
1145                 seq_printf(m, "Current P-state: %d\n",
1146                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1147         } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1148                    IS_BROADWELL(dev) || IS_GEN9(dev)) {
1149                 u32 rp_state_limits;
1150                 u32 gt_perf_status;
1151                 u32 rp_state_cap;
1152                 u32 rpmodectl, rpinclimit, rpdeclimit;
1153                 u32 rpstat, cagf, reqf;
1154                 u32 rpupei, rpcurup, rpprevup;
1155                 u32 rpdownei, rpcurdown, rpprevdown;
1156                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1157                 int max_freq;
1158
1159                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1160                 if (IS_BROXTON(dev)) {
1161                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1162                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1163                 } else {
1164                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1165                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1166                 }
1167
1168                 /* RPSTAT1 is in the GT power well */
1169                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1170                 if (ret)
1171                         goto out;
1172
1173                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1174
1175                 reqf = I915_READ(GEN6_RPNSWREQ);
1176                 if (IS_GEN9(dev))
1177                         reqf >>= 23;
1178                 else {
1179                         reqf &= ~GEN6_TURBO_DISABLE;
1180                         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1181                                 reqf >>= 24;
1182                         else
1183                                 reqf >>= 25;
1184                 }
1185                 reqf = intel_gpu_freq(dev_priv, reqf);
1186
1187                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1188                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1189                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1190
1191                 rpstat = I915_READ(GEN6_RPSTAT1);
1192                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1193                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1194                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1195                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1196                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1197                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1198                 if (IS_GEN9(dev))
1199                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1200                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1201                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1202                 else
1203                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1204                 cagf = intel_gpu_freq(dev_priv, cagf);
1205
1206                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1207                 mutex_unlock(&dev->struct_mutex);
1208
1209                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1210                         pm_ier = I915_READ(GEN6_PMIER);
1211                         pm_imr = I915_READ(GEN6_PMIMR);
1212                         pm_isr = I915_READ(GEN6_PMISR);
1213                         pm_iir = I915_READ(GEN6_PMIIR);
1214                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1215                 } else {
1216                         pm_ier = I915_READ(GEN8_GT_IER(2));
1217                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1218                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1219                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1220                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1221                 }
1222                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1223                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1224                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1225                 seq_printf(m, "Render p-state ratio: %d\n",
1226                            (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1227                 seq_printf(m, "Render p-state VID: %d\n",
1228                            gt_perf_status & 0xff);
1229                 seq_printf(m, "Render p-state limit: %d\n",
1230                            rp_state_limits & 0xff);
1231                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1232                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1233                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1234                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1235                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1236                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1237                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1238                            GEN6_CURICONT_MASK);
1239                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1240                            GEN6_CURBSYTAVG_MASK);
1241                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1242                            GEN6_CURBSYTAVG_MASK);
1243                 seq_printf(m, "Up threshold: %d%%\n",
1244                            dev_priv->rps.up_threshold);
1245
1246                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1247                            GEN6_CURIAVG_MASK);
1248                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1249                            GEN6_CURBSYTAVG_MASK);
1250                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1251                            GEN6_CURBSYTAVG_MASK);
1252                 seq_printf(m, "Down threshold: %d%%\n",
1253                            dev_priv->rps.down_threshold);
1254
1255                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1256                             rp_state_cap >> 16) & 0xff;
1257                 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1258                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1259                            intel_gpu_freq(dev_priv, max_freq));
1260
1261                 max_freq = (rp_state_cap & 0xff00) >> 8;
1262                 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1263                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1264                            intel_gpu_freq(dev_priv, max_freq));
1265
1266                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1267                             rp_state_cap >> 0) & 0xff;
1268                 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1269                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1270                            intel_gpu_freq(dev_priv, max_freq));
1271                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1272                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1273
1274                 seq_printf(m, "Current freq: %d MHz\n",
1275                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1276                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1277                 seq_printf(m, "Idle freq: %d MHz\n",
1278                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1279                 seq_printf(m, "Min freq: %d MHz\n",
1280                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1281                 seq_printf(m, "Max freq: %d MHz\n",
1282                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1283                 seq_printf(m,
1284                            "efficient (RPe) frequency: %d MHz\n",
1285                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1286         } else if (IS_VALLEYVIEW(dev)) {
1287                 u32 freq_sts;
1288
1289                 mutex_lock(&dev_priv->rps.hw_lock);
1290                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1291                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1292                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1293
1294                 seq_printf(m, "actual GPU freq: %d MHz\n",
1295                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1296
1297                 seq_printf(m, "current GPU freq: %d MHz\n",
1298                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1299
1300                 seq_printf(m, "max GPU freq: %d MHz\n",
1301                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1302
1303                 seq_printf(m, "min GPU freq: %d MHz\n",
1304                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1305
1306                 seq_printf(m, "idle GPU freq: %d MHz\n",
1307                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1308
1309                 seq_printf(m,
1310                            "efficient (RPe) frequency: %d MHz\n",
1311                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1312                 mutex_unlock(&dev_priv->rps.hw_lock);
1313         } else {
1314                 seq_puts(m, "no P-state info available\n");
1315         }
1316
1317 out:
1318         intel_runtime_pm_put(dev_priv);
1319         return ret;
1320 }
1321
1322 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1323 {
1324         struct drm_info_node *node = m->private;
1325         struct drm_device *dev = node->minor->dev;
1326         struct drm_i915_private *dev_priv = dev->dev_private;
1327         struct intel_engine_cs *ring;
1328         u64 acthd[I915_NUM_RINGS];
1329         u32 seqno[I915_NUM_RINGS];
1330         int i;
1331
1332         if (!i915.enable_hangcheck) {
1333                 seq_printf(m, "Hangcheck disabled\n");
1334                 return 0;
1335         }
1336
1337         intel_runtime_pm_get(dev_priv);
1338
1339         for_each_ring(ring, dev_priv, i) {
1340                 seqno[i] = ring->get_seqno(ring, false);
1341                 acthd[i] = intel_ring_get_active_head(ring);
1342         }
1343
1344         intel_runtime_pm_put(dev_priv);
1345
1346         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1347                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1348                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1349                                             jiffies));
1350         } else
1351                 seq_printf(m, "Hangcheck inactive\n");
1352
1353         for_each_ring(ring, dev_priv, i) {
1354                 seq_printf(m, "%s:\n", ring->name);
1355                 seq_printf(m, "\tseqno = %x [current %x]\n",
1356                            ring->hangcheck.seqno, seqno[i]);
1357                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1358                            (long long)ring->hangcheck.acthd,
1359                            (long long)acthd[i]);
1360                 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1361                            (long long)ring->hangcheck.max_acthd);
1362                 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1363                 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1364         }
1365
1366         return 0;
1367 }
1368
1369 static int ironlake_drpc_info(struct seq_file *m)
1370 {
1371         struct drm_info_node *node = m->private;
1372         struct drm_device *dev = node->minor->dev;
1373         struct drm_i915_private *dev_priv = dev->dev_private;
1374         u32 rgvmodectl, rstdbyctl;
1375         u16 crstandvid;
1376         int ret;
1377
1378         ret = mutex_lock_interruptible(&dev->struct_mutex);
1379         if (ret)
1380                 return ret;
1381         intel_runtime_pm_get(dev_priv);
1382
1383         rgvmodectl = I915_READ(MEMMODECTL);
1384         rstdbyctl = I915_READ(RSTDBYCTL);
1385         crstandvid = I915_READ16(CRSTANDVID);
1386
1387         intel_runtime_pm_put(dev_priv);
1388         mutex_unlock(&dev->struct_mutex);
1389
1390         seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1391                    "yes" : "no");
1392         seq_printf(m, "Boost freq: %d\n",
1393                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1394                    MEMMODE_BOOST_FREQ_SHIFT);
1395         seq_printf(m, "HW control enabled: %s\n",
1396                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1397         seq_printf(m, "SW control enabled: %s\n",
1398                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1399         seq_printf(m, "Gated voltage change: %s\n",
1400                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1401         seq_printf(m, "Starting frequency: P%d\n",
1402                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1403         seq_printf(m, "Max P-state: P%d\n",
1404                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1405         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1406         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1407         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1408         seq_printf(m, "Render standby enabled: %s\n",
1409                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1410         seq_puts(m, "Current RS state: ");
1411         switch (rstdbyctl & RSX_STATUS_MASK) {
1412         case RSX_STATUS_ON:
1413                 seq_puts(m, "on\n");
1414                 break;
1415         case RSX_STATUS_RC1:
1416                 seq_puts(m, "RC1\n");
1417                 break;
1418         case RSX_STATUS_RC1E:
1419                 seq_puts(m, "RC1E\n");
1420                 break;
1421         case RSX_STATUS_RS1:
1422                 seq_puts(m, "RS1\n");
1423                 break;
1424         case RSX_STATUS_RS2:
1425                 seq_puts(m, "RS2 (RC6)\n");
1426                 break;
1427         case RSX_STATUS_RS3:
1428                 seq_puts(m, "RC3 (RC6+)\n");
1429                 break;
1430         default:
1431                 seq_puts(m, "unknown\n");
1432                 break;
1433         }
1434
1435         return 0;
1436 }
1437
1438 static int i915_forcewake_domains(struct seq_file *m, void *data)
1439 {
1440         struct drm_info_node *node = m->private;
1441         struct drm_device *dev = node->minor->dev;
1442         struct drm_i915_private *dev_priv = dev->dev_private;
1443         struct intel_uncore_forcewake_domain *fw_domain;
1444         int i;
1445
1446         spin_lock_irq(&dev_priv->uncore.lock);
1447         for_each_fw_domain(fw_domain, dev_priv, i) {
1448                 seq_printf(m, "%s.wake_count = %u\n",
1449                            intel_uncore_forcewake_domain_to_str(i),
1450                            fw_domain->wake_count);
1451         }
1452         spin_unlock_irq(&dev_priv->uncore.lock);
1453
1454         return 0;
1455 }
1456
1457 static int vlv_drpc_info(struct seq_file *m)
1458 {
1459         struct drm_info_node *node = m->private;
1460         struct drm_device *dev = node->minor->dev;
1461         struct drm_i915_private *dev_priv = dev->dev_private;
1462         u32 rpmodectl1, rcctl1, pw_status;
1463
1464         intel_runtime_pm_get(dev_priv);
1465
1466         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1467         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1468         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1469
1470         intel_runtime_pm_put(dev_priv);
1471
1472         seq_printf(m, "Video Turbo Mode: %s\n",
1473                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1474         seq_printf(m, "Turbo enabled: %s\n",
1475                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1476         seq_printf(m, "HW control enabled: %s\n",
1477                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1478         seq_printf(m, "SW control enabled: %s\n",
1479                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1480                           GEN6_RP_MEDIA_SW_MODE));
1481         seq_printf(m, "RC6 Enabled: %s\n",
1482                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1483                                         GEN6_RC_CTL_EI_MODE(1))));
1484         seq_printf(m, "Render Power Well: %s\n",
1485                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1486         seq_printf(m, "Media Power Well: %s\n",
1487                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1488
1489         seq_printf(m, "Render RC6 residency since boot: %u\n",
1490                    I915_READ(VLV_GT_RENDER_RC6));
1491         seq_printf(m, "Media RC6 residency since boot: %u\n",
1492                    I915_READ(VLV_GT_MEDIA_RC6));
1493
1494         return i915_forcewake_domains(m, NULL);
1495 }
1496
1497 static int gen6_drpc_info(struct seq_file *m)
1498 {
1499         struct drm_info_node *node = m->private;
1500         struct drm_device *dev = node->minor->dev;
1501         struct drm_i915_private *dev_priv = dev->dev_private;
1502         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1503         unsigned forcewake_count;
1504         int count = 0, ret;
1505
1506         ret = mutex_lock_interruptible(&dev->struct_mutex);
1507         if (ret)
1508                 return ret;
1509         intel_runtime_pm_get(dev_priv);
1510
1511         spin_lock_irq(&dev_priv->uncore.lock);
1512         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1513         spin_unlock_irq(&dev_priv->uncore.lock);
1514
1515         if (forcewake_count) {
1516                 seq_puts(m, "RC information inaccurate because somebody "
1517                             "holds a forcewake reference \n");
1518         } else {
1519                 /* NB: we cannot use forcewake, else we read the wrong values */
1520                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1521                         udelay(10);
1522                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1523         }
1524
1525         gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1526         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1527
1528         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1529         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1530         mutex_unlock(&dev->struct_mutex);
1531         mutex_lock(&dev_priv->rps.hw_lock);
1532         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1533         mutex_unlock(&dev_priv->rps.hw_lock);
1534
1535         intel_runtime_pm_put(dev_priv);
1536
1537         seq_printf(m, "Video Turbo Mode: %s\n",
1538                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1539         seq_printf(m, "HW control enabled: %s\n",
1540                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1541         seq_printf(m, "SW control enabled: %s\n",
1542                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1543                           GEN6_RP_MEDIA_SW_MODE));
1544         seq_printf(m, "RC1e Enabled: %s\n",
1545                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1546         seq_printf(m, "RC6 Enabled: %s\n",
1547                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1548         seq_printf(m, "Deep RC6 Enabled: %s\n",
1549                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1550         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1551                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1552         seq_puts(m, "Current RC state: ");
1553         switch (gt_core_status & GEN6_RCn_MASK) {
1554         case GEN6_RC0:
1555                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1556                         seq_puts(m, "Core Power Down\n");
1557                 else
1558                         seq_puts(m, "on\n");
1559                 break;
1560         case GEN6_RC3:
1561                 seq_puts(m, "RC3\n");
1562                 break;
1563         case GEN6_RC6:
1564                 seq_puts(m, "RC6\n");
1565                 break;
1566         case GEN6_RC7:
1567                 seq_puts(m, "RC7\n");
1568                 break;
1569         default:
1570                 seq_puts(m, "Unknown\n");
1571                 break;
1572         }
1573
1574         seq_printf(m, "Core Power Down: %s\n",
1575                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1576
1577         /* Not exactly sure what this is */
1578         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1579                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1580         seq_printf(m, "RC6 residency since boot: %u\n",
1581                    I915_READ(GEN6_GT_GFX_RC6));
1582         seq_printf(m, "RC6+ residency since boot: %u\n",
1583                    I915_READ(GEN6_GT_GFX_RC6p));
1584         seq_printf(m, "RC6++ residency since boot: %u\n",
1585                    I915_READ(GEN6_GT_GFX_RC6pp));
1586
1587         seq_printf(m, "RC6   voltage: %dmV\n",
1588                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1589         seq_printf(m, "RC6+  voltage: %dmV\n",
1590                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1591         seq_printf(m, "RC6++ voltage: %dmV\n",
1592                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1593         return 0;
1594 }
1595
1596 static int i915_drpc_info(struct seq_file *m, void *unused)
1597 {
1598         struct drm_info_node *node = m->private;
1599         struct drm_device *dev = node->minor->dev;
1600
1601         if (IS_VALLEYVIEW(dev))
1602                 return vlv_drpc_info(m);
1603         else if (INTEL_INFO(dev)->gen >= 6)
1604                 return gen6_drpc_info(m);
1605         else
1606                 return ironlake_drpc_info(m);
1607 }
1608
1609 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1610 {
1611         struct drm_info_node *node = m->private;
1612         struct drm_device *dev = node->minor->dev;
1613         struct drm_i915_private *dev_priv = dev->dev_private;
1614
1615         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1616                    dev_priv->fb_tracking.busy_bits);
1617
1618         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1619                    dev_priv->fb_tracking.flip_bits);
1620
1621         return 0;
1622 }
1623
1624 static int i915_fbc_status(struct seq_file *m, void *unused)
1625 {
1626         struct drm_info_node *node = m->private;
1627         struct drm_device *dev = node->minor->dev;
1628         struct drm_i915_private *dev_priv = dev->dev_private;
1629
1630         if (!HAS_FBC(dev)) {
1631                 seq_puts(m, "FBC unsupported on this chipset\n");
1632                 return 0;
1633         }
1634
1635         intel_runtime_pm_get(dev_priv);
1636         mutex_lock(&dev_priv->fbc.lock);
1637
1638         if (intel_fbc_enabled(dev))
1639                 seq_puts(m, "FBC enabled\n");
1640         else
1641                 seq_printf(m, "FBC disabled: %s\n",
1642                           intel_no_fbc_reason_str(dev_priv->fbc.no_fbc_reason));
1643
1644         if (INTEL_INFO(dev_priv)->gen >= 7)
1645                 seq_printf(m, "Compressing: %s\n",
1646                            yesno(I915_READ(FBC_STATUS2) &
1647                                  FBC_COMPRESSION_MASK));
1648
1649         mutex_unlock(&dev_priv->fbc.lock);
1650         intel_runtime_pm_put(dev_priv);
1651
1652         return 0;
1653 }
1654
1655 static int i915_fbc_fc_get(void *data, u64 *val)
1656 {
1657         struct drm_device *dev = data;
1658         struct drm_i915_private *dev_priv = dev->dev_private;
1659
1660         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1661                 return -ENODEV;
1662
1663         drm_modeset_lock_all(dev);
1664         *val = dev_priv->fbc.false_color;
1665         drm_modeset_unlock_all(dev);
1666
1667         return 0;
1668 }
1669
1670 static int i915_fbc_fc_set(void *data, u64 val)
1671 {
1672         struct drm_device *dev = data;
1673         struct drm_i915_private *dev_priv = dev->dev_private;
1674         u32 reg;
1675
1676         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1677                 return -ENODEV;
1678
1679         drm_modeset_lock_all(dev);
1680         mutex_lock(&dev_priv->fbc.lock);
1681
1682         reg = I915_READ(ILK_DPFC_CONTROL);
1683         dev_priv->fbc.false_color = val;
1684
1685         I915_WRITE(ILK_DPFC_CONTROL, val ?
1686                    (reg | FBC_CTL_FALSE_COLOR) :
1687                    (reg & ~FBC_CTL_FALSE_COLOR));
1688
1689         mutex_unlock(&dev_priv->fbc.lock);
1690         drm_modeset_unlock_all(dev);
1691         return 0;
1692 }
1693
1694 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1695                         i915_fbc_fc_get, i915_fbc_fc_set,
1696                         "%llu\n");
1697
1698 static int i915_ips_status(struct seq_file *m, void *unused)
1699 {
1700         struct drm_info_node *node = m->private;
1701         struct drm_device *dev = node->minor->dev;
1702         struct drm_i915_private *dev_priv = dev->dev_private;
1703
1704         if (!HAS_IPS(dev)) {
1705                 seq_puts(m, "not supported\n");
1706                 return 0;
1707         }
1708
1709         intel_runtime_pm_get(dev_priv);
1710
1711         seq_printf(m, "Enabled by kernel parameter: %s\n",
1712                    yesno(i915.enable_ips));
1713
1714         if (INTEL_INFO(dev)->gen >= 8) {
1715                 seq_puts(m, "Currently: unknown\n");
1716         } else {
1717                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1718                         seq_puts(m, "Currently: enabled\n");
1719                 else
1720                         seq_puts(m, "Currently: disabled\n");
1721         }
1722
1723         intel_runtime_pm_put(dev_priv);
1724
1725         return 0;
1726 }
1727
1728 static int i915_sr_status(struct seq_file *m, void *unused)
1729 {
1730         struct drm_info_node *node = m->private;
1731         struct drm_device *dev = node->minor->dev;
1732         struct drm_i915_private *dev_priv = dev->dev_private;
1733         bool sr_enabled = false;
1734
1735         intel_runtime_pm_get(dev_priv);
1736
1737         if (HAS_PCH_SPLIT(dev))
1738                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1739         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1740                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1741         else if (IS_I915GM(dev))
1742                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1743         else if (IS_PINEVIEW(dev))
1744                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1745
1746         intel_runtime_pm_put(dev_priv);
1747
1748         seq_printf(m, "self-refresh: %s\n",
1749                    sr_enabled ? "enabled" : "disabled");
1750
1751         return 0;
1752 }
1753
1754 static int i915_emon_status(struct seq_file *m, void *unused)
1755 {
1756         struct drm_info_node *node = m->private;
1757         struct drm_device *dev = node->minor->dev;
1758         struct drm_i915_private *dev_priv = dev->dev_private;
1759         unsigned long temp, chipset, gfx;
1760         int ret;
1761
1762         if (!IS_GEN5(dev))
1763                 return -ENODEV;
1764
1765         ret = mutex_lock_interruptible(&dev->struct_mutex);
1766         if (ret)
1767                 return ret;
1768
1769         temp = i915_mch_val(dev_priv);
1770         chipset = i915_chipset_val(dev_priv);
1771         gfx = i915_gfx_val(dev_priv);
1772         mutex_unlock(&dev->struct_mutex);
1773
1774         seq_printf(m, "GMCH temp: %ld\n", temp);
1775         seq_printf(m, "Chipset power: %ld\n", chipset);
1776         seq_printf(m, "GFX power: %ld\n", gfx);
1777         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1778
1779         return 0;
1780 }
1781
1782 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1783 {
1784         struct drm_info_node *node = m->private;
1785         struct drm_device *dev = node->minor->dev;
1786         struct drm_i915_private *dev_priv = dev->dev_private;
1787         int ret = 0;
1788         int gpu_freq, ia_freq;
1789
1790         if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1791                 seq_puts(m, "unsupported on this chipset\n");
1792                 return 0;
1793         }
1794
1795         intel_runtime_pm_get(dev_priv);
1796
1797         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1798
1799         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1800         if (ret)
1801                 goto out;
1802
1803         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1804
1805         for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1806              gpu_freq <= dev_priv->rps.max_freq_softlimit;
1807              gpu_freq++) {
1808                 ia_freq = gpu_freq;
1809                 sandybridge_pcode_read(dev_priv,
1810                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1811                                        &ia_freq);
1812                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1813                            intel_gpu_freq(dev_priv, gpu_freq),
1814                            ((ia_freq >> 0) & 0xff) * 100,
1815                            ((ia_freq >> 8) & 0xff) * 100);
1816         }
1817
1818         mutex_unlock(&dev_priv->rps.hw_lock);
1819
1820 out:
1821         intel_runtime_pm_put(dev_priv);
1822         return ret;
1823 }
1824
1825 static int i915_opregion(struct seq_file *m, void *unused)
1826 {
1827         struct drm_info_node *node = m->private;
1828         struct drm_device *dev = node->minor->dev;
1829         struct drm_i915_private *dev_priv = dev->dev_private;
1830         struct intel_opregion *opregion = &dev_priv->opregion;
1831         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1832         int ret;
1833
1834         if (data == NULL)
1835                 return -ENOMEM;
1836
1837         ret = mutex_lock_interruptible(&dev->struct_mutex);
1838         if (ret)
1839                 goto out;
1840
1841         if (opregion->header) {
1842                 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1843                 seq_write(m, data, OPREGION_SIZE);
1844         }
1845
1846         mutex_unlock(&dev->struct_mutex);
1847
1848 out:
1849         kfree(data);
1850         return 0;
1851 }
1852
1853 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1854 {
1855         struct drm_info_node *node = m->private;
1856         struct drm_device *dev = node->minor->dev;
1857         struct intel_fbdev *ifbdev = NULL;
1858         struct intel_framebuffer *fb;
1859
1860 #ifdef CONFIG_DRM_I915_FBDEV
1861         struct drm_i915_private *dev_priv = dev->dev_private;
1862
1863         ifbdev = dev_priv->fbdev;
1864         fb = to_intel_framebuffer(ifbdev->helper.fb);
1865
1866         seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1867                    fb->base.width,
1868                    fb->base.height,
1869                    fb->base.depth,
1870                    fb->base.bits_per_pixel,
1871                    fb->base.modifier[0],
1872                    atomic_read(&fb->base.refcount.refcount));
1873         describe_obj(m, fb->obj);
1874         seq_putc(m, '\n');
1875 #endif
1876
1877         mutex_lock(&dev->mode_config.fb_lock);
1878         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1879                 if (ifbdev && &fb->base == ifbdev->helper.fb)
1880                         continue;
1881
1882                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1883                            fb->base.width,
1884                            fb->base.height,
1885                            fb->base.depth,
1886                            fb->base.bits_per_pixel,
1887                            fb->base.modifier[0],
1888                            atomic_read(&fb->base.refcount.refcount));
1889                 describe_obj(m, fb->obj);
1890                 seq_putc(m, '\n');
1891         }
1892         mutex_unlock(&dev->mode_config.fb_lock);
1893
1894         return 0;
1895 }
1896
1897 static void describe_ctx_ringbuf(struct seq_file *m,
1898                                  struct intel_ringbuffer *ringbuf)
1899 {
1900         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1901                    ringbuf->space, ringbuf->head, ringbuf->tail,
1902                    ringbuf->last_retired_head);
1903 }
1904
1905 static int i915_context_status(struct seq_file *m, void *unused)
1906 {
1907         struct drm_info_node *node = m->private;
1908         struct drm_device *dev = node->minor->dev;
1909         struct drm_i915_private *dev_priv = dev->dev_private;
1910         struct intel_engine_cs *ring;
1911         struct intel_context *ctx;
1912         int ret, i;
1913
1914         ret = mutex_lock_interruptible(&dev->struct_mutex);
1915         if (ret)
1916                 return ret;
1917
1918         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1919                 if (!i915.enable_execlists &&
1920                     ctx->legacy_hw_ctx.rcs_state == NULL)
1921                         continue;
1922
1923                 seq_puts(m, "HW context ");
1924                 describe_ctx(m, ctx);
1925                 for_each_ring(ring, dev_priv, i) {
1926                         if (ring->default_context == ctx)
1927                                 seq_printf(m, "(default context %s) ",
1928                                            ring->name);
1929                 }
1930
1931                 if (i915.enable_execlists) {
1932                         seq_putc(m, '\n');
1933                         for_each_ring(ring, dev_priv, i) {
1934                                 struct drm_i915_gem_object *ctx_obj =
1935                                         ctx->engine[i].state;
1936                                 struct intel_ringbuffer *ringbuf =
1937                                         ctx->engine[i].ringbuf;
1938
1939                                 seq_printf(m, "%s: ", ring->name);
1940                                 if (ctx_obj)
1941                                         describe_obj(m, ctx_obj);
1942                                 if (ringbuf)
1943                                         describe_ctx_ringbuf(m, ringbuf);
1944                                 seq_putc(m, '\n');
1945                         }
1946                 } else {
1947                         describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1948                 }
1949
1950                 seq_putc(m, '\n');
1951         }
1952
1953         mutex_unlock(&dev->struct_mutex);
1954
1955         return 0;
1956 }
1957
1958 static void i915_dump_lrc_obj(struct seq_file *m,
1959                               struct intel_engine_cs *ring,
1960                               struct drm_i915_gem_object *ctx_obj)
1961 {
1962         struct page *page;
1963         uint32_t *reg_state;
1964         int j;
1965         unsigned long ggtt_offset = 0;
1966
1967         if (ctx_obj == NULL) {
1968                 seq_printf(m, "Context on %s with no gem object\n",
1969                            ring->name);
1970                 return;
1971         }
1972
1973         seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1974                    intel_execlists_ctx_id(ctx_obj));
1975
1976         if (!i915_gem_obj_ggtt_bound(ctx_obj))
1977                 seq_puts(m, "\tNot bound in GGTT\n");
1978         else
1979                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1980
1981         if (i915_gem_object_get_pages(ctx_obj)) {
1982                 seq_puts(m, "\tFailed to get pages for context object\n");
1983                 return;
1984         }
1985
1986         page = i915_gem_object_get_page(ctx_obj, 1);
1987         if (!WARN_ON(page == NULL)) {
1988                 reg_state = kmap_atomic(page);
1989
1990                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1991                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1992                                    ggtt_offset + 4096 + (j * 4),
1993                                    reg_state[j], reg_state[j + 1],
1994                                    reg_state[j + 2], reg_state[j + 3]);
1995                 }
1996                 kunmap_atomic(reg_state);
1997         }
1998
1999         seq_putc(m, '\n');
2000 }
2001
2002 static int i915_dump_lrc(struct seq_file *m, void *unused)
2003 {
2004         struct drm_info_node *node = (struct drm_info_node *) m->private;
2005         struct drm_device *dev = node->minor->dev;
2006         struct drm_i915_private *dev_priv = dev->dev_private;
2007         struct intel_engine_cs *ring;
2008         struct intel_context *ctx;
2009         int ret, i;
2010
2011         if (!i915.enable_execlists) {
2012                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2013                 return 0;
2014         }
2015
2016         ret = mutex_lock_interruptible(&dev->struct_mutex);
2017         if (ret)
2018                 return ret;
2019
2020         list_for_each_entry(ctx, &dev_priv->context_list, link) {
2021                 for_each_ring(ring, dev_priv, i) {
2022                         if (ring->default_context != ctx)
2023                                 i915_dump_lrc_obj(m, ring,
2024                                                   ctx->engine[i].state);
2025                 }
2026         }
2027
2028         mutex_unlock(&dev->struct_mutex);
2029
2030         return 0;
2031 }
2032
2033 static int i915_execlists(struct seq_file *m, void *data)
2034 {
2035         struct drm_info_node *node = (struct drm_info_node *)m->private;
2036         struct drm_device *dev = node->minor->dev;
2037         struct drm_i915_private *dev_priv = dev->dev_private;
2038         struct intel_engine_cs *ring;
2039         u32 status_pointer;
2040         u8 read_pointer;
2041         u8 write_pointer;
2042         u32 status;
2043         u32 ctx_id;
2044         struct list_head *cursor;
2045         int ring_id, i;
2046         int ret;
2047
2048         if (!i915.enable_execlists) {
2049                 seq_puts(m, "Logical Ring Contexts are disabled\n");
2050                 return 0;
2051         }
2052
2053         ret = mutex_lock_interruptible(&dev->struct_mutex);
2054         if (ret)
2055                 return ret;
2056
2057         intel_runtime_pm_get(dev_priv);
2058
2059         for_each_ring(ring, dev_priv, ring_id) {
2060                 struct drm_i915_gem_request *head_req = NULL;
2061                 int count = 0;
2062                 unsigned long flags;
2063
2064                 seq_printf(m, "%s\n", ring->name);
2065
2066                 status = I915_READ(RING_EXECLIST_STATUS(ring));
2067                 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
2068                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2069                            status, ctx_id);
2070
2071                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2072                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2073
2074                 read_pointer = ring->next_context_status_buffer;
2075                 write_pointer = status_pointer & 0x07;
2076                 if (read_pointer > write_pointer)
2077                         write_pointer += 6;
2078                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2079                            read_pointer, write_pointer);
2080
2081                 for (i = 0; i < 6; i++) {
2082                         status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2083                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2084
2085                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2086                                    i, status, ctx_id);
2087                 }
2088
2089                 spin_lock_irqsave(&ring->execlist_lock, flags);
2090                 list_for_each(cursor, &ring->execlist_queue)
2091                         count++;
2092                 head_req = list_first_entry_or_null(&ring->execlist_queue,
2093                                 struct drm_i915_gem_request, execlist_link);
2094                 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2095
2096                 seq_printf(m, "\t%d requests in queue\n", count);
2097                 if (head_req) {
2098                         struct drm_i915_gem_object *ctx_obj;
2099
2100                         ctx_obj = head_req->ctx->engine[ring_id].state;
2101                         seq_printf(m, "\tHead request id: %u\n",
2102                                    intel_execlists_ctx_id(ctx_obj));
2103                         seq_printf(m, "\tHead request tail: %u\n",
2104                                    head_req->tail);
2105                 }
2106
2107                 seq_putc(m, '\n');
2108         }
2109
2110         intel_runtime_pm_put(dev_priv);
2111         mutex_unlock(&dev->struct_mutex);
2112
2113         return 0;
2114 }
2115
2116 static const char *swizzle_string(unsigned swizzle)
2117 {
2118         switch (swizzle) {
2119         case I915_BIT_6_SWIZZLE_NONE:
2120                 return "none";
2121         case I915_BIT_6_SWIZZLE_9:
2122                 return "bit9";
2123         case I915_BIT_6_SWIZZLE_9_10:
2124                 return "bit9/bit10";
2125         case I915_BIT_6_SWIZZLE_9_11:
2126                 return "bit9/bit11";
2127         case I915_BIT_6_SWIZZLE_9_10_11:
2128                 return "bit9/bit10/bit11";
2129         case I915_BIT_6_SWIZZLE_9_17:
2130                 return "bit9/bit17";
2131         case I915_BIT_6_SWIZZLE_9_10_17:
2132                 return "bit9/bit10/bit17";
2133         case I915_BIT_6_SWIZZLE_UNKNOWN:
2134                 return "unknown";
2135         }
2136
2137         return "bug";
2138 }
2139
2140 static int i915_swizzle_info(struct seq_file *m, void *data)
2141 {
2142         struct drm_info_node *node = m->private;
2143         struct drm_device *dev = node->minor->dev;
2144         struct drm_i915_private *dev_priv = dev->dev_private;
2145         int ret;
2146
2147         ret = mutex_lock_interruptible(&dev->struct_mutex);
2148         if (ret)
2149                 return ret;
2150         intel_runtime_pm_get(dev_priv);
2151
2152         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2153                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2154         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2155                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2156
2157         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2158                 seq_printf(m, "DDC = 0x%08x\n",
2159                            I915_READ(DCC));
2160                 seq_printf(m, "DDC2 = 0x%08x\n",
2161                            I915_READ(DCC2));
2162                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2163                            I915_READ16(C0DRB3));
2164                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2165                            I915_READ16(C1DRB3));
2166         } else if (INTEL_INFO(dev)->gen >= 6) {
2167                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2168                            I915_READ(MAD_DIMM_C0));
2169                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2170                            I915_READ(MAD_DIMM_C1));
2171                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2172                            I915_READ(MAD_DIMM_C2));
2173                 seq_printf(m, "TILECTL = 0x%08x\n",
2174                            I915_READ(TILECTL));
2175                 if (INTEL_INFO(dev)->gen >= 8)
2176                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2177                                    I915_READ(GAMTARBMODE));
2178                 else
2179                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2180                                    I915_READ(ARB_MODE));
2181                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2182                            I915_READ(DISP_ARB_CTL));
2183         }
2184
2185         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2186                 seq_puts(m, "L-shaped memory detected\n");
2187
2188         intel_runtime_pm_put(dev_priv);
2189         mutex_unlock(&dev->struct_mutex);
2190
2191         return 0;
2192 }
2193
2194 static int per_file_ctx(int id, void *ptr, void *data)
2195 {
2196         struct intel_context *ctx = ptr;
2197         struct seq_file *m = data;
2198         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2199
2200         if (!ppgtt) {
2201                 seq_printf(m, "  no ppgtt for context %d\n",
2202                            ctx->user_handle);
2203                 return 0;
2204         }
2205
2206         if (i915_gem_context_is_default(ctx))
2207                 seq_puts(m, "  default context:\n");
2208         else
2209                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2210         ppgtt->debug_dump(ppgtt, m);
2211
2212         return 0;
2213 }
2214
2215 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2216 {
2217         struct drm_i915_private *dev_priv = dev->dev_private;
2218         struct intel_engine_cs *ring;
2219         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2220         int unused, i;
2221
2222         if (!ppgtt)
2223                 return;
2224
2225         for_each_ring(ring, dev_priv, unused) {
2226                 seq_printf(m, "%s\n", ring->name);
2227                 for (i = 0; i < 4; i++) {
2228                         u32 offset = 0x270 + i * 8;
2229                         u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2230                         pdp <<= 32;
2231                         pdp |= I915_READ(ring->mmio_base + offset);
2232                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2233                 }
2234         }
2235 }
2236
2237 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2238 {
2239         struct drm_i915_private *dev_priv = dev->dev_private;
2240         struct intel_engine_cs *ring;
2241         struct drm_file *file;
2242         int i;
2243
2244         if (INTEL_INFO(dev)->gen == 6)
2245                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2246
2247         for_each_ring(ring, dev_priv, i) {
2248                 seq_printf(m, "%s\n", ring->name);
2249                 if (INTEL_INFO(dev)->gen == 7)
2250                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2251                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2252                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2253                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2254         }
2255         if (dev_priv->mm.aliasing_ppgtt) {
2256                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2257
2258                 seq_puts(m, "aliasing PPGTT:\n");
2259                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2260
2261                 ppgtt->debug_dump(ppgtt, m);
2262         }
2263
2264         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2265                 struct drm_i915_file_private *file_priv = file->driver_priv;
2266
2267                 seq_printf(m, "proc: %s\n",
2268                            get_pid_task(file->pid, PIDTYPE_PID)->comm);
2269                 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
2270         }
2271         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2272 }
2273
2274 static int i915_ppgtt_info(struct seq_file *m, void *data)
2275 {
2276         struct drm_info_node *node = m->private;
2277         struct drm_device *dev = node->minor->dev;
2278         struct drm_i915_private *dev_priv = dev->dev_private;
2279
2280         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2281         if (ret)
2282                 return ret;
2283         intel_runtime_pm_get(dev_priv);
2284
2285         if (INTEL_INFO(dev)->gen >= 8)
2286                 gen8_ppgtt_info(m, dev);
2287         else if (INTEL_INFO(dev)->gen >= 6)
2288                 gen6_ppgtt_info(m, dev);
2289
2290         intel_runtime_pm_put(dev_priv);
2291         mutex_unlock(&dev->struct_mutex);
2292
2293         return 0;
2294 }
2295
2296 static int count_irq_waiters(struct drm_i915_private *i915)
2297 {
2298         struct intel_engine_cs *ring;
2299         int count = 0;
2300         int i;
2301
2302         for_each_ring(ring, i915, i)
2303                 count += ring->irq_refcount;
2304
2305         return count;
2306 }
2307
2308 static int i915_rps_boost_info(struct seq_file *m, void *data)
2309 {
2310         struct drm_info_node *node = m->private;
2311         struct drm_device *dev = node->minor->dev;
2312         struct drm_i915_private *dev_priv = dev->dev_private;
2313         struct drm_file *file;
2314
2315         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2316         seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2317         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2318         seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2319                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2320                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2321                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2322                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2323                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2324         spin_lock(&dev_priv->rps.client_lock);
2325         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2326                 struct drm_i915_file_private *file_priv = file->driver_priv;
2327                 struct task_struct *task;
2328
2329                 rcu_read_lock();
2330                 task = pid_task(file->pid, PIDTYPE_PID);
2331                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2332                            task ? task->comm : "<unknown>",
2333                            task ? task->pid : -1,
2334                            file_priv->rps.boosts,
2335                            list_empty(&file_priv->rps.link) ? "" : ", active");
2336                 rcu_read_unlock();
2337         }
2338         seq_printf(m, "Semaphore boosts: %d%s\n",
2339                    dev_priv->rps.semaphores.boosts,
2340                    list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2341         seq_printf(m, "MMIO flip boosts: %d%s\n",
2342                    dev_priv->rps.mmioflips.boosts,
2343                    list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2344         seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2345         spin_unlock(&dev_priv->rps.client_lock);
2346
2347         return 0;
2348 }
2349
2350 static int i915_llc(struct seq_file *m, void *data)
2351 {
2352         struct drm_info_node *node = m->private;
2353         struct drm_device *dev = node->minor->dev;
2354         struct drm_i915_private *dev_priv = dev->dev_private;
2355
2356         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2357         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2358         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2359
2360         return 0;
2361 }
2362
2363 static int i915_edp_psr_status(struct seq_file *m, void *data)
2364 {
2365         struct drm_info_node *node = m->private;
2366         struct drm_device *dev = node->minor->dev;
2367         struct drm_i915_private *dev_priv = dev->dev_private;
2368         u32 psrperf = 0;
2369         u32 stat[3];
2370         enum pipe pipe;
2371         bool enabled = false;
2372
2373         if (!HAS_PSR(dev)) {
2374                 seq_puts(m, "PSR not supported\n");
2375                 return 0;
2376         }
2377
2378         intel_runtime_pm_get(dev_priv);
2379
2380         mutex_lock(&dev_priv->psr.lock);
2381         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2382         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2383         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2384         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2385         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2386                    dev_priv->psr.busy_frontbuffer_bits);
2387         seq_printf(m, "Re-enable work scheduled: %s\n",
2388                    yesno(work_busy(&dev_priv->psr.work.work)));
2389
2390         if (HAS_DDI(dev))
2391                 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2392         else {
2393                 for_each_pipe(dev_priv, pipe) {
2394                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2395                                 VLV_EDP_PSR_CURR_STATE_MASK;
2396                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2397                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2398                                 enabled = true;
2399                 }
2400         }
2401         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2402
2403         if (!HAS_DDI(dev))
2404                 for_each_pipe(dev_priv, pipe) {
2405                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2406                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2407                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2408                 }
2409         seq_puts(m, "\n");
2410
2411         /* CHV PSR has no kind of performance counter */
2412         if (HAS_DDI(dev)) {
2413                 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2414                         EDP_PSR_PERF_CNT_MASK;
2415
2416                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2417         }
2418         mutex_unlock(&dev_priv->psr.lock);
2419
2420         intel_runtime_pm_put(dev_priv);
2421         return 0;
2422 }
2423
2424 static int i915_sink_crc(struct seq_file *m, void *data)
2425 {
2426         struct drm_info_node *node = m->private;
2427         struct drm_device *dev = node->minor->dev;
2428         struct intel_encoder *encoder;
2429         struct intel_connector *connector;
2430         struct intel_dp *intel_dp = NULL;
2431         int ret;
2432         u8 crc[6];
2433
2434         drm_modeset_lock_all(dev);
2435         for_each_intel_connector(dev, connector) {
2436
2437                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2438                         continue;
2439
2440                 if (!connector->base.encoder)
2441                         continue;
2442
2443                 encoder = to_intel_encoder(connector->base.encoder);
2444                 if (encoder->type != INTEL_OUTPUT_EDP)
2445                         continue;
2446
2447                 intel_dp = enc_to_intel_dp(&encoder->base);
2448
2449                 ret = intel_dp_sink_crc(intel_dp, crc);
2450                 if (ret)
2451                         goto out;
2452
2453                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2454                            crc[0], crc[1], crc[2],
2455                            crc[3], crc[4], crc[5]);
2456                 goto out;
2457         }
2458         ret = -ENODEV;
2459 out:
2460         drm_modeset_unlock_all(dev);
2461         return ret;
2462 }
2463
2464 static int i915_energy_uJ(struct seq_file *m, void *data)
2465 {
2466         struct drm_info_node *node = m->private;
2467         struct drm_device *dev = node->minor->dev;
2468         struct drm_i915_private *dev_priv = dev->dev_private;
2469         u64 power;
2470         u32 units;
2471
2472         if (INTEL_INFO(dev)->gen < 6)
2473                 return -ENODEV;
2474
2475         intel_runtime_pm_get(dev_priv);
2476
2477         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2478         power = (power & 0x1f00) >> 8;
2479         units = 1000000 / (1 << power); /* convert to uJ */
2480         power = I915_READ(MCH_SECP_NRG_STTS);
2481         power *= units;
2482
2483         intel_runtime_pm_put(dev_priv);
2484
2485         seq_printf(m, "%llu", (long long unsigned)power);
2486
2487         return 0;
2488 }
2489
2490 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2491 {
2492         struct drm_info_node *node = m->private;
2493         struct drm_device *dev = node->minor->dev;
2494         struct drm_i915_private *dev_priv = dev->dev_private;
2495
2496         if (!HAS_RUNTIME_PM(dev)) {
2497                 seq_puts(m, "not supported\n");
2498                 return 0;
2499         }
2500
2501         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2502         seq_printf(m, "IRQs disabled: %s\n",
2503                    yesno(!intel_irqs_enabled(dev_priv)));
2504 #ifdef CONFIG_PM
2505         seq_printf(m, "Usage count: %d\n",
2506                    atomic_read(&dev->dev->power.usage_count));
2507 #else
2508         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2509 #endif
2510
2511         return 0;
2512 }
2513
2514 static const char *power_domain_str(enum intel_display_power_domain domain)
2515 {
2516         switch (domain) {
2517         case POWER_DOMAIN_PIPE_A:
2518                 return "PIPE_A";
2519         case POWER_DOMAIN_PIPE_B:
2520                 return "PIPE_B";
2521         case POWER_DOMAIN_PIPE_C:
2522                 return "PIPE_C";
2523         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2524                 return "PIPE_A_PANEL_FITTER";
2525         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2526                 return "PIPE_B_PANEL_FITTER";
2527         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2528                 return "PIPE_C_PANEL_FITTER";
2529         case POWER_DOMAIN_TRANSCODER_A:
2530                 return "TRANSCODER_A";
2531         case POWER_DOMAIN_TRANSCODER_B:
2532                 return "TRANSCODER_B";
2533         case POWER_DOMAIN_TRANSCODER_C:
2534                 return "TRANSCODER_C";
2535         case POWER_DOMAIN_TRANSCODER_EDP:
2536                 return "TRANSCODER_EDP";
2537         case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2538                 return "PORT_DDI_A_2_LANES";
2539         case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2540                 return "PORT_DDI_A_4_LANES";
2541         case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2542                 return "PORT_DDI_B_2_LANES";
2543         case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2544                 return "PORT_DDI_B_4_LANES";
2545         case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2546                 return "PORT_DDI_C_2_LANES";
2547         case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2548                 return "PORT_DDI_C_4_LANES";
2549         case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2550                 return "PORT_DDI_D_2_LANES";
2551         case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2552                 return "PORT_DDI_D_4_LANES";
2553         case POWER_DOMAIN_PORT_DSI:
2554                 return "PORT_DSI";
2555         case POWER_DOMAIN_PORT_CRT:
2556                 return "PORT_CRT";
2557         case POWER_DOMAIN_PORT_OTHER:
2558                 return "PORT_OTHER";
2559         case POWER_DOMAIN_VGA:
2560                 return "VGA";
2561         case POWER_DOMAIN_AUDIO:
2562                 return "AUDIO";
2563         case POWER_DOMAIN_PLLS:
2564                 return "PLLS";
2565         case POWER_DOMAIN_AUX_A:
2566                 return "AUX_A";
2567         case POWER_DOMAIN_AUX_B:
2568                 return "AUX_B";
2569         case POWER_DOMAIN_AUX_C:
2570                 return "AUX_C";
2571         case POWER_DOMAIN_AUX_D:
2572                 return "AUX_D";
2573         case POWER_DOMAIN_INIT:
2574                 return "INIT";
2575         default:
2576                 MISSING_CASE(domain);
2577                 return "?";
2578         }
2579 }
2580
2581 static int i915_power_domain_info(struct seq_file *m, void *unused)
2582 {
2583         struct drm_info_node *node = m->private;
2584         struct drm_device *dev = node->minor->dev;
2585         struct drm_i915_private *dev_priv = dev->dev_private;
2586         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2587         int i;
2588
2589         mutex_lock(&power_domains->lock);
2590
2591         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2592         for (i = 0; i < power_domains->power_well_count; i++) {
2593                 struct i915_power_well *power_well;
2594                 enum intel_display_power_domain power_domain;
2595
2596                 power_well = &power_domains->power_wells[i];
2597                 seq_printf(m, "%-25s %d\n", power_well->name,
2598                            power_well->count);
2599
2600                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2601                      power_domain++) {
2602                         if (!(BIT(power_domain) & power_well->domains))
2603                                 continue;
2604
2605                         seq_printf(m, "  %-23s %d\n",
2606                                  power_domain_str(power_domain),
2607                                  power_domains->domain_use_count[power_domain]);
2608                 }
2609         }
2610
2611         mutex_unlock(&power_domains->lock);
2612
2613         return 0;
2614 }
2615
2616 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2617                                  struct drm_display_mode *mode)
2618 {
2619         int i;
2620
2621         for (i = 0; i < tabs; i++)
2622                 seq_putc(m, '\t');
2623
2624         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2625                    mode->base.id, mode->name,
2626                    mode->vrefresh, mode->clock,
2627                    mode->hdisplay, mode->hsync_start,
2628                    mode->hsync_end, mode->htotal,
2629                    mode->vdisplay, mode->vsync_start,
2630                    mode->vsync_end, mode->vtotal,
2631                    mode->type, mode->flags);
2632 }
2633
2634 static void intel_encoder_info(struct seq_file *m,
2635                                struct intel_crtc *intel_crtc,
2636                                struct intel_encoder *intel_encoder)
2637 {
2638         struct drm_info_node *node = m->private;
2639         struct drm_device *dev = node->minor->dev;
2640         struct drm_crtc *crtc = &intel_crtc->base;
2641         struct intel_connector *intel_connector;
2642         struct drm_encoder *encoder;
2643
2644         encoder = &intel_encoder->base;
2645         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2646                    encoder->base.id, encoder->name);
2647         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2648                 struct drm_connector *connector = &intel_connector->base;
2649                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2650                            connector->base.id,
2651                            connector->name,
2652                            drm_get_connector_status_name(connector->status));
2653                 if (connector->status == connector_status_connected) {
2654                         struct drm_display_mode *mode = &crtc->mode;
2655                         seq_printf(m, ", mode:\n");
2656                         intel_seq_print_mode(m, 2, mode);
2657                 } else {
2658                         seq_putc(m, '\n');
2659                 }
2660         }
2661 }
2662
2663 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2664 {
2665         struct drm_info_node *node = m->private;
2666         struct drm_device *dev = node->minor->dev;
2667         struct drm_crtc *crtc = &intel_crtc->base;
2668         struct intel_encoder *intel_encoder;
2669
2670         if (crtc->primary->fb)
2671                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2672                            crtc->primary->fb->base.id, crtc->x, crtc->y,
2673                            crtc->primary->fb->width, crtc->primary->fb->height);
2674         else
2675                 seq_puts(m, "\tprimary plane disabled\n");
2676         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2677                 intel_encoder_info(m, intel_crtc, intel_encoder);
2678 }
2679
2680 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2681 {
2682         struct drm_display_mode *mode = panel->fixed_mode;
2683
2684         seq_printf(m, "\tfixed mode:\n");
2685         intel_seq_print_mode(m, 2, mode);
2686 }
2687
2688 static void intel_dp_info(struct seq_file *m,
2689                           struct intel_connector *intel_connector)
2690 {
2691         struct intel_encoder *intel_encoder = intel_connector->encoder;
2692         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2693
2694         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2695         seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2696                    "no");
2697         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2698                 intel_panel_info(m, &intel_connector->panel);
2699 }
2700
2701 static void intel_hdmi_info(struct seq_file *m,
2702                             struct intel_connector *intel_connector)
2703 {
2704         struct intel_encoder *intel_encoder = intel_connector->encoder;
2705         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2706
2707         seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2708                    "no");
2709 }
2710
2711 static void intel_lvds_info(struct seq_file *m,
2712                             struct intel_connector *intel_connector)
2713 {
2714         intel_panel_info(m, &intel_connector->panel);
2715 }
2716
2717 static void intel_connector_info(struct seq_file *m,
2718                                  struct drm_connector *connector)
2719 {
2720         struct intel_connector *intel_connector = to_intel_connector(connector);
2721         struct intel_encoder *intel_encoder = intel_connector->encoder;
2722         struct drm_display_mode *mode;
2723
2724         seq_printf(m, "connector %d: type %s, status: %s\n",
2725                    connector->base.id, connector->name,
2726                    drm_get_connector_status_name(connector->status));
2727         if (connector->status == connector_status_connected) {
2728                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2729                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2730                            connector->display_info.width_mm,
2731                            connector->display_info.height_mm);
2732                 seq_printf(m, "\tsubpixel order: %s\n",
2733                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2734                 seq_printf(m, "\tCEA rev: %d\n",
2735                            connector->display_info.cea_rev);
2736         }
2737         if (intel_encoder) {
2738                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2739                     intel_encoder->type == INTEL_OUTPUT_EDP)
2740                         intel_dp_info(m, intel_connector);
2741                 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2742                         intel_hdmi_info(m, intel_connector);
2743                 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2744                         intel_lvds_info(m, intel_connector);
2745         }
2746
2747         seq_printf(m, "\tmodes:\n");
2748         list_for_each_entry(mode, &connector->modes, head)
2749                 intel_seq_print_mode(m, 2, mode);
2750 }
2751
2752 static bool cursor_active(struct drm_device *dev, int pipe)
2753 {
2754         struct drm_i915_private *dev_priv = dev->dev_private;
2755         u32 state;
2756
2757         if (IS_845G(dev) || IS_I865G(dev))
2758                 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2759         else
2760                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2761
2762         return state;
2763 }
2764
2765 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2766 {
2767         struct drm_i915_private *dev_priv = dev->dev_private;
2768         u32 pos;
2769
2770         pos = I915_READ(CURPOS(pipe));
2771
2772         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2773         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2774                 *x = -*x;
2775
2776         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2777         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2778                 *y = -*y;
2779
2780         return cursor_active(dev, pipe);
2781 }
2782
2783 static int i915_display_info(struct seq_file *m, void *unused)
2784 {
2785         struct drm_info_node *node = m->private;
2786         struct drm_device *dev = node->minor->dev;
2787         struct drm_i915_private *dev_priv = dev->dev_private;
2788         struct intel_crtc *crtc;
2789         struct drm_connector *connector;
2790
2791         intel_runtime_pm_get(dev_priv);
2792         drm_modeset_lock_all(dev);
2793         seq_printf(m, "CRTC info\n");
2794         seq_printf(m, "---------\n");
2795         for_each_intel_crtc(dev, crtc) {
2796                 bool active;
2797                 struct intel_crtc_state *pipe_config;
2798                 int x, y;
2799
2800                 pipe_config = to_intel_crtc_state(crtc->base.state);
2801
2802                 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2803                            crtc->base.base.id, pipe_name(crtc->pipe),
2804                            yesno(pipe_config->base.active),
2805                            pipe_config->pipe_src_w, pipe_config->pipe_src_h);
2806                 if (pipe_config->base.active) {
2807                         intel_crtc_info(m, crtc);
2808
2809                         active = cursor_position(dev, crtc->pipe, &x, &y);
2810                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2811                                    yesno(crtc->cursor_base),
2812                                    x, y, crtc->base.cursor->state->crtc_w,
2813                                    crtc->base.cursor->state->crtc_h,
2814                                    crtc->cursor_addr, yesno(active));
2815                 }
2816
2817                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2818                            yesno(!crtc->cpu_fifo_underrun_disabled),
2819                            yesno(!crtc->pch_fifo_underrun_disabled));
2820         }
2821
2822         seq_printf(m, "\n");
2823         seq_printf(m, "Connector info\n");
2824         seq_printf(m, "--------------\n");
2825         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2826                 intel_connector_info(m, connector);
2827         }
2828         drm_modeset_unlock_all(dev);
2829         intel_runtime_pm_put(dev_priv);
2830
2831         return 0;
2832 }
2833
2834 static int i915_semaphore_status(struct seq_file *m, void *unused)
2835 {
2836         struct drm_info_node *node = (struct drm_info_node *) m->private;
2837         struct drm_device *dev = node->minor->dev;
2838         struct drm_i915_private *dev_priv = dev->dev_private;
2839         struct intel_engine_cs *ring;
2840         int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2841         int i, j, ret;
2842
2843         if (!i915_semaphore_is_enabled(dev)) {
2844                 seq_puts(m, "Semaphores are disabled\n");
2845                 return 0;
2846         }
2847
2848         ret = mutex_lock_interruptible(&dev->struct_mutex);
2849         if (ret)
2850                 return ret;
2851         intel_runtime_pm_get(dev_priv);
2852
2853         if (IS_BROADWELL(dev)) {
2854                 struct page *page;
2855                 uint64_t *seqno;
2856
2857                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2858
2859                 seqno = (uint64_t *)kmap_atomic(page);
2860                 for_each_ring(ring, dev_priv, i) {
2861                         uint64_t offset;
2862
2863                         seq_printf(m, "%s\n", ring->name);
2864
2865                         seq_puts(m, "  Last signal:");
2866                         for (j = 0; j < num_rings; j++) {
2867                                 offset = i * I915_NUM_RINGS + j;
2868                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2869                                            seqno[offset], offset * 8);
2870                         }
2871                         seq_putc(m, '\n');
2872
2873                         seq_puts(m, "  Last wait:  ");
2874                         for (j = 0; j < num_rings; j++) {
2875                                 offset = i + (j * I915_NUM_RINGS);
2876                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2877                                            seqno[offset], offset * 8);
2878                         }
2879                         seq_putc(m, '\n');
2880
2881                 }
2882                 kunmap_atomic(seqno);
2883         } else {
2884                 seq_puts(m, "  Last signal:");
2885                 for_each_ring(ring, dev_priv, i)
2886                         for (j = 0; j < num_rings; j++)
2887                                 seq_printf(m, "0x%08x\n",
2888                                            I915_READ(ring->semaphore.mbox.signal[j]));
2889                 seq_putc(m, '\n');
2890         }
2891
2892         seq_puts(m, "\nSync seqno:\n");
2893         for_each_ring(ring, dev_priv, i) {
2894                 for (j = 0; j < num_rings; j++) {
2895                         seq_printf(m, "  0x%08x ", ring->semaphore.sync_seqno[j]);
2896                 }
2897                 seq_putc(m, '\n');
2898         }
2899         seq_putc(m, '\n');
2900
2901         intel_runtime_pm_put(dev_priv);
2902         mutex_unlock(&dev->struct_mutex);
2903         return 0;
2904 }
2905
2906 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2907 {
2908         struct drm_info_node *node = (struct drm_info_node *) m->private;
2909         struct drm_device *dev = node->minor->dev;
2910         struct drm_i915_private *dev_priv = dev->dev_private;
2911         int i;
2912
2913         drm_modeset_lock_all(dev);
2914         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2915                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2916
2917                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2918                 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2919                            pll->config.crtc_mask, pll->active, yesno(pll->on));
2920                 seq_printf(m, " tracked hardware state:\n");
2921                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
2922                 seq_printf(m, " dpll_md: 0x%08x\n",
2923                            pll->config.hw_state.dpll_md);
2924                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
2925                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
2926                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
2927         }
2928         drm_modeset_unlock_all(dev);
2929
2930         return 0;
2931 }
2932
2933 static int i915_wa_registers(struct seq_file *m, void *unused)
2934 {
2935         int i;
2936         int ret;
2937         struct drm_info_node *node = (struct drm_info_node *) m->private;
2938         struct drm_device *dev = node->minor->dev;
2939         struct drm_i915_private *dev_priv = dev->dev_private;
2940
2941         ret = mutex_lock_interruptible(&dev->struct_mutex);
2942         if (ret)
2943                 return ret;
2944
2945         intel_runtime_pm_get(dev_priv);
2946
2947         seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2948         for (i = 0; i < dev_priv->workarounds.count; ++i) {
2949                 u32 addr, mask, value, read;
2950                 bool ok;
2951
2952                 addr = dev_priv->workarounds.reg[i].addr;
2953                 mask = dev_priv->workarounds.reg[i].mask;
2954                 value = dev_priv->workarounds.reg[i].value;
2955                 read = I915_READ(addr);
2956                 ok = (value & mask) == (read & mask);
2957                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2958                            addr, value, mask, read, ok ? "OK" : "FAIL");
2959         }
2960
2961         intel_runtime_pm_put(dev_priv);
2962         mutex_unlock(&dev->struct_mutex);
2963
2964         return 0;
2965 }
2966
2967 static int i915_ddb_info(struct seq_file *m, void *unused)
2968 {
2969         struct drm_info_node *node = m->private;
2970         struct drm_device *dev = node->minor->dev;
2971         struct drm_i915_private *dev_priv = dev->dev_private;
2972         struct skl_ddb_allocation *ddb;
2973         struct skl_ddb_entry *entry;
2974         enum pipe pipe;
2975         int plane;
2976
2977         if (INTEL_INFO(dev)->gen < 9)
2978                 return 0;
2979
2980         drm_modeset_lock_all(dev);
2981
2982         ddb = &dev_priv->wm.skl_hw.ddb;
2983
2984         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2985
2986         for_each_pipe(dev_priv, pipe) {
2987                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2988
2989                 for_each_plane(dev_priv, pipe, plane) {
2990                         entry = &ddb->plane[pipe][plane];
2991                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
2992                                    entry->start, entry->end,
2993                                    skl_ddb_entry_size(entry));
2994                 }
2995
2996                 entry = &ddb->cursor[pipe];
2997                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
2998                            entry->end, skl_ddb_entry_size(entry));
2999         }
3000
3001         drm_modeset_unlock_all(dev);
3002
3003         return 0;
3004 }
3005
3006 static void drrs_status_per_crtc(struct seq_file *m,
3007                 struct drm_device *dev, struct intel_crtc *intel_crtc)
3008 {
3009         struct intel_encoder *intel_encoder;
3010         struct drm_i915_private *dev_priv = dev->dev_private;
3011         struct i915_drrs *drrs = &dev_priv->drrs;
3012         int vrefresh = 0;
3013
3014         for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3015                 /* Encoder connected on this CRTC */
3016                 switch (intel_encoder->type) {
3017                 case INTEL_OUTPUT_EDP:
3018                         seq_puts(m, "eDP:\n");
3019                         break;
3020                 case INTEL_OUTPUT_DSI:
3021                         seq_puts(m, "DSI:\n");
3022                         break;
3023                 case INTEL_OUTPUT_HDMI:
3024                         seq_puts(m, "HDMI:\n");
3025                         break;
3026                 case INTEL_OUTPUT_DISPLAYPORT:
3027                         seq_puts(m, "DP:\n");
3028                         break;
3029                 default:
3030                         seq_printf(m, "Other encoder (id=%d).\n",
3031                                                 intel_encoder->type);
3032                         return;
3033                 }
3034         }
3035
3036         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3037                 seq_puts(m, "\tVBT: DRRS_type: Static");
3038         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3039                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3040         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3041                 seq_puts(m, "\tVBT: DRRS_type: None");
3042         else
3043                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3044
3045         seq_puts(m, "\n\n");
3046
3047         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3048                 struct intel_panel *panel;
3049
3050                 mutex_lock(&drrs->mutex);
3051                 /* DRRS Supported */
3052                 seq_puts(m, "\tDRRS Supported: Yes\n");
3053
3054                 /* disable_drrs() will make drrs->dp NULL */
3055                 if (!drrs->dp) {
3056                         seq_puts(m, "Idleness DRRS: Disabled");
3057                         mutex_unlock(&drrs->mutex);
3058                         return;
3059                 }
3060
3061                 panel = &drrs->dp->attached_connector->panel;
3062                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3063                                         drrs->busy_frontbuffer_bits);
3064
3065                 seq_puts(m, "\n\t\t");
3066                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3067                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3068                         vrefresh = panel->fixed_mode->vrefresh;
3069                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3070                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3071                         vrefresh = panel->downclock_mode->vrefresh;
3072                 } else {
3073                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3074                                                 drrs->refresh_rate_type);
3075                         mutex_unlock(&drrs->mutex);
3076                         return;
3077                 }
3078                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3079
3080                 seq_puts(m, "\n\t\t");
3081                 mutex_unlock(&drrs->mutex);
3082         } else {
3083                 /* DRRS not supported. Print the VBT parameter*/
3084                 seq_puts(m, "\tDRRS Supported : No");
3085         }
3086         seq_puts(m, "\n");
3087 }
3088
3089 static int i915_drrs_status(struct seq_file *m, void *unused)
3090 {
3091         struct drm_info_node *node = m->private;
3092         struct drm_device *dev = node->minor->dev;
3093         struct intel_crtc *intel_crtc;
3094         int active_crtc_cnt = 0;
3095
3096         for_each_intel_crtc(dev, intel_crtc) {
3097                 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3098
3099                 if (intel_crtc->base.state->active) {
3100                         active_crtc_cnt++;
3101                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3102
3103                         drrs_status_per_crtc(m, dev, intel_crtc);
3104                 }
3105
3106                 drm_modeset_unlock(&intel_crtc->base.mutex);
3107         }
3108
3109         if (!active_crtc_cnt)
3110                 seq_puts(m, "No active crtc found\n");
3111
3112         return 0;
3113 }
3114
3115 struct pipe_crc_info {
3116         const char *name;
3117         struct drm_device *dev;
3118         enum pipe pipe;
3119 };
3120
3121 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3122 {
3123         struct drm_info_node *node = (struct drm_info_node *) m->private;
3124         struct drm_device *dev = node->minor->dev;
3125         struct drm_encoder *encoder;
3126         struct intel_encoder *intel_encoder;
3127         struct intel_digital_port *intel_dig_port;
3128         drm_modeset_lock_all(dev);
3129         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3130                 intel_encoder = to_intel_encoder(encoder);
3131                 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3132                         continue;
3133                 intel_dig_port = enc_to_dig_port(encoder);
3134                 if (!intel_dig_port->dp.can_mst)
3135                         continue;
3136
3137                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3138         }
3139         drm_modeset_unlock_all(dev);
3140         return 0;
3141 }
3142
3143 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3144 {
3145         struct pipe_crc_info *info = inode->i_private;
3146         struct drm_i915_private *dev_priv = info->dev->dev_private;
3147         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3148
3149         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3150                 return -ENODEV;
3151
3152         spin_lock_irq(&pipe_crc->lock);
3153
3154         if (pipe_crc->opened) {
3155                 spin_unlock_irq(&pipe_crc->lock);
3156                 return -EBUSY; /* already open */
3157         }
3158
3159         pipe_crc->opened = true;
3160         filep->private_data = inode->i_private;
3161
3162         spin_unlock_irq(&pipe_crc->lock);
3163
3164         return 0;
3165 }
3166
3167 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3168 {
3169         struct pipe_crc_info *info = inode->i_private;
3170         struct drm_i915_private *dev_priv = info->dev->dev_private;
3171         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3172
3173         spin_lock_irq(&pipe_crc->lock);
3174         pipe_crc->opened = false;
3175         spin_unlock_irq(&pipe_crc->lock);
3176
3177         return 0;
3178 }
3179
3180 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3181 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3182 /* account for \'0' */
3183 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3184
3185 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3186 {
3187         assert_spin_locked(&pipe_crc->lock);
3188         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3189                         INTEL_PIPE_CRC_ENTRIES_NR);
3190 }
3191
3192 static ssize_t
3193 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3194                    loff_t *pos)
3195 {
3196         struct pipe_crc_info *info = filep->private_data;
3197         struct drm_device *dev = info->dev;
3198         struct drm_i915_private *dev_priv = dev->dev_private;
3199         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3200         char buf[PIPE_CRC_BUFFER_LEN];
3201         int n_entries;
3202         ssize_t bytes_read;
3203
3204         /*
3205          * Don't allow user space to provide buffers not big enough to hold
3206          * a line of data.
3207          */
3208         if (count < PIPE_CRC_LINE_LEN)
3209                 return -EINVAL;
3210
3211         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3212                 return 0;
3213
3214         /* nothing to read */
3215         spin_lock_irq(&pipe_crc->lock);
3216         while (pipe_crc_data_count(pipe_crc) == 0) {
3217                 int ret;
3218
3219                 if (filep->f_flags & O_NONBLOCK) {
3220                         spin_unlock_irq(&pipe_crc->lock);
3221                         return -EAGAIN;
3222                 }
3223
3224                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3225                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3226                 if (ret) {
3227                         spin_unlock_irq(&pipe_crc->lock);
3228                         return ret;
3229                 }
3230         }
3231
3232         /* We now have one or more entries to read */
3233         n_entries = count / PIPE_CRC_LINE_LEN;
3234
3235         bytes_read = 0;
3236         while (n_entries > 0) {
3237                 struct intel_pipe_crc_entry *entry =
3238                         &pipe_crc->entries[pipe_crc->tail];
3239                 int ret;
3240
3241                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3242                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3243                         break;
3244
3245                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3246                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3247
3248                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3249                                        "%8u %8x %8x %8x %8x %8x\n",
3250                                        entry->frame, entry->crc[0],
3251                                        entry->crc[1], entry->crc[2],
3252                                        entry->crc[3], entry->crc[4]);
3253
3254                 spin_unlock_irq(&pipe_crc->lock);
3255
3256                 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3257                 if (ret == PIPE_CRC_LINE_LEN)
3258                         return -EFAULT;
3259
3260                 user_buf += PIPE_CRC_LINE_LEN;
3261                 n_entries--;
3262
3263                 spin_lock_irq(&pipe_crc->lock);
3264         }
3265
3266         spin_unlock_irq(&pipe_crc->lock);
3267
3268         return bytes_read;
3269 }
3270
3271 static const struct file_operations i915_pipe_crc_fops = {
3272         .owner = THIS_MODULE,
3273         .open = i915_pipe_crc_open,
3274         .read = i915_pipe_crc_read,
3275         .release = i915_pipe_crc_release,
3276 };
3277
3278 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3279         {
3280                 .name = "i915_pipe_A_crc",
3281                 .pipe = PIPE_A,
3282         },
3283         {
3284                 .name = "i915_pipe_B_crc",
3285                 .pipe = PIPE_B,
3286         },
3287         {
3288                 .name = "i915_pipe_C_crc",
3289                 .pipe = PIPE_C,
3290         },
3291 };
3292
3293 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3294                                 enum pipe pipe)
3295 {
3296         struct drm_device *dev = minor->dev;
3297         struct dentry *ent;
3298         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3299
3300         info->dev = dev;
3301         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3302                                   &i915_pipe_crc_fops);
3303         if (!ent)
3304                 return -ENOMEM;
3305
3306         return drm_add_fake_info_node(minor, ent, info);
3307 }
3308
3309 static const char * const pipe_crc_sources[] = {
3310         "none",
3311         "plane1",
3312         "plane2",
3313         "pf",
3314         "pipe",
3315         "TV",
3316         "DP-B",
3317         "DP-C",
3318         "DP-D",
3319         "auto",
3320 };
3321
3322 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3323 {
3324         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3325         return pipe_crc_sources[source];
3326 }
3327
3328 static int display_crc_ctl_show(struct seq_file *m, void *data)
3329 {
3330         struct drm_device *dev = m->private;
3331         struct drm_i915_private *dev_priv = dev->dev_private;
3332         int i;
3333
3334         for (i = 0; i < I915_MAX_PIPES; i++)
3335                 seq_printf(m, "%c %s\n", pipe_name(i),
3336                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3337
3338         return 0;
3339 }
3340
3341 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3342 {
3343         struct drm_device *dev = inode->i_private;
3344
3345         return single_open(file, display_crc_ctl_show, dev);
3346 }
3347
3348 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3349                                  uint32_t *val)
3350 {
3351         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3352                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3353
3354         switch (*source) {
3355         case INTEL_PIPE_CRC_SOURCE_PIPE:
3356                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3357                 break;
3358         case INTEL_PIPE_CRC_SOURCE_NONE:
3359                 *val = 0;
3360                 break;
3361         default:
3362                 return -EINVAL;
3363         }
3364
3365         return 0;
3366 }
3367
3368 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3369                                      enum intel_pipe_crc_source *source)
3370 {
3371         struct intel_encoder *encoder;
3372         struct intel_crtc *crtc;
3373         struct intel_digital_port *dig_port;
3374         int ret = 0;
3375
3376         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3377
3378         drm_modeset_lock_all(dev);
3379         for_each_intel_encoder(dev, encoder) {
3380                 if (!encoder->base.crtc)
3381                         continue;
3382
3383                 crtc = to_intel_crtc(encoder->base.crtc);
3384
3385                 if (crtc->pipe != pipe)
3386                         continue;
3387
3388                 switch (encoder->type) {
3389                 case INTEL_OUTPUT_TVOUT:
3390                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3391                         break;
3392                 case INTEL_OUTPUT_DISPLAYPORT:
3393                 case INTEL_OUTPUT_EDP:
3394                         dig_port = enc_to_dig_port(&encoder->base);
3395                         switch (dig_port->port) {
3396                         case PORT_B:
3397                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3398                                 break;
3399                         case PORT_C:
3400                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3401                                 break;
3402                         case PORT_D:
3403                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3404                                 break;
3405                         default:
3406                                 WARN(1, "nonexisting DP port %c\n",
3407                                      port_name(dig_port->port));
3408                                 break;
3409                         }
3410                         break;
3411                 default:
3412                         break;
3413                 }
3414         }
3415         drm_modeset_unlock_all(dev);
3416
3417         return ret;
3418 }
3419
3420 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3421                                 enum pipe pipe,
3422                                 enum intel_pipe_crc_source *source,
3423                                 uint32_t *val)
3424 {
3425         struct drm_i915_private *dev_priv = dev->dev_private;
3426         bool need_stable_symbols = false;
3427
3428         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3429                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3430                 if (ret)
3431                         return ret;
3432         }
3433
3434         switch (*source) {
3435         case INTEL_PIPE_CRC_SOURCE_PIPE:
3436                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3437                 break;
3438         case INTEL_PIPE_CRC_SOURCE_DP_B:
3439                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3440                 need_stable_symbols = true;
3441                 break;
3442         case INTEL_PIPE_CRC_SOURCE_DP_C:
3443                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3444                 need_stable_symbols = true;
3445                 break;
3446         case INTEL_PIPE_CRC_SOURCE_DP_D:
3447                 if (!IS_CHERRYVIEW(dev))
3448                         return -EINVAL;
3449                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3450                 need_stable_symbols = true;
3451                 break;
3452         case INTEL_PIPE_CRC_SOURCE_NONE:
3453                 *val = 0;
3454                 break;
3455         default:
3456                 return -EINVAL;
3457         }
3458
3459         /*
3460          * When the pipe CRC tap point is after the transcoders we need
3461          * to tweak symbol-level features to produce a deterministic series of
3462          * symbols for a given frame. We need to reset those features only once
3463          * a frame (instead of every nth symbol):
3464          *   - DC-balance: used to ensure a better clock recovery from the data
3465          *     link (SDVO)
3466          *   - DisplayPort scrambling: used for EMI reduction
3467          */
3468         if (need_stable_symbols) {
3469                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3470
3471                 tmp |= DC_BALANCE_RESET_VLV;
3472                 switch (pipe) {
3473                 case PIPE_A:
3474                         tmp |= PIPE_A_SCRAMBLE_RESET;
3475                         break;
3476                 case PIPE_B:
3477                         tmp |= PIPE_B_SCRAMBLE_RESET;
3478                         break;
3479                 case PIPE_C:
3480                         tmp |= PIPE_C_SCRAMBLE_RESET;
3481                         break;
3482                 default:
3483                         return -EINVAL;
3484                 }
3485                 I915_WRITE(PORT_DFT2_G4X, tmp);
3486         }
3487
3488         return 0;
3489 }
3490
3491 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3492                                  enum pipe pipe,
3493                                  enum intel_pipe_crc_source *source,
3494                                  uint32_t *val)
3495 {
3496         struct drm_i915_private *dev_priv = dev->dev_private;
3497         bool need_stable_symbols = false;
3498
3499         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3500                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3501                 if (ret)
3502                         return ret;
3503         }
3504
3505         switch (*source) {
3506         case INTEL_PIPE_CRC_SOURCE_PIPE:
3507                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3508                 break;
3509         case INTEL_PIPE_CRC_SOURCE_TV:
3510                 if (!SUPPORTS_TV(dev))
3511                         return -EINVAL;
3512                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3513                 break;
3514         case INTEL_PIPE_CRC_SOURCE_DP_B:
3515                 if (!IS_G4X(dev))
3516                         return -EINVAL;
3517                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3518                 need_stable_symbols = true;
3519                 break;
3520         case INTEL_PIPE_CRC_SOURCE_DP_C:
3521                 if (!IS_G4X(dev))
3522                         return -EINVAL;
3523                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3524                 need_stable_symbols = true;
3525                 break;
3526         case INTEL_PIPE_CRC_SOURCE_DP_D:
3527                 if (!IS_G4X(dev))
3528                         return -EINVAL;
3529                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3530                 need_stable_symbols = true;
3531                 break;
3532         case INTEL_PIPE_CRC_SOURCE_NONE:
3533                 *val = 0;
3534                 break;
3535         default:
3536                 return -EINVAL;
3537         }
3538
3539         /*
3540          * When the pipe CRC tap point is after the transcoders we need
3541          * to tweak symbol-level features to produce a deterministic series of
3542          * symbols for a given frame. We need to reset those features only once
3543          * a frame (instead of every nth symbol):
3544          *   - DC-balance: used to ensure a better clock recovery from the data
3545          *     link (SDVO)
3546          *   - DisplayPort scrambling: used for EMI reduction
3547          */
3548         if (need_stable_symbols) {
3549                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3550
3551                 WARN_ON(!IS_G4X(dev));
3552
3553                 I915_WRITE(PORT_DFT_I9XX,
3554                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3555
3556                 if (pipe == PIPE_A)
3557                         tmp |= PIPE_A_SCRAMBLE_RESET;
3558                 else
3559                         tmp |= PIPE_B_SCRAMBLE_RESET;
3560
3561                 I915_WRITE(PORT_DFT2_G4X, tmp);
3562         }
3563
3564         return 0;
3565 }
3566
3567 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3568                                          enum pipe pipe)
3569 {
3570         struct drm_i915_private *dev_priv = dev->dev_private;
3571         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3572
3573         switch (pipe) {
3574         case PIPE_A:
3575                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3576                 break;
3577         case PIPE_B:
3578                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3579                 break;
3580         case PIPE_C:
3581                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3582                 break;
3583         default:
3584                 return;
3585         }
3586         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3587                 tmp &= ~DC_BALANCE_RESET_VLV;
3588         I915_WRITE(PORT_DFT2_G4X, tmp);
3589
3590 }
3591
3592 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3593                                          enum pipe pipe)
3594 {
3595         struct drm_i915_private *dev_priv = dev->dev_private;
3596         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3597
3598         if (pipe == PIPE_A)
3599                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3600         else
3601                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3602         I915_WRITE(PORT_DFT2_G4X, tmp);
3603
3604         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3605                 I915_WRITE(PORT_DFT_I9XX,
3606                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3607         }
3608 }
3609
3610 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3611                                 uint32_t *val)
3612 {
3613         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3614                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3615
3616         switch (*source) {
3617         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3618                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3619                 break;
3620         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3621                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3622                 break;
3623         case INTEL_PIPE_CRC_SOURCE_PIPE:
3624                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3625                 break;
3626         case INTEL_PIPE_CRC_SOURCE_NONE:
3627                 *val = 0;
3628                 break;
3629         default:
3630                 return -EINVAL;
3631         }
3632
3633         return 0;
3634 }
3635
3636 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3637 {
3638         struct drm_i915_private *dev_priv = dev->dev_private;
3639         struct intel_crtc *crtc =
3640                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3641         struct intel_crtc_state *pipe_config;
3642
3643         drm_modeset_lock_all(dev);
3644         pipe_config = to_intel_crtc_state(crtc->base.state);
3645
3646         /*
3647          * If we use the eDP transcoder we need to make sure that we don't
3648          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3649          * relevant on hsw with pipe A when using the always-on power well
3650          * routing.
3651          */
3652         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3653             !pipe_config->pch_pfit.enabled) {
3654                 bool active = pipe_config->base.active;
3655
3656                 if (active) {
3657                         intel_crtc_control(&crtc->base, false);
3658                         pipe_config = to_intel_crtc_state(crtc->base.state);
3659                 }
3660
3661                 pipe_config->pch_pfit.force_thru = true;
3662
3663                 intel_display_power_get(dev_priv,
3664                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3665
3666                 if (active)
3667                         intel_crtc_control(&crtc->base, true);
3668         }
3669         drm_modeset_unlock_all(dev);
3670 }
3671
3672 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3673 {
3674         struct drm_i915_private *dev_priv = dev->dev_private;
3675         struct intel_crtc *crtc =
3676                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3677         struct intel_crtc_state *pipe_config;
3678
3679         drm_modeset_lock_all(dev);
3680         /*
3681          * If we use the eDP transcoder we need to make sure that we don't
3682          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3683          * relevant on hsw with pipe A when using the always-on power well
3684          * routing.
3685          */
3686         pipe_config = to_intel_crtc_state(crtc->base.state);
3687         if (pipe_config->pch_pfit.force_thru) {
3688                 bool active = pipe_config->base.active;
3689
3690                 if (active) {
3691                         intel_crtc_control(&crtc->base, false);
3692                         pipe_config = to_intel_crtc_state(crtc->base.state);
3693                 }
3694
3695                 pipe_config->pch_pfit.force_thru = false;
3696
3697                 intel_display_power_put(dev_priv,
3698                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3699
3700                 if (active)
3701                         intel_crtc_control(&crtc->base, true);
3702         }
3703         drm_modeset_unlock_all(dev);
3704 }
3705
3706 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3707                                 enum pipe pipe,
3708                                 enum intel_pipe_crc_source *source,
3709                                 uint32_t *val)
3710 {
3711         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3712                 *source = INTEL_PIPE_CRC_SOURCE_PF;
3713
3714         switch (*source) {
3715         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3716                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3717                 break;
3718         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3719                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3720                 break;
3721         case INTEL_PIPE_CRC_SOURCE_PF:
3722                 if (IS_HASWELL(dev) && pipe == PIPE_A)
3723                         hsw_trans_edp_pipe_A_crc_wa(dev);
3724
3725                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3726                 break;
3727         case INTEL_PIPE_CRC_SOURCE_NONE:
3728                 *val = 0;
3729                 break;
3730         default:
3731                 return -EINVAL;
3732         }
3733
3734         return 0;
3735 }
3736
3737 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3738                                enum intel_pipe_crc_source source)
3739 {
3740         struct drm_i915_private *dev_priv = dev->dev_private;
3741         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3742         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3743                                                                         pipe));
3744         u32 val = 0; /* shut up gcc */
3745         int ret;
3746
3747         if (pipe_crc->source == source)
3748                 return 0;
3749
3750         /* forbid changing the source without going back to 'none' */
3751         if (pipe_crc->source && source)
3752                 return -EINVAL;
3753
3754         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3755                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3756                 return -EIO;
3757         }
3758
3759         if (IS_GEN2(dev))
3760                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3761         else if (INTEL_INFO(dev)->gen < 5)
3762                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3763         else if (IS_VALLEYVIEW(dev))
3764                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3765         else if (IS_GEN5(dev) || IS_GEN6(dev))
3766                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3767         else
3768                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3769
3770         if (ret != 0)
3771                 return ret;
3772
3773         /* none -> real source transition */
3774         if (source) {
3775                 struct intel_pipe_crc_entry *entries;
3776
3777                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3778                                  pipe_name(pipe), pipe_crc_source_name(source));
3779
3780                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3781                                   sizeof(pipe_crc->entries[0]),
3782                                   GFP_KERNEL);
3783                 if (!entries)
3784                         return -ENOMEM;
3785
3786                 /*
3787                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3788                  * enabled and disabled dynamically based on package C states,
3789                  * user space can't make reliable use of the CRCs, so let's just
3790                  * completely disable it.
3791                  */
3792                 hsw_disable_ips(crtc);
3793
3794                 spin_lock_irq(&pipe_crc->lock);
3795                 kfree(pipe_crc->entries);
3796                 pipe_crc->entries = entries;
3797                 pipe_crc->head = 0;
3798                 pipe_crc->tail = 0;
3799                 spin_unlock_irq(&pipe_crc->lock);
3800         }
3801
3802         pipe_crc->source = source;
3803
3804         I915_WRITE(PIPE_CRC_CTL(pipe), val);
3805         POSTING_READ(PIPE_CRC_CTL(pipe));
3806
3807         /* real source -> none transition */
3808         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3809                 struct intel_pipe_crc_entry *entries;
3810                 struct intel_crtc *crtc =
3811                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3812
3813                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3814                                  pipe_name(pipe));
3815
3816                 drm_modeset_lock(&crtc->base.mutex, NULL);
3817                 if (crtc->base.state->active)
3818                         intel_wait_for_vblank(dev, pipe);
3819                 drm_modeset_unlock(&crtc->base.mutex);
3820
3821                 spin_lock_irq(&pipe_crc->lock);
3822                 entries = pipe_crc->entries;
3823                 pipe_crc->entries = NULL;
3824                 pipe_crc->head = 0;
3825                 pipe_crc->tail = 0;
3826                 spin_unlock_irq(&pipe_crc->lock);
3827
3828                 kfree(entries);
3829
3830                 if (IS_G4X(dev))
3831                         g4x_undo_pipe_scramble_reset(dev, pipe);
3832                 else if (IS_VALLEYVIEW(dev))
3833                         vlv_undo_pipe_scramble_reset(dev, pipe);
3834                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3835                         hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3836
3837                 hsw_enable_ips(crtc);
3838         }
3839
3840         return 0;
3841 }
3842
3843 /*
3844  * Parse pipe CRC command strings:
3845  *   command: wsp* object wsp+ name wsp+ source wsp*
3846  *   object: 'pipe'
3847  *   name: (A | B | C)
3848  *   source: (none | plane1 | plane2 | pf)
3849  *   wsp: (#0x20 | #0x9 | #0xA)+
3850  *
3851  * eg.:
3852  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
3853  *  "pipe A none"    ->  Stop CRC
3854  */
3855 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3856 {
3857         int n_words = 0;
3858
3859         while (*buf) {
3860                 char *end;
3861
3862                 /* skip leading white space */
3863                 buf = skip_spaces(buf);
3864                 if (!*buf)
3865                         break;  /* end of buffer */
3866
3867                 /* find end of word */
3868                 for (end = buf; *end && !isspace(*end); end++)
3869                         ;
3870
3871                 if (n_words == max_words) {
3872                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3873                                          max_words);
3874                         return -EINVAL; /* ran out of words[] before bytes */
3875                 }
3876
3877                 if (*end)
3878                         *end++ = '\0';
3879                 words[n_words++] = buf;
3880                 buf = end;
3881         }
3882
3883         return n_words;
3884 }
3885
3886 enum intel_pipe_crc_object {
3887         PIPE_CRC_OBJECT_PIPE,
3888 };
3889
3890 static const char * const pipe_crc_objects[] = {
3891         "pipe",
3892 };
3893
3894 static int
3895 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3896 {
3897         int i;
3898
3899         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3900                 if (!strcmp(buf, pipe_crc_objects[i])) {
3901                         *o = i;
3902                         return 0;
3903                     }
3904
3905         return -EINVAL;
3906 }
3907
3908 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3909 {
3910         const char name = buf[0];
3911
3912         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3913                 return -EINVAL;
3914
3915         *pipe = name - 'A';
3916
3917         return 0;
3918 }
3919
3920 static int
3921 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3922 {
3923         int i;
3924
3925         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3926                 if (!strcmp(buf, pipe_crc_sources[i])) {
3927                         *s = i;
3928                         return 0;
3929                     }
3930
3931         return -EINVAL;
3932 }
3933
3934 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3935 {
3936 #define N_WORDS 3
3937         int n_words;
3938         char *words[N_WORDS];
3939         enum pipe pipe;
3940         enum intel_pipe_crc_object object;
3941         enum intel_pipe_crc_source source;
3942
3943         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3944         if (n_words != N_WORDS) {
3945                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3946                                  N_WORDS);
3947                 return -EINVAL;
3948         }
3949
3950         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3951                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3952                 return -EINVAL;
3953         }
3954
3955         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3956                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3957                 return -EINVAL;
3958         }
3959
3960         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3961                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3962                 return -EINVAL;
3963         }
3964
3965         return pipe_crc_set_source(dev, pipe, source);
3966 }
3967
3968 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3969                                      size_t len, loff_t *offp)
3970 {
3971         struct seq_file *m = file->private_data;
3972         struct drm_device *dev = m->private;
3973         char *tmpbuf;
3974         int ret;
3975
3976         if (len == 0)
3977                 return 0;
3978
3979         if (len > PAGE_SIZE - 1) {
3980                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3981                                  PAGE_SIZE);
3982                 return -E2BIG;
3983         }
3984
3985         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3986         if (!tmpbuf)
3987                 return -ENOMEM;
3988
3989         if (copy_from_user(tmpbuf, ubuf, len)) {
3990                 ret = -EFAULT;
3991                 goto out;
3992         }
3993         tmpbuf[len] = '\0';
3994
3995         ret = display_crc_ctl_parse(dev, tmpbuf, len);
3996
3997 out:
3998         kfree(tmpbuf);
3999         if (ret < 0)
4000                 return ret;
4001
4002         *offp += len;
4003         return len;
4004 }
4005
4006 static const struct file_operations i915_display_crc_ctl_fops = {
4007         .owner = THIS_MODULE,
4008         .open = display_crc_ctl_open,
4009         .read = seq_read,
4010         .llseek = seq_lseek,
4011         .release = single_release,
4012         .write = display_crc_ctl_write
4013 };
4014
4015 static ssize_t i915_displayport_test_active_write(struct file *file,
4016                                             const char __user *ubuf,
4017                                             size_t len, loff_t *offp)
4018 {
4019         char *input_buffer;
4020         int status = 0;
4021         struct seq_file *m;
4022         struct drm_device *dev;
4023         struct drm_connector *connector;
4024         struct list_head *connector_list;
4025         struct intel_dp *intel_dp;
4026         int val = 0;
4027
4028         m = file->private_data;
4029         if (!m) {
4030                 status = -ENODEV;
4031                 return status;
4032         }
4033         dev = m->private;
4034
4035         if (!dev) {
4036                 status = -ENODEV;
4037                 return status;
4038         }
4039         connector_list = &dev->mode_config.connector_list;
4040
4041         if (len == 0)
4042                 return 0;
4043
4044         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4045         if (!input_buffer)
4046                 return -ENOMEM;
4047
4048         if (copy_from_user(input_buffer, ubuf, len)) {
4049                 status = -EFAULT;
4050                 goto out;
4051         }
4052
4053         input_buffer[len] = '\0';
4054         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4055
4056         list_for_each_entry(connector, connector_list, head) {
4057
4058                 if (connector->connector_type !=
4059                     DRM_MODE_CONNECTOR_DisplayPort)
4060                         continue;
4061
4062                 if (connector->connector_type ==
4063                     DRM_MODE_CONNECTOR_DisplayPort &&
4064                     connector->status == connector_status_connected &&
4065                     connector->encoder != NULL) {
4066                         intel_dp = enc_to_intel_dp(connector->encoder);
4067                         status = kstrtoint(input_buffer, 10, &val);
4068                         if (status < 0)
4069                                 goto out;
4070                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4071                         /* To prevent erroneous activation of the compliance
4072                          * testing code, only accept an actual value of 1 here
4073                          */
4074                         if (val == 1)
4075                                 intel_dp->compliance_test_active = 1;
4076                         else
4077                                 intel_dp->compliance_test_active = 0;
4078                 }
4079         }
4080 out:
4081         kfree(input_buffer);
4082         if (status < 0)
4083                 return status;
4084
4085         *offp += len;
4086         return len;
4087 }
4088
4089 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4090 {
4091         struct drm_device *dev = m->private;
4092         struct drm_connector *connector;
4093         struct list_head *connector_list = &dev->mode_config.connector_list;
4094         struct intel_dp *intel_dp;
4095
4096         if (!dev)
4097                 return -ENODEV;
4098
4099         list_for_each_entry(connector, connector_list, head) {
4100
4101                 if (connector->connector_type !=
4102                     DRM_MODE_CONNECTOR_DisplayPort)
4103                         continue;
4104
4105                 if (connector->status == connector_status_connected &&
4106                     connector->encoder != NULL) {
4107                         intel_dp = enc_to_intel_dp(connector->encoder);
4108                         if (intel_dp->compliance_test_active)
4109                                 seq_puts(m, "1");
4110                         else
4111                                 seq_puts(m, "0");
4112                 } else
4113                         seq_puts(m, "0");
4114         }
4115
4116         return 0;
4117 }
4118
4119 static int i915_displayport_test_active_open(struct inode *inode,
4120                                        struct file *file)
4121 {
4122         struct drm_device *dev = inode->i_private;
4123
4124         return single_open(file, i915_displayport_test_active_show, dev);
4125 }
4126
4127 static const struct file_operations i915_displayport_test_active_fops = {
4128         .owner = THIS_MODULE,
4129         .open = i915_displayport_test_active_open,
4130         .read = seq_read,
4131         .llseek = seq_lseek,
4132         .release = single_release,
4133         .write = i915_displayport_test_active_write
4134 };
4135
4136 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4137 {
4138         struct drm_device *dev = m->private;
4139         struct drm_connector *connector;
4140         struct list_head *connector_list = &dev->mode_config.connector_list;
4141         struct intel_dp *intel_dp;
4142
4143         if (!dev)
4144                 return -ENODEV;
4145
4146         list_for_each_entry(connector, connector_list, head) {
4147
4148                 if (connector->connector_type !=
4149                     DRM_MODE_CONNECTOR_DisplayPort)
4150                         continue;
4151
4152                 if (connector->status == connector_status_connected &&
4153                     connector->encoder != NULL) {
4154                         intel_dp = enc_to_intel_dp(connector->encoder);
4155                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4156                 } else
4157                         seq_puts(m, "0");
4158         }
4159
4160         return 0;
4161 }
4162 static int i915_displayport_test_data_open(struct inode *inode,
4163                                        struct file *file)
4164 {
4165         struct drm_device *dev = inode->i_private;
4166
4167         return single_open(file, i915_displayport_test_data_show, dev);
4168 }
4169
4170 static const struct file_operations i915_displayport_test_data_fops = {
4171         .owner = THIS_MODULE,
4172         .open = i915_displayport_test_data_open,
4173         .read = seq_read,
4174         .llseek = seq_lseek,
4175         .release = single_release
4176 };
4177
4178 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4179 {
4180         struct drm_device *dev = m->private;
4181         struct drm_connector *connector;
4182         struct list_head *connector_list = &dev->mode_config.connector_list;
4183         struct intel_dp *intel_dp;
4184
4185         if (!dev)
4186                 return -ENODEV;
4187
4188         list_for_each_entry(connector, connector_list, head) {
4189
4190                 if (connector->connector_type !=
4191                     DRM_MODE_CONNECTOR_DisplayPort)
4192                         continue;
4193
4194                 if (connector->status == connector_status_connected &&
4195                     connector->encoder != NULL) {
4196                         intel_dp = enc_to_intel_dp(connector->encoder);
4197                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4198                 } else
4199                         seq_puts(m, "0");
4200         }
4201
4202         return 0;
4203 }
4204
4205 static int i915_displayport_test_type_open(struct inode *inode,
4206                                        struct file *file)
4207 {
4208         struct drm_device *dev = inode->i_private;
4209
4210         return single_open(file, i915_displayport_test_type_show, dev);
4211 }
4212
4213 static const struct file_operations i915_displayport_test_type_fops = {
4214         .owner = THIS_MODULE,
4215         .open = i915_displayport_test_type_open,
4216         .read = seq_read,
4217         .llseek = seq_lseek,
4218         .release = single_release
4219 };
4220
4221 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4222 {
4223         struct drm_device *dev = m->private;
4224         int level;
4225         int num_levels;
4226
4227         if (IS_CHERRYVIEW(dev))
4228                 num_levels = 3;
4229         else if (IS_VALLEYVIEW(dev))
4230                 num_levels = 1;
4231         else
4232                 num_levels = ilk_wm_max_level(dev) + 1;
4233
4234         drm_modeset_lock_all(dev);
4235
4236         for (level = 0; level < num_levels; level++) {
4237                 unsigned int latency = wm[level];
4238
4239                 /*
4240                  * - WM1+ latency values in 0.5us units
4241                  * - latencies are in us on gen9/vlv/chv
4242                  */
4243                 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
4244                         latency *= 10;
4245                 else if (level > 0)
4246                         latency *= 5;
4247
4248                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4249                            level, wm[level], latency / 10, latency % 10);
4250         }
4251
4252         drm_modeset_unlock_all(dev);
4253 }
4254
4255 static int pri_wm_latency_show(struct seq_file *m, void *data)
4256 {
4257         struct drm_device *dev = m->private;
4258         struct drm_i915_private *dev_priv = dev->dev_private;
4259         const uint16_t *latencies;
4260
4261         if (INTEL_INFO(dev)->gen >= 9)
4262                 latencies = dev_priv->wm.skl_latency;
4263         else
4264                 latencies = to_i915(dev)->wm.pri_latency;
4265
4266         wm_latency_show(m, latencies);
4267
4268         return 0;
4269 }
4270
4271 static int spr_wm_latency_show(struct seq_file *m, void *data)
4272 {
4273         struct drm_device *dev = m->private;
4274         struct drm_i915_private *dev_priv = dev->dev_private;
4275         const uint16_t *latencies;
4276
4277         if (INTEL_INFO(dev)->gen >= 9)
4278                 latencies = dev_priv->wm.skl_latency;
4279         else
4280                 latencies = to_i915(dev)->wm.spr_latency;
4281
4282         wm_latency_show(m, latencies);
4283
4284         return 0;
4285 }
4286
4287 static int cur_wm_latency_show(struct seq_file *m, void *data)
4288 {
4289         struct drm_device *dev = m->private;
4290         struct drm_i915_private *dev_priv = dev->dev_private;
4291         const uint16_t *latencies;
4292
4293         if (INTEL_INFO(dev)->gen >= 9)
4294                 latencies = dev_priv->wm.skl_latency;
4295         else
4296                 latencies = to_i915(dev)->wm.cur_latency;
4297
4298         wm_latency_show(m, latencies);
4299
4300         return 0;
4301 }
4302
4303 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4304 {
4305         struct drm_device *dev = inode->i_private;
4306
4307         if (INTEL_INFO(dev)->gen < 5)
4308                 return -ENODEV;
4309
4310         return single_open(file, pri_wm_latency_show, dev);
4311 }
4312
4313 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4314 {
4315         struct drm_device *dev = inode->i_private;
4316
4317         if (HAS_GMCH_DISPLAY(dev))
4318                 return -ENODEV;
4319
4320         return single_open(file, spr_wm_latency_show, dev);
4321 }
4322
4323 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4324 {
4325         struct drm_device *dev = inode->i_private;
4326
4327         if (HAS_GMCH_DISPLAY(dev))
4328                 return -ENODEV;
4329
4330         return single_open(file, cur_wm_latency_show, dev);
4331 }
4332
4333 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4334                                 size_t len, loff_t *offp, uint16_t wm[8])
4335 {
4336         struct seq_file *m = file->private_data;
4337         struct drm_device *dev = m->private;
4338         uint16_t new[8] = { 0 };
4339         int num_levels;
4340         int level;
4341         int ret;
4342         char tmp[32];
4343
4344         if (IS_CHERRYVIEW(dev))
4345                 num_levels = 3;
4346         else if (IS_VALLEYVIEW(dev))
4347                 num_levels = 1;
4348         else
4349                 num_levels = ilk_wm_max_level(dev) + 1;
4350
4351         if (len >= sizeof(tmp))
4352                 return -EINVAL;
4353
4354         if (copy_from_user(tmp, ubuf, len))
4355                 return -EFAULT;
4356
4357         tmp[len] = '\0';
4358
4359         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4360                      &new[0], &new[1], &new[2], &new[3],
4361                      &new[4], &new[5], &new[6], &new[7]);
4362         if (ret != num_levels)
4363                 return -EINVAL;
4364
4365         drm_modeset_lock_all(dev);
4366
4367         for (level = 0; level < num_levels; level++)
4368                 wm[level] = new[level];
4369
4370         drm_modeset_unlock_all(dev);
4371
4372         return len;
4373 }
4374
4375
4376 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4377                                     size_t len, loff_t *offp)
4378 {
4379         struct seq_file *m = file->private_data;
4380         struct drm_device *dev = m->private;
4381         struct drm_i915_private *dev_priv = dev->dev_private;
4382         uint16_t *latencies;
4383
4384         if (INTEL_INFO(dev)->gen >= 9)
4385                 latencies = dev_priv->wm.skl_latency;
4386         else
4387                 latencies = to_i915(dev)->wm.pri_latency;
4388
4389         return wm_latency_write(file, ubuf, len, offp, latencies);
4390 }
4391
4392 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4393                                     size_t len, loff_t *offp)
4394 {
4395         struct seq_file *m = file->private_data;
4396         struct drm_device *dev = m->private;
4397         struct drm_i915_private *dev_priv = dev->dev_private;
4398         uint16_t *latencies;
4399
4400         if (INTEL_INFO(dev)->gen >= 9)
4401                 latencies = dev_priv->wm.skl_latency;
4402         else
4403                 latencies = to_i915(dev)->wm.spr_latency;
4404
4405         return wm_latency_write(file, ubuf, len, offp, latencies);
4406 }
4407
4408 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4409                                     size_t len, loff_t *offp)
4410 {
4411         struct seq_file *m = file->private_data;
4412         struct drm_device *dev = m->private;
4413         struct drm_i915_private *dev_priv = dev->dev_private;
4414         uint16_t *latencies;
4415
4416         if (INTEL_INFO(dev)->gen >= 9)
4417                 latencies = dev_priv->wm.skl_latency;
4418         else
4419                 latencies = to_i915(dev)->wm.cur_latency;
4420
4421         return wm_latency_write(file, ubuf, len, offp, latencies);
4422 }
4423
4424 static const struct file_operations i915_pri_wm_latency_fops = {
4425         .owner = THIS_MODULE,
4426         .open = pri_wm_latency_open,
4427         .read = seq_read,
4428         .llseek = seq_lseek,
4429         .release = single_release,
4430         .write = pri_wm_latency_write
4431 };
4432
4433 static const struct file_operations i915_spr_wm_latency_fops = {
4434         .owner = THIS_MODULE,
4435         .open = spr_wm_latency_open,
4436         .read = seq_read,
4437         .llseek = seq_lseek,
4438         .release = single_release,
4439         .write = spr_wm_latency_write
4440 };
4441
4442 static const struct file_operations i915_cur_wm_latency_fops = {
4443         .owner = THIS_MODULE,
4444         .open = cur_wm_latency_open,
4445         .read = seq_read,
4446         .llseek = seq_lseek,
4447         .release = single_release,
4448         .write = cur_wm_latency_write
4449 };
4450
4451 static int
4452 i915_wedged_get(void *data, u64 *val)
4453 {
4454         struct drm_device *dev = data;
4455         struct drm_i915_private *dev_priv = dev->dev_private;
4456
4457         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4458
4459         return 0;
4460 }
4461
4462 static int
4463 i915_wedged_set(void *data, u64 val)
4464 {
4465         struct drm_device *dev = data;
4466         struct drm_i915_private *dev_priv = dev->dev_private;
4467
4468         /*
4469          * There is no safeguard against this debugfs entry colliding
4470          * with the hangcheck calling same i915_handle_error() in
4471          * parallel, causing an explosion. For now we assume that the
4472          * test harness is responsible enough not to inject gpu hangs
4473          * while it is writing to 'i915_wedged'
4474          */
4475
4476         if (i915_reset_in_progress(&dev_priv->gpu_error))
4477                 return -EAGAIN;
4478
4479         intel_runtime_pm_get(dev_priv);
4480
4481         i915_handle_error(dev, val,
4482                           "Manually setting wedged to %llu", val);
4483
4484         intel_runtime_pm_put(dev_priv);
4485
4486         return 0;
4487 }
4488
4489 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4490                         i915_wedged_get, i915_wedged_set,
4491                         "%llu\n");
4492
4493 static int
4494 i915_ring_stop_get(void *data, u64 *val)
4495 {
4496         struct drm_device *dev = data;
4497         struct drm_i915_private *dev_priv = dev->dev_private;
4498
4499         *val = dev_priv->gpu_error.stop_rings;
4500
4501         return 0;
4502 }
4503
4504 static int
4505 i915_ring_stop_set(void *data, u64 val)
4506 {
4507         struct drm_device *dev = data;
4508         struct drm_i915_private *dev_priv = dev->dev_private;
4509         int ret;
4510
4511         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4512
4513         ret = mutex_lock_interruptible(&dev->struct_mutex);
4514         if (ret)
4515                 return ret;
4516
4517         dev_priv->gpu_error.stop_rings = val;
4518         mutex_unlock(&dev->struct_mutex);
4519
4520         return 0;
4521 }
4522
4523 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4524                         i915_ring_stop_get, i915_ring_stop_set,
4525                         "0x%08llx\n");
4526
4527 static int
4528 i915_ring_missed_irq_get(void *data, u64 *val)
4529 {
4530         struct drm_device *dev = data;
4531         struct drm_i915_private *dev_priv = dev->dev_private;
4532
4533         *val = dev_priv->gpu_error.missed_irq_rings;
4534         return 0;
4535 }
4536
4537 static int
4538 i915_ring_missed_irq_set(void *data, u64 val)
4539 {
4540         struct drm_device *dev = data;
4541         struct drm_i915_private *dev_priv = dev->dev_private;
4542         int ret;
4543
4544         /* Lock against concurrent debugfs callers */
4545         ret = mutex_lock_interruptible(&dev->struct_mutex);
4546         if (ret)
4547                 return ret;
4548         dev_priv->gpu_error.missed_irq_rings = val;
4549         mutex_unlock(&dev->struct_mutex);
4550
4551         return 0;
4552 }
4553
4554 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4555                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4556                         "0x%08llx\n");
4557
4558 static int
4559 i915_ring_test_irq_get(void *data, u64 *val)
4560 {
4561         struct drm_device *dev = data;
4562         struct drm_i915_private *dev_priv = dev->dev_private;
4563
4564         *val = dev_priv->gpu_error.test_irq_rings;
4565
4566         return 0;
4567 }
4568
4569 static int
4570 i915_ring_test_irq_set(void *data, u64 val)
4571 {
4572         struct drm_device *dev = data;
4573         struct drm_i915_private *dev_priv = dev->dev_private;
4574         int ret;
4575
4576         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4577
4578         /* Lock against concurrent debugfs callers */
4579         ret = mutex_lock_interruptible(&dev->struct_mutex);
4580         if (ret)
4581                 return ret;
4582
4583         dev_priv->gpu_error.test_irq_rings = val;
4584         mutex_unlock(&dev->struct_mutex);
4585
4586         return 0;
4587 }
4588
4589 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4590                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4591                         "0x%08llx\n");
4592
4593 #define DROP_UNBOUND 0x1
4594 #define DROP_BOUND 0x2
4595 #define DROP_RETIRE 0x4
4596 #define DROP_ACTIVE 0x8
4597 #define DROP_ALL (DROP_UNBOUND | \
4598                   DROP_BOUND | \
4599                   DROP_RETIRE | \
4600                   DROP_ACTIVE)
4601 static int
4602 i915_drop_caches_get(void *data, u64 *val)
4603 {
4604         *val = DROP_ALL;
4605
4606         return 0;
4607 }
4608
4609 static int
4610 i915_drop_caches_set(void *data, u64 val)
4611 {
4612         struct drm_device *dev = data;
4613         struct drm_i915_private *dev_priv = dev->dev_private;
4614         int ret;
4615
4616         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4617
4618         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4619          * on ioctls on -EAGAIN. */
4620         ret = mutex_lock_interruptible(&dev->struct_mutex);
4621         if (ret)
4622                 return ret;
4623
4624         if (val & DROP_ACTIVE) {
4625                 ret = i915_gpu_idle(dev);
4626                 if (ret)
4627                         goto unlock;
4628         }
4629
4630         if (val & (DROP_RETIRE | DROP_ACTIVE))
4631                 i915_gem_retire_requests(dev);
4632
4633         if (val & DROP_BOUND)
4634                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4635
4636         if (val & DROP_UNBOUND)
4637                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4638
4639 unlock:
4640         mutex_unlock(&dev->struct_mutex);
4641
4642         return ret;
4643 }
4644
4645 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4646                         i915_drop_caches_get, i915_drop_caches_set,
4647                         "0x%08llx\n");
4648
4649 static int
4650 i915_max_freq_get(void *data, u64 *val)
4651 {
4652         struct drm_device *dev = data;
4653         struct drm_i915_private *dev_priv = dev->dev_private;
4654         int ret;
4655
4656         if (INTEL_INFO(dev)->gen < 6)
4657                 return -ENODEV;
4658
4659         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4660
4661         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4662         if (ret)
4663                 return ret;
4664
4665         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4666         mutex_unlock(&dev_priv->rps.hw_lock);
4667
4668         return 0;
4669 }
4670
4671 static int
4672 i915_max_freq_set(void *data, u64 val)
4673 {
4674         struct drm_device *dev = data;
4675         struct drm_i915_private *dev_priv = dev->dev_private;
4676         u32 hw_max, hw_min;
4677         int ret;
4678
4679         if (INTEL_INFO(dev)->gen < 6)
4680                 return -ENODEV;
4681
4682         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4683
4684         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4685
4686         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4687         if (ret)
4688                 return ret;
4689
4690         /*
4691          * Turbo will still be enabled, but won't go above the set value.
4692          */
4693         val = intel_freq_opcode(dev_priv, val);
4694
4695         hw_max = dev_priv->rps.max_freq;
4696         hw_min = dev_priv->rps.min_freq;
4697
4698         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4699                 mutex_unlock(&dev_priv->rps.hw_lock);
4700                 return -EINVAL;
4701         }
4702
4703         dev_priv->rps.max_freq_softlimit = val;
4704
4705         intel_set_rps(dev, val);
4706
4707         mutex_unlock(&dev_priv->rps.hw_lock);
4708
4709         return 0;
4710 }
4711
4712 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4713                         i915_max_freq_get, i915_max_freq_set,
4714                         "%llu\n");
4715
4716 static int
4717 i915_min_freq_get(void *data, u64 *val)
4718 {
4719         struct drm_device *dev = data;
4720         struct drm_i915_private *dev_priv = dev->dev_private;
4721         int ret;
4722
4723         if (INTEL_INFO(dev)->gen < 6)
4724                 return -ENODEV;
4725
4726         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4727
4728         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4729         if (ret)
4730                 return ret;
4731
4732         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4733         mutex_unlock(&dev_priv->rps.hw_lock);
4734
4735         return 0;
4736 }
4737
4738 static int
4739 i915_min_freq_set(void *data, u64 val)
4740 {
4741         struct drm_device *dev = data;
4742         struct drm_i915_private *dev_priv = dev->dev_private;
4743         u32 hw_max, hw_min;
4744         int ret;
4745
4746         if (INTEL_INFO(dev)->gen < 6)
4747                 return -ENODEV;
4748
4749         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4750
4751         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4752
4753         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4754         if (ret)
4755                 return ret;
4756
4757         /*
4758          * Turbo will still be enabled, but won't go below the set value.
4759          */
4760         val = intel_freq_opcode(dev_priv, val);
4761
4762         hw_max = dev_priv->rps.max_freq;
4763         hw_min = dev_priv->rps.min_freq;
4764
4765         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4766                 mutex_unlock(&dev_priv->rps.hw_lock);
4767                 return -EINVAL;
4768         }
4769
4770         dev_priv->rps.min_freq_softlimit = val;
4771
4772         intel_set_rps(dev, val);
4773
4774         mutex_unlock(&dev_priv->rps.hw_lock);
4775
4776         return 0;
4777 }
4778
4779 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4780                         i915_min_freq_get, i915_min_freq_set,
4781                         "%llu\n");
4782
4783 static int
4784 i915_cache_sharing_get(void *data, u64 *val)
4785 {
4786         struct drm_device *dev = data;
4787         struct drm_i915_private *dev_priv = dev->dev_private;
4788         u32 snpcr;
4789         int ret;
4790
4791         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4792                 return -ENODEV;
4793
4794         ret = mutex_lock_interruptible(&dev->struct_mutex);
4795         if (ret)
4796                 return ret;
4797         intel_runtime_pm_get(dev_priv);
4798
4799         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4800
4801         intel_runtime_pm_put(dev_priv);
4802         mutex_unlock(&dev_priv->dev->struct_mutex);
4803
4804         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4805
4806         return 0;
4807 }
4808
4809 static int
4810 i915_cache_sharing_set(void *data, u64 val)
4811 {
4812         struct drm_device *dev = data;
4813         struct drm_i915_private *dev_priv = dev->dev_private;
4814         u32 snpcr;
4815
4816         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4817                 return -ENODEV;
4818
4819         if (val > 3)
4820                 return -EINVAL;
4821
4822         intel_runtime_pm_get(dev_priv);
4823         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4824
4825         /* Update the cache sharing policy here as well */
4826         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4827         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4828         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4829         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4830
4831         intel_runtime_pm_put(dev_priv);
4832         return 0;
4833 }
4834
4835 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4836                         i915_cache_sharing_get, i915_cache_sharing_set,
4837                         "%llu\n");
4838
4839 struct sseu_dev_status {
4840         unsigned int slice_total;
4841         unsigned int subslice_total;
4842         unsigned int subslice_per_slice;
4843         unsigned int eu_total;
4844         unsigned int eu_per_subslice;
4845 };
4846
4847 static void cherryview_sseu_device_status(struct drm_device *dev,
4848                                           struct sseu_dev_status *stat)
4849 {
4850         struct drm_i915_private *dev_priv = dev->dev_private;
4851         const int ss_max = 2;
4852         int ss;
4853         u32 sig1[ss_max], sig2[ss_max];
4854
4855         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4856         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4857         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4858         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4859
4860         for (ss = 0; ss < ss_max; ss++) {
4861                 unsigned int eu_cnt;
4862
4863                 if (sig1[ss] & CHV_SS_PG_ENABLE)
4864                         /* skip disabled subslice */
4865                         continue;
4866
4867                 stat->slice_total = 1;
4868                 stat->subslice_per_slice++;
4869                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4870                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4871                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4872                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4873                 stat->eu_total += eu_cnt;
4874                 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
4875         }
4876         stat->subslice_total = stat->subslice_per_slice;
4877 }
4878
4879 static void gen9_sseu_device_status(struct drm_device *dev,
4880                                     struct sseu_dev_status *stat)
4881 {
4882         struct drm_i915_private *dev_priv = dev->dev_private;
4883         int s_max = 3, ss_max = 4;
4884         int s, ss;
4885         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4886
4887         /* BXT has a single slice and at most 3 subslices. */
4888         if (IS_BROXTON(dev)) {
4889                 s_max = 1;
4890                 ss_max = 3;
4891         }
4892
4893         for (s = 0; s < s_max; s++) {
4894                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4895                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4896                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4897         }
4898
4899         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4900                      GEN9_PGCTL_SSA_EU19_ACK |
4901                      GEN9_PGCTL_SSA_EU210_ACK |
4902                      GEN9_PGCTL_SSA_EU311_ACK;
4903         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4904                      GEN9_PGCTL_SSB_EU19_ACK |
4905                      GEN9_PGCTL_SSB_EU210_ACK |
4906                      GEN9_PGCTL_SSB_EU311_ACK;
4907
4908         for (s = 0; s < s_max; s++) {
4909                 unsigned int ss_cnt = 0;
4910
4911                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4912                         /* skip disabled slice */
4913                         continue;
4914
4915                 stat->slice_total++;
4916
4917                 if (IS_SKYLAKE(dev))
4918                         ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
4919
4920                 for (ss = 0; ss < ss_max; ss++) {
4921                         unsigned int eu_cnt;
4922
4923                         if (IS_BROXTON(dev) &&
4924                             !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4925                                 /* skip disabled subslice */
4926                                 continue;
4927
4928                         if (IS_BROXTON(dev))
4929                                 ss_cnt++;
4930
4931                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4932                                                eu_mask[ss%2]);
4933                         stat->eu_total += eu_cnt;
4934                         stat->eu_per_subslice = max(stat->eu_per_subslice,
4935                                                     eu_cnt);
4936                 }
4937
4938                 stat->subslice_total += ss_cnt;
4939                 stat->subslice_per_slice = max(stat->subslice_per_slice,
4940                                                ss_cnt);
4941         }
4942 }
4943
4944 static int i915_sseu_status(struct seq_file *m, void *unused)
4945 {
4946         struct drm_info_node *node = (struct drm_info_node *) m->private;
4947         struct drm_device *dev = node->minor->dev;
4948         struct sseu_dev_status stat;
4949
4950         if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
4951                 return -ENODEV;
4952
4953         seq_puts(m, "SSEU Device Info\n");
4954         seq_printf(m, "  Available Slice Total: %u\n",
4955                    INTEL_INFO(dev)->slice_total);
4956         seq_printf(m, "  Available Subslice Total: %u\n",
4957                    INTEL_INFO(dev)->subslice_total);
4958         seq_printf(m, "  Available Subslice Per Slice: %u\n",
4959                    INTEL_INFO(dev)->subslice_per_slice);
4960         seq_printf(m, "  Available EU Total: %u\n",
4961                    INTEL_INFO(dev)->eu_total);
4962         seq_printf(m, "  Available EU Per Subslice: %u\n",
4963                    INTEL_INFO(dev)->eu_per_subslice);
4964         seq_printf(m, "  Has Slice Power Gating: %s\n",
4965                    yesno(INTEL_INFO(dev)->has_slice_pg));
4966         seq_printf(m, "  Has Subslice Power Gating: %s\n",
4967                    yesno(INTEL_INFO(dev)->has_subslice_pg));
4968         seq_printf(m, "  Has EU Power Gating: %s\n",
4969                    yesno(INTEL_INFO(dev)->has_eu_pg));
4970
4971         seq_puts(m, "SSEU Device Status\n");
4972         memset(&stat, 0, sizeof(stat));
4973         if (IS_CHERRYVIEW(dev)) {
4974                 cherryview_sseu_device_status(dev, &stat);
4975         } else if (INTEL_INFO(dev)->gen >= 9) {
4976                 gen9_sseu_device_status(dev, &stat);
4977         }
4978         seq_printf(m, "  Enabled Slice Total: %u\n",
4979                    stat.slice_total);
4980         seq_printf(m, "  Enabled Subslice Total: %u\n",
4981                    stat.subslice_total);
4982         seq_printf(m, "  Enabled Subslice Per Slice: %u\n",
4983                    stat.subslice_per_slice);
4984         seq_printf(m, "  Enabled EU Total: %u\n",
4985                    stat.eu_total);
4986         seq_printf(m, "  Enabled EU Per Subslice: %u\n",
4987                    stat.eu_per_subslice);
4988
4989         return 0;
4990 }
4991
4992 static int i915_forcewake_open(struct inode *inode, struct file *file)
4993 {
4994         struct drm_device *dev = inode->i_private;
4995         struct drm_i915_private *dev_priv = dev->dev_private;
4996
4997         if (INTEL_INFO(dev)->gen < 6)
4998                 return 0;
4999
5000         intel_runtime_pm_get(dev_priv);
5001         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5002
5003         return 0;
5004 }
5005
5006 static int i915_forcewake_release(struct inode *inode, struct file *file)
5007 {
5008         struct drm_device *dev = inode->i_private;
5009         struct drm_i915_private *dev_priv = dev->dev_private;
5010
5011         if (INTEL_INFO(dev)->gen < 6)
5012                 return 0;
5013
5014         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5015         intel_runtime_pm_put(dev_priv);
5016
5017         return 0;
5018 }
5019
5020 static const struct file_operations i915_forcewake_fops = {
5021         .owner = THIS_MODULE,
5022         .open = i915_forcewake_open,
5023         .release = i915_forcewake_release,
5024 };
5025
5026 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5027 {
5028         struct drm_device *dev = minor->dev;
5029         struct dentry *ent;
5030
5031         ent = debugfs_create_file("i915_forcewake_user",
5032                                   S_IRUSR,
5033                                   root, dev,
5034                                   &i915_forcewake_fops);
5035         if (!ent)
5036                 return -ENOMEM;
5037
5038         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5039 }
5040
5041 static int i915_debugfs_create(struct dentry *root,
5042                                struct drm_minor *minor,
5043                                const char *name,
5044                                const struct file_operations *fops)
5045 {
5046         struct drm_device *dev = minor->dev;
5047         struct dentry *ent;
5048
5049         ent = debugfs_create_file(name,
5050                                   S_IRUGO | S_IWUSR,
5051                                   root, dev,
5052                                   fops);
5053         if (!ent)
5054                 return -ENOMEM;
5055
5056         return drm_add_fake_info_node(minor, ent, fops);
5057 }
5058
5059 static const struct drm_info_list i915_debugfs_list[] = {
5060         {"i915_capabilities", i915_capabilities, 0},
5061         {"i915_gem_objects", i915_gem_object_info, 0},
5062         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5063         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5064         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5065         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5066         {"i915_gem_stolen", i915_gem_stolen_list_info },
5067         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5068         {"i915_gem_request", i915_gem_request_info, 0},
5069         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5070         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5071         {"i915_gem_interrupt", i915_interrupt_info, 0},
5072         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5073         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5074         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5075         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5076         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5077         {"i915_frequency_info", i915_frequency_info, 0},
5078         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5079         {"i915_drpc_info", i915_drpc_info, 0},
5080         {"i915_emon_status", i915_emon_status, 0},
5081         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5082         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5083         {"i915_fbc_status", i915_fbc_status, 0},
5084         {"i915_ips_status", i915_ips_status, 0},
5085         {"i915_sr_status", i915_sr_status, 0},
5086         {"i915_opregion", i915_opregion, 0},
5087         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5088         {"i915_context_status", i915_context_status, 0},
5089         {"i915_dump_lrc", i915_dump_lrc, 0},
5090         {"i915_execlists", i915_execlists, 0},
5091         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5092         {"i915_swizzle_info", i915_swizzle_info, 0},
5093         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5094         {"i915_llc", i915_llc, 0},
5095         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5096         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5097         {"i915_energy_uJ", i915_energy_uJ, 0},
5098         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5099         {"i915_power_domain_info", i915_power_domain_info, 0},
5100         {"i915_display_info", i915_display_info, 0},
5101         {"i915_semaphore_status", i915_semaphore_status, 0},
5102         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5103         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5104         {"i915_wa_registers", i915_wa_registers, 0},
5105         {"i915_ddb_info", i915_ddb_info, 0},
5106         {"i915_sseu_status", i915_sseu_status, 0},
5107         {"i915_drrs_status", i915_drrs_status, 0},
5108         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5109 };
5110 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5111
5112 static const struct i915_debugfs_files {
5113         const char *name;
5114         const struct file_operations *fops;
5115 } i915_debugfs_files[] = {
5116         {"i915_wedged", &i915_wedged_fops},
5117         {"i915_max_freq", &i915_max_freq_fops},
5118         {"i915_min_freq", &i915_min_freq_fops},
5119         {"i915_cache_sharing", &i915_cache_sharing_fops},
5120         {"i915_ring_stop", &i915_ring_stop_fops},
5121         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5122         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5123         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5124         {"i915_error_state", &i915_error_state_fops},
5125         {"i915_next_seqno", &i915_next_seqno_fops},
5126         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5127         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5128         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5129         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5130         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5131         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5132         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5133         {"i915_dp_test_active", &i915_displayport_test_active_fops}
5134 };
5135
5136 void intel_display_crc_init(struct drm_device *dev)
5137 {
5138         struct drm_i915_private *dev_priv = dev->dev_private;
5139         enum pipe pipe;
5140
5141         for_each_pipe(dev_priv, pipe) {
5142                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5143
5144                 pipe_crc->opened = false;
5145                 spin_lock_init(&pipe_crc->lock);
5146                 init_waitqueue_head(&pipe_crc->wq);
5147         }
5148 }
5149
5150 int i915_debugfs_init(struct drm_minor *minor)
5151 {
5152         int ret, i;
5153
5154         ret = i915_forcewake_create(minor->debugfs_root, minor);
5155         if (ret)
5156                 return ret;
5157
5158         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5159                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5160                 if (ret)
5161                         return ret;
5162         }
5163
5164         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5165                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5166                                           i915_debugfs_files[i].name,
5167                                           i915_debugfs_files[i].fops);
5168                 if (ret)
5169                         return ret;
5170         }
5171
5172         return drm_debugfs_create_files(i915_debugfs_list,
5173                                         I915_DEBUGFS_ENTRIES,
5174                                         minor->debugfs_root, minor);
5175 }
5176
5177 void i915_debugfs_cleanup(struct drm_minor *minor)
5178 {
5179         int i;
5180
5181         drm_debugfs_remove_files(i915_debugfs_list,
5182                                  I915_DEBUGFS_ENTRIES, minor);
5183
5184         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5185                                  1, minor);
5186
5187         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5188                 struct drm_info_list *info_list =
5189                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5190
5191                 drm_debugfs_remove_files(info_list, 1, minor);
5192         }
5193
5194         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5195                 struct drm_info_list *info_list =
5196                         (struct drm_info_list *) i915_debugfs_files[i].fops;
5197
5198                 drm_debugfs_remove_files(info_list, 1, minor);
5199         }
5200 }
5201
5202 struct dpcd_block {
5203         /* DPCD dump start address. */
5204         unsigned int offset;
5205         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5206         unsigned int end;
5207         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5208         size_t size;
5209         /* Only valid for eDP. */
5210         bool edp;
5211 };
5212
5213 static const struct dpcd_block i915_dpcd_debug[] = {
5214         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5215         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5216         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5217         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5218         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5219         { .offset = DP_SET_POWER },
5220         { .offset = DP_EDP_DPCD_REV },
5221         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5222         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5223         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5224 };
5225
5226 static int i915_dpcd_show(struct seq_file *m, void *data)
5227 {
5228         struct drm_connector *connector = m->private;
5229         struct intel_dp *intel_dp =
5230                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5231         uint8_t buf[16];
5232         ssize_t err;
5233         int i;
5234
5235         if (connector->status != connector_status_connected)
5236                 return -ENODEV;
5237
5238         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5239                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5240                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5241
5242                 if (b->edp &&
5243                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5244                         continue;
5245
5246                 /* low tech for now */
5247                 if (WARN_ON(size > sizeof(buf)))
5248                         continue;
5249
5250                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5251                 if (err <= 0) {
5252                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5253                                   size, b->offset, err);
5254                         continue;
5255                 }
5256
5257                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5258         }
5259
5260         return 0;
5261 }
5262
5263 static int i915_dpcd_open(struct inode *inode, struct file *file)
5264 {
5265         return single_open(file, i915_dpcd_show, inode->i_private);
5266 }
5267
5268 static const struct file_operations i915_dpcd_fops = {
5269         .owner = THIS_MODULE,
5270         .open = i915_dpcd_open,
5271         .read = seq_read,
5272         .llseek = seq_lseek,
5273         .release = single_release,
5274 };
5275
5276 /**
5277  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5278  * @connector: pointer to a registered drm_connector
5279  *
5280  * Cleanup will be done by drm_connector_unregister() through a call to
5281  * drm_debugfs_connector_remove().
5282  *
5283  * Returns 0 on success, negative error codes on error.
5284  */
5285 int i915_debugfs_connector_add(struct drm_connector *connector)
5286 {
5287         struct dentry *root = connector->debugfs_entry;
5288
5289         /* The connector must have been registered beforehands. */
5290         if (!root)
5291                 return -ENODEV;
5292
5293         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5294             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5295                 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5296                                     &i915_dpcd_fops);
5297
5298         return 0;
5299 }