2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 static const char *yesno(int v)
51 return v ? "yes" : "no";
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
57 drm_add_fake_info_node(struct drm_minor *minor,
61 struct drm_info_node *node;
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
71 node->info_ent = (void *) key;
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
80 static int i915_capabilities(struct seq_file *m, void *data)
82 struct drm_info_node *node = m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
86 seq_printf(m, "gen: %d\n", info->gen);
87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
99 if (obj->user_pin_count > 0)
101 else if (i915_gem_obj_is_pinned(obj))
107 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
109 switch (obj->tiling_mode) {
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
117 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
119 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
123 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
125 struct i915_vma *vma;
128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
131 get_tiling_flag(obj),
132 get_global_flag(obj),
133 obj->base.size / 1024,
134 obj->base.read_domains,
135 obj->base.write_domain,
136 obj->last_read_seqno,
137 obj->last_write_seqno,
138 obj->last_fenced_seqno,
139 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
143 seq_printf(m, " (name: %d)", obj->base.name);
144 list_for_each_entry(vma, &obj->vma_list, vma_link)
145 if (vma->pin_count > 0)
147 seq_printf(m, " (pinned x %d)", pin_count);
148 if (obj->pin_display)
149 seq_printf(m, " (display)");
150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
157 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
158 vma->node.start, vma->node.size);
161 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
162 if (obj->pin_mappable || obj->fault_mappable) {
164 if (obj->pin_mappable)
166 if (obj->fault_mappable)
169 seq_printf(m, " (%s mappable)", s);
171 if (obj->ring != NULL)
172 seq_printf(m, " (%s)", obj->ring->name);
173 if (obj->frontbuffer_bits)
174 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
177 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
179 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
180 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
184 static int i915_gem_object_list_info(struct seq_file *m, void *data)
186 struct drm_info_node *node = m->private;
187 uintptr_t list = (uintptr_t) node->info_ent->data;
188 struct list_head *head;
189 struct drm_device *dev = node->minor->dev;
190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct i915_address_space *vm = &dev_priv->gtt.base;
192 struct i915_vma *vma;
193 size_t total_obj_size, total_gtt_size;
196 ret = mutex_lock_interruptible(&dev->struct_mutex);
200 /* FIXME: the user of this interface might want more than just GGTT */
203 seq_puts(m, "Active:\n");
204 head = &vm->active_list;
207 seq_puts(m, "Inactive:\n");
208 head = &vm->inactive_list;
211 mutex_unlock(&dev->struct_mutex);
215 total_obj_size = total_gtt_size = count = 0;
216 list_for_each_entry(vma, head, mm_list) {
218 describe_obj(m, vma->obj);
220 total_obj_size += vma->obj->base.size;
221 total_gtt_size += vma->node.size;
224 mutex_unlock(&dev->struct_mutex);
226 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
227 count, total_obj_size, total_gtt_size);
231 static int obj_rank_by_stolen(void *priv,
232 struct list_head *A, struct list_head *B)
234 struct drm_i915_gem_object *a =
235 container_of(A, struct drm_i915_gem_object, obj_exec_link);
236 struct drm_i915_gem_object *b =
237 container_of(B, struct drm_i915_gem_object, obj_exec_link);
239 return a->stolen->start - b->stolen->start;
242 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
244 struct drm_info_node *node = m->private;
245 struct drm_device *dev = node->minor->dev;
246 struct drm_i915_private *dev_priv = dev->dev_private;
247 struct drm_i915_gem_object *obj;
248 size_t total_obj_size, total_gtt_size;
252 ret = mutex_lock_interruptible(&dev->struct_mutex);
256 total_obj_size = total_gtt_size = count = 0;
257 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
258 if (obj->stolen == NULL)
261 list_add(&obj->obj_exec_link, &stolen);
263 total_obj_size += obj->base.size;
264 total_gtt_size += i915_gem_obj_ggtt_size(obj);
267 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
268 if (obj->stolen == NULL)
271 list_add(&obj->obj_exec_link, &stolen);
273 total_obj_size += obj->base.size;
276 list_sort(NULL, &stolen, obj_rank_by_stolen);
277 seq_puts(m, "Stolen:\n");
278 while (!list_empty(&stolen)) {
279 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
281 describe_obj(m, obj);
283 list_del_init(&obj->obj_exec_link);
285 mutex_unlock(&dev->struct_mutex);
287 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
288 count, total_obj_size, total_gtt_size);
292 #define count_objects(list, member) do { \
293 list_for_each_entry(obj, list, member) { \
294 size += i915_gem_obj_ggtt_size(obj); \
296 if (obj->map_and_fenceable) { \
297 mappable_size += i915_gem_obj_ggtt_size(obj); \
304 struct drm_i915_file_private *file_priv;
306 size_t total, unbound;
307 size_t global, shared;
308 size_t active, inactive;
311 static int per_file_stats(int id, void *ptr, void *data)
313 struct drm_i915_gem_object *obj = ptr;
314 struct file_stats *stats = data;
315 struct i915_vma *vma;
318 stats->total += obj->base.size;
320 if (obj->base.name || obj->base.dma_buf)
321 stats->shared += obj->base.size;
323 if (USES_FULL_PPGTT(obj->base.dev)) {
324 list_for_each_entry(vma, &obj->vma_list, vma_link) {
325 struct i915_hw_ppgtt *ppgtt;
327 if (!drm_mm_node_allocated(&vma->node))
330 if (i915_is_ggtt(vma->vm)) {
331 stats->global += obj->base.size;
335 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
336 if (ppgtt->file_priv != stats->file_priv)
339 if (obj->ring) /* XXX per-vma statistic */
340 stats->active += obj->base.size;
342 stats->inactive += obj->base.size;
347 if (i915_gem_obj_ggtt_bound(obj)) {
348 stats->global += obj->base.size;
350 stats->active += obj->base.size;
352 stats->inactive += obj->base.size;
357 if (!list_empty(&obj->global_list))
358 stats->unbound += obj->base.size;
363 #define count_vmas(list, member) do { \
364 list_for_each_entry(vma, list, member) { \
365 size += i915_gem_obj_ggtt_size(vma->obj); \
367 if (vma->obj->map_and_fenceable) { \
368 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
374 static int i915_gem_object_info(struct seq_file *m, void* data)
376 struct drm_info_node *node = m->private;
377 struct drm_device *dev = node->minor->dev;
378 struct drm_i915_private *dev_priv = dev->dev_private;
379 u32 count, mappable_count, purgeable_count;
380 size_t size, mappable_size, purgeable_size;
381 struct drm_i915_gem_object *obj;
382 struct i915_address_space *vm = &dev_priv->gtt.base;
383 struct drm_file *file;
384 struct i915_vma *vma;
387 ret = mutex_lock_interruptible(&dev->struct_mutex);
391 seq_printf(m, "%u objects, %zu bytes\n",
392 dev_priv->mm.object_count,
393 dev_priv->mm.object_memory);
395 size = count = mappable_size = mappable_count = 0;
396 count_objects(&dev_priv->mm.bound_list, global_list);
397 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
398 count, mappable_count, size, mappable_size);
400 size = count = mappable_size = mappable_count = 0;
401 count_vmas(&vm->active_list, mm_list);
402 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
403 count, mappable_count, size, mappable_size);
405 size = count = mappable_size = mappable_count = 0;
406 count_vmas(&vm->inactive_list, mm_list);
407 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
408 count, mappable_count, size, mappable_size);
410 size = count = purgeable_size = purgeable_count = 0;
411 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
412 size += obj->base.size, ++count;
413 if (obj->madv == I915_MADV_DONTNEED)
414 purgeable_size += obj->base.size, ++purgeable_count;
416 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
418 size = count = mappable_size = mappable_count = 0;
419 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
420 if (obj->fault_mappable) {
421 size += i915_gem_obj_ggtt_size(obj);
424 if (obj->pin_mappable) {
425 mappable_size += i915_gem_obj_ggtt_size(obj);
428 if (obj->madv == I915_MADV_DONTNEED) {
429 purgeable_size += obj->base.size;
433 seq_printf(m, "%u purgeable objects, %zu bytes\n",
434 purgeable_count, purgeable_size);
435 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
436 mappable_count, mappable_size);
437 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
440 seq_printf(m, "%zu [%lu] gtt total\n",
441 dev_priv->gtt.base.total,
442 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
445 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
446 struct file_stats stats;
447 struct task_struct *task;
449 memset(&stats, 0, sizeof(stats));
450 stats.file_priv = file->driver_priv;
451 spin_lock(&file->table_lock);
452 idr_for_each(&file->object_idr, per_file_stats, &stats);
453 spin_unlock(&file->table_lock);
455 * Although we have a valid reference on file->pid, that does
456 * not guarantee that the task_struct who called get_pid() is
457 * still alive (e.g. get_pid(current) => fork() => exit()).
458 * Therefore, we need to protect this ->comm access using RCU.
461 task = pid_task(file->pid, PIDTYPE_PID);
462 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
463 task ? task->comm : "<unknown>",
474 mutex_unlock(&dev->struct_mutex);
479 static int i915_gem_gtt_info(struct seq_file *m, void *data)
481 struct drm_info_node *node = m->private;
482 struct drm_device *dev = node->minor->dev;
483 uintptr_t list = (uintptr_t) node->info_ent->data;
484 struct drm_i915_private *dev_priv = dev->dev_private;
485 struct drm_i915_gem_object *obj;
486 size_t total_obj_size, total_gtt_size;
489 ret = mutex_lock_interruptible(&dev->struct_mutex);
493 total_obj_size = total_gtt_size = count = 0;
494 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
495 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
499 describe_obj(m, obj);
501 total_obj_size += obj->base.size;
502 total_gtt_size += i915_gem_obj_ggtt_size(obj);
506 mutex_unlock(&dev->struct_mutex);
508 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
509 count, total_obj_size, total_gtt_size);
514 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
516 struct drm_info_node *node = m->private;
517 struct drm_device *dev = node->minor->dev;
518 struct drm_i915_private *dev_priv = dev->dev_private;
519 struct intel_crtc *crtc;
522 ret = mutex_lock_interruptible(&dev->struct_mutex);
526 for_each_intel_crtc(dev, crtc) {
527 const char pipe = pipe_name(crtc->pipe);
528 const char plane = plane_name(crtc->plane);
529 struct intel_unpin_work *work;
531 spin_lock_irq(&dev->event_lock);
532 work = crtc->unpin_work;
534 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
539 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
540 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
543 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
546 if (work->flip_queued_ring) {
547 seq_printf(m, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n",
548 work->flip_queued_ring->name,
549 work->flip_queued_seqno,
550 dev_priv->next_seqno,
551 work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
552 i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
553 work->flip_queued_seqno));
555 seq_printf(m, "Flip not associated with any ring\n");
556 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
557 work->flip_queued_vblank,
558 work->flip_ready_vblank,
559 drm_vblank_count(dev, crtc->pipe));
560 if (work->enable_stall_check)
561 seq_puts(m, "Stall check enabled, ");
563 seq_puts(m, "Stall check waiting for page flip ioctl, ");
564 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
566 if (INTEL_INFO(dev)->gen >= 4)
567 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
569 addr = I915_READ(DSPADDR(crtc->plane));
570 seq_printf(m, "Current scanout address 0x%08x\n", addr);
572 if (work->pending_flip_obj) {
573 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
574 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
577 spin_unlock_irq(&dev->event_lock);
580 mutex_unlock(&dev->struct_mutex);
585 static int i915_gem_request_info(struct seq_file *m, void *data)
587 struct drm_info_node *node = m->private;
588 struct drm_device *dev = node->minor->dev;
589 struct drm_i915_private *dev_priv = dev->dev_private;
590 struct intel_engine_cs *ring;
591 struct drm_i915_gem_request *gem_request;
594 ret = mutex_lock_interruptible(&dev->struct_mutex);
599 for_each_ring(ring, dev_priv, i) {
600 if (list_empty(&ring->request_list))
603 seq_printf(m, "%s requests:\n", ring->name);
604 list_for_each_entry(gem_request,
607 seq_printf(m, " %d @ %d\n",
609 (int) (jiffies - gem_request->emitted_jiffies));
613 mutex_unlock(&dev->struct_mutex);
616 seq_puts(m, "No requests\n");
621 static void i915_ring_seqno_info(struct seq_file *m,
622 struct intel_engine_cs *ring)
624 if (ring->get_seqno) {
625 seq_printf(m, "Current sequence (%s): %u\n",
626 ring->name, ring->get_seqno(ring, false));
630 static int i915_gem_seqno_info(struct seq_file *m, void *data)
632 struct drm_info_node *node = m->private;
633 struct drm_device *dev = node->minor->dev;
634 struct drm_i915_private *dev_priv = dev->dev_private;
635 struct intel_engine_cs *ring;
638 ret = mutex_lock_interruptible(&dev->struct_mutex);
641 intel_runtime_pm_get(dev_priv);
643 for_each_ring(ring, dev_priv, i)
644 i915_ring_seqno_info(m, ring);
646 intel_runtime_pm_put(dev_priv);
647 mutex_unlock(&dev->struct_mutex);
653 static int i915_interrupt_info(struct seq_file *m, void *data)
655 struct drm_info_node *node = m->private;
656 struct drm_device *dev = node->minor->dev;
657 struct drm_i915_private *dev_priv = dev->dev_private;
658 struct intel_engine_cs *ring;
661 ret = mutex_lock_interruptible(&dev->struct_mutex);
664 intel_runtime_pm_get(dev_priv);
666 if (IS_CHERRYVIEW(dev)) {
667 seq_printf(m, "Master Interrupt Control:\t%08x\n",
668 I915_READ(GEN8_MASTER_IRQ));
670 seq_printf(m, "Display IER:\t%08x\n",
672 seq_printf(m, "Display IIR:\t%08x\n",
674 seq_printf(m, "Display IIR_RW:\t%08x\n",
675 I915_READ(VLV_IIR_RW));
676 seq_printf(m, "Display IMR:\t%08x\n",
678 for_each_pipe(dev_priv, pipe)
679 seq_printf(m, "Pipe %c stat:\t%08x\n",
681 I915_READ(PIPESTAT(pipe)));
683 seq_printf(m, "Port hotplug:\t%08x\n",
684 I915_READ(PORT_HOTPLUG_EN));
685 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
686 I915_READ(VLV_DPFLIPSTAT));
687 seq_printf(m, "DPINVGTT:\t%08x\n",
688 I915_READ(DPINVGTT));
690 for (i = 0; i < 4; i++) {
691 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
692 i, I915_READ(GEN8_GT_IMR(i)));
693 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
694 i, I915_READ(GEN8_GT_IIR(i)));
695 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
696 i, I915_READ(GEN8_GT_IER(i)));
699 seq_printf(m, "PCU interrupt mask:\t%08x\n",
700 I915_READ(GEN8_PCU_IMR));
701 seq_printf(m, "PCU interrupt identity:\t%08x\n",
702 I915_READ(GEN8_PCU_IIR));
703 seq_printf(m, "PCU interrupt enable:\t%08x\n",
704 I915_READ(GEN8_PCU_IER));
705 } else if (INTEL_INFO(dev)->gen >= 8) {
706 seq_printf(m, "Master Interrupt Control:\t%08x\n",
707 I915_READ(GEN8_MASTER_IRQ));
709 for (i = 0; i < 4; i++) {
710 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
711 i, I915_READ(GEN8_GT_IMR(i)));
712 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
713 i, I915_READ(GEN8_GT_IIR(i)));
714 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
715 i, I915_READ(GEN8_GT_IER(i)));
718 for_each_pipe(dev_priv, pipe) {
719 if (!intel_display_power_is_enabled(dev_priv,
720 POWER_DOMAIN_PIPE(pipe))) {
721 seq_printf(m, "Pipe %c power disabled\n",
725 seq_printf(m, "Pipe %c IMR:\t%08x\n",
727 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
728 seq_printf(m, "Pipe %c IIR:\t%08x\n",
730 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
731 seq_printf(m, "Pipe %c IER:\t%08x\n",
733 I915_READ(GEN8_DE_PIPE_IER(pipe)));
736 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
737 I915_READ(GEN8_DE_PORT_IMR));
738 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
739 I915_READ(GEN8_DE_PORT_IIR));
740 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
741 I915_READ(GEN8_DE_PORT_IER));
743 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
744 I915_READ(GEN8_DE_MISC_IMR));
745 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
746 I915_READ(GEN8_DE_MISC_IIR));
747 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
748 I915_READ(GEN8_DE_MISC_IER));
750 seq_printf(m, "PCU interrupt mask:\t%08x\n",
751 I915_READ(GEN8_PCU_IMR));
752 seq_printf(m, "PCU interrupt identity:\t%08x\n",
753 I915_READ(GEN8_PCU_IIR));
754 seq_printf(m, "PCU interrupt enable:\t%08x\n",
755 I915_READ(GEN8_PCU_IER));
756 } else if (IS_VALLEYVIEW(dev)) {
757 seq_printf(m, "Display IER:\t%08x\n",
759 seq_printf(m, "Display IIR:\t%08x\n",
761 seq_printf(m, "Display IIR_RW:\t%08x\n",
762 I915_READ(VLV_IIR_RW));
763 seq_printf(m, "Display IMR:\t%08x\n",
765 for_each_pipe(dev_priv, pipe)
766 seq_printf(m, "Pipe %c stat:\t%08x\n",
768 I915_READ(PIPESTAT(pipe)));
770 seq_printf(m, "Master IER:\t%08x\n",
771 I915_READ(VLV_MASTER_IER));
773 seq_printf(m, "Render IER:\t%08x\n",
775 seq_printf(m, "Render IIR:\t%08x\n",
777 seq_printf(m, "Render IMR:\t%08x\n",
780 seq_printf(m, "PM IER:\t\t%08x\n",
781 I915_READ(GEN6_PMIER));
782 seq_printf(m, "PM IIR:\t\t%08x\n",
783 I915_READ(GEN6_PMIIR));
784 seq_printf(m, "PM IMR:\t\t%08x\n",
785 I915_READ(GEN6_PMIMR));
787 seq_printf(m, "Port hotplug:\t%08x\n",
788 I915_READ(PORT_HOTPLUG_EN));
789 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
790 I915_READ(VLV_DPFLIPSTAT));
791 seq_printf(m, "DPINVGTT:\t%08x\n",
792 I915_READ(DPINVGTT));
794 } else if (!HAS_PCH_SPLIT(dev)) {
795 seq_printf(m, "Interrupt enable: %08x\n",
797 seq_printf(m, "Interrupt identity: %08x\n",
799 seq_printf(m, "Interrupt mask: %08x\n",
801 for_each_pipe(dev_priv, pipe)
802 seq_printf(m, "Pipe %c stat: %08x\n",
804 I915_READ(PIPESTAT(pipe)));
806 seq_printf(m, "North Display Interrupt enable: %08x\n",
808 seq_printf(m, "North Display Interrupt identity: %08x\n",
810 seq_printf(m, "North Display Interrupt mask: %08x\n",
812 seq_printf(m, "South Display Interrupt enable: %08x\n",
814 seq_printf(m, "South Display Interrupt identity: %08x\n",
816 seq_printf(m, "South Display Interrupt mask: %08x\n",
818 seq_printf(m, "Graphics Interrupt enable: %08x\n",
820 seq_printf(m, "Graphics Interrupt identity: %08x\n",
822 seq_printf(m, "Graphics Interrupt mask: %08x\n",
825 for_each_ring(ring, dev_priv, i) {
826 if (INTEL_INFO(dev)->gen >= 6) {
828 "Graphics Interrupt mask (%s): %08x\n",
829 ring->name, I915_READ_IMR(ring));
831 i915_ring_seqno_info(m, ring);
833 intel_runtime_pm_put(dev_priv);
834 mutex_unlock(&dev->struct_mutex);
839 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
841 struct drm_info_node *node = m->private;
842 struct drm_device *dev = node->minor->dev;
843 struct drm_i915_private *dev_priv = dev->dev_private;
846 ret = mutex_lock_interruptible(&dev->struct_mutex);
850 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
851 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
852 for (i = 0; i < dev_priv->num_fence_regs; i++) {
853 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
855 seq_printf(m, "Fence %d, pin count = %d, object = ",
856 i, dev_priv->fence_regs[i].pin_count);
858 seq_puts(m, "unused");
860 describe_obj(m, obj);
864 mutex_unlock(&dev->struct_mutex);
868 static int i915_hws_info(struct seq_file *m, void *data)
870 struct drm_info_node *node = m->private;
871 struct drm_device *dev = node->minor->dev;
872 struct drm_i915_private *dev_priv = dev->dev_private;
873 struct intel_engine_cs *ring;
877 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
878 hws = ring->status_page.page_addr;
882 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
883 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
885 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
891 i915_error_state_write(struct file *filp,
892 const char __user *ubuf,
896 struct i915_error_state_file_priv *error_priv = filp->private_data;
897 struct drm_device *dev = error_priv->dev;
900 DRM_DEBUG_DRIVER("Resetting error state\n");
902 ret = mutex_lock_interruptible(&dev->struct_mutex);
906 i915_destroy_error_state(dev);
907 mutex_unlock(&dev->struct_mutex);
912 static int i915_error_state_open(struct inode *inode, struct file *file)
914 struct drm_device *dev = inode->i_private;
915 struct i915_error_state_file_priv *error_priv;
917 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
921 error_priv->dev = dev;
923 i915_error_state_get(dev, error_priv);
925 file->private_data = error_priv;
930 static int i915_error_state_release(struct inode *inode, struct file *file)
932 struct i915_error_state_file_priv *error_priv = file->private_data;
934 i915_error_state_put(error_priv);
940 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
941 size_t count, loff_t *pos)
943 struct i915_error_state_file_priv *error_priv = file->private_data;
944 struct drm_i915_error_state_buf error_str;
946 ssize_t ret_count = 0;
949 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
953 ret = i915_error_state_to_str(&error_str, error_priv);
957 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
964 *pos = error_str.start + ret_count;
966 i915_error_state_buf_release(&error_str);
967 return ret ?: ret_count;
970 static const struct file_operations i915_error_state_fops = {
971 .owner = THIS_MODULE,
972 .open = i915_error_state_open,
973 .read = i915_error_state_read,
974 .write = i915_error_state_write,
975 .llseek = default_llseek,
976 .release = i915_error_state_release,
980 i915_next_seqno_get(void *data, u64 *val)
982 struct drm_device *dev = data;
983 struct drm_i915_private *dev_priv = dev->dev_private;
986 ret = mutex_lock_interruptible(&dev->struct_mutex);
990 *val = dev_priv->next_seqno;
991 mutex_unlock(&dev->struct_mutex);
997 i915_next_seqno_set(void *data, u64 val)
999 struct drm_device *dev = data;
1002 ret = mutex_lock_interruptible(&dev->struct_mutex);
1006 ret = i915_gem_set_seqno(dev, val);
1007 mutex_unlock(&dev->struct_mutex);
1012 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1013 i915_next_seqno_get, i915_next_seqno_set,
1016 static int i915_frequency_info(struct seq_file *m, void *unused)
1018 struct drm_info_node *node = m->private;
1019 struct drm_device *dev = node->minor->dev;
1020 struct drm_i915_private *dev_priv = dev->dev_private;
1023 intel_runtime_pm_get(dev_priv);
1025 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1028 u16 rgvswctl = I915_READ16(MEMSWCTL);
1029 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1031 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1032 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1033 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1035 seq_printf(m, "Current P-state: %d\n",
1036 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1037 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1038 IS_BROADWELL(dev)) {
1039 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1040 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1041 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1042 u32 rpmodectl, rpinclimit, rpdeclimit;
1043 u32 rpstat, cagf, reqf;
1044 u32 rpupei, rpcurup, rpprevup;
1045 u32 rpdownei, rpcurdown, rpprevdown;
1046 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1049 /* RPSTAT1 is in the GT power well */
1050 ret = mutex_lock_interruptible(&dev->struct_mutex);
1054 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
1056 reqf = I915_READ(GEN6_RPNSWREQ);
1057 reqf &= ~GEN6_TURBO_DISABLE;
1058 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1062 reqf *= GT_FREQUENCY_MULTIPLIER;
1064 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1065 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1066 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1068 rpstat = I915_READ(GEN6_RPSTAT1);
1069 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1070 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1071 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1072 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1073 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1074 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1075 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1076 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1078 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1079 cagf *= GT_FREQUENCY_MULTIPLIER;
1081 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
1082 mutex_unlock(&dev->struct_mutex);
1084 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1085 pm_ier = I915_READ(GEN6_PMIER);
1086 pm_imr = I915_READ(GEN6_PMIMR);
1087 pm_isr = I915_READ(GEN6_PMISR);
1088 pm_iir = I915_READ(GEN6_PMIIR);
1089 pm_mask = I915_READ(GEN6_PMINTRMSK);
1091 pm_ier = I915_READ(GEN8_GT_IER(2));
1092 pm_imr = I915_READ(GEN8_GT_IMR(2));
1093 pm_isr = I915_READ(GEN8_GT_ISR(2));
1094 pm_iir = I915_READ(GEN8_GT_IIR(2));
1095 pm_mask = I915_READ(GEN6_PMINTRMSK);
1097 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1098 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1099 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1100 seq_printf(m, "Render p-state ratio: %d\n",
1101 (gt_perf_status & 0xff00) >> 8);
1102 seq_printf(m, "Render p-state VID: %d\n",
1103 gt_perf_status & 0xff);
1104 seq_printf(m, "Render p-state limit: %d\n",
1105 rp_state_limits & 0xff);
1106 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1107 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1108 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1109 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1110 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1111 seq_printf(m, "CAGF: %dMHz\n", cagf);
1112 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1113 GEN6_CURICONT_MASK);
1114 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1115 GEN6_CURBSYTAVG_MASK);
1116 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1117 GEN6_CURBSYTAVG_MASK);
1118 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1120 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1121 GEN6_CURBSYTAVG_MASK);
1122 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1123 GEN6_CURBSYTAVG_MASK);
1125 max_freq = (rp_state_cap & 0xff0000) >> 16;
1126 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1127 max_freq * GT_FREQUENCY_MULTIPLIER);
1129 max_freq = (rp_state_cap & 0xff00) >> 8;
1130 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1131 max_freq * GT_FREQUENCY_MULTIPLIER);
1133 max_freq = rp_state_cap & 0xff;
1134 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1135 max_freq * GT_FREQUENCY_MULTIPLIER);
1137 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1138 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
1139 } else if (IS_VALLEYVIEW(dev)) {
1142 mutex_lock(&dev_priv->rps.hw_lock);
1143 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1144 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1145 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1147 seq_printf(m, "max GPU freq: %d MHz\n",
1148 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1150 seq_printf(m, "min GPU freq: %d MHz\n",
1151 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1153 seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
1154 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1156 seq_printf(m, "current GPU freq: %d MHz\n",
1157 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1158 mutex_unlock(&dev_priv->rps.hw_lock);
1160 seq_puts(m, "no P-state info available\n");
1164 intel_runtime_pm_put(dev_priv);
1168 static int ironlake_drpc_info(struct seq_file *m)
1170 struct drm_info_node *node = m->private;
1171 struct drm_device *dev = node->minor->dev;
1172 struct drm_i915_private *dev_priv = dev->dev_private;
1173 u32 rgvmodectl, rstdbyctl;
1177 ret = mutex_lock_interruptible(&dev->struct_mutex);
1180 intel_runtime_pm_get(dev_priv);
1182 rgvmodectl = I915_READ(MEMMODECTL);
1183 rstdbyctl = I915_READ(RSTDBYCTL);
1184 crstandvid = I915_READ16(CRSTANDVID);
1186 intel_runtime_pm_put(dev_priv);
1187 mutex_unlock(&dev->struct_mutex);
1189 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1191 seq_printf(m, "Boost freq: %d\n",
1192 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1193 MEMMODE_BOOST_FREQ_SHIFT);
1194 seq_printf(m, "HW control enabled: %s\n",
1195 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1196 seq_printf(m, "SW control enabled: %s\n",
1197 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1198 seq_printf(m, "Gated voltage change: %s\n",
1199 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1200 seq_printf(m, "Starting frequency: P%d\n",
1201 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1202 seq_printf(m, "Max P-state: P%d\n",
1203 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1204 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1205 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1206 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1207 seq_printf(m, "Render standby enabled: %s\n",
1208 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1209 seq_puts(m, "Current RS state: ");
1210 switch (rstdbyctl & RSX_STATUS_MASK) {
1212 seq_puts(m, "on\n");
1214 case RSX_STATUS_RC1:
1215 seq_puts(m, "RC1\n");
1217 case RSX_STATUS_RC1E:
1218 seq_puts(m, "RC1E\n");
1220 case RSX_STATUS_RS1:
1221 seq_puts(m, "RS1\n");
1223 case RSX_STATUS_RS2:
1224 seq_puts(m, "RS2 (RC6)\n");
1226 case RSX_STATUS_RS3:
1227 seq_puts(m, "RC3 (RC6+)\n");
1230 seq_puts(m, "unknown\n");
1237 static int vlv_drpc_info(struct seq_file *m)
1240 struct drm_info_node *node = m->private;
1241 struct drm_device *dev = node->minor->dev;
1242 struct drm_i915_private *dev_priv = dev->dev_private;
1243 u32 rpmodectl1, rcctl1, pw_status;
1244 unsigned fw_rendercount = 0, fw_mediacount = 0;
1246 intel_runtime_pm_get(dev_priv);
1248 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1249 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1250 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1252 intel_runtime_pm_put(dev_priv);
1254 seq_printf(m, "Video Turbo Mode: %s\n",
1255 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1256 seq_printf(m, "Turbo enabled: %s\n",
1257 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1258 seq_printf(m, "HW control enabled: %s\n",
1259 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1260 seq_printf(m, "SW control enabled: %s\n",
1261 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1262 GEN6_RP_MEDIA_SW_MODE));
1263 seq_printf(m, "RC6 Enabled: %s\n",
1264 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1265 GEN6_RC_CTL_EI_MODE(1))));
1266 seq_printf(m, "Render Power Well: %s\n",
1267 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1268 seq_printf(m, "Media Power Well: %s\n",
1269 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1271 seq_printf(m, "Render RC6 residency since boot: %u\n",
1272 I915_READ(VLV_GT_RENDER_RC6));
1273 seq_printf(m, "Media RC6 residency since boot: %u\n",
1274 I915_READ(VLV_GT_MEDIA_RC6));
1276 spin_lock_irq(&dev_priv->uncore.lock);
1277 fw_rendercount = dev_priv->uncore.fw_rendercount;
1278 fw_mediacount = dev_priv->uncore.fw_mediacount;
1279 spin_unlock_irq(&dev_priv->uncore.lock);
1281 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1282 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1289 static int gen6_drpc_info(struct seq_file *m)
1292 struct drm_info_node *node = m->private;
1293 struct drm_device *dev = node->minor->dev;
1294 struct drm_i915_private *dev_priv = dev->dev_private;
1295 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1296 unsigned forcewake_count;
1299 ret = mutex_lock_interruptible(&dev->struct_mutex);
1302 intel_runtime_pm_get(dev_priv);
1304 spin_lock_irq(&dev_priv->uncore.lock);
1305 forcewake_count = dev_priv->uncore.forcewake_count;
1306 spin_unlock_irq(&dev_priv->uncore.lock);
1308 if (forcewake_count) {
1309 seq_puts(m, "RC information inaccurate because somebody "
1310 "holds a forcewake reference \n");
1312 /* NB: we cannot use forcewake, else we read the wrong values */
1313 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1315 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1318 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1319 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1321 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1322 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1323 mutex_unlock(&dev->struct_mutex);
1324 mutex_lock(&dev_priv->rps.hw_lock);
1325 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1326 mutex_unlock(&dev_priv->rps.hw_lock);
1328 intel_runtime_pm_put(dev_priv);
1330 seq_printf(m, "Video Turbo Mode: %s\n",
1331 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1332 seq_printf(m, "HW control enabled: %s\n",
1333 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1334 seq_printf(m, "SW control enabled: %s\n",
1335 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1336 GEN6_RP_MEDIA_SW_MODE));
1337 seq_printf(m, "RC1e Enabled: %s\n",
1338 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1339 seq_printf(m, "RC6 Enabled: %s\n",
1340 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1341 seq_printf(m, "Deep RC6 Enabled: %s\n",
1342 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1343 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1344 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1345 seq_puts(m, "Current RC state: ");
1346 switch (gt_core_status & GEN6_RCn_MASK) {
1348 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1349 seq_puts(m, "Core Power Down\n");
1351 seq_puts(m, "on\n");
1354 seq_puts(m, "RC3\n");
1357 seq_puts(m, "RC6\n");
1360 seq_puts(m, "RC7\n");
1363 seq_puts(m, "Unknown\n");
1367 seq_printf(m, "Core Power Down: %s\n",
1368 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1370 /* Not exactly sure what this is */
1371 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1372 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1373 seq_printf(m, "RC6 residency since boot: %u\n",
1374 I915_READ(GEN6_GT_GFX_RC6));
1375 seq_printf(m, "RC6+ residency since boot: %u\n",
1376 I915_READ(GEN6_GT_GFX_RC6p));
1377 seq_printf(m, "RC6++ residency since boot: %u\n",
1378 I915_READ(GEN6_GT_GFX_RC6pp));
1380 seq_printf(m, "RC6 voltage: %dmV\n",
1381 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1382 seq_printf(m, "RC6+ voltage: %dmV\n",
1383 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1384 seq_printf(m, "RC6++ voltage: %dmV\n",
1385 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1389 static int i915_drpc_info(struct seq_file *m, void *unused)
1391 struct drm_info_node *node = m->private;
1392 struct drm_device *dev = node->minor->dev;
1394 if (IS_VALLEYVIEW(dev))
1395 return vlv_drpc_info(m);
1396 else if (INTEL_INFO(dev)->gen >= 6)
1397 return gen6_drpc_info(m);
1399 return ironlake_drpc_info(m);
1402 static int i915_fbc_status(struct seq_file *m, void *unused)
1404 struct drm_info_node *node = m->private;
1405 struct drm_device *dev = node->minor->dev;
1406 struct drm_i915_private *dev_priv = dev->dev_private;
1408 if (!HAS_FBC(dev)) {
1409 seq_puts(m, "FBC unsupported on this chipset\n");
1413 intel_runtime_pm_get(dev_priv);
1415 if (intel_fbc_enabled(dev)) {
1416 seq_puts(m, "FBC enabled\n");
1418 seq_puts(m, "FBC disabled: ");
1419 switch (dev_priv->fbc.no_fbc_reason) {
1421 seq_puts(m, "FBC actived, but currently disabled in hardware");
1423 case FBC_UNSUPPORTED:
1424 seq_puts(m, "unsupported by this chipset");
1427 seq_puts(m, "no outputs");
1429 case FBC_STOLEN_TOO_SMALL:
1430 seq_puts(m, "not enough stolen memory");
1432 case FBC_UNSUPPORTED_MODE:
1433 seq_puts(m, "mode not supported");
1435 case FBC_MODE_TOO_LARGE:
1436 seq_puts(m, "mode too large");
1439 seq_puts(m, "FBC unsupported on plane");
1442 seq_puts(m, "scanout buffer not tiled");
1444 case FBC_MULTIPLE_PIPES:
1445 seq_puts(m, "multiple pipes are enabled");
1447 case FBC_MODULE_PARAM:
1448 seq_puts(m, "disabled per module param (default off)");
1450 case FBC_CHIP_DEFAULT:
1451 seq_puts(m, "disabled per chip default");
1454 seq_puts(m, "unknown reason");
1459 intel_runtime_pm_put(dev_priv);
1464 static int i915_fbc_fc_get(void *data, u64 *val)
1466 struct drm_device *dev = data;
1467 struct drm_i915_private *dev_priv = dev->dev_private;
1469 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1472 drm_modeset_lock_all(dev);
1473 *val = dev_priv->fbc.false_color;
1474 drm_modeset_unlock_all(dev);
1479 static int i915_fbc_fc_set(void *data, u64 val)
1481 struct drm_device *dev = data;
1482 struct drm_i915_private *dev_priv = dev->dev_private;
1485 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1488 drm_modeset_lock_all(dev);
1490 reg = I915_READ(ILK_DPFC_CONTROL);
1491 dev_priv->fbc.false_color = val;
1493 I915_WRITE(ILK_DPFC_CONTROL, val ?
1494 (reg | FBC_CTL_FALSE_COLOR) :
1495 (reg & ~FBC_CTL_FALSE_COLOR));
1497 drm_modeset_unlock_all(dev);
1501 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1502 i915_fbc_fc_get, i915_fbc_fc_set,
1505 static int i915_ips_status(struct seq_file *m, void *unused)
1507 struct drm_info_node *node = m->private;
1508 struct drm_device *dev = node->minor->dev;
1509 struct drm_i915_private *dev_priv = dev->dev_private;
1511 if (!HAS_IPS(dev)) {
1512 seq_puts(m, "not supported\n");
1516 intel_runtime_pm_get(dev_priv);
1518 seq_printf(m, "Enabled by kernel parameter: %s\n",
1519 yesno(i915.enable_ips));
1521 if (INTEL_INFO(dev)->gen >= 8) {
1522 seq_puts(m, "Currently: unknown\n");
1524 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1525 seq_puts(m, "Currently: enabled\n");
1527 seq_puts(m, "Currently: disabled\n");
1530 intel_runtime_pm_put(dev_priv);
1535 static int i915_sr_status(struct seq_file *m, void *unused)
1537 struct drm_info_node *node = m->private;
1538 struct drm_device *dev = node->minor->dev;
1539 struct drm_i915_private *dev_priv = dev->dev_private;
1540 bool sr_enabled = false;
1542 intel_runtime_pm_get(dev_priv);
1544 if (HAS_PCH_SPLIT(dev))
1545 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1546 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1547 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1548 else if (IS_I915GM(dev))
1549 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1550 else if (IS_PINEVIEW(dev))
1551 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1553 intel_runtime_pm_put(dev_priv);
1555 seq_printf(m, "self-refresh: %s\n",
1556 sr_enabled ? "enabled" : "disabled");
1561 static int i915_emon_status(struct seq_file *m, void *unused)
1563 struct drm_info_node *node = m->private;
1564 struct drm_device *dev = node->minor->dev;
1565 struct drm_i915_private *dev_priv = dev->dev_private;
1566 unsigned long temp, chipset, gfx;
1572 ret = mutex_lock_interruptible(&dev->struct_mutex);
1576 temp = i915_mch_val(dev_priv);
1577 chipset = i915_chipset_val(dev_priv);
1578 gfx = i915_gfx_val(dev_priv);
1579 mutex_unlock(&dev->struct_mutex);
1581 seq_printf(m, "GMCH temp: %ld\n", temp);
1582 seq_printf(m, "Chipset power: %ld\n", chipset);
1583 seq_printf(m, "GFX power: %ld\n", gfx);
1584 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1589 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1591 struct drm_info_node *node = m->private;
1592 struct drm_device *dev = node->minor->dev;
1593 struct drm_i915_private *dev_priv = dev->dev_private;
1595 int gpu_freq, ia_freq;
1597 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1598 seq_puts(m, "unsupported on this chipset\n");
1602 intel_runtime_pm_get(dev_priv);
1604 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1606 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1610 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1612 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1613 gpu_freq <= dev_priv->rps.max_freq_softlimit;
1616 sandybridge_pcode_read(dev_priv,
1617 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1619 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1620 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1621 ((ia_freq >> 0) & 0xff) * 100,
1622 ((ia_freq >> 8) & 0xff) * 100);
1625 mutex_unlock(&dev_priv->rps.hw_lock);
1628 intel_runtime_pm_put(dev_priv);
1632 static int i915_opregion(struct seq_file *m, void *unused)
1634 struct drm_info_node *node = m->private;
1635 struct drm_device *dev = node->minor->dev;
1636 struct drm_i915_private *dev_priv = dev->dev_private;
1637 struct intel_opregion *opregion = &dev_priv->opregion;
1638 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1644 ret = mutex_lock_interruptible(&dev->struct_mutex);
1648 if (opregion->header) {
1649 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1650 seq_write(m, data, OPREGION_SIZE);
1653 mutex_unlock(&dev->struct_mutex);
1660 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1662 struct drm_info_node *node = m->private;
1663 struct drm_device *dev = node->minor->dev;
1664 struct intel_fbdev *ifbdev = NULL;
1665 struct intel_framebuffer *fb;
1667 #ifdef CONFIG_DRM_I915_FBDEV
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1670 ifbdev = dev_priv->fbdev;
1671 fb = to_intel_framebuffer(ifbdev->helper.fb);
1673 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1677 fb->base.bits_per_pixel,
1678 atomic_read(&fb->base.refcount.refcount));
1679 describe_obj(m, fb->obj);
1683 mutex_lock(&dev->mode_config.fb_lock);
1684 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1685 if (ifbdev && &fb->base == ifbdev->helper.fb)
1688 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1692 fb->base.bits_per_pixel,
1693 atomic_read(&fb->base.refcount.refcount));
1694 describe_obj(m, fb->obj);
1697 mutex_unlock(&dev->mode_config.fb_lock);
1702 static void describe_ctx_ringbuf(struct seq_file *m,
1703 struct intel_ringbuffer *ringbuf)
1705 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1706 ringbuf->space, ringbuf->head, ringbuf->tail,
1707 ringbuf->last_retired_head);
1710 static int i915_context_status(struct seq_file *m, void *unused)
1712 struct drm_info_node *node = m->private;
1713 struct drm_device *dev = node->minor->dev;
1714 struct drm_i915_private *dev_priv = dev->dev_private;
1715 struct intel_engine_cs *ring;
1716 struct intel_context *ctx;
1719 ret = mutex_lock_interruptible(&dev->struct_mutex);
1723 if (dev_priv->ips.pwrctx) {
1724 seq_puts(m, "power context ");
1725 describe_obj(m, dev_priv->ips.pwrctx);
1729 if (dev_priv->ips.renderctx) {
1730 seq_puts(m, "render context ");
1731 describe_obj(m, dev_priv->ips.renderctx);
1735 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1736 if (!i915.enable_execlists &&
1737 ctx->legacy_hw_ctx.rcs_state == NULL)
1740 seq_puts(m, "HW context ");
1741 describe_ctx(m, ctx);
1742 for_each_ring(ring, dev_priv, i) {
1743 if (ring->default_context == ctx)
1744 seq_printf(m, "(default context %s) ",
1748 if (i915.enable_execlists) {
1750 for_each_ring(ring, dev_priv, i) {
1751 struct drm_i915_gem_object *ctx_obj =
1752 ctx->engine[i].state;
1753 struct intel_ringbuffer *ringbuf =
1754 ctx->engine[i].ringbuf;
1756 seq_printf(m, "%s: ", ring->name);
1758 describe_obj(m, ctx_obj);
1760 describe_ctx_ringbuf(m, ringbuf);
1764 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1770 mutex_unlock(&dev->struct_mutex);
1775 static int i915_dump_lrc(struct seq_file *m, void *unused)
1777 struct drm_info_node *node = (struct drm_info_node *) m->private;
1778 struct drm_device *dev = node->minor->dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1780 struct intel_engine_cs *ring;
1781 struct intel_context *ctx;
1784 if (!i915.enable_execlists) {
1785 seq_printf(m, "Logical Ring Contexts are disabled\n");
1789 ret = mutex_lock_interruptible(&dev->struct_mutex);
1793 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1794 for_each_ring(ring, dev_priv, i) {
1795 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state;
1797 if (ring->default_context == ctx)
1802 uint32_t *reg_state;
1805 i915_gem_obj_ggtt_pin(ctx_obj,
1806 GEN8_LR_CONTEXT_ALIGN, 0);
1808 page = i915_gem_object_get_page(ctx_obj, 1);
1809 reg_state = kmap_atomic(page);
1811 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1812 intel_execlists_ctx_id(ctx_obj));
1814 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1815 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1816 i915_gem_obj_ggtt_offset(ctx_obj) + 4096 + (j * 4),
1817 reg_state[j], reg_state[j + 1],
1818 reg_state[j + 2], reg_state[j + 3]);
1820 kunmap_atomic(reg_state);
1822 i915_gem_object_ggtt_unpin(ctx_obj);
1829 mutex_unlock(&dev->struct_mutex);
1834 static int i915_execlists(struct seq_file *m, void *data)
1836 struct drm_info_node *node = (struct drm_info_node *)m->private;
1837 struct drm_device *dev = node->minor->dev;
1838 struct drm_i915_private *dev_priv = dev->dev_private;
1839 struct intel_engine_cs *ring;
1845 struct list_head *cursor;
1849 if (!i915.enable_execlists) {
1850 seq_puts(m, "Logical Ring Contexts are disabled\n");
1854 ret = mutex_lock_interruptible(&dev->struct_mutex);
1858 intel_runtime_pm_get(dev_priv);
1860 for_each_ring(ring, dev_priv, ring_id) {
1861 struct intel_ctx_submit_request *head_req = NULL;
1863 unsigned long flags;
1865 seq_printf(m, "%s\n", ring->name);
1867 status = I915_READ(RING_EXECLIST_STATUS(ring));
1868 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1869 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1872 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
1873 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
1875 read_pointer = ring->next_context_status_buffer;
1876 write_pointer = status_pointer & 0x07;
1877 if (read_pointer > write_pointer)
1879 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1880 read_pointer, write_pointer);
1882 for (i = 0; i < 6; i++) {
1883 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
1884 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
1886 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
1890 spin_lock_irqsave(&ring->execlist_lock, flags);
1891 list_for_each(cursor, &ring->execlist_queue)
1893 head_req = list_first_entry_or_null(&ring->execlist_queue,
1894 struct intel_ctx_submit_request, execlist_link);
1895 spin_unlock_irqrestore(&ring->execlist_lock, flags);
1897 seq_printf(m, "\t%d requests in queue\n", count);
1899 struct drm_i915_gem_object *ctx_obj;
1901 ctx_obj = head_req->ctx->engine[ring_id].state;
1902 seq_printf(m, "\tHead request id: %u\n",
1903 intel_execlists_ctx_id(ctx_obj));
1904 seq_printf(m, "\tHead request tail: %u\n",
1911 intel_runtime_pm_put(dev_priv);
1912 mutex_unlock(&dev->struct_mutex);
1917 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1919 struct drm_info_node *node = m->private;
1920 struct drm_device *dev = node->minor->dev;
1921 struct drm_i915_private *dev_priv = dev->dev_private;
1922 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
1924 spin_lock_irq(&dev_priv->uncore.lock);
1925 if (IS_VALLEYVIEW(dev)) {
1926 fw_rendercount = dev_priv->uncore.fw_rendercount;
1927 fw_mediacount = dev_priv->uncore.fw_mediacount;
1929 forcewake_count = dev_priv->uncore.forcewake_count;
1930 spin_unlock_irq(&dev_priv->uncore.lock);
1932 if (IS_VALLEYVIEW(dev)) {
1933 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1934 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1936 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1941 static const char *swizzle_string(unsigned swizzle)
1944 case I915_BIT_6_SWIZZLE_NONE:
1946 case I915_BIT_6_SWIZZLE_9:
1948 case I915_BIT_6_SWIZZLE_9_10:
1949 return "bit9/bit10";
1950 case I915_BIT_6_SWIZZLE_9_11:
1951 return "bit9/bit11";
1952 case I915_BIT_6_SWIZZLE_9_10_11:
1953 return "bit9/bit10/bit11";
1954 case I915_BIT_6_SWIZZLE_9_17:
1955 return "bit9/bit17";
1956 case I915_BIT_6_SWIZZLE_9_10_17:
1957 return "bit9/bit10/bit17";
1958 case I915_BIT_6_SWIZZLE_UNKNOWN:
1965 static int i915_swizzle_info(struct seq_file *m, void *data)
1967 struct drm_info_node *node = m->private;
1968 struct drm_device *dev = node->minor->dev;
1969 struct drm_i915_private *dev_priv = dev->dev_private;
1972 ret = mutex_lock_interruptible(&dev->struct_mutex);
1975 intel_runtime_pm_get(dev_priv);
1977 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1978 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1979 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1980 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1982 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1983 seq_printf(m, "DDC = 0x%08x\n",
1985 seq_printf(m, "DDC2 = 0x%08x\n",
1987 seq_printf(m, "C0DRB3 = 0x%04x\n",
1988 I915_READ16(C0DRB3));
1989 seq_printf(m, "C1DRB3 = 0x%04x\n",
1990 I915_READ16(C1DRB3));
1991 } else if (INTEL_INFO(dev)->gen >= 6) {
1992 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1993 I915_READ(MAD_DIMM_C0));
1994 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1995 I915_READ(MAD_DIMM_C1));
1996 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1997 I915_READ(MAD_DIMM_C2));
1998 seq_printf(m, "TILECTL = 0x%08x\n",
1999 I915_READ(TILECTL));
2000 if (INTEL_INFO(dev)->gen >= 8)
2001 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2002 I915_READ(GAMTARBMODE));
2004 seq_printf(m, "ARB_MODE = 0x%08x\n",
2005 I915_READ(ARB_MODE));
2006 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2007 I915_READ(DISP_ARB_CTL));
2010 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2011 seq_puts(m, "L-shaped memory detected\n");
2013 intel_runtime_pm_put(dev_priv);
2014 mutex_unlock(&dev->struct_mutex);
2019 static int per_file_ctx(int id, void *ptr, void *data)
2021 struct intel_context *ctx = ptr;
2022 struct seq_file *m = data;
2023 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2026 seq_printf(m, " no ppgtt for context %d\n",
2031 if (i915_gem_context_is_default(ctx))
2032 seq_puts(m, " default context:\n");
2034 seq_printf(m, " context %d:\n", ctx->user_handle);
2035 ppgtt->debug_dump(ppgtt, m);
2040 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2042 struct drm_i915_private *dev_priv = dev->dev_private;
2043 struct intel_engine_cs *ring;
2044 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2050 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
2051 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
2052 for_each_ring(ring, dev_priv, unused) {
2053 seq_printf(m, "%s\n", ring->name);
2054 for (i = 0; i < 4; i++) {
2055 u32 offset = 0x270 + i * 8;
2056 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2058 pdp |= I915_READ(ring->mmio_base + offset);
2059 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2064 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2066 struct drm_i915_private *dev_priv = dev->dev_private;
2067 struct intel_engine_cs *ring;
2068 struct drm_file *file;
2071 if (INTEL_INFO(dev)->gen == 6)
2072 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2074 for_each_ring(ring, dev_priv, i) {
2075 seq_printf(m, "%s\n", ring->name);
2076 if (INTEL_INFO(dev)->gen == 7)
2077 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2078 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2079 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2080 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2082 if (dev_priv->mm.aliasing_ppgtt) {
2083 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2085 seq_puts(m, "aliasing PPGTT:\n");
2086 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
2088 ppgtt->debug_dump(ppgtt, m);
2091 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2092 struct drm_i915_file_private *file_priv = file->driver_priv;
2094 seq_printf(m, "proc: %s\n",
2095 get_pid_task(file->pid, PIDTYPE_PID)->comm);
2096 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
2098 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2101 static int i915_ppgtt_info(struct seq_file *m, void *data)
2103 struct drm_info_node *node = m->private;
2104 struct drm_device *dev = node->minor->dev;
2105 struct drm_i915_private *dev_priv = dev->dev_private;
2107 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2110 intel_runtime_pm_get(dev_priv);
2112 if (INTEL_INFO(dev)->gen >= 8)
2113 gen8_ppgtt_info(m, dev);
2114 else if (INTEL_INFO(dev)->gen >= 6)
2115 gen6_ppgtt_info(m, dev);
2117 intel_runtime_pm_put(dev_priv);
2118 mutex_unlock(&dev->struct_mutex);
2123 static int i915_llc(struct seq_file *m, void *data)
2125 struct drm_info_node *node = m->private;
2126 struct drm_device *dev = node->minor->dev;
2127 struct drm_i915_private *dev_priv = dev->dev_private;
2129 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2130 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2131 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2136 static int i915_edp_psr_status(struct seq_file *m, void *data)
2138 struct drm_info_node *node = m->private;
2139 struct drm_device *dev = node->minor->dev;
2140 struct drm_i915_private *dev_priv = dev->dev_private;
2142 bool enabled = false;
2144 intel_runtime_pm_get(dev_priv);
2146 mutex_lock(&dev_priv->psr.lock);
2147 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2148 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2149 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2150 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2151 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2152 dev_priv->psr.busy_frontbuffer_bits);
2153 seq_printf(m, "Re-enable work scheduled: %s\n",
2154 yesno(work_busy(&dev_priv->psr.work.work)));
2156 enabled = HAS_PSR(dev) &&
2157 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2158 seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
2161 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2162 EDP_PSR_PERF_CNT_MASK;
2163 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2164 mutex_unlock(&dev_priv->psr.lock);
2166 intel_runtime_pm_put(dev_priv);
2170 static int i915_sink_crc(struct seq_file *m, void *data)
2172 struct drm_info_node *node = m->private;
2173 struct drm_device *dev = node->minor->dev;
2174 struct intel_encoder *encoder;
2175 struct intel_connector *connector;
2176 struct intel_dp *intel_dp = NULL;
2180 drm_modeset_lock_all(dev);
2181 list_for_each_entry(connector, &dev->mode_config.connector_list,
2184 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2187 if (!connector->base.encoder)
2190 encoder = to_intel_encoder(connector->base.encoder);
2191 if (encoder->type != INTEL_OUTPUT_EDP)
2194 intel_dp = enc_to_intel_dp(&encoder->base);
2196 ret = intel_dp_sink_crc(intel_dp, crc);
2200 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2201 crc[0], crc[1], crc[2],
2202 crc[3], crc[4], crc[5]);
2207 drm_modeset_unlock_all(dev);
2211 static int i915_energy_uJ(struct seq_file *m, void *data)
2213 struct drm_info_node *node = m->private;
2214 struct drm_device *dev = node->minor->dev;
2215 struct drm_i915_private *dev_priv = dev->dev_private;
2219 if (INTEL_INFO(dev)->gen < 6)
2222 intel_runtime_pm_get(dev_priv);
2224 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2225 power = (power & 0x1f00) >> 8;
2226 units = 1000000 / (1 << power); /* convert to uJ */
2227 power = I915_READ(MCH_SECP_NRG_STTS);
2230 intel_runtime_pm_put(dev_priv);
2232 seq_printf(m, "%llu", (long long unsigned)power);
2237 static int i915_pc8_status(struct seq_file *m, void *unused)
2239 struct drm_info_node *node = m->private;
2240 struct drm_device *dev = node->minor->dev;
2241 struct drm_i915_private *dev_priv = dev->dev_private;
2243 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2244 seq_puts(m, "not supported\n");
2248 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2249 seq_printf(m, "IRQs disabled: %s\n",
2250 yesno(!intel_irqs_enabled(dev_priv)));
2255 static const char *power_domain_str(enum intel_display_power_domain domain)
2258 case POWER_DOMAIN_PIPE_A:
2260 case POWER_DOMAIN_PIPE_B:
2262 case POWER_DOMAIN_PIPE_C:
2264 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2265 return "PIPE_A_PANEL_FITTER";
2266 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2267 return "PIPE_B_PANEL_FITTER";
2268 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2269 return "PIPE_C_PANEL_FITTER";
2270 case POWER_DOMAIN_TRANSCODER_A:
2271 return "TRANSCODER_A";
2272 case POWER_DOMAIN_TRANSCODER_B:
2273 return "TRANSCODER_B";
2274 case POWER_DOMAIN_TRANSCODER_C:
2275 return "TRANSCODER_C";
2276 case POWER_DOMAIN_TRANSCODER_EDP:
2277 return "TRANSCODER_EDP";
2278 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2279 return "PORT_DDI_A_2_LANES";
2280 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2281 return "PORT_DDI_A_4_LANES";
2282 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2283 return "PORT_DDI_B_2_LANES";
2284 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2285 return "PORT_DDI_B_4_LANES";
2286 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2287 return "PORT_DDI_C_2_LANES";
2288 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2289 return "PORT_DDI_C_4_LANES";
2290 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2291 return "PORT_DDI_D_2_LANES";
2292 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2293 return "PORT_DDI_D_4_LANES";
2294 case POWER_DOMAIN_PORT_DSI:
2296 case POWER_DOMAIN_PORT_CRT:
2298 case POWER_DOMAIN_PORT_OTHER:
2299 return "PORT_OTHER";
2300 case POWER_DOMAIN_VGA:
2302 case POWER_DOMAIN_AUDIO:
2304 case POWER_DOMAIN_PLLS:
2306 case POWER_DOMAIN_INIT:
2314 static int i915_power_domain_info(struct seq_file *m, void *unused)
2316 struct drm_info_node *node = m->private;
2317 struct drm_device *dev = node->minor->dev;
2318 struct drm_i915_private *dev_priv = dev->dev_private;
2319 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2322 mutex_lock(&power_domains->lock);
2324 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2325 for (i = 0; i < power_domains->power_well_count; i++) {
2326 struct i915_power_well *power_well;
2327 enum intel_display_power_domain power_domain;
2329 power_well = &power_domains->power_wells[i];
2330 seq_printf(m, "%-25s %d\n", power_well->name,
2333 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2335 if (!(BIT(power_domain) & power_well->domains))
2338 seq_printf(m, " %-23s %d\n",
2339 power_domain_str(power_domain),
2340 power_domains->domain_use_count[power_domain]);
2344 mutex_unlock(&power_domains->lock);
2349 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2350 struct drm_display_mode *mode)
2354 for (i = 0; i < tabs; i++)
2357 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2358 mode->base.id, mode->name,
2359 mode->vrefresh, mode->clock,
2360 mode->hdisplay, mode->hsync_start,
2361 mode->hsync_end, mode->htotal,
2362 mode->vdisplay, mode->vsync_start,
2363 mode->vsync_end, mode->vtotal,
2364 mode->type, mode->flags);
2367 static void intel_encoder_info(struct seq_file *m,
2368 struct intel_crtc *intel_crtc,
2369 struct intel_encoder *intel_encoder)
2371 struct drm_info_node *node = m->private;
2372 struct drm_device *dev = node->minor->dev;
2373 struct drm_crtc *crtc = &intel_crtc->base;
2374 struct intel_connector *intel_connector;
2375 struct drm_encoder *encoder;
2377 encoder = &intel_encoder->base;
2378 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2379 encoder->base.id, encoder->name);
2380 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2381 struct drm_connector *connector = &intel_connector->base;
2382 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2385 drm_get_connector_status_name(connector->status));
2386 if (connector->status == connector_status_connected) {
2387 struct drm_display_mode *mode = &crtc->mode;
2388 seq_printf(m, ", mode:\n");
2389 intel_seq_print_mode(m, 2, mode);
2396 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2398 struct drm_info_node *node = m->private;
2399 struct drm_device *dev = node->minor->dev;
2400 struct drm_crtc *crtc = &intel_crtc->base;
2401 struct intel_encoder *intel_encoder;
2403 if (crtc->primary->fb)
2404 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2405 crtc->primary->fb->base.id, crtc->x, crtc->y,
2406 crtc->primary->fb->width, crtc->primary->fb->height);
2408 seq_puts(m, "\tprimary plane disabled\n");
2409 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2410 intel_encoder_info(m, intel_crtc, intel_encoder);
2413 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2415 struct drm_display_mode *mode = panel->fixed_mode;
2417 seq_printf(m, "\tfixed mode:\n");
2418 intel_seq_print_mode(m, 2, mode);
2421 static void intel_dp_info(struct seq_file *m,
2422 struct intel_connector *intel_connector)
2424 struct intel_encoder *intel_encoder = intel_connector->encoder;
2425 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2427 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2428 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2430 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2431 intel_panel_info(m, &intel_connector->panel);
2434 static void intel_hdmi_info(struct seq_file *m,
2435 struct intel_connector *intel_connector)
2437 struct intel_encoder *intel_encoder = intel_connector->encoder;
2438 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2440 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2444 static void intel_lvds_info(struct seq_file *m,
2445 struct intel_connector *intel_connector)
2447 intel_panel_info(m, &intel_connector->panel);
2450 static void intel_connector_info(struct seq_file *m,
2451 struct drm_connector *connector)
2453 struct intel_connector *intel_connector = to_intel_connector(connector);
2454 struct intel_encoder *intel_encoder = intel_connector->encoder;
2455 struct drm_display_mode *mode;
2457 seq_printf(m, "connector %d: type %s, status: %s\n",
2458 connector->base.id, connector->name,
2459 drm_get_connector_status_name(connector->status));
2460 if (connector->status == connector_status_connected) {
2461 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2462 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2463 connector->display_info.width_mm,
2464 connector->display_info.height_mm);
2465 seq_printf(m, "\tsubpixel order: %s\n",
2466 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2467 seq_printf(m, "\tCEA rev: %d\n",
2468 connector->display_info.cea_rev);
2470 if (intel_encoder) {
2471 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2472 intel_encoder->type == INTEL_OUTPUT_EDP)
2473 intel_dp_info(m, intel_connector);
2474 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2475 intel_hdmi_info(m, intel_connector);
2476 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2477 intel_lvds_info(m, intel_connector);
2480 seq_printf(m, "\tmodes:\n");
2481 list_for_each_entry(mode, &connector->modes, head)
2482 intel_seq_print_mode(m, 2, mode);
2485 static bool cursor_active(struct drm_device *dev, int pipe)
2487 struct drm_i915_private *dev_priv = dev->dev_private;
2490 if (IS_845G(dev) || IS_I865G(dev))
2491 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2493 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2498 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2500 struct drm_i915_private *dev_priv = dev->dev_private;
2503 pos = I915_READ(CURPOS(pipe));
2505 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2506 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2509 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2510 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2513 return cursor_active(dev, pipe);
2516 static int i915_display_info(struct seq_file *m, void *unused)
2518 struct drm_info_node *node = m->private;
2519 struct drm_device *dev = node->minor->dev;
2520 struct drm_i915_private *dev_priv = dev->dev_private;
2521 struct intel_crtc *crtc;
2522 struct drm_connector *connector;
2524 intel_runtime_pm_get(dev_priv);
2525 drm_modeset_lock_all(dev);
2526 seq_printf(m, "CRTC info\n");
2527 seq_printf(m, "---------\n");
2528 for_each_intel_crtc(dev, crtc) {
2532 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2533 crtc->base.base.id, pipe_name(crtc->pipe),
2534 yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h);
2536 intel_crtc_info(m, crtc);
2538 active = cursor_position(dev, crtc->pipe, &x, &y);
2539 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2540 yesno(crtc->cursor_base),
2541 x, y, crtc->cursor_width, crtc->cursor_height,
2542 crtc->cursor_addr, yesno(active));
2545 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2546 yesno(!crtc->cpu_fifo_underrun_disabled),
2547 yesno(!crtc->pch_fifo_underrun_disabled));
2550 seq_printf(m, "\n");
2551 seq_printf(m, "Connector info\n");
2552 seq_printf(m, "--------------\n");
2553 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2554 intel_connector_info(m, connector);
2556 drm_modeset_unlock_all(dev);
2557 intel_runtime_pm_put(dev_priv);
2562 static int i915_semaphore_status(struct seq_file *m, void *unused)
2564 struct drm_info_node *node = (struct drm_info_node *) m->private;
2565 struct drm_device *dev = node->minor->dev;
2566 struct drm_i915_private *dev_priv = dev->dev_private;
2567 struct intel_engine_cs *ring;
2568 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2571 if (!i915_semaphore_is_enabled(dev)) {
2572 seq_puts(m, "Semaphores are disabled\n");
2576 ret = mutex_lock_interruptible(&dev->struct_mutex);
2579 intel_runtime_pm_get(dev_priv);
2581 if (IS_BROADWELL(dev)) {
2585 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2587 seqno = (uint64_t *)kmap_atomic(page);
2588 for_each_ring(ring, dev_priv, i) {
2591 seq_printf(m, "%s\n", ring->name);
2593 seq_puts(m, " Last signal:");
2594 for (j = 0; j < num_rings; j++) {
2595 offset = i * I915_NUM_RINGS + j;
2596 seq_printf(m, "0x%08llx (0x%02llx) ",
2597 seqno[offset], offset * 8);
2601 seq_puts(m, " Last wait: ");
2602 for (j = 0; j < num_rings; j++) {
2603 offset = i + (j * I915_NUM_RINGS);
2604 seq_printf(m, "0x%08llx (0x%02llx) ",
2605 seqno[offset], offset * 8);
2610 kunmap_atomic(seqno);
2612 seq_puts(m, " Last signal:");
2613 for_each_ring(ring, dev_priv, i)
2614 for (j = 0; j < num_rings; j++)
2615 seq_printf(m, "0x%08x\n",
2616 I915_READ(ring->semaphore.mbox.signal[j]));
2620 seq_puts(m, "\nSync seqno:\n");
2621 for_each_ring(ring, dev_priv, i) {
2622 for (j = 0; j < num_rings; j++) {
2623 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2629 intel_runtime_pm_put(dev_priv);
2630 mutex_unlock(&dev->struct_mutex);
2634 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2636 struct drm_info_node *node = (struct drm_info_node *) m->private;
2637 struct drm_device *dev = node->minor->dev;
2638 struct drm_i915_private *dev_priv = dev->dev_private;
2641 drm_modeset_lock_all(dev);
2642 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2643 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2645 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2646 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2647 pll->config.crtc_mask, pll->active, yesno(pll->on));
2648 seq_printf(m, " tracked hardware state:\n");
2649 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2650 seq_printf(m, " dpll_md: 0x%08x\n",
2651 pll->config.hw_state.dpll_md);
2652 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2653 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2654 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
2656 drm_modeset_unlock_all(dev);
2661 static int i915_wa_registers(struct seq_file *m, void *unused)
2665 struct drm_info_node *node = (struct drm_info_node *) m->private;
2666 struct drm_device *dev = node->minor->dev;
2667 struct drm_i915_private *dev_priv = dev->dev_private;
2669 ret = mutex_lock_interruptible(&dev->struct_mutex);
2673 intel_runtime_pm_get(dev_priv);
2675 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2676 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2677 u32 addr, mask, value, read;
2680 addr = dev_priv->workarounds.reg[i].addr;
2681 mask = dev_priv->workarounds.reg[i].mask;
2682 value = dev_priv->workarounds.reg[i].value;
2683 read = I915_READ(addr);
2684 ok = (value & mask) == (read & mask);
2685 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2686 addr, value, mask, read, ok ? "OK" : "FAIL");
2689 intel_runtime_pm_put(dev_priv);
2690 mutex_unlock(&dev->struct_mutex);
2695 static int i915_ddb_info(struct seq_file *m, void *unused)
2697 struct drm_info_node *node = m->private;
2698 struct drm_device *dev = node->minor->dev;
2699 struct drm_i915_private *dev_priv = dev->dev_private;
2700 struct skl_ddb_allocation *ddb;
2701 struct skl_ddb_entry *entry;
2705 drm_modeset_lock_all(dev);
2707 ddb = &dev_priv->wm.skl_hw.ddb;
2709 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2711 for_each_pipe(dev_priv, pipe) {
2712 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2714 for_each_plane(pipe, plane) {
2715 entry = &ddb->plane[pipe][plane];
2716 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2717 entry->start, entry->end,
2718 skl_ddb_entry_size(entry));
2721 entry = &ddb->cursor[pipe];
2722 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2723 entry->end, skl_ddb_entry_size(entry));
2726 drm_modeset_unlock_all(dev);
2731 struct pipe_crc_info {
2733 struct drm_device *dev;
2737 static int i915_dp_mst_info(struct seq_file *m, void *unused)
2739 struct drm_info_node *node = (struct drm_info_node *) m->private;
2740 struct drm_device *dev = node->minor->dev;
2741 struct drm_encoder *encoder;
2742 struct intel_encoder *intel_encoder;
2743 struct intel_digital_port *intel_dig_port;
2744 drm_modeset_lock_all(dev);
2745 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2746 intel_encoder = to_intel_encoder(encoder);
2747 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2749 intel_dig_port = enc_to_dig_port(encoder);
2750 if (!intel_dig_port->dp.can_mst)
2753 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2755 drm_modeset_unlock_all(dev);
2759 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2761 struct pipe_crc_info *info = inode->i_private;
2762 struct drm_i915_private *dev_priv = info->dev->dev_private;
2763 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2765 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2768 spin_lock_irq(&pipe_crc->lock);
2770 if (pipe_crc->opened) {
2771 spin_unlock_irq(&pipe_crc->lock);
2772 return -EBUSY; /* already open */
2775 pipe_crc->opened = true;
2776 filep->private_data = inode->i_private;
2778 spin_unlock_irq(&pipe_crc->lock);
2783 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2785 struct pipe_crc_info *info = inode->i_private;
2786 struct drm_i915_private *dev_priv = info->dev->dev_private;
2787 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2789 spin_lock_irq(&pipe_crc->lock);
2790 pipe_crc->opened = false;
2791 spin_unlock_irq(&pipe_crc->lock);
2796 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2797 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2798 /* account for \'0' */
2799 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2801 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2803 assert_spin_locked(&pipe_crc->lock);
2804 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2805 INTEL_PIPE_CRC_ENTRIES_NR);
2809 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2812 struct pipe_crc_info *info = filep->private_data;
2813 struct drm_device *dev = info->dev;
2814 struct drm_i915_private *dev_priv = dev->dev_private;
2815 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2816 char buf[PIPE_CRC_BUFFER_LEN];
2817 int head, tail, n_entries, n;
2821 * Don't allow user space to provide buffers not big enough to hold
2824 if (count < PIPE_CRC_LINE_LEN)
2827 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2830 /* nothing to read */
2831 spin_lock_irq(&pipe_crc->lock);
2832 while (pipe_crc_data_count(pipe_crc) == 0) {
2835 if (filep->f_flags & O_NONBLOCK) {
2836 spin_unlock_irq(&pipe_crc->lock);
2840 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2841 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2843 spin_unlock_irq(&pipe_crc->lock);
2848 /* We now have one or more entries to read */
2849 head = pipe_crc->head;
2850 tail = pipe_crc->tail;
2851 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2852 count / PIPE_CRC_LINE_LEN);
2853 spin_unlock_irq(&pipe_crc->lock);
2858 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
2861 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2862 "%8u %8x %8x %8x %8x %8x\n",
2863 entry->frame, entry->crc[0],
2864 entry->crc[1], entry->crc[2],
2865 entry->crc[3], entry->crc[4]);
2867 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2868 buf, PIPE_CRC_LINE_LEN);
2869 if (ret == PIPE_CRC_LINE_LEN)
2872 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2873 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2875 } while (--n_entries);
2877 spin_lock_irq(&pipe_crc->lock);
2878 pipe_crc->tail = tail;
2879 spin_unlock_irq(&pipe_crc->lock);
2884 static const struct file_operations i915_pipe_crc_fops = {
2885 .owner = THIS_MODULE,
2886 .open = i915_pipe_crc_open,
2887 .read = i915_pipe_crc_read,
2888 .release = i915_pipe_crc_release,
2891 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2893 .name = "i915_pipe_A_crc",
2897 .name = "i915_pipe_B_crc",
2901 .name = "i915_pipe_C_crc",
2906 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2909 struct drm_device *dev = minor->dev;
2911 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2914 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2915 &i915_pipe_crc_fops);
2919 return drm_add_fake_info_node(minor, ent, info);
2922 static const char * const pipe_crc_sources[] = {
2935 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2937 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2938 return pipe_crc_sources[source];
2941 static int display_crc_ctl_show(struct seq_file *m, void *data)
2943 struct drm_device *dev = m->private;
2944 struct drm_i915_private *dev_priv = dev->dev_private;
2947 for (i = 0; i < I915_MAX_PIPES; i++)
2948 seq_printf(m, "%c %s\n", pipe_name(i),
2949 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2954 static int display_crc_ctl_open(struct inode *inode, struct file *file)
2956 struct drm_device *dev = inode->i_private;
2958 return single_open(file, display_crc_ctl_show, dev);
2961 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2964 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2965 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2968 case INTEL_PIPE_CRC_SOURCE_PIPE:
2969 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2971 case INTEL_PIPE_CRC_SOURCE_NONE:
2981 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2982 enum intel_pipe_crc_source *source)
2984 struct intel_encoder *encoder;
2985 struct intel_crtc *crtc;
2986 struct intel_digital_port *dig_port;
2989 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2991 drm_modeset_lock_all(dev);
2992 for_each_intel_encoder(dev, encoder) {
2993 if (!encoder->base.crtc)
2996 crtc = to_intel_crtc(encoder->base.crtc);
2998 if (crtc->pipe != pipe)
3001 switch (encoder->type) {
3002 case INTEL_OUTPUT_TVOUT:
3003 *source = INTEL_PIPE_CRC_SOURCE_TV;
3005 case INTEL_OUTPUT_DISPLAYPORT:
3006 case INTEL_OUTPUT_EDP:
3007 dig_port = enc_to_dig_port(&encoder->base);
3008 switch (dig_port->port) {
3010 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3013 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3016 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3019 WARN(1, "nonexisting DP port %c\n",
3020 port_name(dig_port->port));
3028 drm_modeset_unlock_all(dev);
3033 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3035 enum intel_pipe_crc_source *source,
3038 struct drm_i915_private *dev_priv = dev->dev_private;
3039 bool need_stable_symbols = false;
3041 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3042 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3048 case INTEL_PIPE_CRC_SOURCE_PIPE:
3049 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3051 case INTEL_PIPE_CRC_SOURCE_DP_B:
3052 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3053 need_stable_symbols = true;
3055 case INTEL_PIPE_CRC_SOURCE_DP_C:
3056 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3057 need_stable_symbols = true;
3059 case INTEL_PIPE_CRC_SOURCE_NONE:
3067 * When the pipe CRC tap point is after the transcoders we need
3068 * to tweak symbol-level features to produce a deterministic series of
3069 * symbols for a given frame. We need to reset those features only once
3070 * a frame (instead of every nth symbol):
3071 * - DC-balance: used to ensure a better clock recovery from the data
3073 * - DisplayPort scrambling: used for EMI reduction
3075 if (need_stable_symbols) {
3076 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3078 tmp |= DC_BALANCE_RESET_VLV;
3080 tmp |= PIPE_A_SCRAMBLE_RESET;
3082 tmp |= PIPE_B_SCRAMBLE_RESET;
3084 I915_WRITE(PORT_DFT2_G4X, tmp);
3090 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3092 enum intel_pipe_crc_source *source,
3095 struct drm_i915_private *dev_priv = dev->dev_private;
3096 bool need_stable_symbols = false;
3098 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3099 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3105 case INTEL_PIPE_CRC_SOURCE_PIPE:
3106 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3108 case INTEL_PIPE_CRC_SOURCE_TV:
3109 if (!SUPPORTS_TV(dev))
3111 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3113 case INTEL_PIPE_CRC_SOURCE_DP_B:
3116 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3117 need_stable_symbols = true;
3119 case INTEL_PIPE_CRC_SOURCE_DP_C:
3122 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3123 need_stable_symbols = true;
3125 case INTEL_PIPE_CRC_SOURCE_DP_D:
3128 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3129 need_stable_symbols = true;
3131 case INTEL_PIPE_CRC_SOURCE_NONE:
3139 * When the pipe CRC tap point is after the transcoders we need
3140 * to tweak symbol-level features to produce a deterministic series of
3141 * symbols for a given frame. We need to reset those features only once
3142 * a frame (instead of every nth symbol):
3143 * - DC-balance: used to ensure a better clock recovery from the data
3145 * - DisplayPort scrambling: used for EMI reduction
3147 if (need_stable_symbols) {
3148 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3150 WARN_ON(!IS_G4X(dev));
3152 I915_WRITE(PORT_DFT_I9XX,
3153 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3156 tmp |= PIPE_A_SCRAMBLE_RESET;
3158 tmp |= PIPE_B_SCRAMBLE_RESET;
3160 I915_WRITE(PORT_DFT2_G4X, tmp);
3166 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3169 struct drm_i915_private *dev_priv = dev->dev_private;
3170 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3173 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3175 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3176 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3177 tmp &= ~DC_BALANCE_RESET_VLV;
3178 I915_WRITE(PORT_DFT2_G4X, tmp);
3182 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3185 struct drm_i915_private *dev_priv = dev->dev_private;
3186 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3189 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3191 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3192 I915_WRITE(PORT_DFT2_G4X, tmp);
3194 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3195 I915_WRITE(PORT_DFT_I9XX,
3196 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3200 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3203 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3204 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3207 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3208 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3210 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3211 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3213 case INTEL_PIPE_CRC_SOURCE_PIPE:
3214 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3216 case INTEL_PIPE_CRC_SOURCE_NONE:
3226 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3228 struct drm_i915_private *dev_priv = dev->dev_private;
3229 struct intel_crtc *crtc =
3230 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3232 drm_modeset_lock_all(dev);
3234 * If we use the eDP transcoder we need to make sure that we don't
3235 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3236 * relevant on hsw with pipe A when using the always-on power well
3239 if (crtc->config.cpu_transcoder == TRANSCODER_EDP &&
3240 !crtc->config.pch_pfit.enabled) {
3241 crtc->config.pch_pfit.force_thru = true;
3243 intel_display_power_get(dev_priv,
3244 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3246 dev_priv->display.crtc_disable(&crtc->base);
3247 dev_priv->display.crtc_enable(&crtc->base);
3249 drm_modeset_unlock_all(dev);
3252 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3254 struct drm_i915_private *dev_priv = dev->dev_private;
3255 struct intel_crtc *crtc =
3256 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3258 drm_modeset_lock_all(dev);
3260 * If we use the eDP transcoder we need to make sure that we don't
3261 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3262 * relevant on hsw with pipe A when using the always-on power well
3265 if (crtc->config.pch_pfit.force_thru) {
3266 crtc->config.pch_pfit.force_thru = false;
3268 dev_priv->display.crtc_disable(&crtc->base);
3269 dev_priv->display.crtc_enable(&crtc->base);
3271 intel_display_power_put(dev_priv,
3272 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3274 drm_modeset_unlock_all(dev);
3277 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3279 enum intel_pipe_crc_source *source,
3282 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3283 *source = INTEL_PIPE_CRC_SOURCE_PF;
3286 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3287 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3289 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3290 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3292 case INTEL_PIPE_CRC_SOURCE_PF:
3293 if (IS_HASWELL(dev) && pipe == PIPE_A)
3294 hsw_trans_edp_pipe_A_crc_wa(dev);
3296 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3298 case INTEL_PIPE_CRC_SOURCE_NONE:
3308 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3309 enum intel_pipe_crc_source source)
3311 struct drm_i915_private *dev_priv = dev->dev_private;
3312 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3313 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3315 u32 val = 0; /* shut up gcc */
3318 if (pipe_crc->source == source)
3321 /* forbid changing the source without going back to 'none' */
3322 if (pipe_crc->source && source)
3326 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3327 else if (INTEL_INFO(dev)->gen < 5)
3328 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3329 else if (IS_VALLEYVIEW(dev))
3330 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3331 else if (IS_GEN5(dev) || IS_GEN6(dev))
3332 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3334 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3339 /* none -> real source transition */
3341 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3342 pipe_name(pipe), pipe_crc_source_name(source));
3344 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
3345 INTEL_PIPE_CRC_ENTRIES_NR,
3347 if (!pipe_crc->entries)
3351 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3352 * enabled and disabled dynamically based on package C states,
3353 * user space can't make reliable use of the CRCs, so let's just
3354 * completely disable it.
3356 hsw_disable_ips(crtc);
3358 spin_lock_irq(&pipe_crc->lock);
3361 spin_unlock_irq(&pipe_crc->lock);
3364 pipe_crc->source = source;
3366 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3367 POSTING_READ(PIPE_CRC_CTL(pipe));
3369 /* real source -> none transition */
3370 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3371 struct intel_pipe_crc_entry *entries;
3372 struct intel_crtc *crtc =
3373 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3375 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3378 drm_modeset_lock(&crtc->base.mutex, NULL);
3380 intel_wait_for_vblank(dev, pipe);
3381 drm_modeset_unlock(&crtc->base.mutex);
3383 spin_lock_irq(&pipe_crc->lock);
3384 entries = pipe_crc->entries;
3385 pipe_crc->entries = NULL;
3386 spin_unlock_irq(&pipe_crc->lock);
3391 g4x_undo_pipe_scramble_reset(dev, pipe);
3392 else if (IS_VALLEYVIEW(dev))
3393 vlv_undo_pipe_scramble_reset(dev, pipe);
3394 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3395 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3397 hsw_enable_ips(crtc);
3404 * Parse pipe CRC command strings:
3405 * command: wsp* object wsp+ name wsp+ source wsp*
3408 * source: (none | plane1 | plane2 | pf)
3409 * wsp: (#0x20 | #0x9 | #0xA)+
3412 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3413 * "pipe A none" -> Stop CRC
3415 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3422 /* skip leading white space */
3423 buf = skip_spaces(buf);
3425 break; /* end of buffer */
3427 /* find end of word */
3428 for (end = buf; *end && !isspace(*end); end++)
3431 if (n_words == max_words) {
3432 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3434 return -EINVAL; /* ran out of words[] before bytes */
3439 words[n_words++] = buf;
3446 enum intel_pipe_crc_object {
3447 PIPE_CRC_OBJECT_PIPE,
3450 static const char * const pipe_crc_objects[] = {
3455 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3459 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3460 if (!strcmp(buf, pipe_crc_objects[i])) {
3468 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3470 const char name = buf[0];
3472 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3481 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3485 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3486 if (!strcmp(buf, pipe_crc_sources[i])) {
3494 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3498 char *words[N_WORDS];
3500 enum intel_pipe_crc_object object;
3501 enum intel_pipe_crc_source source;
3503 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3504 if (n_words != N_WORDS) {
3505 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3510 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3511 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3515 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3516 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3520 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3521 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3525 return pipe_crc_set_source(dev, pipe, source);
3528 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3529 size_t len, loff_t *offp)
3531 struct seq_file *m = file->private_data;
3532 struct drm_device *dev = m->private;
3539 if (len > PAGE_SIZE - 1) {
3540 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3545 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3549 if (copy_from_user(tmpbuf, ubuf, len)) {
3555 ret = display_crc_ctl_parse(dev, tmpbuf, len);
3566 static const struct file_operations i915_display_crc_ctl_fops = {
3567 .owner = THIS_MODULE,
3568 .open = display_crc_ctl_open,
3570 .llseek = seq_lseek,
3571 .release = single_release,
3572 .write = display_crc_ctl_write
3575 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3577 struct drm_device *dev = m->private;
3578 int num_levels = ilk_wm_max_level(dev) + 1;
3581 drm_modeset_lock_all(dev);
3583 for (level = 0; level < num_levels; level++) {
3584 unsigned int latency = wm[level];
3587 * - WM1+ latency values in 0.5us units
3588 * - latencies are in us on gen9
3590 if (INTEL_INFO(dev)->gen >= 9)
3595 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3596 level, wm[level], latency / 10, latency % 10);
3599 drm_modeset_unlock_all(dev);
3602 static int pri_wm_latency_show(struct seq_file *m, void *data)
3604 struct drm_device *dev = m->private;
3605 struct drm_i915_private *dev_priv = dev->dev_private;
3606 const uint16_t *latencies;
3608 if (INTEL_INFO(dev)->gen >= 9)
3609 latencies = dev_priv->wm.skl_latency;
3611 latencies = to_i915(dev)->wm.pri_latency;
3613 wm_latency_show(m, latencies);
3618 static int spr_wm_latency_show(struct seq_file *m, void *data)
3620 struct drm_device *dev = m->private;
3621 struct drm_i915_private *dev_priv = dev->dev_private;
3622 const uint16_t *latencies;
3624 if (INTEL_INFO(dev)->gen >= 9)
3625 latencies = dev_priv->wm.skl_latency;
3627 latencies = to_i915(dev)->wm.spr_latency;
3629 wm_latency_show(m, latencies);
3634 static int cur_wm_latency_show(struct seq_file *m, void *data)
3636 struct drm_device *dev = m->private;
3637 struct drm_i915_private *dev_priv = dev->dev_private;
3638 const uint16_t *latencies;
3640 if (INTEL_INFO(dev)->gen >= 9)
3641 latencies = dev_priv->wm.skl_latency;
3643 latencies = to_i915(dev)->wm.cur_latency;
3645 wm_latency_show(m, latencies);
3650 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3652 struct drm_device *dev = inode->i_private;
3654 if (HAS_GMCH_DISPLAY(dev))
3657 return single_open(file, pri_wm_latency_show, dev);
3660 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3662 struct drm_device *dev = inode->i_private;
3664 if (HAS_GMCH_DISPLAY(dev))
3667 return single_open(file, spr_wm_latency_show, dev);
3670 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3672 struct drm_device *dev = inode->i_private;
3674 if (HAS_GMCH_DISPLAY(dev))
3677 return single_open(file, cur_wm_latency_show, dev);
3680 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3681 size_t len, loff_t *offp, uint16_t wm[8])
3683 struct seq_file *m = file->private_data;
3684 struct drm_device *dev = m->private;
3685 uint16_t new[8] = { 0 };
3686 int num_levels = ilk_wm_max_level(dev) + 1;
3691 if (len >= sizeof(tmp))
3694 if (copy_from_user(tmp, ubuf, len))
3699 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3700 &new[0], &new[1], &new[2], &new[3],
3701 &new[4], &new[5], &new[6], &new[7]);
3702 if (ret != num_levels)
3705 drm_modeset_lock_all(dev);
3707 for (level = 0; level < num_levels; level++)
3708 wm[level] = new[level];
3710 drm_modeset_unlock_all(dev);
3716 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3717 size_t len, loff_t *offp)
3719 struct seq_file *m = file->private_data;
3720 struct drm_device *dev = m->private;
3721 struct drm_i915_private *dev_priv = dev->dev_private;
3722 uint16_t *latencies;
3724 if (INTEL_INFO(dev)->gen >= 9)
3725 latencies = dev_priv->wm.skl_latency;
3727 latencies = to_i915(dev)->wm.pri_latency;
3729 return wm_latency_write(file, ubuf, len, offp, latencies);
3732 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3733 size_t len, loff_t *offp)
3735 struct seq_file *m = file->private_data;
3736 struct drm_device *dev = m->private;
3737 struct drm_i915_private *dev_priv = dev->dev_private;
3738 uint16_t *latencies;
3740 if (INTEL_INFO(dev)->gen >= 9)
3741 latencies = dev_priv->wm.skl_latency;
3743 latencies = to_i915(dev)->wm.spr_latency;
3745 return wm_latency_write(file, ubuf, len, offp, latencies);
3748 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3749 size_t len, loff_t *offp)
3751 struct seq_file *m = file->private_data;
3752 struct drm_device *dev = m->private;
3753 struct drm_i915_private *dev_priv = dev->dev_private;
3754 uint16_t *latencies;
3756 if (INTEL_INFO(dev)->gen >= 9)
3757 latencies = dev_priv->wm.skl_latency;
3759 latencies = to_i915(dev)->wm.cur_latency;
3761 return wm_latency_write(file, ubuf, len, offp, latencies);
3764 static const struct file_operations i915_pri_wm_latency_fops = {
3765 .owner = THIS_MODULE,
3766 .open = pri_wm_latency_open,
3768 .llseek = seq_lseek,
3769 .release = single_release,
3770 .write = pri_wm_latency_write
3773 static const struct file_operations i915_spr_wm_latency_fops = {
3774 .owner = THIS_MODULE,
3775 .open = spr_wm_latency_open,
3777 .llseek = seq_lseek,
3778 .release = single_release,
3779 .write = spr_wm_latency_write
3782 static const struct file_operations i915_cur_wm_latency_fops = {
3783 .owner = THIS_MODULE,
3784 .open = cur_wm_latency_open,
3786 .llseek = seq_lseek,
3787 .release = single_release,
3788 .write = cur_wm_latency_write
3792 i915_wedged_get(void *data, u64 *val)
3794 struct drm_device *dev = data;
3795 struct drm_i915_private *dev_priv = dev->dev_private;
3797 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
3803 i915_wedged_set(void *data, u64 val)
3805 struct drm_device *dev = data;
3806 struct drm_i915_private *dev_priv = dev->dev_private;
3808 intel_runtime_pm_get(dev_priv);
3810 i915_handle_error(dev, val,
3811 "Manually setting wedged to %llu", val);
3813 intel_runtime_pm_put(dev_priv);
3818 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3819 i915_wedged_get, i915_wedged_set,
3823 i915_ring_stop_get(void *data, u64 *val)
3825 struct drm_device *dev = data;
3826 struct drm_i915_private *dev_priv = dev->dev_private;
3828 *val = dev_priv->gpu_error.stop_rings;
3834 i915_ring_stop_set(void *data, u64 val)
3836 struct drm_device *dev = data;
3837 struct drm_i915_private *dev_priv = dev->dev_private;
3840 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
3842 ret = mutex_lock_interruptible(&dev->struct_mutex);
3846 dev_priv->gpu_error.stop_rings = val;
3847 mutex_unlock(&dev->struct_mutex);
3852 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3853 i915_ring_stop_get, i915_ring_stop_set,
3857 i915_ring_missed_irq_get(void *data, u64 *val)
3859 struct drm_device *dev = data;
3860 struct drm_i915_private *dev_priv = dev->dev_private;
3862 *val = dev_priv->gpu_error.missed_irq_rings;
3867 i915_ring_missed_irq_set(void *data, u64 val)
3869 struct drm_device *dev = data;
3870 struct drm_i915_private *dev_priv = dev->dev_private;
3873 /* Lock against concurrent debugfs callers */
3874 ret = mutex_lock_interruptible(&dev->struct_mutex);
3877 dev_priv->gpu_error.missed_irq_rings = val;
3878 mutex_unlock(&dev->struct_mutex);
3883 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3884 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3888 i915_ring_test_irq_get(void *data, u64 *val)
3890 struct drm_device *dev = data;
3891 struct drm_i915_private *dev_priv = dev->dev_private;
3893 *val = dev_priv->gpu_error.test_irq_rings;
3899 i915_ring_test_irq_set(void *data, u64 val)
3901 struct drm_device *dev = data;
3902 struct drm_i915_private *dev_priv = dev->dev_private;
3905 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3907 /* Lock against concurrent debugfs callers */
3908 ret = mutex_lock_interruptible(&dev->struct_mutex);
3912 dev_priv->gpu_error.test_irq_rings = val;
3913 mutex_unlock(&dev->struct_mutex);
3918 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3919 i915_ring_test_irq_get, i915_ring_test_irq_set,
3922 #define DROP_UNBOUND 0x1
3923 #define DROP_BOUND 0x2
3924 #define DROP_RETIRE 0x4
3925 #define DROP_ACTIVE 0x8
3926 #define DROP_ALL (DROP_UNBOUND | \
3931 i915_drop_caches_get(void *data, u64 *val)
3939 i915_drop_caches_set(void *data, u64 val)
3941 struct drm_device *dev = data;
3942 struct drm_i915_private *dev_priv = dev->dev_private;
3945 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
3947 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3948 * on ioctls on -EAGAIN. */
3949 ret = mutex_lock_interruptible(&dev->struct_mutex);
3953 if (val & DROP_ACTIVE) {
3954 ret = i915_gpu_idle(dev);
3959 if (val & (DROP_RETIRE | DROP_ACTIVE))
3960 i915_gem_retire_requests(dev);
3962 if (val & DROP_BOUND)
3963 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
3965 if (val & DROP_UNBOUND)
3966 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
3969 mutex_unlock(&dev->struct_mutex);
3974 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3975 i915_drop_caches_get, i915_drop_caches_set,
3979 i915_max_freq_get(void *data, u64 *val)
3981 struct drm_device *dev = data;
3982 struct drm_i915_private *dev_priv = dev->dev_private;
3985 if (INTEL_INFO(dev)->gen < 6)
3988 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3990 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3994 if (IS_VALLEYVIEW(dev))
3995 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
3997 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
3998 mutex_unlock(&dev_priv->rps.hw_lock);
4004 i915_max_freq_set(void *data, u64 val)
4006 struct drm_device *dev = data;
4007 struct drm_i915_private *dev_priv = dev->dev_private;
4008 u32 rp_state_cap, hw_max, hw_min;
4011 if (INTEL_INFO(dev)->gen < 6)
4014 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4016 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4018 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4023 * Turbo will still be enabled, but won't go above the set value.
4025 if (IS_VALLEYVIEW(dev)) {
4026 val = vlv_freq_opcode(dev_priv, val);
4028 hw_max = dev_priv->rps.max_freq;
4029 hw_min = dev_priv->rps.min_freq;
4031 do_div(val, GT_FREQUENCY_MULTIPLIER);
4033 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4034 hw_max = dev_priv->rps.max_freq;
4035 hw_min = (rp_state_cap >> 16) & 0xff;
4038 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4039 mutex_unlock(&dev_priv->rps.hw_lock);
4043 dev_priv->rps.max_freq_softlimit = val;
4045 if (IS_VALLEYVIEW(dev))
4046 valleyview_set_rps(dev, val);
4048 gen6_set_rps(dev, val);
4050 mutex_unlock(&dev_priv->rps.hw_lock);
4055 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4056 i915_max_freq_get, i915_max_freq_set,
4060 i915_min_freq_get(void *data, u64 *val)
4062 struct drm_device *dev = data;
4063 struct drm_i915_private *dev_priv = dev->dev_private;
4066 if (INTEL_INFO(dev)->gen < 6)
4069 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4071 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4075 if (IS_VALLEYVIEW(dev))
4076 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4078 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4079 mutex_unlock(&dev_priv->rps.hw_lock);
4085 i915_min_freq_set(void *data, u64 val)
4087 struct drm_device *dev = data;
4088 struct drm_i915_private *dev_priv = dev->dev_private;
4089 u32 rp_state_cap, hw_max, hw_min;
4092 if (INTEL_INFO(dev)->gen < 6)
4095 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4097 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4099 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4104 * Turbo will still be enabled, but won't go below the set value.
4106 if (IS_VALLEYVIEW(dev)) {
4107 val = vlv_freq_opcode(dev_priv, val);
4109 hw_max = dev_priv->rps.max_freq;
4110 hw_min = dev_priv->rps.min_freq;
4112 do_div(val, GT_FREQUENCY_MULTIPLIER);
4114 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4115 hw_max = dev_priv->rps.max_freq;
4116 hw_min = (rp_state_cap >> 16) & 0xff;
4119 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4120 mutex_unlock(&dev_priv->rps.hw_lock);
4124 dev_priv->rps.min_freq_softlimit = val;
4126 if (IS_VALLEYVIEW(dev))
4127 valleyview_set_rps(dev, val);
4129 gen6_set_rps(dev, val);
4131 mutex_unlock(&dev_priv->rps.hw_lock);
4136 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4137 i915_min_freq_get, i915_min_freq_set,
4141 i915_cache_sharing_get(void *data, u64 *val)
4143 struct drm_device *dev = data;
4144 struct drm_i915_private *dev_priv = dev->dev_private;
4148 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4151 ret = mutex_lock_interruptible(&dev->struct_mutex);
4154 intel_runtime_pm_get(dev_priv);
4156 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4158 intel_runtime_pm_put(dev_priv);
4159 mutex_unlock(&dev_priv->dev->struct_mutex);
4161 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4167 i915_cache_sharing_set(void *data, u64 val)
4169 struct drm_device *dev = data;
4170 struct drm_i915_private *dev_priv = dev->dev_private;
4173 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4179 intel_runtime_pm_get(dev_priv);
4180 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4182 /* Update the cache sharing policy here as well */
4183 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4184 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4185 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4186 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4188 intel_runtime_pm_put(dev_priv);
4192 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4193 i915_cache_sharing_get, i915_cache_sharing_set,
4196 static int i915_forcewake_open(struct inode *inode, struct file *file)
4198 struct drm_device *dev = inode->i_private;
4199 struct drm_i915_private *dev_priv = dev->dev_private;
4201 if (INTEL_INFO(dev)->gen < 6)
4204 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4209 static int i915_forcewake_release(struct inode *inode, struct file *file)
4211 struct drm_device *dev = inode->i_private;
4212 struct drm_i915_private *dev_priv = dev->dev_private;
4214 if (INTEL_INFO(dev)->gen < 6)
4217 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4222 static const struct file_operations i915_forcewake_fops = {
4223 .owner = THIS_MODULE,
4224 .open = i915_forcewake_open,
4225 .release = i915_forcewake_release,
4228 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4230 struct drm_device *dev = minor->dev;
4233 ent = debugfs_create_file("i915_forcewake_user",
4236 &i915_forcewake_fops);
4240 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
4243 static int i915_debugfs_create(struct dentry *root,
4244 struct drm_minor *minor,
4246 const struct file_operations *fops)
4248 struct drm_device *dev = minor->dev;
4251 ent = debugfs_create_file(name,
4258 return drm_add_fake_info_node(minor, ent, fops);
4261 static const struct drm_info_list i915_debugfs_list[] = {
4262 {"i915_capabilities", i915_capabilities, 0},
4263 {"i915_gem_objects", i915_gem_object_info, 0},
4264 {"i915_gem_gtt", i915_gem_gtt_info, 0},
4265 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
4266 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
4267 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
4268 {"i915_gem_stolen", i915_gem_stolen_list_info },
4269 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
4270 {"i915_gem_request", i915_gem_request_info, 0},
4271 {"i915_gem_seqno", i915_gem_seqno_info, 0},
4272 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4273 {"i915_gem_interrupt", i915_interrupt_info, 0},
4274 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4275 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4276 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
4277 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
4278 {"i915_frequency_info", i915_frequency_info, 0},
4279 {"i915_drpc_info", i915_drpc_info, 0},
4280 {"i915_emon_status", i915_emon_status, 0},
4281 {"i915_ring_freq_table", i915_ring_freq_table, 0},
4282 {"i915_fbc_status", i915_fbc_status, 0},
4283 {"i915_ips_status", i915_ips_status, 0},
4284 {"i915_sr_status", i915_sr_status, 0},
4285 {"i915_opregion", i915_opregion, 0},
4286 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4287 {"i915_context_status", i915_context_status, 0},
4288 {"i915_dump_lrc", i915_dump_lrc, 0},
4289 {"i915_execlists", i915_execlists, 0},
4290 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
4291 {"i915_swizzle_info", i915_swizzle_info, 0},
4292 {"i915_ppgtt_info", i915_ppgtt_info, 0},
4293 {"i915_llc", i915_llc, 0},
4294 {"i915_edp_psr_status", i915_edp_psr_status, 0},
4295 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4296 {"i915_energy_uJ", i915_energy_uJ, 0},
4297 {"i915_pc8_status", i915_pc8_status, 0},
4298 {"i915_power_domain_info", i915_power_domain_info, 0},
4299 {"i915_display_info", i915_display_info, 0},
4300 {"i915_semaphore_status", i915_semaphore_status, 0},
4301 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4302 {"i915_dp_mst_info", i915_dp_mst_info, 0},
4303 {"i915_wa_registers", i915_wa_registers, 0},
4304 {"i915_ddb_info", i915_ddb_info, 0},
4306 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4308 static const struct i915_debugfs_files {
4310 const struct file_operations *fops;
4311 } i915_debugfs_files[] = {
4312 {"i915_wedged", &i915_wedged_fops},
4313 {"i915_max_freq", &i915_max_freq_fops},
4314 {"i915_min_freq", &i915_min_freq_fops},
4315 {"i915_cache_sharing", &i915_cache_sharing_fops},
4316 {"i915_ring_stop", &i915_ring_stop_fops},
4317 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4318 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4319 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4320 {"i915_error_state", &i915_error_state_fops},
4321 {"i915_next_seqno", &i915_next_seqno_fops},
4322 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4323 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4324 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4325 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4326 {"i915_fbc_false_color", &i915_fbc_fc_fops},
4329 void intel_display_crc_init(struct drm_device *dev)
4331 struct drm_i915_private *dev_priv = dev->dev_private;
4334 for_each_pipe(dev_priv, pipe) {
4335 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4337 pipe_crc->opened = false;
4338 spin_lock_init(&pipe_crc->lock);
4339 init_waitqueue_head(&pipe_crc->wq);
4343 int i915_debugfs_init(struct drm_minor *minor)
4347 ret = i915_forcewake_create(minor->debugfs_root, minor);
4351 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4352 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4357 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4358 ret = i915_debugfs_create(minor->debugfs_root, minor,
4359 i915_debugfs_files[i].name,
4360 i915_debugfs_files[i].fops);
4365 return drm_debugfs_create_files(i915_debugfs_list,
4366 I915_DEBUGFS_ENTRIES,
4367 minor->debugfs_root, minor);
4370 void i915_debugfs_cleanup(struct drm_minor *minor)
4374 drm_debugfs_remove_files(i915_debugfs_list,
4375 I915_DEBUGFS_ENTRIES, minor);
4377 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4380 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4381 struct drm_info_list *info_list =
4382 (struct drm_info_list *)&i915_pipe_crc_data[i];
4384 drm_debugfs_remove_files(info_list, 1, minor);
4387 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4388 struct drm_info_list *info_list =
4389 (struct drm_info_list *) i915_debugfs_files[i].fops;
4391 drm_debugfs_remove_files(info_list, 1, minor);