drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 static const char *yesno(int v)
  50 {
  51         return v ? "yes" : "no";
  52 }
  53
  54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  55  * allocated we need to hook into the minor for release. */
  56 static int
  57 drm_add_fake_info_node(struct drm_minor *minor,
  58                        struct dentry *ent,
  59                        const void *key)
  60 {
  61         struct drm_info_node *node;
  62
  63         node = kmalloc(sizeof(*node), GFP_KERNEL);
  64         if (node == NULL) {
  65                 debugfs_remove(ent);
  66                 return -ENOMEM;
  67         }
  68
  69         node->minor = minor;
  70         node->dent = ent;
  71         node->info_ent = (void *) key;
  72
  73         mutex_lock(&minor->debugfs_lock);
  74         list_add(&node->list, &minor->debugfs_list);
  75         mutex_unlock(&minor->debugfs_lock);
  76
  77         return 0;
  78 }
  79
  80 static int i915_capabilities(struct seq_file *m, void *data)
  81 {
  82         struct drm_info_node *node = m->private;
  83         struct drm_device *dev = node->minor->dev;
  84         const struct intel_device_info *info = INTEL_INFO(dev);
  85
  86         seq_printf(m, "gen: %d\n", info->gen);
  87         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  88 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  89 #define SEP_SEMICOLON ;
  90         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  91 #undef PRINT_FLAG
  92 #undef SEP_SEMICOLON
  93
  94         return 0;
  95 }
  96
  97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  98 {
  99         if (obj->pin_display)
 100                 return "p";
 101         else
 102                 return " ";
 103 }
 104
 105 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 106 {
 107         switch (obj->tiling_mode) {
 108         default:
 109         case I915_TILING_NONE: return " ";
 110         case I915_TILING_X: return "X";
 111         case I915_TILING_Y: return "Y";
 112         }
 113 }
 114
 115 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 116 {
 117         return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
 118 }
 119
 120 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 121 {
 122         u64 size = 0;
 123         struct i915_vma *vma;
 124
 125         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 126                 if (i915_is_ggtt(vma->vm) &&
 127                     drm_mm_node_allocated(&vma->node))
 128                         size += vma->node.size;
 129         }
 130
 131         return size;
 132 }
 133
 134 static void
 135 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 136 {
 137         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 138         struct intel_engine_cs *ring;
 139         struct i915_vma *vma;
 140         int pin_count = 0;
 141         int i;
 142
 143         seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
 144                    &obj->base,
 145                    obj->active ? "*" : " ",
 146                    get_pin_flag(obj),
 147                    get_tiling_flag(obj),
 148                    get_global_flag(obj),
 149                    obj->base.size / 1024,
 150                    obj->base.read_domains,
 151                    obj->base.write_domain);
 152         for_each_ring(ring, dev_priv, i)
 153                 seq_printf(m, "%x ",
 154                                 i915_gem_request_get_seqno(obj->last_read_req[i]));
 155         seq_printf(m, "] %x %x%s%s%s",
 156                    i915_gem_request_get_seqno(obj->last_write_req),
 157                    i915_gem_request_get_seqno(obj->last_fenced_req),
 158                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 159                    obj->dirty ? " dirty" : "",
 160                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 161         if (obj->base.name)
 162                 seq_printf(m, " (name: %d)", obj->base.name);
 163         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 164                 if (vma->pin_count > 0)
 165                         pin_count++;
 166         }
 167         seq_printf(m, " (pinned x %d)", pin_count);
 168         if (obj->pin_display)
 169                 seq_printf(m, " (display)");
 170         if (obj->fence_reg != I915_FENCE_REG_NONE)
 171                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 172         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 173                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 174                            i915_is_ggtt(vma->vm) ? "g" : "pp",
 175                            vma->node.start, vma->node.size);
 176                 if (i915_is_ggtt(vma->vm))
 177                         seq_printf(m, ", type: %u)", vma->ggtt_view.type);
 178                 else
 179                         seq_puts(m, ")");
 180         }
 181         if (obj->stolen)
 182                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 183         if (obj->pin_display || obj->fault_mappable) {
 184                 char s[3], *t = s;
 185                 if (obj->pin_display)
 186                         *t++ = 'p';
 187                 if (obj->fault_mappable)
 188                         *t++ = 'f';
 189                 *t = '\0';
 190                 seq_printf(m, " (%s mappable)", s);
 191         }
 192         if (obj->last_write_req != NULL)
 193                 seq_printf(m, " (%s)",
 194                            i915_gem_request_get_ring(obj->last_write_req)->name);
 195         if (obj->frontbuffer_bits)
 196                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 197 }
 198
 199 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
 200 {
 201         seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
 202         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 203         seq_putc(m, ' ');
 204 }
 205
 206 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 207 {
 208         struct drm_info_node *node = m->private;
 209         uintptr_t list = (uintptr_t) node->info_ent->data;
 210         struct list_head *head;
 211         struct drm_device *dev = node->minor->dev;
 212         struct drm_i915_private *dev_priv = dev->dev_private;
 213         struct i915_address_space *vm = &dev_priv->gtt.base;
 214         struct i915_vma *vma;
 215         u64 total_obj_size, total_gtt_size;
 216         int count, ret;
 217
 218         ret = mutex_lock_interruptible(&dev->struct_mutex);
 219         if (ret)
 220                 return ret;
 221
 222         /* FIXME: the user of this interface might want more than just GGTT */
 223         switch (list) {
 224         case ACTIVE_LIST:
 225                 seq_puts(m, "Active:\n");
 226                 head = &vm->active_list;
 227                 break;
 228         case INACTIVE_LIST:
 229                 seq_puts(m, "Inactive:\n");
 230                 head = &vm->inactive_list;
 231                 break;
 232         default:
 233                 mutex_unlock(&dev->struct_mutex);
 234                 return -EINVAL;
 235         }
 236
 237         total_obj_size = total_gtt_size = count = 0;
 238         list_for_each_entry(vma, head, mm_list) {
 239                 seq_printf(m, "   ");
 240                 describe_obj(m, vma->obj);
 241                 seq_printf(m, "\n");
 242                 total_obj_size += vma->obj->base.size;
 243                 total_gtt_size += vma->node.size;
 244                 count++;
 245         }
 246         mutex_unlock(&dev->struct_mutex);
 247
 248         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 249                    count, total_obj_size, total_gtt_size);
 250         return 0;
 251 }
 252
 253 static int obj_rank_by_stolen(void *priv,
 254                               struct list_head *A, struct list_head *B)
 255 {
 256         struct drm_i915_gem_object *a =
 257                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 258         struct drm_i915_gem_object *b =
 259                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 260
 261         return a->stolen->start - b->stolen->start;
 262 }
 263
 264 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 265 {
 266         struct drm_info_node *node = m->private;
 267         struct drm_device *dev = node->minor->dev;
 268         struct drm_i915_private *dev_priv = dev->dev_private;
 269         struct drm_i915_gem_object *obj;
 270         u64 total_obj_size, total_gtt_size;
 271         LIST_HEAD(stolen);
 272         int count, ret;
 273
 274         ret = mutex_lock_interruptible(&dev->struct_mutex);
 275         if (ret)
 276                 return ret;
 277
 278         total_obj_size = total_gtt_size = count = 0;
 279         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 280                 if (obj->stolen == NULL)
 281                         continue;
 282
 283                 list_add(&obj->obj_exec_link, &stolen);
 284
 285                 total_obj_size += obj->base.size;
 286                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 287                 count++;
 288         }
 289         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 290                 if (obj->stolen == NULL)
 291                         continue;
 292
 293                 list_add(&obj->obj_exec_link, &stolen);
 294
 295                 total_obj_size += obj->base.size;
 296                 count++;
 297         }
 298         list_sort(NULL, &stolen, obj_rank_by_stolen);
 299         seq_puts(m, "Stolen:\n");
 300         while (!list_empty(&stolen)) {
 301                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 302                 seq_puts(m, "   ");
 303                 describe_obj(m, obj);
 304                 seq_putc(m, '\n');
 305                 list_del_init(&obj->obj_exec_link);
 306         }
 307         mutex_unlock(&dev->struct_mutex);
 308
 309         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 310                    count, total_obj_size, total_gtt_size);
 311         return 0;
 312 }
 313
 314 #define count_objects(list, member) do { \
 315         list_for_each_entry(obj, list, member) { \
 316                 size += i915_gem_obj_total_ggtt_size(obj); \
 317                 ++count; \
 318                 if (obj->map_and_fenceable) { \
 319                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 320                         ++mappable_count; \
 321                 } \
 322         } \
 323 } while (0)
 324
 325 struct file_stats {
 326         struct drm_i915_file_private *file_priv;
 327         unsigned long count;
 328         u64 total, unbound;
 329         u64 global, shared;
 330         u64 active, inactive;
 331 };
 332
 333 static int per_file_stats(int id, void *ptr, void *data)
 334 {
 335         struct drm_i915_gem_object *obj = ptr;
 336         struct file_stats *stats = data;
 337         struct i915_vma *vma;
 338
 339         stats->count++;
 340         stats->total += obj->base.size;
 341
 342         if (obj->base.name || obj->base.dma_buf)
 343                 stats->shared += obj->base.size;
 344
 345         if (USES_FULL_PPGTT(obj->base.dev)) {
 346                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
 347                         struct i915_hw_ppgtt *ppgtt;
 348
 349                         if (!drm_mm_node_allocated(&vma->node))
 350                                 continue;
 351
 352                         if (i915_is_ggtt(vma->vm)) {
 353                                 stats->global += obj->base.size;
 354                                 continue;
 355                         }
 356
 357                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 358                         if (ppgtt->file_priv != stats->file_priv)
 359                                 continue;
 360
 361                         if (obj->active) /* XXX per-vma statistic */
 362                                 stats->active += obj->base.size;
 363                         else
 364                                 stats->inactive += obj->base.size;
 365
 366                         return 0;
 367                 }
 368         } else {
 369                 if (i915_gem_obj_ggtt_bound(obj)) {
 370                         stats->global += obj->base.size;
 371                         if (obj->active)
 372                                 stats->active += obj->base.size;
 373                         else
 374                                 stats->inactive += obj->base.size;
 375                         return 0;
 376                 }
 377         }
 378
 379         if (!list_empty(&obj->global_list))
 380                 stats->unbound += obj->base.size;
 381
 382         return 0;
 383 }
 384
 385 #define print_file_stats(m, name, stats) do { \
 386         if (stats.count) \
 387                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 388                            name, \
 389                            stats.count, \
 390                            stats.total, \
 391                            stats.active, \
 392                            stats.inactive, \
 393                            stats.global, \
 394                            stats.shared, \
 395                            stats.unbound); \
 396 } while (0)
 397
 398 static void print_batch_pool_stats(struct seq_file *m,
 399                                    struct drm_i915_private *dev_priv)
 400 {
 401         struct drm_i915_gem_object *obj;
 402         struct file_stats stats;
 403         struct intel_engine_cs *ring;
 404         int i, j;
 405
 406         memset(&stats, 0, sizeof(stats));
 407
 408         for_each_ring(ring, dev_priv, i) {
 409                 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
 410                         list_for_each_entry(obj,
 411                                             &ring->batch_pool.cache_list[j],
 412                                             batch_pool_link)
 413                                 per_file_stats(0, obj, &stats);
 414                 }
 415         }
 416
 417         print_file_stats(m, "[k]batch pool", stats);
 418 }
 419
 420 #define count_vmas(list, member) do { \
 421         list_for_each_entry(vma, list, member) { \
 422                 size += i915_gem_obj_total_ggtt_size(vma->obj); \
 423                 ++count; \
 424                 if (vma->obj->map_and_fenceable) { \
 425                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 426                         ++mappable_count; \
 427                 } \
 428         } \
 429 } while (0)
 430
 431 static int i915_gem_object_info(struct seq_file *m, void* data)
 432 {
 433         struct drm_info_node *node = m->private;
 434         struct drm_device *dev = node->minor->dev;
 435         struct drm_i915_private *dev_priv = dev->dev_private;
 436         u32 count, mappable_count, purgeable_count;
 437         u64 size, mappable_size, purgeable_size;
 438         struct drm_i915_gem_object *obj;
 439         struct i915_address_space *vm = &dev_priv->gtt.base;
 440         struct drm_file *file;
 441         struct i915_vma *vma;
 442         int ret;
 443
 444         ret = mutex_lock_interruptible(&dev->struct_mutex);
 445         if (ret)
 446                 return ret;
 447
 448         seq_printf(m, "%u objects, %zu bytes\n",
 449                    dev_priv->mm.object_count,
 450                    dev_priv->mm.object_memory);
 451
 452         size = count = mappable_size = mappable_count = 0;
 453         count_objects(&dev_priv->mm.bound_list, global_list);
 454         seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
 455                    count, mappable_count, size, mappable_size);
 456
 457         size = count = mappable_size = mappable_count = 0;
 458         count_vmas(&vm->active_list, mm_list);
 459         seq_printf(m, "  %u [%u] active objects, %llu [%llu] bytes\n",
 460                    count, mappable_count, size, mappable_size);
 461
 462         size = count = mappable_size = mappable_count = 0;
 463         count_vmas(&vm->inactive_list, mm_list);
 464         seq_printf(m, "  %u [%u] inactive objects, %llu [%llu] bytes\n",
 465                    count, mappable_count, size, mappable_size);
 466
 467         size = count = purgeable_size = purgeable_count = 0;
 468         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 469                 size += obj->base.size, ++count;
 470                 if (obj->madv == I915_MADV_DONTNEED)
 471                         purgeable_size += obj->base.size, ++purgeable_count;
 472         }
 473         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 474
 475         size = count = mappable_size = mappable_count = 0;
 476         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 477                 if (obj->fault_mappable) {
 478                         size += i915_gem_obj_ggtt_size(obj);
 479                         ++count;
 480                 }
 481                 if (obj->pin_display) {
 482                         mappable_size += i915_gem_obj_ggtt_size(obj);
 483                         ++mappable_count;
 484                 }
 485                 if (obj->madv == I915_MADV_DONTNEED) {
 486                         purgeable_size += obj->base.size;
 487                         ++purgeable_count;
 488                 }
 489         }
 490         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 491                    purgeable_count, purgeable_size);
 492         seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
 493                    mappable_count, mappable_size);
 494         seq_printf(m, "%u fault mappable objects, %llu bytes\n",
 495                    count, size);
 496
 497         seq_printf(m, "%llu [%llu] gtt total\n",
 498                    dev_priv->gtt.base.total,
 499                    (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 500
 501         seq_putc(m, '\n');
 502         print_batch_pool_stats(m, dev_priv);
 503         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 504                 struct file_stats stats;
 505                 struct task_struct *task;
 506
 507                 memset(&stats, 0, sizeof(stats));
 508                 stats.file_priv = file->driver_priv;
 509                 spin_lock(&file->table_lock);
 510                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 511                 spin_unlock(&file->table_lock);
 512                 /*
 513                  * Although we have a valid reference on file->pid, that does
 514                  * not guarantee that the task_struct who called get_pid() is
 515                  * still alive (e.g. get_pid(current) => fork() => exit()).
 516                  * Therefore, we need to protect this ->comm access using RCU.
 517                  */
 518                 rcu_read_lock();
 519                 task = pid_task(file->pid, PIDTYPE_PID);
 520                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 521                 rcu_read_unlock();
 522         }
 523
 524         mutex_unlock(&dev->struct_mutex);
 525
 526         return 0;
 527 }
 528
 529 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 530 {
 531         struct drm_info_node *node = m->private;
 532         struct drm_device *dev = node->minor->dev;
 533         uintptr_t list = (uintptr_t) node->info_ent->data;
 534         struct drm_i915_private *dev_priv = dev->dev_private;
 535         struct drm_i915_gem_object *obj;
 536         u64 total_obj_size, total_gtt_size;
 537         int count, ret;
 538
 539         ret = mutex_lock_interruptible(&dev->struct_mutex);
 540         if (ret)
 541                 return ret;
 542
 543         total_obj_size = total_gtt_size = count = 0;
 544         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 545                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 546                         continue;
 547
 548                 seq_puts(m, "   ");
 549                 describe_obj(m, obj);
 550                 seq_putc(m, '\n');
 551                 total_obj_size += obj->base.size;
 552                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 553                 count++;
 554         }
 555
 556         mutex_unlock(&dev->struct_mutex);
 557
 558         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 559                    count, total_obj_size, total_gtt_size);
 560
 561         return 0;
 562 }
 563
 564 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 565 {
 566         struct drm_info_node *node = m->private;
 567         struct drm_device *dev = node->minor->dev;
 568         struct drm_i915_private *dev_priv = dev->dev_private;
 569         struct intel_crtc *crtc;
 570         int ret;
 571
 572         ret = mutex_lock_interruptible(&dev->struct_mutex);
 573         if (ret)
 574                 return ret;
 575
 576         for_each_intel_crtc(dev, crtc) {
 577                 const char pipe = pipe_name(crtc->pipe);
 578                 const char plane = plane_name(crtc->plane);
 579                 struct intel_unpin_work *work;
 580
 581                 spin_lock_irq(&dev->event_lock);
 582                 work = crtc->unpin_work;
 583                 if (work == NULL) {
 584                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 585                                    pipe, plane);
 586                 } else {
 587                         u32 addr;
 588
 589                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 590                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 591                                            pipe, plane);
 592                         } else {
 593                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 594                                            pipe, plane);
 595                         }
 596                         if (work->flip_queued_req) {
 597                                 struct intel_engine_cs *ring =
 598                                         i915_gem_request_get_ring(work->flip_queued_req);
 599
 600                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 601                                            ring->name,
 602                                            i915_gem_request_get_seqno(work->flip_queued_req),
 603                                            dev_priv->next_seqno,
 604                                            ring->get_seqno(ring, true),
 605                                            i915_gem_request_completed(work->flip_queued_req, true));
 606                         } else
 607                                 seq_printf(m, "Flip not associated with any ring\n");
 608                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 609                                    work->flip_queued_vblank,
 610                                    work->flip_ready_vblank,
 611                                    drm_crtc_vblank_count(&crtc->base));
 612                         if (work->enable_stall_check)
 613                                 seq_puts(m, "Stall check enabled, ");
 614                         else
 615                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 616                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 617
 618                         if (INTEL_INFO(dev)->gen >= 4)
 619                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 620                         else
 621                                 addr = I915_READ(DSPADDR(crtc->plane));
 622                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 623
 624                         if (work->pending_flip_obj) {
 625                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 626                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 627                         }
 628                 }
 629                 spin_unlock_irq(&dev->event_lock);
 630         }
 631
 632         mutex_unlock(&dev->struct_mutex);
 633
 634         return 0;
 635 }
 636
 637 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 638 {
 639         struct drm_info_node *node = m->private;
 640         struct drm_device *dev = node->minor->dev;
 641         struct drm_i915_private *dev_priv = dev->dev_private;
 642         struct drm_i915_gem_object *obj;
 643         struct intel_engine_cs *ring;
 644         int total = 0;
 645         int ret, i, j;
 646
 647         ret = mutex_lock_interruptible(&dev->struct_mutex);
 648         if (ret)
 649                 return ret;
 650
 651         for_each_ring(ring, dev_priv, i) {
 652                 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
 653                         int count;
 654
 655                         count = 0;
 656                         list_for_each_entry(obj,
 657                                             &ring->batch_pool.cache_list[j],
 658                                             batch_pool_link)
 659                                 count++;
 660                         seq_printf(m, "%s cache[%d]: %d objects\n",
 661                                    ring->name, j, count);
 662
 663                         list_for_each_entry(obj,
 664                                             &ring->batch_pool.cache_list[j],
 665                                             batch_pool_link) {
 666                                 seq_puts(m, "   ");
 667                                 describe_obj(m, obj);
 668                                 seq_putc(m, '\n');
 669                         }
 670
 671                         total += count;
 672                 }
 673         }
 674
 675         seq_printf(m, "total: %d\n", total);
 676
 677         mutex_unlock(&dev->struct_mutex);
 678
 679         return 0;
 680 }
 681
 682 static int i915_gem_request_info(struct seq_file *m, void *data)
 683 {
 684         struct drm_info_node *node = m->private;
 685         struct drm_device *dev = node->minor->dev;
 686         struct drm_i915_private *dev_priv = dev->dev_private;
 687         struct intel_engine_cs *ring;
 688         struct drm_i915_gem_request *req;
 689         int ret, any, i;
 690
 691         ret = mutex_lock_interruptible(&dev->struct_mutex);
 692         if (ret)
 693                 return ret;
 694
 695         any = 0;
 696         for_each_ring(ring, dev_priv, i) {
 697                 int count;
 698
 699                 count = 0;
 700                 list_for_each_entry(req, &ring->request_list, list)
 701                         count++;
 702                 if (count == 0)
 703                         continue;
 704
 705                 seq_printf(m, "%s requests: %d\n", ring->name, count);
 706                 list_for_each_entry(req, &ring->request_list, list) {
 707                         struct task_struct *task;
 708
 709                         rcu_read_lock();
 710                         task = NULL;
 711                         if (req->pid)
 712                                 task = pid_task(req->pid, PIDTYPE_PID);
 713                         seq_printf(m, "    %x @ %d: %s [%d]\n",
 714                                    req->seqno,
 715                                    (int) (jiffies - req->emitted_jiffies),
 716                                    task ? task->comm : "<unknown>",
 717                                    task ? task->pid : -1);
 718                         rcu_read_unlock();
 719                 }
 720
 721                 any++;
 722         }
 723         mutex_unlock(&dev->struct_mutex);
 724
 725         if (any == 0)
 726                 seq_puts(m, "No requests\n");
 727
 728         return 0;
 729 }
 730
 731 static void i915_ring_seqno_info(struct seq_file *m,
 732                                  struct intel_engine_cs *ring)
 733 {
 734         if (ring->get_seqno) {
 735                 seq_printf(m, "Current sequence (%s): %x\n",
 736                            ring->name, ring->get_seqno(ring, false));
 737         }
 738 }
 739
 740 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 741 {
 742         struct drm_info_node *node = m->private;
 743         struct drm_device *dev = node->minor->dev;
 744         struct drm_i915_private *dev_priv = dev->dev_private;
 745         struct intel_engine_cs *ring;
 746         int ret, i;
 747
 748         ret = mutex_lock_interruptible(&dev->struct_mutex);
 749         if (ret)
 750                 return ret;
 751         intel_runtime_pm_get(dev_priv);
 752
 753         for_each_ring(ring, dev_priv, i)
 754                 i915_ring_seqno_info(m, ring);
 755
 756         intel_runtime_pm_put(dev_priv);
 757         mutex_unlock(&dev->struct_mutex);
 758
 759         return 0;
 760 }
 761
 762
 763 static int i915_interrupt_info(struct seq_file *m, void *data)
 764 {
 765         struct drm_info_node *node = m->private;
 766         struct drm_device *dev = node->minor->dev;
 767         struct drm_i915_private *dev_priv = dev->dev_private;
 768         struct intel_engine_cs *ring;
 769         int ret, i, pipe;
 770
 771         ret = mutex_lock_interruptible(&dev->struct_mutex);
 772         if (ret)
 773                 return ret;
 774         intel_runtime_pm_get(dev_priv);
 775
 776         if (IS_CHERRYVIEW(dev)) {
 777                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 778                            I915_READ(GEN8_MASTER_IRQ));
 779
 780                 seq_printf(m, "Display IER:\t%08x\n",
 781                            I915_READ(VLV_IER));
 782                 seq_printf(m, "Display IIR:\t%08x\n",
 783                            I915_READ(VLV_IIR));
 784                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 785                            I915_READ(VLV_IIR_RW));
 786                 seq_printf(m, "Display IMR:\t%08x\n",
 787                            I915_READ(VLV_IMR));
 788                 for_each_pipe(dev_priv, pipe)
 789                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 790                                    pipe_name(pipe),
 791                                    I915_READ(PIPESTAT(pipe)));
 792
 793                 seq_printf(m, "Port hotplug:\t%08x\n",
 794                            I915_READ(PORT_HOTPLUG_EN));
 795                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 796                            I915_READ(VLV_DPFLIPSTAT));
 797                 seq_printf(m, "DPINVGTT:\t%08x\n",
 798                            I915_READ(DPINVGTT));
 799
 800                 for (i = 0; i < 4; i++) {
 801                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 802                                    i, I915_READ(GEN8_GT_IMR(i)));
 803                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 804                                    i, I915_READ(GEN8_GT_IIR(i)));
 805                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 806                                    i, I915_READ(GEN8_GT_IER(i)));
 807                 }
 808
 809                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 810                            I915_READ(GEN8_PCU_IMR));
 811                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 812                            I915_READ(GEN8_PCU_IIR));
 813                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 814                            I915_READ(GEN8_PCU_IER));
 815         } else if (INTEL_INFO(dev)->gen >= 8) {
 816                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 817                            I915_READ(GEN8_MASTER_IRQ));
 818
 819                 for (i = 0; i < 4; i++) {
 820                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 821                                    i, I915_READ(GEN8_GT_IMR(i)));
 822                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 823                                    i, I915_READ(GEN8_GT_IIR(i)));
 824                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 825                                    i, I915_READ(GEN8_GT_IER(i)));
 826                 }
 827
 828                 for_each_pipe(dev_priv, pipe) {
 829                         if (!intel_display_power_is_enabled(dev_priv,
 830                                                 POWER_DOMAIN_PIPE(pipe))) {
 831                                 seq_printf(m, "Pipe %c power disabled\n",
 832                                            pipe_name(pipe));
 833                                 continue;
 834                         }
 835                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 836                                    pipe_name(pipe),
 837                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 838                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 839                                    pipe_name(pipe),
 840                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 841                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 842                                    pipe_name(pipe),
 843                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 844                 }
 845
 846                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 847                            I915_READ(GEN8_DE_PORT_IMR));
 848                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 849                            I915_READ(GEN8_DE_PORT_IIR));
 850                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 851                            I915_READ(GEN8_DE_PORT_IER));
 852
 853                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 854                            I915_READ(GEN8_DE_MISC_IMR));
 855                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 856                            I915_READ(GEN8_DE_MISC_IIR));
 857                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 858                            I915_READ(GEN8_DE_MISC_IER));
 859
 860                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 861                            I915_READ(GEN8_PCU_IMR));
 862                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 863                            I915_READ(GEN8_PCU_IIR));
 864                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 865                            I915_READ(GEN8_PCU_IER));
 866         } else if (IS_VALLEYVIEW(dev)) {
 867                 seq_printf(m, "Display IER:\t%08x\n",
 868                            I915_READ(VLV_IER));
 869                 seq_printf(m, "Display IIR:\t%08x\n",
 870                            I915_READ(VLV_IIR));
 871                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 872                            I915_READ(VLV_IIR_RW));
 873                 seq_printf(m, "Display IMR:\t%08x\n",
 874                            I915_READ(VLV_IMR));
 875                 for_each_pipe(dev_priv, pipe)
 876                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 877                                    pipe_name(pipe),
 878                                    I915_READ(PIPESTAT(pipe)));
 879
 880                 seq_printf(m, "Master IER:\t%08x\n",
 881                            I915_READ(VLV_MASTER_IER));
 882
 883                 seq_printf(m, "Render IER:\t%08x\n",
 884                            I915_READ(GTIER));
 885                 seq_printf(m, "Render IIR:\t%08x\n",
 886                            I915_READ(GTIIR));
 887                 seq_printf(m, "Render IMR:\t%08x\n",
 888                            I915_READ(GTIMR));
 889
 890                 seq_printf(m, "PM IER:\t\t%08x\n",
 891                            I915_READ(GEN6_PMIER));
 892                 seq_printf(m, "PM IIR:\t\t%08x\n",
 893                            I915_READ(GEN6_PMIIR));
 894                 seq_printf(m, "PM IMR:\t\t%08x\n",
 895                            I915_READ(GEN6_PMIMR));
 896
 897                 seq_printf(m, "Port hotplug:\t%08x\n",
 898                            I915_READ(PORT_HOTPLUG_EN));
 899                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 900                            I915_READ(VLV_DPFLIPSTAT));
 901                 seq_printf(m, "DPINVGTT:\t%08x\n",
 902                            I915_READ(DPINVGTT));
 903
 904         } else if (!HAS_PCH_SPLIT(dev)) {
 905                 seq_printf(m, "Interrupt enable:    %08x\n",
 906                            I915_READ(IER));
 907                 seq_printf(m, "Interrupt identity:  %08x\n",
 908                            I915_READ(IIR));
 909                 seq_printf(m, "Interrupt mask:      %08x\n",
 910                            I915_READ(IMR));
 911                 for_each_pipe(dev_priv, pipe)
 912                         seq_printf(m, "Pipe %c stat:         %08x\n",
 913                                    pipe_name(pipe),
 914                                    I915_READ(PIPESTAT(pipe)));
 915         } else {
 916                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 917                            I915_READ(DEIER));
 918                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 919                            I915_READ(DEIIR));
 920                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 921                            I915_READ(DEIMR));
 922                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 923                            I915_READ(SDEIER));
 924                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 925                            I915_READ(SDEIIR));
 926                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 927                            I915_READ(SDEIMR));
 928                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 929                            I915_READ(GTIER));
 930                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 931                            I915_READ(GTIIR));
 932                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 933                            I915_READ(GTIMR));
 934         }
 935         for_each_ring(ring, dev_priv, i) {
 936                 if (INTEL_INFO(dev)->gen >= 6) {
 937                         seq_printf(m,
 938                                    "Graphics Interrupt mask (%s):       %08x\n",
 939                                    ring->name, I915_READ_IMR(ring));
 940                 }
 941                 i915_ring_seqno_info(m, ring);
 942         }
 943         intel_runtime_pm_put(dev_priv);
 944         mutex_unlock(&dev->struct_mutex);
 945
 946         return 0;
 947 }
 948
 949 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 950 {
 951         struct drm_info_node *node = m->private;
 952         struct drm_device *dev = node->minor->dev;
 953         struct drm_i915_private *dev_priv = dev->dev_private;
 954         int i, ret;
 955
 956         ret = mutex_lock_interruptible(&dev->struct_mutex);
 957         if (ret)
 958                 return ret;
 959
 960         seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 961         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 962         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 963                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 964
 965                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 966                            i, dev_priv->fence_regs[i].pin_count);
 967                 if (obj == NULL)
 968                         seq_puts(m, "unused");
 969                 else
 970                         describe_obj(m, obj);
 971                 seq_putc(m, '\n');
 972         }
 973
 974         mutex_unlock(&dev->struct_mutex);
 975         return 0;
 976 }
 977
 978 static int i915_hws_info(struct seq_file *m, void *data)
 979 {
 980         struct drm_info_node *node = m->private;
 981         struct drm_device *dev = node->minor->dev;
 982         struct drm_i915_private *dev_priv = dev->dev_private;
 983         struct intel_engine_cs *ring;
 984         const u32 *hws;
 985         int i;
 986
 987         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 988         hws = ring->status_page.page_addr;
 989         if (hws == NULL)
 990                 return 0;
 991
 992         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 993                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 994                            i * 4,
 995                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 996         }
 997         return 0;
 998 }
 999
1000 static ssize_t
1001 i915_error_state_write(struct file *filp,
1002                        const char __user *ubuf,
1003                        size_t cnt,
1004                        loff_t *ppos)
1005 {
1006         struct i915_error_state_file_priv *error_priv = filp->private_data;
1007         struct drm_device *dev = error_priv->dev;
1008         int ret;
1009
1010         DRM_DEBUG_DRIVER("Resetting error state\n");
1011
1012         ret = mutex_lock_interruptible(&dev->struct_mutex);
1013         if (ret)
1014                 return ret;
1015
1016         i915_destroy_error_state(dev);
1017         mutex_unlock(&dev->struct_mutex);
1018
1019         return cnt;
1020 }
1021
1022 static int i915_error_state_open(struct inode *inode, struct file *file)
1023 {
1024         struct drm_device *dev = inode->i_private;
1025         struct i915_error_state_file_priv *error_priv;
1026
1027         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1028         if (!error_priv)
1029                 return -ENOMEM;
1030
1031         error_priv->dev = dev;
1032
1033         i915_error_state_get(dev, error_priv);
1034
1035         file->private_data = error_priv;
1036
1037         return 0;
1038 }
1039
1040 static int i915_error_state_release(struct inode *inode, struct file *file)
1041 {
1042         struct i915_error_state_file_priv *error_priv = file->private_data;
1043
1044         i915_error_state_put(error_priv);
1045         kfree(error_priv);
1046
1047         return 0;
1048 }
1049
1050 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1051                                      size_t count, loff_t *pos)
1052 {
1053         struct i915_error_state_file_priv *error_priv = file->private_data;
1054         struct drm_i915_error_state_buf error_str;
1055         loff_t tmp_pos = 0;
1056         ssize_t ret_count = 0;
1057         int ret;
1058
1059         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1060         if (ret)
1061                 return ret;
1062
1063         ret = i915_error_state_to_str(&error_str, error_priv);
1064         if (ret)
1065                 goto out;
1066
1067         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1068                                             error_str.buf,
1069                                             error_str.bytes);
1070
1071         if (ret_count < 0)
1072                 ret = ret_count;
1073         else
1074                 *pos = error_str.start + ret_count;
1075 out:
1076         i915_error_state_buf_release(&error_str);
1077         return ret ?: ret_count;
1078 }
1079
1080 static const struct file_operations i915_error_state_fops = {
1081         .owner = THIS_MODULE,
1082         .open = i915_error_state_open,
1083         .read = i915_error_state_read,
1084         .write = i915_error_state_write,
1085         .llseek = default_llseek,
1086         .release = i915_error_state_release,
1087 };
1088
1089 static int
1090 i915_next_seqno_get(void *data, u64 *val)
1091 {
1092         struct drm_device *dev = data;
1093         struct drm_i915_private *dev_priv = dev->dev_private;
1094         int ret;
1095
1096         ret = mutex_lock_interruptible(&dev->struct_mutex);
1097         if (ret)
1098                 return ret;
1099
1100         *val = dev_priv->next_seqno;
1101         mutex_unlock(&dev->struct_mutex);
1102
1103         return 0;
1104 }
1105
1106 static int
1107 i915_next_seqno_set(void *data, u64 val)
1108 {
1109         struct drm_device *dev = data;
1110         int ret;
1111
1112         ret = mutex_lock_interruptible(&dev->struct_mutex);
1113         if (ret)
1114                 return ret;
1115
1116         ret = i915_gem_set_seqno(dev, val);
1117         mutex_unlock(&dev->struct_mutex);
1118
1119         return ret;
1120 }
1121
1122 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1123                         i915_next_seqno_get, i915_next_seqno_set,
1124                         "0x%llx\n");
1125
1126 static int i915_frequency_info(struct seq_file *m, void *unused)
1127 {
1128         struct drm_info_node *node = m->private;
1129         struct drm_device *dev = node->minor->dev;
1130         struct drm_i915_private *dev_priv = dev->dev_private;
1131         int ret = 0;
1132
1133         intel_runtime_pm_get(dev_priv);
1134
1135         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1136
1137         if (IS_GEN5(dev)) {
1138                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1139                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1140
1141                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1142                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1143                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1144                            MEMSTAT_VID_SHIFT);
1145                 seq_printf(m, "Current P-state: %d\n",
1146                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1147         } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1148                    IS_BROADWELL(dev) || IS_GEN9(dev)) {
1149                 u32 rp_state_limits;
1150                 u32 gt_perf_status;
1151                 u32 rp_state_cap;
1152                 u32 rpmodectl, rpinclimit, rpdeclimit;
1153                 u32 rpstat, cagf, reqf;
1154                 u32 rpupei, rpcurup, rpprevup;
1155                 u32 rpdownei, rpcurdown, rpprevdown;
1156                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1157                 int max_freq;
1158
1159                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1160                 if (IS_BROXTON(dev)) {
1161                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1162                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1163                 } else {
1164                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1165                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1166                 }
1167
1168                 /* RPSTAT1 is in the GT power well */
1169                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1170                 if (ret)
1171                         goto out;
1172
1173                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1174
1175                 reqf = I915_READ(GEN6_RPNSWREQ);
1176                 if (IS_GEN9(dev))
1177                         reqf >>= 23;
1178                 else {
1179                         reqf &= ~GEN6_TURBO_DISABLE;
1180                         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1181                                 reqf >>= 24;
1182                         else
1183                                 reqf >>= 25;
1184                 }
1185                 reqf = intel_gpu_freq(dev_priv, reqf);
1186
1187                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1188                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1189                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1190
1191                 rpstat = I915_READ(GEN6_RPSTAT1);
1192                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1193                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1194                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1195                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1196                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1197                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1198                 if (IS_GEN9(dev))
1199                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1200                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1201                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1202                 else
1203                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1204                 cagf = intel_gpu_freq(dev_priv, cagf);
1205
1206                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1207                 mutex_unlock(&dev->struct_mutex);
1208
1209                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1210                         pm_ier = I915_READ(GEN6_PMIER);
1211                         pm_imr = I915_READ(GEN6_PMIMR);
1212                         pm_isr = I915_READ(GEN6_PMISR);
1213                         pm_iir = I915_READ(GEN6_PMIIR);
1214                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1215                 } else {
1216                         pm_ier = I915_READ(GEN8_GT_IER(2));
1217                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1218                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1219                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1220                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1221                 }
1222                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1223                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1224                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1225                 seq_printf(m, "Render p-state ratio: %d\n",
1226                            (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1227                 seq_printf(m, "Render p-state VID: %d\n",
1228                            gt_perf_status & 0xff);
1229                 seq_printf(m, "Render p-state limit: %d\n",
1230                            rp_state_limits & 0xff);
1231                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1232                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1233                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1234                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1235                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1236                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1237                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1238                            GEN6_CURICONT_MASK);
1239                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1240                            GEN6_CURBSYTAVG_MASK);
1241                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1242                            GEN6_CURBSYTAVG_MASK);
1243                 seq_printf(m, "Up threshold: %d%%\n",
1244                            dev_priv->rps.up_threshold);
1245
1246                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1247                            GEN6_CURIAVG_MASK);
1248                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1249                            GEN6_CURBSYTAVG_MASK);
1250                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1251                            GEN6_CURBSYTAVG_MASK);
1252                 seq_printf(m, "Down threshold: %d%%\n",
1253                            dev_priv->rps.down_threshold);
1254
1255                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1256                             rp_state_cap >> 16) & 0xff;
1257                 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1258                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1259                            intel_gpu_freq(dev_priv, max_freq));
1260
1261                 max_freq = (rp_state_cap & 0xff00) >> 8;
1262                 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1263                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1264                            intel_gpu_freq(dev_priv, max_freq));
1265
1266                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1267                             rp_state_cap >> 0) & 0xff;
1268                 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1269                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1270                            intel_gpu_freq(dev_priv, max_freq));
1271                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1272                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1273
1274                 seq_printf(m, "Current freq: %d MHz\n",
1275                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1276                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1277                 seq_printf(m, "Idle freq: %d MHz\n",
1278                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1279                 seq_printf(m, "Min freq: %d MHz\n",
1280                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1281                 seq_printf(m, "Max freq: %d MHz\n",
1282                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1283                 seq_printf(m,
1284                            "efficient (RPe) frequency: %d MHz\n",
1285                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1286         } else if (IS_VALLEYVIEW(dev)) {
1287                 u32 freq_sts;
1288
1289                 mutex_lock(&dev_priv->rps.hw_lock);
1290                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1291                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1292                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1293
1294                 seq_printf(m, "actual GPU freq: %d MHz\n",
1295                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1296
1297                 seq_printf(m, "current GPU freq: %d MHz\n",
1298                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1299
1300                 seq_printf(m, "max GPU freq: %d MHz\n",
1301                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1302
1303                 seq_printf(m, "min GPU freq: %d MHz\n",
1304                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1305
1306                 seq_printf(m, "idle GPU freq: %d MHz\n",
1307                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1308
1309                 seq_printf(m,
1310                            "efficient (RPe) frequency: %d MHz\n",
1311                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1312                 mutex_unlock(&dev_priv->rps.hw_lock);
1313         } else {
1314                 seq_puts(m, "no P-state info available\n");
1315         }
1316
1317 out:
1318         intel_runtime_pm_put(dev_priv);
1319         return ret;
1320 }
1321
1322 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1323 {
1324         struct drm_info_node *node = m->private;
1325         struct drm_device *dev = node->minor->dev;
1326         struct drm_i915_private *dev_priv = dev->dev_private;
1327         struct intel_engine_cs *ring;
1328         u64 acthd[I915_NUM_RINGS];
1329         u32 seqno[I915_NUM_RINGS];
1330         int i;
1331
1332         if (!i915.enable_hangcheck) {
1333                 seq_printf(m, "Hangcheck disabled\n");
1334                 return 0;
1335         }
1336
1337         intel_runtime_pm_get(dev_priv);
1338
1339         for_each_ring(ring, dev_priv, i) {
1340                 seqno[i] = ring->get_seqno(ring, false);
1341                 acthd[i] = intel_ring_get_active_head(ring);
1342         }
1343
1344         intel_runtime_pm_put(dev_priv);
1345
1346         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1347                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1348                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1349                                             jiffies));
1350         } else
1351                 seq_printf(m, "Hangcheck inactive\n");
1352
1353         for_each_ring(ring, dev_priv, i) {
1354                 seq_printf(m, "%s:\n", ring->name);
1355                 seq_printf(m, "\tseqno = %x [current %x]\n",
1356                            ring->hangcheck.seqno, seqno[i]);
1357                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1358                            (long long)ring->hangcheck.acthd,
1359                            (long long)acthd[i]);
1360                 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1361                            (long long)ring->hangcheck.max_acthd);
1362                 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1363                 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1364         }
1365
1366         return 0;
1367 }
1368
1369 static int ironlake_drpc_info(struct seq_file *m)
1370 {
1371         struct drm_info_node *node = m->private;
1372         struct drm_device *dev = node->minor->dev;
1373         struct drm_i915_private *dev_priv = dev->dev_private;
1374         u32 rgvmodectl, rstdbyctl;
1375         u16 crstandvid;
1376         int ret;
1377
1378         ret = mutex_lock_interruptible(&dev->struct_mutex);
1379         if (ret)
1380                 return ret;
1381         intel_runtime_pm_get(dev_priv);
1382
1383         rgvmodectl = I915_READ(MEMMODECTL);
1384         rstdbyctl = I915_READ(RSTDBYCTL);
1385         crstandvid = I915_READ16(CRSTANDVID);
1386
1387         intel_runtime_pm_put(dev_priv);
1388         mutex_unlock(&dev->struct_mutex);
1389
1390         seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1391                    "yes" : "no");
1392         seq_printf(m, "Boost freq: %d\n",
1393                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1394                    MEMMODE_BOOST_FREQ_SHIFT);
1395         seq_printf(m, "HW control enabled: %s\n",
1396                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1397         seq_printf(m, "SW control enabled: %s\n",
1398                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1399         seq_printf(m, "Gated voltage change: %s\n",
1400                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1401         seq_printf(m, "Starting frequency: P%d\n",
1402                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1403         seq_printf(m, "Max P-state: P%d\n",
1404                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1405         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1406         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1407         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1408         seq_printf(m, "Render standby enabled: %s\n",
1409                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1410         seq_puts(m, "Current RS state: ");
1411         switch (rstdbyctl & RSX_STATUS_MASK) {
1412         case RSX_STATUS_ON:
1413                 seq_puts(m, "on\n");
1414                 break;
1415         case RSX_STATUS_RC1:
1416                 seq_puts(m, "RC1\n");
1417                 break;
1418         case RSX_STATUS_RC1E:
1419                 seq_puts(m, "RC1E\n");
1420                 break;
1421         case RSX_STATUS_RS1:
1422                 seq_puts(m, "RS1\n");
1423                 break;
1424         case RSX_STATUS_RS2:
1425                 seq_puts(m, "RS2 (RC6)\n");
1426                 break;
1427         case RSX_STATUS_RS3:
1428                 seq_puts(m, "RC3 (RC6+)\n");
1429                 break;
1430         default:
1431                 seq_puts(m, "unknown\n");
1432                 break;
1433         }
1434
1435         return 0;
1436 }
1437
1438 static int i915_forcewake_domains(struct seq_file *m, void *data)
1439 {
1440         struct drm_info_node *node = m->private;
1441         struct drm_device *dev = node->minor->dev;
1442         struct drm_i915_private *dev_priv = dev->dev_private;
1443         struct intel_uncore_forcewake_domain *fw_domain;
1444         int i;
1445
1446         spin_lock_irq(&dev_priv->uncore.lock);
1447         for_each_fw_domain(fw_domain, dev_priv, i) {
1448                 seq_printf(m, "%s.wake_count = %u\n",
1449                            intel_uncore_forcewake_domain_to_str(i),
1450                            fw_domain->wake_count);
1451         }
1452         spin_unlock_irq(&dev_priv->uncore.lock);
1453
1454         return 0;
1455 }
1456
1457 static int vlv_drpc_info(struct seq_file *m)
1458 {
1459         struct drm_info_node *node = m->private;
1460         struct drm_device *dev = node->minor->dev;
1461         struct drm_i915_private *dev_priv = dev->dev_private;
1462         u32 rpmodectl1, rcctl1, pw_status;
1463
1464         intel_runtime_pm_get(dev_priv);
1465
1466         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1467         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1468         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1469
1470         intel_runtime_pm_put(dev_priv);
1471
1472         seq_printf(m, "Video Turbo Mode: %s\n",
1473                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1474         seq_printf(m, "Turbo enabled: %s\n",
1475                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1476         seq_printf(m, "HW control enabled: %s\n",
1477                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1478         seq_printf(m, "SW control enabled: %s\n",
1479                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1480                           GEN6_RP_MEDIA_SW_MODE));
1481         seq_printf(m, "RC6 Enabled: %s\n",
1482                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1483                                         GEN6_RC_CTL_EI_MODE(1))));
1484         seq_printf(m, "Render Power Well: %s\n",
1485                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1486         seq_printf(m, "Media Power Well: %s\n",
1487                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1488
1489         seq_printf(m, "Render RC6 residency since boot: %u\n",
1490                    I915_READ(VLV_GT_RENDER_RC6));
1491         seq_printf(m, "Media RC6 residency since boot: %u\n",
1492                    I915_READ(VLV_GT_MEDIA_RC6));
1493
1494         return i915_forcewake_domains(m, NULL);
1495 }
1496
1497 static int gen6_drpc_info(struct seq_file *m)
1498 {
1499         struct drm_info_node *node = m->private;
1500         struct drm_device *dev = node->minor->dev;
1501         struct drm_i915_private *dev_priv = dev->dev_private;
1502         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1503         unsigned forcewake_count;
1504         int count = 0, ret;
1505
1506         ret = mutex_lock_interruptible(&dev->struct_mutex);
1507         if (ret)
1508                 return ret;
1509         intel_runtime_pm_get(dev_priv);
1510
1511         spin_lock_irq(&dev_priv->uncore.lock);
1512         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1513         spin_unlock_irq(&dev_priv->uncore.lock);
1514
1515         if (forcewake_count) {
1516                 seq_puts(m, "RC information inaccurate because somebody "
1517                             "holds a forcewake reference \n");
1518         } else {
1519                 /* NB: we cannot use forcewake, else we read the wrong values */
1520                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1521                         udelay(10);
1522                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1523         }
1524
1525         gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1526         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1527
1528         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1529         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1530         mutex_unlock(&dev->struct_mutex);
1531         mutex_lock(&dev_priv->rps.hw_lock);
1532         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1533         mutex_unlock(&dev_priv->rps.hw_lock);
1534
1535         intel_runtime_pm_put(dev_priv);
1536
1537         seq_printf(m, "Video Turbo Mode: %s\n",
1538                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1539         seq_printf(m, "HW control enabled: %s\n",
1540                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1541         seq_printf(m, "SW control enabled: %s\n",
1542                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1543                           GEN6_RP_MEDIA_SW_MODE));
1544         seq_printf(m, "RC1e Enabled: %s\n",
1545                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1546         seq_printf(m, "RC6 Enabled: %s\n",
1547                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1548         seq_printf(m, "Deep RC6 Enabled: %s\n",
1549                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1550         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1551                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1552         seq_puts(m, "Current RC state: ");
1553         switch (gt_core_status & GEN6_RCn_MASK) {
1554         case GEN6_RC0:
1555                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1556                         seq_puts(m, "Core Power Down\n");
1557                 else
1558                         seq_puts(m, "on\n");
1559                 break;
1560         case GEN6_RC3:
1561                 seq_puts(m, "RC3\n");
1562                 break;
1563         case GEN6_RC6:
1564                 seq_puts(m, "RC6\n");
1565                 break;
1566         case GEN6_RC7:
1567                 seq_puts(m, "RC7\n");
1568                 break;
1569         default:
1570                 seq_puts(m, "Unknown\n");
1571                 break;
1572         }
1573
1574         seq_printf(m, "Core Power Down: %s\n",
1575                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1576
1577         /* Not exactly sure what this is */
1578         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1579                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1580         seq_printf(m, "RC6 residency since boot: %u\n",
1581                    I915_READ(GEN6_GT_GFX_RC6));
1582         seq_printf(m, "RC6+ residency since boot: %u\n",
1583                    I915_READ(GEN6_GT_GFX_RC6p));
1584         seq_printf(m, "RC6++ residency since boot: %u\n",
1585                    I915_READ(GEN6_GT_GFX_RC6pp));
1586
1587         seq_printf(m, "RC6   voltage: %dmV\n",
1588                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1589         seq_printf(m, "RC6+  voltage: %dmV\n",
1590                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1591         seq_printf(m, "RC6++ voltage: %dmV\n",
1592                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1593         return 0;
1594 }
1595
1596 static int i915_drpc_info(struct seq_file *m, void *unused)
1597 {
1598         struct drm_info_node *node = m->private;
1599         struct drm_device *dev = node->minor->dev;
1600
1601         if (IS_VALLEYVIEW(dev))
1602                 return vlv_drpc_info(m);
1603         else if (INTEL_INFO(dev)->gen >= 6)
1604                 return gen6_drpc_info(m);
1605         else
1606                 return ironlake_drpc_info(m);
1607 }
1608
1609 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1610 {
1611         struct drm_info_node *node = m->private;
1612         struct drm_device *dev = node->minor->dev;
1613         struct drm_i915_private *dev_priv = dev->dev_private;
1614
1615         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1616                    dev_priv->fb_tracking.busy_bits);
1617
1618         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1619                    dev_priv->fb_tracking.flip_bits);
1620
1621         return 0;
1622 }
1623
1624 static int i915_fbc_status(struct seq_file *m, void *unused)
1625 {
1626         struct drm_info_node *node = m->private;
1627         struct drm_device *dev = node->minor->dev;
1628         struct drm_i915_private *dev_priv = dev->dev_private;
1629
1630         if (!HAS_FBC(dev)) {
1631                 seq_puts(m, "FBC unsupported on this chipset\n");
1632                 return 0;
1633         }
1634
1635         intel_runtime_pm_get(dev_priv);
1636         mutex_lock(&dev_priv->fbc.lock);
1637
1638         if (intel_fbc_enabled(dev_priv))
1639                 seq_puts(m, "FBC enabled\n");
1640         else
1641                 seq_printf(m, "FBC disabled: %s\n",
1642                           intel_no_fbc_reason_str(dev_priv->fbc.no_fbc_reason));
1643
1644         if (INTEL_INFO(dev_priv)->gen >= 7)
1645                 seq_printf(m, "Compressing: %s\n",
1646                            yesno(I915_READ(FBC_STATUS2) &
1647                                  FBC_COMPRESSION_MASK));
1648
1649         mutex_unlock(&dev_priv->fbc.lock);
1650         intel_runtime_pm_put(dev_priv);
1651
1652         return 0;
1653 }
1654
1655 static int i915_fbc_fc_get(void *data, u64 *val)
1656 {
1657         struct drm_device *dev = data;
1658         struct drm_i915_private *dev_priv = dev->dev_private;
1659
1660         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1661                 return -ENODEV;
1662
1663         *val = dev_priv->fbc.false_color;
1664
1665         return 0;
1666 }
1667
1668 static int i915_fbc_fc_set(void *data, u64 val)
1669 {
1670         struct drm_device *dev = data;
1671         struct drm_i915_private *dev_priv = dev->dev_private;
1672         u32 reg;
1673
1674         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1675                 return -ENODEV;
1676
1677         mutex_lock(&dev_priv->fbc.lock);
1678
1679         reg = I915_READ(ILK_DPFC_CONTROL);
1680         dev_priv->fbc.false_color = val;
1681
1682         I915_WRITE(ILK_DPFC_CONTROL, val ?
1683                    (reg | FBC_CTL_FALSE_COLOR) :
1684                    (reg & ~FBC_CTL_FALSE_COLOR));
1685
1686         mutex_unlock(&dev_priv->fbc.lock);
1687         return 0;
1688 }
1689
1690 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1691                         i915_fbc_fc_get, i915_fbc_fc_set,
1692                         "%llu\n");
1693
1694 static int i915_ips_status(struct seq_file *m, void *unused)
1695 {
1696         struct drm_info_node *node = m->private;
1697         struct drm_device *dev = node->minor->dev;
1698         struct drm_i915_private *dev_priv = dev->dev_private;
1699
1700         if (!HAS_IPS(dev)) {
1701                 seq_puts(m, "not supported\n");
1702                 return 0;
1703         }
1704
1705         intel_runtime_pm_get(dev_priv);
1706
1707         seq_printf(m, "Enabled by kernel parameter: %s\n",
1708                    yesno(i915.enable_ips));
1709
1710         if (INTEL_INFO(dev)->gen >= 8) {
1711                 seq_puts(m, "Currently: unknown\n");
1712         } else {
1713                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1714                         seq_puts(m, "Currently: enabled\n");
1715                 else
1716                         seq_puts(m, "Currently: disabled\n");
1717         }
1718
1719         intel_runtime_pm_put(dev_priv);
1720
1721         return 0;
1722 }
1723
1724 static int i915_sr_status(struct seq_file *m, void *unused)
1725 {
1726         struct drm_info_node *node = m->private;
1727         struct drm_device *dev = node->minor->dev;
1728         struct drm_i915_private *dev_priv = dev->dev_private;
1729         bool sr_enabled = false;
1730
1731         intel_runtime_pm_get(dev_priv);
1732
1733         if (HAS_PCH_SPLIT(dev))
1734                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1735         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1736                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1737         else if (IS_I915GM(dev))
1738                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1739         else if (IS_PINEVIEW(dev))
1740                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1741
1742         intel_runtime_pm_put(dev_priv);
1743
1744         seq_printf(m, "self-refresh: %s\n",
1745                    sr_enabled ? "enabled" : "disabled");
1746
1747         return 0;
1748 }
1749
1750 static int i915_emon_status(struct seq_file *m, void *unused)
1751 {
1752         struct drm_info_node *node = m->private;
1753         struct drm_device *dev = node->minor->dev;
1754         struct drm_i915_private *dev_priv = dev->dev_private;
1755         unsigned long temp, chipset, gfx;
1756         int ret;
1757
1758         if (!IS_GEN5(dev))
1759                 return -ENODEV;
1760
1761         ret = mutex_lock_interruptible(&dev->struct_mutex);
1762         if (ret)
1763                 return ret;
1764
1765         temp = i915_mch_val(dev_priv);
1766         chipset = i915_chipset_val(dev_priv);
1767         gfx = i915_gfx_val(dev_priv);
1768         mutex_unlock(&dev->struct_mutex);
1769
1770         seq_printf(m, "GMCH temp: %ld\n", temp);
1771         seq_printf(m, "Chipset power: %ld\n", chipset);
1772         seq_printf(m, "GFX power: %ld\n", gfx);
1773         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1774
1775         return 0;
1776 }
1777
1778 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1779 {
1780         struct drm_info_node *node = m->private;
1781         struct drm_device *dev = node->minor->dev;
1782         struct drm_i915_private *dev_priv = dev->dev_private;
1783         int ret = 0;
1784         int gpu_freq, ia_freq;
1785         unsigned int max_gpu_freq, min_gpu_freq;
1786
1787         if (!HAS_CORE_RING_FREQ(dev)) {
1788                 seq_puts(m, "unsupported on this chipset\n");
1789                 return 0;
1790         }
1791
1792         intel_runtime_pm_get(dev_priv);
1793
1794         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1795
1796         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1797         if (ret)
1798                 goto out;
1799
1800         if (IS_SKYLAKE(dev)) {
1801                 /* Convert GT frequency to 50 HZ units */
1802                 min_gpu_freq =
1803                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1804                 max_gpu_freq =
1805                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1806         } else {
1807                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1808                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1809         }
1810
1811         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1812
1813         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1814                 ia_freq = gpu_freq;
1815                 sandybridge_pcode_read(dev_priv,
1816                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1817                                        &ia_freq);
1818                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1819                            intel_gpu_freq(dev_priv, (gpu_freq *
1820                                 (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))),
1821                            ((ia_freq >> 0) & 0xff) * 100,
1822                            ((ia_freq >> 8) & 0xff) * 100);
1823         }
1824
1825         mutex_unlock(&dev_priv->rps.hw_lock);
1826
1827 out:
1828         intel_runtime_pm_put(dev_priv);
1829         return ret;
1830 }
1831
1832 static int i915_opregion(struct seq_file *m, void *unused)
1833 {
1834         struct drm_info_node *node = m->private;
1835         struct drm_device *dev = node->minor->dev;
1836         struct drm_i915_private *dev_priv = dev->dev_private;
1837         struct intel_opregion *opregion = &dev_priv->opregion;
1838         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1839         int ret;
1840
1841         if (data == NULL)
1842                 return -ENOMEM;
1843
1844         ret = mutex_lock_interruptible(&dev->struct_mutex);
1845         if (ret)
1846                 goto out;
1847
1848         if (opregion->header) {
1849                 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1850                 seq_write(m, data, OPREGION_SIZE);
1851         }
1852
1853         mutex_unlock(&dev->struct_mutex);
1854
1855 out:
1856         kfree(data);
1857         return 0;
1858 }
1859
1860 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1861 {
1862         struct drm_info_node *node = m->private;
1863         struct drm_device *dev = node->minor->dev;
1864         struct intel_fbdev *ifbdev = NULL;
1865         struct intel_framebuffer *fb;
1866
1867 #ifdef CONFIG_DRM_I915_FBDEV
1868         struct drm_i915_private *dev_priv = dev->dev_private;
1869
1870         ifbdev = dev_priv->fbdev;
1871         fb = to_intel_framebuffer(ifbdev->helper.fb);
1872
1873         seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1874                    fb->base.width,
1875                    fb->base.height,
1876                    fb->base.depth,
1877                    fb->base.bits_per_pixel,
1878                    fb->base.modifier[0],
1879                    atomic_read(&fb->base.refcount.refcount));
1880         describe_obj(m, fb->obj);
1881         seq_putc(m, '\n');
1882 #endif
1883
1884         mutex_lock(&dev->mode_config.fb_lock);
1885         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1886                 if (ifbdev && &fb->base == ifbdev->helper.fb)
1887                         continue;
1888
1889                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1890                            fb->base.width,
1891                            fb->base.height,
1892                            fb->base.depth,
1893                            fb->base.bits_per_pixel,
1894                            fb->base.modifier[0],
1895                            atomic_read(&fb->base.refcount.refcount));
1896                 describe_obj(m, fb->obj);
1897                 seq_putc(m, '\n');
1898         }
1899         mutex_unlock(&dev->mode_config.fb_lock);
1900
1901         return 0;
1902 }
1903
1904 static void describe_ctx_ringbuf(struct seq_file *m,
1905                                  struct intel_ringbuffer *ringbuf)
1906 {
1907         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1908                    ringbuf->space, ringbuf->head, ringbuf->tail,
1909                    ringbuf->last_retired_head);
1910 }
1911
1912 static int i915_context_status(struct seq_file *m, void *unused)
1913 {
1914         struct drm_info_node *node = m->private;
1915         struct drm_device *dev = node->minor->dev;
1916         struct drm_i915_private *dev_priv = dev->dev_private;
1917         struct intel_engine_cs *ring;
1918         struct intel_context *ctx;
1919         int ret, i;
1920
1921         ret = mutex_lock_interruptible(&dev->struct_mutex);
1922         if (ret)
1923                 return ret;
1924
1925         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1926                 if (!i915.enable_execlists &&
1927                     ctx->legacy_hw_ctx.rcs_state == NULL)
1928                         continue;
1929
1930                 seq_puts(m, "HW context ");
1931                 describe_ctx(m, ctx);
1932                 for_each_ring(ring, dev_priv, i) {
1933                         if (ring->default_context == ctx)
1934                                 seq_printf(m, "(default context %s) ",
1935                                            ring->name);
1936                 }
1937
1938                 if (i915.enable_execlists) {
1939                         seq_putc(m, '\n');
1940                         for_each_ring(ring, dev_priv, i) {
1941                                 struct drm_i915_gem_object *ctx_obj =
1942                                         ctx->engine[i].state;
1943                                 struct intel_ringbuffer *ringbuf =
1944                                         ctx->engine[i].ringbuf;
1945
1946                                 seq_printf(m, "%s: ", ring->name);
1947                                 if (ctx_obj)
1948                                         describe_obj(m, ctx_obj);
1949                                 if (ringbuf)
1950                                         describe_ctx_ringbuf(m, ringbuf);
1951                                 seq_putc(m, '\n');
1952                         }
1953                 } else {
1954                         describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1955                 }
1956
1957                 seq_putc(m, '\n');
1958         }
1959
1960         mutex_unlock(&dev->struct_mutex);
1961
1962         return 0;
1963 }
1964
1965 static void i915_dump_lrc_obj(struct seq_file *m,
1966                               struct intel_engine_cs *ring,
1967                               struct drm_i915_gem_object *ctx_obj)
1968 {
1969         struct page *page;
1970         uint32_t *reg_state;
1971         int j;
1972         unsigned long ggtt_offset = 0;
1973
1974         if (ctx_obj == NULL) {
1975                 seq_printf(m, "Context on %s with no gem object\n",
1976                            ring->name);
1977                 return;
1978         }
1979
1980         seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1981                    intel_execlists_ctx_id(ctx_obj));
1982
1983         if (!i915_gem_obj_ggtt_bound(ctx_obj))
1984                 seq_puts(m, "\tNot bound in GGTT\n");
1985         else
1986                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1987
1988         if (i915_gem_object_get_pages(ctx_obj)) {
1989                 seq_puts(m, "\tFailed to get pages for context object\n");
1990                 return;
1991         }
1992
1993         page = i915_gem_object_get_page(ctx_obj, 1);
1994         if (!WARN_ON(page == NULL)) {
1995                 reg_state = kmap_atomic(page);
1996
1997                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1998                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1999                                    ggtt_offset + 4096 + (j * 4),
2000                                    reg_state[j], reg_state[j + 1],
2001                                    reg_state[j + 2], reg_state[j + 3]);
2002                 }
2003                 kunmap_atomic(reg_state);
2004         }
2005
2006         seq_putc(m, '\n');
2007 }
2008
2009 static int i915_dump_lrc(struct seq_file *m, void *unused)
2010 {
2011         struct drm_info_node *node = (struct drm_info_node *) m->private;
2012         struct drm_device *dev = node->minor->dev;
2013         struct drm_i915_private *dev_priv = dev->dev_private;
2014         struct intel_engine_cs *ring;
2015         struct intel_context *ctx;
2016         int ret, i;
2017
2018         if (!i915.enable_execlists) {
2019                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2020                 return 0;
2021         }
2022
2023         ret = mutex_lock_interruptible(&dev->struct_mutex);
2024         if (ret)
2025                 return ret;
2026
2027         list_for_each_entry(ctx, &dev_priv->context_list, link) {
2028                 for_each_ring(ring, dev_priv, i) {
2029                         if (ring->default_context != ctx)
2030                                 i915_dump_lrc_obj(m, ring,
2031                                                   ctx->engine[i].state);
2032                 }
2033         }
2034
2035         mutex_unlock(&dev->struct_mutex);
2036
2037         return 0;
2038 }
2039
2040 static int i915_execlists(struct seq_file *m, void *data)
2041 {
2042         struct drm_info_node *node = (struct drm_info_node *)m->private;
2043         struct drm_device *dev = node->minor->dev;
2044         struct drm_i915_private *dev_priv = dev->dev_private;
2045         struct intel_engine_cs *ring;
2046         u32 status_pointer;
2047         u8 read_pointer;
2048         u8 write_pointer;
2049         u32 status;
2050         u32 ctx_id;
2051         struct list_head *cursor;
2052         int ring_id, i;
2053         int ret;
2054
2055         if (!i915.enable_execlists) {
2056                 seq_puts(m, "Logical Ring Contexts are disabled\n");
2057                 return 0;
2058         }
2059
2060         ret = mutex_lock_interruptible(&dev->struct_mutex);
2061         if (ret)
2062                 return ret;
2063
2064         intel_runtime_pm_get(dev_priv);
2065
2066         for_each_ring(ring, dev_priv, ring_id) {
2067                 struct drm_i915_gem_request *head_req = NULL;
2068                 int count = 0;
2069                 unsigned long flags;
2070
2071                 seq_printf(m, "%s\n", ring->name);
2072
2073                 status = I915_READ(RING_EXECLIST_STATUS(ring));
2074                 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
2075                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2076                            status, ctx_id);
2077
2078                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2079                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2080
2081                 read_pointer = ring->next_context_status_buffer;
2082                 write_pointer = status_pointer & 0x07;
2083                 if (read_pointer > write_pointer)
2084                         write_pointer += 6;
2085                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2086                            read_pointer, write_pointer);
2087
2088                 for (i = 0; i < 6; i++) {
2089                         status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2090                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2091
2092                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2093                                    i, status, ctx_id);
2094                 }
2095
2096                 spin_lock_irqsave(&ring->execlist_lock, flags);
2097                 list_for_each(cursor, &ring->execlist_queue)
2098                         count++;
2099                 head_req = list_first_entry_or_null(&ring->execlist_queue,
2100                                 struct drm_i915_gem_request, execlist_link);
2101                 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2102
2103                 seq_printf(m, "\t%d requests in queue\n", count);
2104                 if (head_req) {
2105                         struct drm_i915_gem_object *ctx_obj;
2106
2107                         ctx_obj = head_req->ctx->engine[ring_id].state;
2108                         seq_printf(m, "\tHead request id: %u\n",
2109                                    intel_execlists_ctx_id(ctx_obj));
2110                         seq_printf(m, "\tHead request tail: %u\n",
2111                                    head_req->tail);
2112                 }
2113
2114                 seq_putc(m, '\n');
2115         }
2116
2117         intel_runtime_pm_put(dev_priv);
2118         mutex_unlock(&dev->struct_mutex);
2119
2120         return 0;
2121 }
2122
2123 static const char *swizzle_string(unsigned swizzle)
2124 {
2125         switch (swizzle) {
2126         case I915_BIT_6_SWIZZLE_NONE:
2127                 return "none";
2128         case I915_BIT_6_SWIZZLE_9:
2129                 return "bit9";
2130         case I915_BIT_6_SWIZZLE_9_10:
2131                 return "bit9/bit10";
2132         case I915_BIT_6_SWIZZLE_9_11:
2133                 return "bit9/bit11";
2134         case I915_BIT_6_SWIZZLE_9_10_11:
2135                 return "bit9/bit10/bit11";
2136         case I915_BIT_6_SWIZZLE_9_17:
2137                 return "bit9/bit17";
2138         case I915_BIT_6_SWIZZLE_9_10_17:
2139                 return "bit9/bit10/bit17";
2140         case I915_BIT_6_SWIZZLE_UNKNOWN:
2141                 return "unknown";
2142         }
2143
2144         return "bug";
2145 }
2146
2147 static int i915_swizzle_info(struct seq_file *m, void *data)
2148 {
2149         struct drm_info_node *node = m->private;
2150         struct drm_device *dev = node->minor->dev;
2151         struct drm_i915_private *dev_priv = dev->dev_private;
2152         int ret;
2153
2154         ret = mutex_lock_interruptible(&dev->struct_mutex);
2155         if (ret)
2156                 return ret;
2157         intel_runtime_pm_get(dev_priv);
2158
2159         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2160                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2161         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2162                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2163
2164         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2165                 seq_printf(m, "DDC = 0x%08x\n",
2166                            I915_READ(DCC));
2167                 seq_printf(m, "DDC2 = 0x%08x\n",
2168                            I915_READ(DCC2));
2169                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2170                            I915_READ16(C0DRB3));
2171                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2172                            I915_READ16(C1DRB3));
2173         } else if (INTEL_INFO(dev)->gen >= 6) {
2174                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2175                            I915_READ(MAD_DIMM_C0));
2176                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2177                            I915_READ(MAD_DIMM_C1));
2178                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2179                            I915_READ(MAD_DIMM_C2));
2180                 seq_printf(m, "TILECTL = 0x%08x\n",
2181                            I915_READ(TILECTL));
2182                 if (INTEL_INFO(dev)->gen >= 8)
2183                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2184                                    I915_READ(GAMTARBMODE));
2185                 else
2186                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2187                                    I915_READ(ARB_MODE));
2188                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2189                            I915_READ(DISP_ARB_CTL));
2190         }
2191
2192         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2193                 seq_puts(m, "L-shaped memory detected\n");
2194
2195         intel_runtime_pm_put(dev_priv);
2196         mutex_unlock(&dev->struct_mutex);
2197
2198         return 0;
2199 }
2200
2201 static int per_file_ctx(int id, void *ptr, void *data)
2202 {
2203         struct intel_context *ctx = ptr;
2204         struct seq_file *m = data;
2205         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2206
2207         if (!ppgtt) {
2208                 seq_printf(m, "  no ppgtt for context %d\n",
2209                            ctx->user_handle);
2210                 return 0;
2211         }
2212
2213         if (i915_gem_context_is_default(ctx))
2214                 seq_puts(m, "  default context:\n");
2215         else
2216                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2217         ppgtt->debug_dump(ppgtt, m);
2218
2219         return 0;
2220 }
2221
2222 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2223 {
2224         struct drm_i915_private *dev_priv = dev->dev_private;
2225         struct intel_engine_cs *ring;
2226         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2227         int unused, i;
2228
2229         if (!ppgtt)
2230                 return;
2231
2232         for_each_ring(ring, dev_priv, unused) {
2233                 seq_printf(m, "%s\n", ring->name);
2234                 for (i = 0; i < 4; i++) {
2235                         u32 offset = 0x270 + i * 8;
2236                         u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2237                         pdp <<= 32;
2238                         pdp |= I915_READ(ring->mmio_base + offset);
2239                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2240                 }
2241         }
2242 }
2243
2244 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2245 {
2246         struct drm_i915_private *dev_priv = dev->dev_private;
2247         struct intel_engine_cs *ring;
2248         struct drm_file *file;
2249         int i;
2250
2251         if (INTEL_INFO(dev)->gen == 6)
2252                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2253
2254         for_each_ring(ring, dev_priv, i) {
2255                 seq_printf(m, "%s\n", ring->name);
2256                 if (INTEL_INFO(dev)->gen == 7)
2257                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2258                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2259                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2260                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2261         }
2262         if (dev_priv->mm.aliasing_ppgtt) {
2263                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2264
2265                 seq_puts(m, "aliasing PPGTT:\n");
2266                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2267
2268                 ppgtt->debug_dump(ppgtt, m);
2269         }
2270
2271         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2272                 struct drm_i915_file_private *file_priv = file->driver_priv;
2273
2274                 seq_printf(m, "proc: %s\n",
2275                            get_pid_task(file->pid, PIDTYPE_PID)->comm);
2276                 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
2277         }
2278         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2279 }
2280
2281 static int i915_ppgtt_info(struct seq_file *m, void *data)
2282 {
2283         struct drm_info_node *node = m->private;
2284         struct drm_device *dev = node->minor->dev;
2285         struct drm_i915_private *dev_priv = dev->dev_private;
2286
2287         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2288         if (ret)
2289                 return ret;
2290         intel_runtime_pm_get(dev_priv);
2291
2292         if (INTEL_INFO(dev)->gen >= 8)
2293                 gen8_ppgtt_info(m, dev);
2294         else if (INTEL_INFO(dev)->gen >= 6)
2295                 gen6_ppgtt_info(m, dev);
2296
2297         intel_runtime_pm_put(dev_priv);
2298         mutex_unlock(&dev->struct_mutex);
2299
2300         return 0;
2301 }
2302
2303 static int count_irq_waiters(struct drm_i915_private *i915)
2304 {
2305         struct intel_engine_cs *ring;
2306         int count = 0;
2307         int i;
2308
2309         for_each_ring(ring, i915, i)
2310                 count += ring->irq_refcount;
2311
2312         return count;
2313 }
2314
2315 static int i915_rps_boost_info(struct seq_file *m, void *data)
2316 {
2317         struct drm_info_node *node = m->private;
2318         struct drm_device *dev = node->minor->dev;
2319         struct drm_i915_private *dev_priv = dev->dev_private;
2320         struct drm_file *file;
2321
2322         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2323         seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2324         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2325         seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2326                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2327                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2328                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2329                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2330                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2331         spin_lock(&dev_priv->rps.client_lock);
2332         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2333                 struct drm_i915_file_private *file_priv = file->driver_priv;
2334                 struct task_struct *task;
2335
2336                 rcu_read_lock();
2337                 task = pid_task(file->pid, PIDTYPE_PID);
2338                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2339                            task ? task->comm : "<unknown>",
2340                            task ? task->pid : -1,
2341                            file_priv->rps.boosts,
2342                            list_empty(&file_priv->rps.link) ? "" : ", active");
2343                 rcu_read_unlock();
2344         }
2345         seq_printf(m, "Semaphore boosts: %d%s\n",
2346                    dev_priv->rps.semaphores.boosts,
2347                    list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2348         seq_printf(m, "MMIO flip boosts: %d%s\n",
2349                    dev_priv->rps.mmioflips.boosts,
2350                    list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2351         seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2352         spin_unlock(&dev_priv->rps.client_lock);
2353
2354         return 0;
2355 }
2356
2357 static int i915_llc(struct seq_file *m, void *data)
2358 {
2359         struct drm_info_node *node = m->private;
2360         struct drm_device *dev = node->minor->dev;
2361         struct drm_i915_private *dev_priv = dev->dev_private;
2362
2363         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2364         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2365         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2366
2367         return 0;
2368 }
2369
2370 static int i915_edp_psr_status(struct seq_file *m, void *data)
2371 {
2372         struct drm_info_node *node = m->private;
2373         struct drm_device *dev = node->minor->dev;
2374         struct drm_i915_private *dev_priv = dev->dev_private;
2375         u32 psrperf = 0;
2376         u32 stat[3];
2377         enum pipe pipe;
2378         bool enabled = false;
2379
2380         if (!HAS_PSR(dev)) {
2381                 seq_puts(m, "PSR not supported\n");
2382                 return 0;
2383         }
2384
2385         intel_runtime_pm_get(dev_priv);
2386
2387         mutex_lock(&dev_priv->psr.lock);
2388         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2389         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2390         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2391         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2392         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2393                    dev_priv->psr.busy_frontbuffer_bits);
2394         seq_printf(m, "Re-enable work scheduled: %s\n",
2395                    yesno(work_busy(&dev_priv->psr.work.work)));
2396
2397         if (HAS_DDI(dev))
2398                 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2399         else {
2400                 for_each_pipe(dev_priv, pipe) {
2401                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2402                                 VLV_EDP_PSR_CURR_STATE_MASK;
2403                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2404                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2405                                 enabled = true;
2406                 }
2407         }
2408         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2409
2410         if (!HAS_DDI(dev))
2411                 for_each_pipe(dev_priv, pipe) {
2412                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2413                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2414                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2415                 }
2416         seq_puts(m, "\n");
2417
2418         /* CHV PSR has no kind of performance counter */
2419         if (HAS_DDI(dev)) {
2420                 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2421                         EDP_PSR_PERF_CNT_MASK;
2422
2423                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2424         }
2425         mutex_unlock(&dev_priv->psr.lock);
2426
2427         intel_runtime_pm_put(dev_priv);
2428         return 0;
2429 }
2430
2431 static int i915_sink_crc(struct seq_file *m, void *data)
2432 {
2433         struct drm_info_node *node = m->private;
2434         struct drm_device *dev = node->minor->dev;
2435         struct intel_encoder *encoder;
2436         struct intel_connector *connector;
2437         struct intel_dp *intel_dp = NULL;
2438         int ret;
2439         u8 crc[6];
2440
2441         drm_modeset_lock_all(dev);
2442         for_each_intel_connector(dev, connector) {
2443
2444                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2445                         continue;
2446
2447                 if (!connector->base.encoder)
2448                         continue;
2449
2450                 encoder = to_intel_encoder(connector->base.encoder);
2451                 if (encoder->type != INTEL_OUTPUT_EDP)
2452                         continue;
2453
2454                 intel_dp = enc_to_intel_dp(&encoder->base);
2455
2456                 ret = intel_dp_sink_crc(intel_dp, crc);
2457                 if (ret)
2458                         goto out;
2459
2460                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2461                            crc[0], crc[1], crc[2],
2462                            crc[3], crc[4], crc[5]);
2463                 goto out;
2464         }
2465         ret = -ENODEV;
2466 out:
2467         drm_modeset_unlock_all(dev);
2468         return ret;
2469 }
2470
2471 static int i915_energy_uJ(struct seq_file *m, void *data)
2472 {
2473         struct drm_info_node *node = m->private;
2474         struct drm_device *dev = node->minor->dev;
2475         struct drm_i915_private *dev_priv = dev->dev_private;
2476         u64 power;
2477         u32 units;
2478
2479         if (INTEL_INFO(dev)->gen < 6)
2480                 return -ENODEV;
2481
2482         intel_runtime_pm_get(dev_priv);
2483
2484         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2485         power = (power & 0x1f00) >> 8;
2486         units = 1000000 / (1 << power); /* convert to uJ */
2487         power = I915_READ(MCH_SECP_NRG_STTS);
2488         power *= units;
2489
2490         intel_runtime_pm_put(dev_priv);
2491
2492         seq_printf(m, "%llu", (long long unsigned)power);
2493
2494         return 0;
2495 }
2496
2497 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2498 {
2499         struct drm_info_node *node = m->private;
2500         struct drm_device *dev = node->minor->dev;
2501         struct drm_i915_private *dev_priv = dev->dev_private;
2502
2503         if (!HAS_RUNTIME_PM(dev)) {
2504                 seq_puts(m, "not supported\n");
2505                 return 0;
2506         }
2507
2508         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2509         seq_printf(m, "IRQs disabled: %s\n",
2510                    yesno(!intel_irqs_enabled(dev_priv)));
2511 #ifdef CONFIG_PM
2512         seq_printf(m, "Usage count: %d\n",
2513                    atomic_read(&dev->dev->power.usage_count));
2514 #else
2515         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2516 #endif
2517
2518         return 0;
2519 }
2520
2521 static const char *power_domain_str(enum intel_display_power_domain domain)
2522 {
2523         switch (domain) {
2524         case POWER_DOMAIN_PIPE_A:
2525                 return "PIPE_A";
2526         case POWER_DOMAIN_PIPE_B:
2527                 return "PIPE_B";
2528         case POWER_DOMAIN_PIPE_C:
2529                 return "PIPE_C";
2530         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2531                 return "PIPE_A_PANEL_FITTER";
2532         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2533                 return "PIPE_B_PANEL_FITTER";
2534         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2535                 return "PIPE_C_PANEL_FITTER";
2536         case POWER_DOMAIN_TRANSCODER_A:
2537                 return "TRANSCODER_A";
2538         case POWER_DOMAIN_TRANSCODER_B:
2539                 return "TRANSCODER_B";
2540         case POWER_DOMAIN_TRANSCODER_C:
2541                 return "TRANSCODER_C";
2542         case POWER_DOMAIN_TRANSCODER_EDP:
2543                 return "TRANSCODER_EDP";
2544         case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2545                 return "PORT_DDI_A_2_LANES";
2546         case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2547                 return "PORT_DDI_A_4_LANES";
2548         case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2549                 return "PORT_DDI_B_2_LANES";
2550         case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2551                 return "PORT_DDI_B_4_LANES";
2552         case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2553                 return "PORT_DDI_C_2_LANES";
2554         case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2555                 return "PORT_DDI_C_4_LANES";
2556         case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2557                 return "PORT_DDI_D_2_LANES";
2558         case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2559                 return "PORT_DDI_D_4_LANES";
2560         case POWER_DOMAIN_PORT_DSI:
2561                 return "PORT_DSI";
2562         case POWER_DOMAIN_PORT_CRT:
2563                 return "PORT_CRT";
2564         case POWER_DOMAIN_PORT_OTHER:
2565                 return "PORT_OTHER";
2566         case POWER_DOMAIN_VGA:
2567                 return "VGA";
2568         case POWER_DOMAIN_AUDIO:
2569                 return "AUDIO";
2570         case POWER_DOMAIN_PLLS:
2571                 return "PLLS";
2572         case POWER_DOMAIN_AUX_A:
2573                 return "AUX_A";
2574         case POWER_DOMAIN_AUX_B:
2575                 return "AUX_B";
2576         case POWER_DOMAIN_AUX_C:
2577                 return "AUX_C";
2578         case POWER_DOMAIN_AUX_D:
2579                 return "AUX_D";
2580         case POWER_DOMAIN_INIT:
2581                 return "INIT";
2582         default:
2583                 MISSING_CASE(domain);
2584                 return "?";
2585         }
2586 }
2587
2588 static int i915_power_domain_info(struct seq_file *m, void *unused)
2589 {
2590         struct drm_info_node *node = m->private;
2591         struct drm_device *dev = node->minor->dev;
2592         struct drm_i915_private *dev_priv = dev->dev_private;
2593         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2594         int i;
2595
2596         mutex_lock(&power_domains->lock);
2597
2598         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2599         for (i = 0; i < power_domains->power_well_count; i++) {
2600                 struct i915_power_well *power_well;
2601                 enum intel_display_power_domain power_domain;
2602
2603                 power_well = &power_domains->power_wells[i];
2604                 seq_printf(m, "%-25s %d\n", power_well->name,
2605                            power_well->count);
2606
2607                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2608                      power_domain++) {
2609                         if (!(BIT(power_domain) & power_well->domains))
2610                                 continue;
2611
2612                         seq_printf(m, "  %-23s %d\n",
2613                                  power_domain_str(power_domain),
2614                                  power_domains->domain_use_count[power_domain]);
2615                 }
2616         }
2617
2618         mutex_unlock(&power_domains->lock);
2619
2620         return 0;
2621 }
2622
2623 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2624                                  struct drm_display_mode *mode)
2625 {
2626         int i;
2627
2628         for (i = 0; i < tabs; i++)
2629                 seq_putc(m, '\t');
2630
2631         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2632                    mode->base.id, mode->name,
2633                    mode->vrefresh, mode->clock,
2634                    mode->hdisplay, mode->hsync_start,
2635                    mode->hsync_end, mode->htotal,
2636                    mode->vdisplay, mode->vsync_start,
2637                    mode->vsync_end, mode->vtotal,
2638                    mode->type, mode->flags);
2639 }
2640
2641 static void intel_encoder_info(struct seq_file *m,
2642                                struct intel_crtc *intel_crtc,
2643                                struct intel_encoder *intel_encoder)
2644 {
2645         struct drm_info_node *node = m->private;
2646         struct drm_device *dev = node->minor->dev;
2647         struct drm_crtc *crtc = &intel_crtc->base;
2648         struct intel_connector *intel_connector;
2649         struct drm_encoder *encoder;
2650
2651         encoder = &intel_encoder->base;
2652         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2653                    encoder->base.id, encoder->name);
2654         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2655                 struct drm_connector *connector = &intel_connector->base;
2656                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2657                            connector->base.id,
2658                            connector->name,
2659                            drm_get_connector_status_name(connector->status));
2660                 if (connector->status == connector_status_connected) {
2661                         struct drm_display_mode *mode = &crtc->mode;
2662                         seq_printf(m, ", mode:\n");
2663                         intel_seq_print_mode(m, 2, mode);
2664                 } else {
2665                         seq_putc(m, '\n');
2666                 }
2667         }
2668 }
2669
2670 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2671 {
2672         struct drm_info_node *node = m->private;
2673         struct drm_device *dev = node->minor->dev;
2674         struct drm_crtc *crtc = &intel_crtc->base;
2675         struct intel_encoder *intel_encoder;
2676
2677         if (crtc->primary->fb)
2678                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2679                            crtc->primary->fb->base.id, crtc->x, crtc->y,
2680                            crtc->primary->fb->width, crtc->primary->fb->height);
2681         else
2682                 seq_puts(m, "\tprimary plane disabled\n");
2683         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2684                 intel_encoder_info(m, intel_crtc, intel_encoder);
2685 }
2686
2687 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2688 {
2689         struct drm_display_mode *mode = panel->fixed_mode;
2690
2691         seq_printf(m, "\tfixed mode:\n");
2692         intel_seq_print_mode(m, 2, mode);
2693 }
2694
2695 static void intel_dp_info(struct seq_file *m,
2696                           struct intel_connector *intel_connector)
2697 {
2698         struct intel_encoder *intel_encoder = intel_connector->encoder;
2699         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2700
2701         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2702         seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2703                    "no");
2704         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2705                 intel_panel_info(m, &intel_connector->panel);
2706 }
2707
2708 static void intel_hdmi_info(struct seq_file *m,
2709                             struct intel_connector *intel_connector)
2710 {
2711         struct intel_encoder *intel_encoder = intel_connector->encoder;
2712         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2713
2714         seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2715                    "no");
2716 }
2717
2718 static void intel_lvds_info(struct seq_file *m,
2719                             struct intel_connector *intel_connector)
2720 {
2721         intel_panel_info(m, &intel_connector->panel);
2722 }
2723
2724 static void intel_connector_info(struct seq_file *m,
2725                                  struct drm_connector *connector)
2726 {
2727         struct intel_connector *intel_connector = to_intel_connector(connector);
2728         struct intel_encoder *intel_encoder = intel_connector->encoder;
2729         struct drm_display_mode *mode;
2730
2731         seq_printf(m, "connector %d: type %s, status: %s\n",
2732                    connector->base.id, connector->name,
2733                    drm_get_connector_status_name(connector->status));
2734         if (connector->status == connector_status_connected) {
2735                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2736                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2737                            connector->display_info.width_mm,
2738                            connector->display_info.height_mm);
2739                 seq_printf(m, "\tsubpixel order: %s\n",
2740                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2741                 seq_printf(m, "\tCEA rev: %d\n",
2742                            connector->display_info.cea_rev);
2743         }
2744         if (intel_encoder) {
2745                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2746                     intel_encoder->type == INTEL_OUTPUT_EDP)
2747                         intel_dp_info(m, intel_connector);
2748                 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2749                         intel_hdmi_info(m, intel_connector);
2750                 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2751                         intel_lvds_info(m, intel_connector);
2752         }
2753
2754         seq_printf(m, "\tmodes:\n");
2755         list_for_each_entry(mode, &connector->modes, head)
2756                 intel_seq_print_mode(m, 2, mode);
2757 }
2758
2759 static bool cursor_active(struct drm_device *dev, int pipe)
2760 {
2761         struct drm_i915_private *dev_priv = dev->dev_private;
2762         u32 state;
2763
2764         if (IS_845G(dev) || IS_I865G(dev))
2765                 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2766         else
2767                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2768
2769         return state;
2770 }
2771
2772 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2773 {
2774         struct drm_i915_private *dev_priv = dev->dev_private;
2775         u32 pos;
2776
2777         pos = I915_READ(CURPOS(pipe));
2778
2779         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2780         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2781                 *x = -*x;
2782
2783         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2784         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2785                 *y = -*y;
2786
2787         return cursor_active(dev, pipe);
2788 }
2789
2790 static int i915_display_info(struct seq_file *m, void *unused)
2791 {
2792         struct drm_info_node *node = m->private;
2793         struct drm_device *dev = node->minor->dev;
2794         struct drm_i915_private *dev_priv = dev->dev_private;
2795         struct intel_crtc *crtc;
2796         struct drm_connector *connector;
2797
2798         intel_runtime_pm_get(dev_priv);
2799         drm_modeset_lock_all(dev);
2800         seq_printf(m, "CRTC info\n");
2801         seq_printf(m, "---------\n");
2802         for_each_intel_crtc(dev, crtc) {
2803                 bool active;
2804                 struct intel_crtc_state *pipe_config;
2805                 int x, y;
2806
2807                 pipe_config = to_intel_crtc_state(crtc->base.state);
2808
2809                 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2810                            crtc->base.base.id, pipe_name(crtc->pipe),
2811                            yesno(pipe_config->base.active),
2812                            pipe_config->pipe_src_w, pipe_config->pipe_src_h);
2813                 if (pipe_config->base.active) {
2814                         intel_crtc_info(m, crtc);
2815
2816                         active = cursor_position(dev, crtc->pipe, &x, &y);
2817                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2818                                    yesno(crtc->cursor_base),
2819                                    x, y, crtc->base.cursor->state->crtc_w,
2820                                    crtc->base.cursor->state->crtc_h,
2821                                    crtc->cursor_addr, yesno(active));
2822                 }
2823
2824                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2825                            yesno(!crtc->cpu_fifo_underrun_disabled),
2826                            yesno(!crtc->pch_fifo_underrun_disabled));
2827         }
2828
2829         seq_printf(m, "\n");
2830         seq_printf(m, "Connector info\n");
2831         seq_printf(m, "--------------\n");
2832         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2833                 intel_connector_info(m, connector);
2834         }
2835         drm_modeset_unlock_all(dev);
2836         intel_runtime_pm_put(dev_priv);
2837
2838         return 0;
2839 }
2840
2841 static int i915_semaphore_status(struct seq_file *m, void *unused)
2842 {
2843         struct drm_info_node *node = (struct drm_info_node *) m->private;
2844         struct drm_device *dev = node->minor->dev;
2845         struct drm_i915_private *dev_priv = dev->dev_private;
2846         struct intel_engine_cs *ring;
2847         int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2848         int i, j, ret;
2849
2850         if (!i915_semaphore_is_enabled(dev)) {
2851                 seq_puts(m, "Semaphores are disabled\n");
2852                 return 0;
2853         }
2854
2855         ret = mutex_lock_interruptible(&dev->struct_mutex);
2856         if (ret)
2857                 return ret;
2858         intel_runtime_pm_get(dev_priv);
2859
2860         if (IS_BROADWELL(dev)) {
2861                 struct page *page;
2862                 uint64_t *seqno;
2863
2864                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2865
2866                 seqno = (uint64_t *)kmap_atomic(page);
2867                 for_each_ring(ring, dev_priv, i) {
2868                         uint64_t offset;
2869
2870                         seq_printf(m, "%s\n", ring->name);
2871
2872                         seq_puts(m, "  Last signal:");
2873                         for (j = 0; j < num_rings; j++) {
2874                                 offset = i * I915_NUM_RINGS + j;
2875                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2876                                            seqno[offset], offset * 8);
2877                         }
2878                         seq_putc(m, '\n');
2879
2880                         seq_puts(m, "  Last wait:  ");
2881                         for (j = 0; j < num_rings; j++) {
2882                                 offset = i + (j * I915_NUM_RINGS);
2883                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2884                                            seqno[offset], offset * 8);
2885                         }
2886                         seq_putc(m, '\n');
2887
2888                 }
2889                 kunmap_atomic(seqno);
2890         } else {
2891                 seq_puts(m, "  Last signal:");
2892                 for_each_ring(ring, dev_priv, i)
2893                         for (j = 0; j < num_rings; j++)
2894                                 seq_printf(m, "0x%08x\n",
2895                                            I915_READ(ring->semaphore.mbox.signal[j]));
2896                 seq_putc(m, '\n');
2897         }
2898
2899         seq_puts(m, "\nSync seqno:\n");
2900         for_each_ring(ring, dev_priv, i) {
2901                 for (j = 0; j < num_rings; j++) {
2902                         seq_printf(m, "  0x%08x ", ring->semaphore.sync_seqno[j]);
2903                 }
2904                 seq_putc(m, '\n');
2905         }
2906         seq_putc(m, '\n');
2907
2908         intel_runtime_pm_put(dev_priv);
2909         mutex_unlock(&dev->struct_mutex);
2910         return 0;
2911 }
2912
2913 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2914 {
2915         struct drm_info_node *node = (struct drm_info_node *) m->private;
2916         struct drm_device *dev = node->minor->dev;
2917         struct drm_i915_private *dev_priv = dev->dev_private;
2918         int i;
2919
2920         drm_modeset_lock_all(dev);
2921         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2922                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2923
2924                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2925                 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2926                            pll->config.crtc_mask, pll->active, yesno(pll->on));
2927                 seq_printf(m, " tracked hardware state:\n");
2928                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
2929                 seq_printf(m, " dpll_md: 0x%08x\n",
2930                            pll->config.hw_state.dpll_md);
2931                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
2932                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
2933                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
2934         }
2935         drm_modeset_unlock_all(dev);
2936
2937         return 0;
2938 }
2939
2940 static int i915_wa_registers(struct seq_file *m, void *unused)
2941 {
2942         int i;
2943         int ret;
2944         struct drm_info_node *node = (struct drm_info_node *) m->private;
2945         struct drm_device *dev = node->minor->dev;
2946         struct drm_i915_private *dev_priv = dev->dev_private;
2947
2948         ret = mutex_lock_interruptible(&dev->struct_mutex);
2949         if (ret)
2950                 return ret;
2951
2952         intel_runtime_pm_get(dev_priv);
2953
2954         seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2955         for (i = 0; i < dev_priv->workarounds.count; ++i) {
2956                 u32 addr, mask, value, read;
2957                 bool ok;
2958
2959                 addr = dev_priv->workarounds.reg[i].addr;
2960                 mask = dev_priv->workarounds.reg[i].mask;
2961                 value = dev_priv->workarounds.reg[i].value;
2962                 read = I915_READ(addr);
2963                 ok = (value & mask) == (read & mask);
2964                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2965                            addr, value, mask, read, ok ? "OK" : "FAIL");
2966         }
2967
2968         intel_runtime_pm_put(dev_priv);
2969         mutex_unlock(&dev->struct_mutex);
2970
2971         return 0;
2972 }
2973
2974 static int i915_ddb_info(struct seq_file *m, void *unused)
2975 {
2976         struct drm_info_node *node = m->private;
2977         struct drm_device *dev = node->minor->dev;
2978         struct drm_i915_private *dev_priv = dev->dev_private;
2979         struct skl_ddb_allocation *ddb;
2980         struct skl_ddb_entry *entry;
2981         enum pipe pipe;
2982         int plane;
2983
2984         if (INTEL_INFO(dev)->gen < 9)
2985                 return 0;
2986
2987         drm_modeset_lock_all(dev);
2988
2989         ddb = &dev_priv->wm.skl_hw.ddb;
2990
2991         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2992
2993         for_each_pipe(dev_priv, pipe) {
2994                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2995
2996                 for_each_plane(dev_priv, pipe, plane) {
2997                         entry = &ddb->plane[pipe][plane];
2998                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
2999                                    entry->start, entry->end,
3000                                    skl_ddb_entry_size(entry));
3001                 }
3002
3003                 entry = &ddb->cursor[pipe];
3004                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3005                            entry->end, skl_ddb_entry_size(entry));
3006         }
3007
3008         drm_modeset_unlock_all(dev);
3009
3010         return 0;
3011 }
3012
3013 static void drrs_status_per_crtc(struct seq_file *m,
3014                 struct drm_device *dev, struct intel_crtc *intel_crtc)
3015 {
3016         struct intel_encoder *intel_encoder;
3017         struct drm_i915_private *dev_priv = dev->dev_private;
3018         struct i915_drrs *drrs = &dev_priv->drrs;
3019         int vrefresh = 0;
3020
3021         for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3022                 /* Encoder connected on this CRTC */
3023                 switch (intel_encoder->type) {
3024                 case INTEL_OUTPUT_EDP:
3025                         seq_puts(m, "eDP:\n");
3026                         break;
3027                 case INTEL_OUTPUT_DSI:
3028                         seq_puts(m, "DSI:\n");
3029                         break;
3030                 case INTEL_OUTPUT_HDMI:
3031                         seq_puts(m, "HDMI:\n");
3032                         break;
3033                 case INTEL_OUTPUT_DISPLAYPORT:
3034                         seq_puts(m, "DP:\n");
3035                         break;
3036                 default:
3037                         seq_printf(m, "Other encoder (id=%d).\n",
3038                                                 intel_encoder->type);
3039                         return;
3040                 }
3041         }
3042
3043         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3044                 seq_puts(m, "\tVBT: DRRS_type: Static");
3045         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3046                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3047         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3048                 seq_puts(m, "\tVBT: DRRS_type: None");
3049         else
3050                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3051
3052         seq_puts(m, "\n\n");
3053
3054         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3055                 struct intel_panel *panel;
3056
3057                 mutex_lock(&drrs->mutex);
3058                 /* DRRS Supported */
3059                 seq_puts(m, "\tDRRS Supported: Yes\n");
3060
3061                 /* disable_drrs() will make drrs->dp NULL */
3062                 if (!drrs->dp) {
3063                         seq_puts(m, "Idleness DRRS: Disabled");
3064                         mutex_unlock(&drrs->mutex);
3065                         return;
3066                 }
3067
3068                 panel = &drrs->dp->attached_connector->panel;
3069                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3070                                         drrs->busy_frontbuffer_bits);
3071
3072                 seq_puts(m, "\n\t\t");
3073                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3074                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3075                         vrefresh = panel->fixed_mode->vrefresh;
3076                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3077                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3078                         vrefresh = panel->downclock_mode->vrefresh;
3079                 } else {
3080                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3081                                                 drrs->refresh_rate_type);
3082                         mutex_unlock(&drrs->mutex);
3083                         return;
3084                 }
3085                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3086
3087                 seq_puts(m, "\n\t\t");
3088                 mutex_unlock(&drrs->mutex);
3089         } else {
3090                 /* DRRS not supported. Print the VBT parameter*/
3091                 seq_puts(m, "\tDRRS Supported : No");
3092         }
3093         seq_puts(m, "\n");
3094 }
3095
3096 static int i915_drrs_status(struct seq_file *m, void *unused)
3097 {
3098         struct drm_info_node *node = m->private;
3099         struct drm_device *dev = node->minor->dev;
3100         struct intel_crtc *intel_crtc;
3101         int active_crtc_cnt = 0;
3102
3103         for_each_intel_crtc(dev, intel_crtc) {
3104                 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3105
3106                 if (intel_crtc->base.state->active) {
3107                         active_crtc_cnt++;
3108                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3109
3110                         drrs_status_per_crtc(m, dev, intel_crtc);
3111                 }
3112
3113                 drm_modeset_unlock(&intel_crtc->base.mutex);
3114         }
3115
3116         if (!active_crtc_cnt)
3117                 seq_puts(m, "No active crtc found\n");
3118
3119         return 0;
3120 }
3121
3122 struct pipe_crc_info {
3123         const char *name;
3124         struct drm_device *dev;
3125         enum pipe pipe;
3126 };
3127
3128 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3129 {
3130         struct drm_info_node *node = (struct drm_info_node *) m->private;
3131         struct drm_device *dev = node->minor->dev;
3132         struct drm_encoder *encoder;
3133         struct intel_encoder *intel_encoder;
3134         struct intel_digital_port *intel_dig_port;
3135         drm_modeset_lock_all(dev);
3136         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3137                 intel_encoder = to_intel_encoder(encoder);
3138                 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3139                         continue;
3140                 intel_dig_port = enc_to_dig_port(encoder);
3141                 if (!intel_dig_port->dp.can_mst)
3142                         continue;
3143
3144                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3145         }
3146         drm_modeset_unlock_all(dev);
3147         return 0;
3148 }
3149
3150 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3151 {
3152         struct pipe_crc_info *info = inode->i_private;
3153         struct drm_i915_private *dev_priv = info->dev->dev_private;
3154         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3155
3156         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3157                 return -ENODEV;
3158
3159         spin_lock_irq(&pipe_crc->lock);
3160
3161         if (pipe_crc->opened) {
3162                 spin_unlock_irq(&pipe_crc->lock);
3163                 return -EBUSY; /* already open */
3164         }
3165
3166         pipe_crc->opened = true;
3167         filep->private_data = inode->i_private;
3168
3169         spin_unlock_irq(&pipe_crc->lock);
3170
3171         return 0;
3172 }
3173
3174 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3175 {
3176         struct pipe_crc_info *info = inode->i_private;
3177         struct drm_i915_private *dev_priv = info->dev->dev_private;
3178         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3179
3180         spin_lock_irq(&pipe_crc->lock);
3181         pipe_crc->opened = false;
3182         spin_unlock_irq(&pipe_crc->lock);
3183
3184         return 0;
3185 }
3186
3187 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3188 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3189 /* account for \'0' */
3190 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3191
3192 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3193 {
3194         assert_spin_locked(&pipe_crc->lock);
3195         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3196                         INTEL_PIPE_CRC_ENTRIES_NR);
3197 }
3198
3199 static ssize_t
3200 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3201                    loff_t *pos)
3202 {
3203         struct pipe_crc_info *info = filep->private_data;
3204         struct drm_device *dev = info->dev;
3205         struct drm_i915_private *dev_priv = dev->dev_private;
3206         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3207         char buf[PIPE_CRC_BUFFER_LEN];
3208         int n_entries;
3209         ssize_t bytes_read;
3210
3211         /*
3212          * Don't allow user space to provide buffers not big enough to hold
3213          * a line of data.
3214          */
3215         if (count < PIPE_CRC_LINE_LEN)
3216                 return -EINVAL;
3217
3218         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3219                 return 0;
3220
3221         /* nothing to read */
3222         spin_lock_irq(&pipe_crc->lock);
3223         while (pipe_crc_data_count(pipe_crc) == 0) {
3224                 int ret;
3225
3226                 if (filep->f_flags & O_NONBLOCK) {
3227                         spin_unlock_irq(&pipe_crc->lock);
3228                         return -EAGAIN;
3229                 }
3230
3231                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3232                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3233                 if (ret) {
3234                         spin_unlock_irq(&pipe_crc->lock);
3235                         return ret;
3236                 }
3237         }
3238
3239         /* We now have one or more entries to read */
3240         n_entries = count / PIPE_CRC_LINE_LEN;
3241
3242         bytes_read = 0;
3243         while (n_entries > 0) {
3244                 struct intel_pipe_crc_entry *entry =
3245                         &pipe_crc->entries[pipe_crc->tail];
3246                 int ret;
3247
3248                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3249                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3250                         break;
3251
3252                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3253                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3254
3255                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3256                                        "%8u %8x %8x %8x %8x %8x\n",
3257                                        entry->frame, entry->crc[0],
3258                                        entry->crc[1], entry->crc[2],
3259                                        entry->crc[3], entry->crc[4]);
3260
3261                 spin_unlock_irq(&pipe_crc->lock);
3262
3263                 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3264                 if (ret == PIPE_CRC_LINE_LEN)
3265                         return -EFAULT;
3266
3267                 user_buf += PIPE_CRC_LINE_LEN;
3268                 n_entries--;
3269
3270                 spin_lock_irq(&pipe_crc->lock);
3271         }
3272
3273         spin_unlock_irq(&pipe_crc->lock);
3274
3275         return bytes_read;
3276 }
3277
3278 static const struct file_operations i915_pipe_crc_fops = {
3279         .owner = THIS_MODULE,
3280         .open = i915_pipe_crc_open,
3281         .read = i915_pipe_crc_read,
3282         .release = i915_pipe_crc_release,
3283 };
3284
3285 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3286         {
3287                 .name = "i915_pipe_A_crc",
3288                 .pipe = PIPE_A,
3289         },
3290         {
3291                 .name = "i915_pipe_B_crc",
3292                 .pipe = PIPE_B,
3293         },
3294         {
3295                 .name = "i915_pipe_C_crc",
3296                 .pipe = PIPE_C,
3297         },
3298 };
3299
3300 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3301                                 enum pipe pipe)
3302 {
3303         struct drm_device *dev = minor->dev;
3304         struct dentry *ent;
3305         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3306
3307         info->dev = dev;
3308         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3309                                   &i915_pipe_crc_fops);
3310         if (!ent)
3311                 return -ENOMEM;
3312
3313         return drm_add_fake_info_node(minor, ent, info);
3314 }
3315
3316 static const char * const pipe_crc_sources[] = {
3317         "none",
3318         "plane1",
3319         "plane2",
3320         "pf",
3321         "pipe",
3322         "TV",
3323         "DP-B",
3324         "DP-C",
3325         "DP-D",
3326         "auto",
3327 };
3328
3329 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3330 {
3331         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3332         return pipe_crc_sources[source];
3333 }
3334
3335 static int display_crc_ctl_show(struct seq_file *m, void *data)
3336 {
3337         struct drm_device *dev = m->private;
3338         struct drm_i915_private *dev_priv = dev->dev_private;
3339         int i;
3340
3341         for (i = 0; i < I915_MAX_PIPES; i++)
3342                 seq_printf(m, "%c %s\n", pipe_name(i),
3343                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3344
3345         return 0;
3346 }
3347
3348 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3349 {
3350         struct drm_device *dev = inode->i_private;
3351
3352         return single_open(file, display_crc_ctl_show, dev);
3353 }
3354
3355 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3356                                  uint32_t *val)
3357 {
3358         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3359                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3360
3361         switch (*source) {
3362         case INTEL_PIPE_CRC_SOURCE_PIPE:
3363                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3364                 break;
3365         case INTEL_PIPE_CRC_SOURCE_NONE:
3366                 *val = 0;
3367                 break;
3368         default:
3369                 return -EINVAL;
3370         }
3371
3372         return 0;
3373 }
3374
3375 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3376                                      enum intel_pipe_crc_source *source)
3377 {
3378         struct intel_encoder *encoder;
3379         struct intel_crtc *crtc;
3380         struct intel_digital_port *dig_port;
3381         int ret = 0;
3382
3383         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3384
3385         drm_modeset_lock_all(dev);
3386         for_each_intel_encoder(dev, encoder) {
3387                 if (!encoder->base.crtc)
3388                         continue;
3389
3390                 crtc = to_intel_crtc(encoder->base.crtc);
3391
3392                 if (crtc->pipe != pipe)
3393                         continue;
3394
3395                 switch (encoder->type) {
3396                 case INTEL_OUTPUT_TVOUT:
3397                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3398                         break;
3399                 case INTEL_OUTPUT_DISPLAYPORT:
3400                 case INTEL_OUTPUT_EDP:
3401                         dig_port = enc_to_dig_port(&encoder->base);
3402                         switch (dig_port->port) {
3403                         case PORT_B:
3404                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3405                                 break;
3406                         case PORT_C:
3407                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3408                                 break;
3409                         case PORT_D:
3410                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3411                                 break;
3412                         default:
3413                                 WARN(1, "nonexisting DP port %c\n",
3414                                      port_name(dig_port->port));
3415                                 break;
3416                         }
3417                         break;
3418                 default:
3419                         break;
3420                 }
3421         }
3422         drm_modeset_unlock_all(dev);
3423
3424         return ret;
3425 }
3426
3427 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3428                                 enum pipe pipe,
3429                                 enum intel_pipe_crc_source *source,
3430                                 uint32_t *val)
3431 {
3432         struct drm_i915_private *dev_priv = dev->dev_private;
3433         bool need_stable_symbols = false;
3434
3435         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3436                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3437                 if (ret)
3438                         return ret;
3439         }
3440
3441         switch (*source) {
3442         case INTEL_PIPE_CRC_SOURCE_PIPE:
3443                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3444                 break;
3445         case INTEL_PIPE_CRC_SOURCE_DP_B:
3446                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3447                 need_stable_symbols = true;
3448                 break;
3449         case INTEL_PIPE_CRC_SOURCE_DP_C:
3450                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3451                 need_stable_symbols = true;
3452                 break;
3453         case INTEL_PIPE_CRC_SOURCE_DP_D:
3454                 if (!IS_CHERRYVIEW(dev))
3455                         return -EINVAL;
3456                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3457                 need_stable_symbols = true;
3458                 break;
3459         case INTEL_PIPE_CRC_SOURCE_NONE:
3460                 *val = 0;
3461                 break;
3462         default:
3463                 return -EINVAL;
3464         }
3465
3466         /*
3467          * When the pipe CRC tap point is after the transcoders we need
3468          * to tweak symbol-level features to produce a deterministic series of
3469          * symbols for a given frame. We need to reset those features only once
3470          * a frame (instead of every nth symbol):
3471          *   - DC-balance: used to ensure a better clock recovery from the data
3472          *     link (SDVO)
3473          *   - DisplayPort scrambling: used for EMI reduction
3474          */
3475         if (need_stable_symbols) {
3476                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3477
3478                 tmp |= DC_BALANCE_RESET_VLV;
3479                 switch (pipe) {
3480                 case PIPE_A:
3481                         tmp |= PIPE_A_SCRAMBLE_RESET;
3482                         break;
3483                 case PIPE_B:
3484                         tmp |= PIPE_B_SCRAMBLE_RESET;
3485                         break;
3486                 case PIPE_C:
3487                         tmp |= PIPE_C_SCRAMBLE_RESET;
3488                         break;
3489                 default:
3490                         return -EINVAL;
3491                 }
3492                 I915_WRITE(PORT_DFT2_G4X, tmp);
3493         }
3494
3495         return 0;
3496 }
3497
3498 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3499                                  enum pipe pipe,
3500                                  enum intel_pipe_crc_source *source,
3501                                  uint32_t *val)
3502 {
3503         struct drm_i915_private *dev_priv = dev->dev_private;
3504         bool need_stable_symbols = false;
3505
3506         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3507                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3508                 if (ret)
3509                         return ret;
3510         }
3511
3512         switch (*source) {
3513         case INTEL_PIPE_CRC_SOURCE_PIPE:
3514                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3515                 break;
3516         case INTEL_PIPE_CRC_SOURCE_TV:
3517                 if (!SUPPORTS_TV(dev))
3518                         return -EINVAL;
3519                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3520                 break;
3521         case INTEL_PIPE_CRC_SOURCE_DP_B:
3522                 if (!IS_G4X(dev))
3523                         return -EINVAL;
3524                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3525                 need_stable_symbols = true;
3526                 break;
3527         case INTEL_PIPE_CRC_SOURCE_DP_C:
3528                 if (!IS_G4X(dev))
3529                         return -EINVAL;
3530                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3531                 need_stable_symbols = true;
3532                 break;
3533         case INTEL_PIPE_CRC_SOURCE_DP_D:
3534                 if (!IS_G4X(dev))
3535                         return -EINVAL;
3536                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3537                 need_stable_symbols = true;
3538                 break;
3539         case INTEL_PIPE_CRC_SOURCE_NONE:
3540                 *val = 0;
3541                 break;
3542         default:
3543                 return -EINVAL;
3544         }
3545
3546         /*
3547          * When the pipe CRC tap point is after the transcoders we need
3548          * to tweak symbol-level features to produce a deterministic series of
3549          * symbols for a given frame. We need to reset those features only once
3550          * a frame (instead of every nth symbol):
3551          *   - DC-balance: used to ensure a better clock recovery from the data
3552          *     link (SDVO)
3553          *   - DisplayPort scrambling: used for EMI reduction
3554          */
3555         if (need_stable_symbols) {
3556                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3557
3558                 WARN_ON(!IS_G4X(dev));
3559
3560                 I915_WRITE(PORT_DFT_I9XX,
3561                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3562
3563                 if (pipe == PIPE_A)
3564                         tmp |= PIPE_A_SCRAMBLE_RESET;
3565                 else
3566                         tmp |= PIPE_B_SCRAMBLE_RESET;
3567
3568                 I915_WRITE(PORT_DFT2_G4X, tmp);
3569         }
3570
3571         return 0;
3572 }
3573
3574 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3575                                          enum pipe pipe)
3576 {
3577         struct drm_i915_private *dev_priv = dev->dev_private;
3578         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3579
3580         switch (pipe) {
3581         case PIPE_A:
3582                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3583                 break;
3584         case PIPE_B:
3585                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3586                 break;
3587         case PIPE_C:
3588                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3589                 break;
3590         default:
3591                 return;
3592         }
3593         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3594                 tmp &= ~DC_BALANCE_RESET_VLV;
3595         I915_WRITE(PORT_DFT2_G4X, tmp);
3596
3597 }
3598
3599 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3600                                          enum pipe pipe)
3601 {
3602         struct drm_i915_private *dev_priv = dev->dev_private;
3603         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3604
3605         if (pipe == PIPE_A)
3606                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3607         else
3608                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3609         I915_WRITE(PORT_DFT2_G4X, tmp);
3610
3611         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3612                 I915_WRITE(PORT_DFT_I9XX,
3613                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3614         }
3615 }
3616
3617 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3618                                 uint32_t *val)
3619 {
3620         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3621                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3622
3623         switch (*source) {
3624         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3625                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3626                 break;
3627         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3628                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3629                 break;
3630         case INTEL_PIPE_CRC_SOURCE_PIPE:
3631                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3632                 break;
3633         case INTEL_PIPE_CRC_SOURCE_NONE:
3634                 *val = 0;
3635                 break;
3636         default:
3637                 return -EINVAL;
3638         }
3639
3640         return 0;
3641 }
3642
3643 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3644 {
3645         struct drm_i915_private *dev_priv = dev->dev_private;
3646         struct intel_crtc *crtc =
3647                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3648         struct intel_crtc_state *pipe_config;
3649
3650         drm_modeset_lock_all(dev);
3651         pipe_config = to_intel_crtc_state(crtc->base.state);
3652
3653         /*
3654          * If we use the eDP transcoder we need to make sure that we don't
3655          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3656          * relevant on hsw with pipe A when using the always-on power well
3657          * routing.
3658          */
3659         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3660             !pipe_config->pch_pfit.enabled) {
3661                 bool active = pipe_config->base.active;
3662
3663                 if (active) {
3664                         intel_crtc_control(&crtc->base, false);
3665                         pipe_config = to_intel_crtc_state(crtc->base.state);
3666                 }
3667
3668                 pipe_config->pch_pfit.force_thru = true;
3669
3670                 intel_display_power_get(dev_priv,
3671                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3672
3673                 if (active)
3674                         intel_crtc_control(&crtc->base, true);
3675         }
3676         drm_modeset_unlock_all(dev);
3677 }
3678
3679 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3680 {
3681         struct drm_i915_private *dev_priv = dev->dev_private;
3682         struct intel_crtc *crtc =
3683                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3684         struct intel_crtc_state *pipe_config;
3685
3686         drm_modeset_lock_all(dev);
3687         /*
3688          * If we use the eDP transcoder we need to make sure that we don't
3689          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3690          * relevant on hsw with pipe A when using the always-on power well
3691          * routing.
3692          */
3693         pipe_config = to_intel_crtc_state(crtc->base.state);
3694         if (pipe_config->pch_pfit.force_thru) {
3695                 bool active = pipe_config->base.active;
3696
3697                 if (active) {
3698                         intel_crtc_control(&crtc->base, false);
3699                         pipe_config = to_intel_crtc_state(crtc->base.state);
3700                 }
3701
3702                 pipe_config->pch_pfit.force_thru = false;
3703
3704                 intel_display_power_put(dev_priv,
3705                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3706
3707                 if (active)
3708                         intel_crtc_control(&crtc->base, true);
3709         }
3710         drm_modeset_unlock_all(dev);
3711 }
3712
3713 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3714                                 enum pipe pipe,
3715                                 enum intel_pipe_crc_source *source,
3716                                 uint32_t *val)
3717 {
3718         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3719                 *source = INTEL_PIPE_CRC_SOURCE_PF;
3720
3721         switch (*source) {
3722         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3723                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3724                 break;
3725         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3726                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3727                 break;
3728         case INTEL_PIPE_CRC_SOURCE_PF:
3729                 if (IS_HASWELL(dev) && pipe == PIPE_A)
3730                         hsw_trans_edp_pipe_A_crc_wa(dev);
3731
3732                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3733                 break;
3734         case INTEL_PIPE_CRC_SOURCE_NONE:
3735                 *val = 0;
3736                 break;
3737         default:
3738                 return -EINVAL;
3739         }
3740
3741         return 0;
3742 }
3743
3744 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3745                                enum intel_pipe_crc_source source)
3746 {
3747         struct drm_i915_private *dev_priv = dev->dev_private;
3748         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3749         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3750                                                                         pipe));
3751         u32 val = 0; /* shut up gcc */
3752         int ret;
3753
3754         if (pipe_crc->source == source)
3755                 return 0;
3756
3757         /* forbid changing the source without going back to 'none' */
3758         if (pipe_crc->source && source)
3759                 return -EINVAL;
3760
3761         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3762                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3763                 return -EIO;
3764         }
3765
3766         if (IS_GEN2(dev))
3767                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3768         else if (INTEL_INFO(dev)->gen < 5)
3769                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3770         else if (IS_VALLEYVIEW(dev))
3771                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3772         else if (IS_GEN5(dev) || IS_GEN6(dev))
3773                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3774         else
3775                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3776
3777         if (ret != 0)
3778                 return ret;
3779
3780         /* none -> real source transition */
3781         if (source) {
3782                 struct intel_pipe_crc_entry *entries;
3783
3784                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3785                                  pipe_name(pipe), pipe_crc_source_name(source));
3786
3787                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3788                                   sizeof(pipe_crc->entries[0]),
3789                                   GFP_KERNEL);
3790                 if (!entries)
3791                         return -ENOMEM;
3792
3793                 /*
3794                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3795                  * enabled and disabled dynamically based on package C states,
3796                  * user space can't make reliable use of the CRCs, so let's just
3797                  * completely disable it.
3798                  */
3799                 hsw_disable_ips(crtc);
3800
3801                 spin_lock_irq(&pipe_crc->lock);
3802                 kfree(pipe_crc->entries);
3803                 pipe_crc->entries = entries;
3804                 pipe_crc->head = 0;
3805                 pipe_crc->tail = 0;
3806                 spin_unlock_irq(&pipe_crc->lock);
3807         }
3808
3809         pipe_crc->source = source;
3810
3811         I915_WRITE(PIPE_CRC_CTL(pipe), val);
3812         POSTING_READ(PIPE_CRC_CTL(pipe));
3813
3814         /* real source -> none transition */
3815         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3816                 struct intel_pipe_crc_entry *entries;
3817                 struct intel_crtc *crtc =
3818                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3819
3820                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3821                                  pipe_name(pipe));
3822
3823                 drm_modeset_lock(&crtc->base.mutex, NULL);
3824                 if (crtc->base.state->active)
3825                         intel_wait_for_vblank(dev, pipe);
3826                 drm_modeset_unlock(&crtc->base.mutex);
3827
3828                 spin_lock_irq(&pipe_crc->lock);
3829                 entries = pipe_crc->entries;
3830                 pipe_crc->entries = NULL;
3831                 pipe_crc->head = 0;
3832                 pipe_crc->tail = 0;
3833                 spin_unlock_irq(&pipe_crc->lock);
3834
3835                 kfree(entries);
3836
3837                 if (IS_G4X(dev))
3838                         g4x_undo_pipe_scramble_reset(dev, pipe);
3839                 else if (IS_VALLEYVIEW(dev))
3840                         vlv_undo_pipe_scramble_reset(dev, pipe);
3841                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3842                         hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3843
3844                 hsw_enable_ips(crtc);
3845         }
3846
3847         return 0;
3848 }
3849
3850 /*
3851  * Parse pipe CRC command strings:
3852  *   command: wsp* object wsp+ name wsp+ source wsp*
3853  *   object: 'pipe'
3854  *   name: (A | B | C)
3855  *   source: (none | plane1 | plane2 | pf)
3856  *   wsp: (#0x20 | #0x9 | #0xA)+
3857  *
3858  * eg.:
3859  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
3860  *  "pipe A none"    ->  Stop CRC
3861  */
3862 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3863 {
3864         int n_words = 0;
3865
3866         while (*buf) {
3867                 char *end;
3868
3869                 /* skip leading white space */
3870                 buf = skip_spaces(buf);
3871                 if (!*buf)
3872                         break;  /* end of buffer */
3873
3874                 /* find end of word */
3875                 for (end = buf; *end && !isspace(*end); end++)
3876                         ;
3877
3878                 if (n_words == max_words) {
3879                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3880                                          max_words);
3881                         return -EINVAL; /* ran out of words[] before bytes */
3882                 }
3883
3884                 if (*end)
3885                         *end++ = '\0';
3886                 words[n_words++] = buf;
3887                 buf = end;
3888         }
3889
3890         return n_words;
3891 }
3892
3893 enum intel_pipe_crc_object {
3894         PIPE_CRC_OBJECT_PIPE,
3895 };
3896
3897 static const char * const pipe_crc_objects[] = {
3898         "pipe",
3899 };
3900
3901 static int
3902 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3903 {
3904         int i;
3905
3906         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3907                 if (!strcmp(buf, pipe_crc_objects[i])) {
3908                         *o = i;
3909                         return 0;
3910                     }
3911
3912         return -EINVAL;
3913 }
3914
3915 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3916 {
3917         const char name = buf[0];
3918
3919         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3920                 return -EINVAL;
3921
3922         *pipe = name - 'A';
3923
3924         return 0;
3925 }
3926
3927 static int
3928 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3929 {
3930         int i;
3931
3932         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3933                 if (!strcmp(buf, pipe_crc_sources[i])) {
3934                         *s = i;
3935                         return 0;
3936                     }
3937
3938         return -EINVAL;
3939 }
3940
3941 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3942 {
3943 #define N_WORDS 3
3944         int n_words;
3945         char *words[N_WORDS];
3946         enum pipe pipe;
3947         enum intel_pipe_crc_object object;
3948         enum intel_pipe_crc_source source;
3949
3950         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3951         if (n_words != N_WORDS) {
3952                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3953                                  N_WORDS);
3954                 return -EINVAL;
3955         }
3956
3957         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3958                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3959                 return -EINVAL;
3960         }
3961
3962         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3963                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3964                 return -EINVAL;
3965         }
3966
3967         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3968                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3969                 return -EINVAL;
3970         }
3971
3972         return pipe_crc_set_source(dev, pipe, source);
3973 }
3974
3975 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3976                                      size_t len, loff_t *offp)
3977 {
3978         struct seq_file *m = file->private_data;
3979         struct drm_device *dev = m->private;
3980         char *tmpbuf;
3981         int ret;
3982
3983         if (len == 0)
3984                 return 0;
3985
3986         if (len > PAGE_SIZE - 1) {
3987                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3988                                  PAGE_SIZE);
3989                 return -E2BIG;
3990         }
3991
3992         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3993         if (!tmpbuf)
3994                 return -ENOMEM;
3995
3996         if (copy_from_user(tmpbuf, ubuf, len)) {
3997                 ret = -EFAULT;
3998                 goto out;
3999         }
4000         tmpbuf[len] = '\0';
4001
4002         ret = display_crc_ctl_parse(dev, tmpbuf, len);
4003
4004 out:
4005         kfree(tmpbuf);
4006         if (ret < 0)
4007                 return ret;
4008
4009         *offp += len;
4010         return len;
4011 }
4012
4013 static const struct file_operations i915_display_crc_ctl_fops = {
4014         .owner = THIS_MODULE,
4015         .open = display_crc_ctl_open,
4016         .read = seq_read,
4017         .llseek = seq_lseek,
4018         .release = single_release,
4019         .write = display_crc_ctl_write
4020 };
4021
4022 static ssize_t i915_displayport_test_active_write(struct file *file,
4023                                             const char __user *ubuf,
4024                                             size_t len, loff_t *offp)
4025 {
4026         char *input_buffer;
4027         int status = 0;
4028         struct seq_file *m;
4029         struct drm_device *dev;
4030         struct drm_connector *connector;
4031         struct list_head *connector_list;
4032         struct intel_dp *intel_dp;
4033         int val = 0;
4034
4035         m = file->private_data;
4036         if (!m) {
4037                 status = -ENODEV;
4038                 return status;
4039         }
4040         dev = m->private;
4041
4042         if (!dev) {
4043                 status = -ENODEV;
4044                 return status;
4045         }
4046         connector_list = &dev->mode_config.connector_list;
4047
4048         if (len == 0)
4049                 return 0;
4050
4051         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4052         if (!input_buffer)
4053                 return -ENOMEM;
4054
4055         if (copy_from_user(input_buffer, ubuf, len)) {
4056                 status = -EFAULT;
4057                 goto out;
4058         }
4059
4060         input_buffer[len] = '\0';
4061         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4062
4063         list_for_each_entry(connector, connector_list, head) {
4064
4065                 if (connector->connector_type !=
4066                     DRM_MODE_CONNECTOR_DisplayPort)
4067                         continue;
4068
4069                 if (connector->connector_type ==
4070                     DRM_MODE_CONNECTOR_DisplayPort &&
4071                     connector->status == connector_status_connected &&
4072                     connector->encoder != NULL) {
4073                         intel_dp = enc_to_intel_dp(connector->encoder);
4074                         status = kstrtoint(input_buffer, 10, &val);
4075                         if (status < 0)
4076                                 goto out;
4077                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4078                         /* To prevent erroneous activation of the compliance
4079                          * testing code, only accept an actual value of 1 here
4080                          */
4081                         if (val == 1)
4082                                 intel_dp->compliance_test_active = 1;
4083                         else
4084                                 intel_dp->compliance_test_active = 0;
4085                 }
4086         }
4087 out:
4088         kfree(input_buffer);
4089         if (status < 0)
4090                 return status;
4091
4092         *offp += len;
4093         return len;
4094 }
4095
4096 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4097 {
4098         struct drm_device *dev = m->private;
4099         struct drm_connector *connector;
4100         struct list_head *connector_list = &dev->mode_config.connector_list;
4101         struct intel_dp *intel_dp;
4102
4103         if (!dev)
4104                 return -ENODEV;
4105
4106         list_for_each_entry(connector, connector_list, head) {
4107
4108                 if (connector->connector_type !=
4109                     DRM_MODE_CONNECTOR_DisplayPort)
4110                         continue;
4111
4112                 if (connector->status == connector_status_connected &&
4113                     connector->encoder != NULL) {
4114                         intel_dp = enc_to_intel_dp(connector->encoder);
4115                         if (intel_dp->compliance_test_active)
4116                                 seq_puts(m, "1");
4117                         else
4118                                 seq_puts(m, "0");
4119                 } else
4120                         seq_puts(m, "0");
4121         }
4122
4123         return 0;
4124 }
4125
4126 static int i915_displayport_test_active_open(struct inode *inode,
4127                                        struct file *file)
4128 {
4129         struct drm_device *dev = inode->i_private;
4130
4131         return single_open(file, i915_displayport_test_active_show, dev);
4132 }
4133
4134 static const struct file_operations i915_displayport_test_active_fops = {
4135         .owner = THIS_MODULE,
4136         .open = i915_displayport_test_active_open,
4137         .read = seq_read,
4138         .llseek = seq_lseek,
4139         .release = single_release,
4140         .write = i915_displayport_test_active_write
4141 };
4142
4143 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4144 {
4145         struct drm_device *dev = m->private;
4146         struct drm_connector *connector;
4147         struct list_head *connector_list = &dev->mode_config.connector_list;
4148         struct intel_dp *intel_dp;
4149
4150         if (!dev)
4151                 return -ENODEV;
4152
4153         list_for_each_entry(connector, connector_list, head) {
4154
4155                 if (connector->connector_type !=
4156                     DRM_MODE_CONNECTOR_DisplayPort)
4157                         continue;
4158
4159                 if (connector->status == connector_status_connected &&
4160                     connector->encoder != NULL) {
4161                         intel_dp = enc_to_intel_dp(connector->encoder);
4162                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4163                 } else
4164                         seq_puts(m, "0");
4165         }
4166
4167         return 0;
4168 }
4169 static int i915_displayport_test_data_open(struct inode *inode,
4170                                        struct file *file)
4171 {
4172         struct drm_device *dev = inode->i_private;
4173
4174         return single_open(file, i915_displayport_test_data_show, dev);
4175 }
4176
4177 static const struct file_operations i915_displayport_test_data_fops = {
4178         .owner = THIS_MODULE,
4179         .open = i915_displayport_test_data_open,
4180         .read = seq_read,
4181         .llseek = seq_lseek,
4182         .release = single_release
4183 };
4184
4185 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4186 {
4187         struct drm_device *dev = m->private;
4188         struct drm_connector *connector;
4189         struct list_head *connector_list = &dev->mode_config.connector_list;
4190         struct intel_dp *intel_dp;
4191
4192         if (!dev)
4193                 return -ENODEV;
4194
4195         list_for_each_entry(connector, connector_list, head) {
4196
4197                 if (connector->connector_type !=
4198                     DRM_MODE_CONNECTOR_DisplayPort)
4199                         continue;
4200
4201                 if (connector->status == connector_status_connected &&
4202                     connector->encoder != NULL) {
4203                         intel_dp = enc_to_intel_dp(connector->encoder);
4204                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4205                 } else
4206                         seq_puts(m, "0");
4207         }
4208
4209         return 0;
4210 }
4211
4212 static int i915_displayport_test_type_open(struct inode *inode,
4213                                        struct file *file)
4214 {
4215         struct drm_device *dev = inode->i_private;
4216
4217         return single_open(file, i915_displayport_test_type_show, dev);
4218 }
4219
4220 static const struct file_operations i915_displayport_test_type_fops = {
4221         .owner = THIS_MODULE,
4222         .open = i915_displayport_test_type_open,
4223         .read = seq_read,
4224         .llseek = seq_lseek,
4225         .release = single_release
4226 };
4227
4228 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4229 {
4230         struct drm_device *dev = m->private;
4231         int level;
4232         int num_levels;
4233
4234         if (IS_CHERRYVIEW(dev))
4235                 num_levels = 3;
4236         else if (IS_VALLEYVIEW(dev))
4237                 num_levels = 1;
4238         else
4239                 num_levels = ilk_wm_max_level(dev) + 1;
4240
4241         drm_modeset_lock_all(dev);
4242
4243         for (level = 0; level < num_levels; level++) {
4244                 unsigned int latency = wm[level];
4245
4246                 /*
4247                  * - WM1+ latency values in 0.5us units
4248                  * - latencies are in us on gen9/vlv/chv
4249                  */
4250                 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
4251                         latency *= 10;
4252                 else if (level > 0)
4253                         latency *= 5;
4254
4255                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4256                            level, wm[level], latency / 10, latency % 10);
4257         }
4258
4259         drm_modeset_unlock_all(dev);
4260 }
4261
4262 static int pri_wm_latency_show(struct seq_file *m, void *data)
4263 {
4264         struct drm_device *dev = m->private;
4265         struct drm_i915_private *dev_priv = dev->dev_private;
4266         const uint16_t *latencies;
4267
4268         if (INTEL_INFO(dev)->gen >= 9)
4269                 latencies = dev_priv->wm.skl_latency;
4270         else
4271                 latencies = to_i915(dev)->wm.pri_latency;
4272
4273         wm_latency_show(m, latencies);
4274
4275         return 0;
4276 }
4277
4278 static int spr_wm_latency_show(struct seq_file *m, void *data)
4279 {
4280         struct drm_device *dev = m->private;
4281         struct drm_i915_private *dev_priv = dev->dev_private;
4282         const uint16_t *latencies;
4283
4284         if (INTEL_INFO(dev)->gen >= 9)
4285                 latencies = dev_priv->wm.skl_latency;
4286         else
4287                 latencies = to_i915(dev)->wm.spr_latency;
4288
4289         wm_latency_show(m, latencies);
4290
4291         return 0;
4292 }
4293
4294 static int cur_wm_latency_show(struct seq_file *m, void *data)
4295 {
4296         struct drm_device *dev = m->private;
4297         struct drm_i915_private *dev_priv = dev->dev_private;
4298         const uint16_t *latencies;
4299
4300         if (INTEL_INFO(dev)->gen >= 9)
4301                 latencies = dev_priv->wm.skl_latency;
4302         else
4303                 latencies = to_i915(dev)->wm.cur_latency;
4304
4305         wm_latency_show(m, latencies);
4306
4307         return 0;
4308 }
4309
4310 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4311 {
4312         struct drm_device *dev = inode->i_private;
4313
4314         if (INTEL_INFO(dev)->gen < 5)
4315                 return -ENODEV;
4316
4317         return single_open(file, pri_wm_latency_show, dev);
4318 }
4319
4320 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4321 {
4322         struct drm_device *dev = inode->i_private;
4323
4324         if (HAS_GMCH_DISPLAY(dev))
4325                 return -ENODEV;
4326
4327         return single_open(file, spr_wm_latency_show, dev);
4328 }
4329
4330 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4331 {
4332         struct drm_device *dev = inode->i_private;
4333
4334         if (HAS_GMCH_DISPLAY(dev))
4335                 return -ENODEV;
4336
4337         return single_open(file, cur_wm_latency_show, dev);
4338 }
4339
4340 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4341                                 size_t len, loff_t *offp, uint16_t wm[8])
4342 {
4343         struct seq_file *m = file->private_data;
4344         struct drm_device *dev = m->private;
4345         uint16_t new[8] = { 0 };
4346         int num_levels;
4347         int level;
4348         int ret;
4349         char tmp[32];
4350
4351         if (IS_CHERRYVIEW(dev))
4352                 num_levels = 3;
4353         else if (IS_VALLEYVIEW(dev))
4354                 num_levels = 1;
4355         else
4356                 num_levels = ilk_wm_max_level(dev) + 1;
4357
4358         if (len >= sizeof(tmp))
4359                 return -EINVAL;
4360
4361         if (copy_from_user(tmp, ubuf, len))
4362                 return -EFAULT;
4363
4364         tmp[len] = '\0';
4365
4366         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4367                      &new[0], &new[1], &new[2], &new[3],
4368                      &new[4], &new[5], &new[6], &new[7]);
4369         if (ret != num_levels)
4370                 return -EINVAL;
4371
4372         drm_modeset_lock_all(dev);
4373
4374         for (level = 0; level < num_levels; level++)
4375                 wm[level] = new[level];
4376
4377         drm_modeset_unlock_all(dev);
4378
4379         return len;
4380 }
4381
4382
4383 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4384                                     size_t len, loff_t *offp)
4385 {
4386         struct seq_file *m = file->private_data;
4387         struct drm_device *dev = m->private;
4388         struct drm_i915_private *dev_priv = dev->dev_private;
4389         uint16_t *latencies;
4390
4391         if (INTEL_INFO(dev)->gen >= 9)
4392                 latencies = dev_priv->wm.skl_latency;
4393         else
4394                 latencies = to_i915(dev)->wm.pri_latency;
4395
4396         return wm_latency_write(file, ubuf, len, offp, latencies);
4397 }
4398
4399 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4400                                     size_t len, loff_t *offp)
4401 {
4402         struct seq_file *m = file->private_data;
4403         struct drm_device *dev = m->private;
4404         struct drm_i915_private *dev_priv = dev->dev_private;
4405         uint16_t *latencies;
4406
4407         if (INTEL_INFO(dev)->gen >= 9)
4408                 latencies = dev_priv->wm.skl_latency;
4409         else
4410                 latencies = to_i915(dev)->wm.spr_latency;
4411
4412         return wm_latency_write(file, ubuf, len, offp, latencies);
4413 }
4414
4415 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4416                                     size_t len, loff_t *offp)
4417 {
4418         struct seq_file *m = file->private_data;
4419         struct drm_device *dev = m->private;
4420         struct drm_i915_private *dev_priv = dev->dev_private;
4421         uint16_t *latencies;
4422
4423         if (INTEL_INFO(dev)->gen >= 9)
4424                 latencies = dev_priv->wm.skl_latency;
4425         else
4426                 latencies = to_i915(dev)->wm.cur_latency;
4427
4428         return wm_latency_write(file, ubuf, len, offp, latencies);
4429 }
4430
4431 static const struct file_operations i915_pri_wm_latency_fops = {
4432         .owner = THIS_MODULE,
4433         .open = pri_wm_latency_open,
4434         .read = seq_read,
4435         .llseek = seq_lseek,
4436         .release = single_release,
4437         .write = pri_wm_latency_write
4438 };
4439
4440 static const struct file_operations i915_spr_wm_latency_fops = {
4441         .owner = THIS_MODULE,
4442         .open = spr_wm_latency_open,
4443         .read = seq_read,
4444         .llseek = seq_lseek,
4445         .release = single_release,
4446         .write = spr_wm_latency_write
4447 };
4448
4449 static const struct file_operations i915_cur_wm_latency_fops = {
4450         .owner = THIS_MODULE,
4451         .open = cur_wm_latency_open,
4452         .read = seq_read,
4453         .llseek = seq_lseek,
4454         .release = single_release,
4455         .write = cur_wm_latency_write
4456 };
4457
4458 static int
4459 i915_wedged_get(void *data, u64 *val)
4460 {
4461         struct drm_device *dev = data;
4462         struct drm_i915_private *dev_priv = dev->dev_private;
4463
4464         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4465
4466         return 0;
4467 }
4468
4469 static int
4470 i915_wedged_set(void *data, u64 val)
4471 {
4472         struct drm_device *dev = data;
4473         struct drm_i915_private *dev_priv = dev->dev_private;
4474
4475         /*
4476          * There is no safeguard against this debugfs entry colliding
4477          * with the hangcheck calling same i915_handle_error() in
4478          * parallel, causing an explosion. For now we assume that the
4479          * test harness is responsible enough not to inject gpu hangs
4480          * while it is writing to 'i915_wedged'
4481          */
4482
4483         if (i915_reset_in_progress(&dev_priv->gpu_error))
4484                 return -EAGAIN;
4485
4486         intel_runtime_pm_get(dev_priv);
4487
4488         i915_handle_error(dev, val,
4489                           "Manually setting wedged to %llu", val);
4490
4491         intel_runtime_pm_put(dev_priv);
4492
4493         return 0;
4494 }
4495
4496 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4497                         i915_wedged_get, i915_wedged_set,
4498                         "%llu\n");
4499
4500 static int
4501 i915_ring_stop_get(void *data, u64 *val)
4502 {
4503         struct drm_device *dev = data;
4504         struct drm_i915_private *dev_priv = dev->dev_private;
4505
4506         *val = dev_priv->gpu_error.stop_rings;
4507
4508         return 0;
4509 }
4510
4511 static int
4512 i915_ring_stop_set(void *data, u64 val)
4513 {
4514         struct drm_device *dev = data;
4515         struct drm_i915_private *dev_priv = dev->dev_private;
4516         int ret;
4517
4518         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4519
4520         ret = mutex_lock_interruptible(&dev->struct_mutex);
4521         if (ret)
4522                 return ret;
4523
4524         dev_priv->gpu_error.stop_rings = val;
4525         mutex_unlock(&dev->struct_mutex);
4526
4527         return 0;
4528 }
4529
4530 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4531                         i915_ring_stop_get, i915_ring_stop_set,
4532                         "0x%08llx\n");
4533
4534 static int
4535 i915_ring_missed_irq_get(void *data, u64 *val)
4536 {
4537         struct drm_device *dev = data;
4538         struct drm_i915_private *dev_priv = dev->dev_private;
4539
4540         *val = dev_priv->gpu_error.missed_irq_rings;
4541         return 0;
4542 }
4543
4544 static int
4545 i915_ring_missed_irq_set(void *data, u64 val)
4546 {
4547         struct drm_device *dev = data;
4548         struct drm_i915_private *dev_priv = dev->dev_private;
4549         int ret;
4550
4551         /* Lock against concurrent debugfs callers */
4552         ret = mutex_lock_interruptible(&dev->struct_mutex);
4553         if (ret)
4554                 return ret;
4555         dev_priv->gpu_error.missed_irq_rings = val;
4556         mutex_unlock(&dev->struct_mutex);
4557
4558         return 0;
4559 }
4560
4561 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4562                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4563                         "0x%08llx\n");
4564
4565 static int
4566 i915_ring_test_irq_get(void *data, u64 *val)
4567 {
4568         struct drm_device *dev = data;
4569         struct drm_i915_private *dev_priv = dev->dev_private;
4570
4571         *val = dev_priv->gpu_error.test_irq_rings;
4572
4573         return 0;
4574 }
4575
4576 static int
4577 i915_ring_test_irq_set(void *data, u64 val)
4578 {
4579         struct drm_device *dev = data;
4580         struct drm_i915_private *dev_priv = dev->dev_private;
4581         int ret;
4582
4583         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4584
4585         /* Lock against concurrent debugfs callers */
4586         ret = mutex_lock_interruptible(&dev->struct_mutex);
4587         if (ret)
4588                 return ret;
4589
4590         dev_priv->gpu_error.test_irq_rings = val;
4591         mutex_unlock(&dev->struct_mutex);
4592
4593         return 0;
4594 }
4595
4596 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4597                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4598                         "0x%08llx\n");
4599
4600 #define DROP_UNBOUND 0x1
4601 #define DROP_BOUND 0x2
4602 #define DROP_RETIRE 0x4
4603 #define DROP_ACTIVE 0x8
4604 #define DROP_ALL (DROP_UNBOUND | \
4605                   DROP_BOUND | \
4606                   DROP_RETIRE | \
4607                   DROP_ACTIVE)
4608 static int
4609 i915_drop_caches_get(void *data, u64 *val)
4610 {
4611         *val = DROP_ALL;
4612
4613         return 0;
4614 }
4615
4616 static int
4617 i915_drop_caches_set(void *data, u64 val)
4618 {
4619         struct drm_device *dev = data;
4620         struct drm_i915_private *dev_priv = dev->dev_private;
4621         int ret;
4622
4623         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4624
4625         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4626          * on ioctls on -EAGAIN. */
4627         ret = mutex_lock_interruptible(&dev->struct_mutex);
4628         if (ret)
4629                 return ret;
4630
4631         if (val & DROP_ACTIVE) {
4632                 ret = i915_gpu_idle(dev);
4633                 if (ret)
4634                         goto unlock;
4635         }
4636
4637         if (val & (DROP_RETIRE | DROP_ACTIVE))
4638                 i915_gem_retire_requests(dev);
4639
4640         if (val & DROP_BOUND)
4641                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4642
4643         if (val & DROP_UNBOUND)
4644                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4645
4646 unlock:
4647         mutex_unlock(&dev->struct_mutex);
4648
4649         return ret;
4650 }
4651
4652 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4653                         i915_drop_caches_get, i915_drop_caches_set,
4654                         "0x%08llx\n");
4655
4656 static int
4657 i915_max_freq_get(void *data, u64 *val)
4658 {
4659         struct drm_device *dev = data;
4660         struct drm_i915_private *dev_priv = dev->dev_private;
4661         int ret;
4662
4663         if (INTEL_INFO(dev)->gen < 6)
4664                 return -ENODEV;
4665
4666         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4667
4668         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4669         if (ret)
4670                 return ret;
4671
4672         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4673         mutex_unlock(&dev_priv->rps.hw_lock);
4674
4675         return 0;
4676 }
4677
4678 static int
4679 i915_max_freq_set(void *data, u64 val)
4680 {
4681         struct drm_device *dev = data;
4682         struct drm_i915_private *dev_priv = dev->dev_private;
4683         u32 hw_max, hw_min;
4684         int ret;
4685
4686         if (INTEL_INFO(dev)->gen < 6)
4687                 return -ENODEV;
4688
4689         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4690
4691         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4692
4693         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4694         if (ret)
4695                 return ret;
4696
4697         /*
4698          * Turbo will still be enabled, but won't go above the set value.
4699          */
4700         val = intel_freq_opcode(dev_priv, val);
4701
4702         hw_max = dev_priv->rps.max_freq;
4703         hw_min = dev_priv->rps.min_freq;
4704
4705         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4706                 mutex_unlock(&dev_priv->rps.hw_lock);
4707                 return -EINVAL;
4708         }
4709
4710         dev_priv->rps.max_freq_softlimit = val;
4711
4712         intel_set_rps(dev, val);
4713
4714         mutex_unlock(&dev_priv->rps.hw_lock);
4715
4716         return 0;
4717 }
4718
4719 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4720                         i915_max_freq_get, i915_max_freq_set,
4721                         "%llu\n");
4722
4723 static int
4724 i915_min_freq_get(void *data, u64 *val)
4725 {
4726         struct drm_device *dev = data;
4727         struct drm_i915_private *dev_priv = dev->dev_private;
4728         int ret;
4729
4730         if (INTEL_INFO(dev)->gen < 6)
4731                 return -ENODEV;
4732
4733         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4734
4735         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4736         if (ret)
4737                 return ret;
4738
4739         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4740         mutex_unlock(&dev_priv->rps.hw_lock);
4741
4742         return 0;
4743 }
4744
4745 static int
4746 i915_min_freq_set(void *data, u64 val)
4747 {
4748         struct drm_device *dev = data;
4749         struct drm_i915_private *dev_priv = dev->dev_private;
4750         u32 hw_max, hw_min;
4751         int ret;
4752
4753         if (INTEL_INFO(dev)->gen < 6)
4754                 return -ENODEV;
4755
4756         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4757
4758         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4759
4760         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4761         if (ret)
4762                 return ret;
4763
4764         /*
4765          * Turbo will still be enabled, but won't go below the set value.
4766          */
4767         val = intel_freq_opcode(dev_priv, val);
4768
4769         hw_max = dev_priv->rps.max_freq;
4770         hw_min = dev_priv->rps.min_freq;
4771
4772         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4773                 mutex_unlock(&dev_priv->rps.hw_lock);
4774                 return -EINVAL;
4775         }
4776
4777         dev_priv->rps.min_freq_softlimit = val;
4778
4779         intel_set_rps(dev, val);
4780
4781         mutex_unlock(&dev_priv->rps.hw_lock);
4782
4783         return 0;
4784 }
4785
4786 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4787                         i915_min_freq_get, i915_min_freq_set,
4788                         "%llu\n");
4789
4790 static int
4791 i915_cache_sharing_get(void *data, u64 *val)
4792 {
4793         struct drm_device *dev = data;
4794         struct drm_i915_private *dev_priv = dev->dev_private;
4795         u32 snpcr;
4796         int ret;
4797
4798         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4799                 return -ENODEV;
4800
4801         ret = mutex_lock_interruptible(&dev->struct_mutex);
4802         if (ret)
4803                 return ret;
4804         intel_runtime_pm_get(dev_priv);
4805
4806         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4807
4808         intel_runtime_pm_put(dev_priv);
4809         mutex_unlock(&dev_priv->dev->struct_mutex);
4810
4811         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4812
4813         return 0;
4814 }
4815
4816 static int
4817 i915_cache_sharing_set(void *data, u64 val)
4818 {
4819         struct drm_device *dev = data;
4820         struct drm_i915_private *dev_priv = dev->dev_private;
4821         u32 snpcr;
4822
4823         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4824                 return -ENODEV;
4825
4826         if (val > 3)
4827                 return -EINVAL;
4828
4829         intel_runtime_pm_get(dev_priv);
4830         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4831
4832         /* Update the cache sharing policy here as well */
4833         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4834         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4835         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4836         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4837
4838         intel_runtime_pm_put(dev_priv);
4839         return 0;
4840 }
4841
4842 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4843                         i915_cache_sharing_get, i915_cache_sharing_set,
4844                         "%llu\n");
4845
4846 struct sseu_dev_status {
4847         unsigned int slice_total;
4848         unsigned int subslice_total;
4849         unsigned int subslice_per_slice;
4850         unsigned int eu_total;
4851         unsigned int eu_per_subslice;
4852 };
4853
4854 static void cherryview_sseu_device_status(struct drm_device *dev,
4855                                           struct sseu_dev_status *stat)
4856 {
4857         struct drm_i915_private *dev_priv = dev->dev_private;
4858         const int ss_max = 2;
4859         int ss;
4860         u32 sig1[ss_max], sig2[ss_max];
4861
4862         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4863         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4864         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4865         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4866
4867         for (ss = 0; ss < ss_max; ss++) {
4868                 unsigned int eu_cnt;
4869
4870                 if (sig1[ss] & CHV_SS_PG_ENABLE)
4871                         /* skip disabled subslice */
4872                         continue;
4873
4874                 stat->slice_total = 1;
4875                 stat->subslice_per_slice++;
4876                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4877                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4878                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4879                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4880                 stat->eu_total += eu_cnt;
4881                 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
4882         }
4883         stat->subslice_total = stat->subslice_per_slice;
4884 }
4885
4886 static void gen9_sseu_device_status(struct drm_device *dev,
4887                                     struct sseu_dev_status *stat)
4888 {
4889         struct drm_i915_private *dev_priv = dev->dev_private;
4890         int s_max = 3, ss_max = 4;
4891         int s, ss;
4892         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4893
4894         /* BXT has a single slice and at most 3 subslices. */
4895         if (IS_BROXTON(dev)) {
4896                 s_max = 1;
4897                 ss_max = 3;
4898         }
4899
4900         for (s = 0; s < s_max; s++) {
4901                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4902                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4903                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4904         }
4905
4906         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4907                      GEN9_PGCTL_SSA_EU19_ACK |
4908                      GEN9_PGCTL_SSA_EU210_ACK |
4909                      GEN9_PGCTL_SSA_EU311_ACK;
4910         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4911                      GEN9_PGCTL_SSB_EU19_ACK |
4912                      GEN9_PGCTL_SSB_EU210_ACK |
4913                      GEN9_PGCTL_SSB_EU311_ACK;
4914
4915         for (s = 0; s < s_max; s++) {
4916                 unsigned int ss_cnt = 0;
4917
4918                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4919                         /* skip disabled slice */
4920                         continue;
4921
4922                 stat->slice_total++;
4923
4924                 if (IS_SKYLAKE(dev))
4925                         ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
4926
4927                 for (ss = 0; ss < ss_max; ss++) {
4928                         unsigned int eu_cnt;
4929
4930                         if (IS_BROXTON(dev) &&
4931                             !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4932                                 /* skip disabled subslice */
4933                                 continue;
4934
4935                         if (IS_BROXTON(dev))
4936                                 ss_cnt++;
4937
4938                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4939                                                eu_mask[ss%2]);
4940                         stat->eu_total += eu_cnt;
4941                         stat->eu_per_subslice = max(stat->eu_per_subslice,
4942                                                     eu_cnt);
4943                 }
4944
4945                 stat->subslice_total += ss_cnt;
4946                 stat->subslice_per_slice = max(stat->subslice_per_slice,
4947                                                ss_cnt);
4948         }
4949 }
4950
4951 static int i915_sseu_status(struct seq_file *m, void *unused)
4952 {
4953         struct drm_info_node *node = (struct drm_info_node *) m->private;
4954         struct drm_device *dev = node->minor->dev;
4955         struct sseu_dev_status stat;
4956
4957         if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
4958                 return -ENODEV;
4959
4960         seq_puts(m, "SSEU Device Info\n");
4961         seq_printf(m, "  Available Slice Total: %u\n",
4962                    INTEL_INFO(dev)->slice_total);
4963         seq_printf(m, "  Available Subslice Total: %u\n",
4964                    INTEL_INFO(dev)->subslice_total);
4965         seq_printf(m, "  Available Subslice Per Slice: %u\n",
4966                    INTEL_INFO(dev)->subslice_per_slice);
4967         seq_printf(m, "  Available EU Total: %u\n",
4968                    INTEL_INFO(dev)->eu_total);
4969         seq_printf(m, "  Available EU Per Subslice: %u\n",
4970                    INTEL_INFO(dev)->eu_per_subslice);
4971         seq_printf(m, "  Has Slice Power Gating: %s\n",
4972                    yesno(INTEL_INFO(dev)->has_slice_pg));
4973         seq_printf(m, "  Has Subslice Power Gating: %s\n",
4974                    yesno(INTEL_INFO(dev)->has_subslice_pg));
4975         seq_printf(m, "  Has EU Power Gating: %s\n",
4976                    yesno(INTEL_INFO(dev)->has_eu_pg));
4977
4978         seq_puts(m, "SSEU Device Status\n");
4979         memset(&stat, 0, sizeof(stat));
4980         if (IS_CHERRYVIEW(dev)) {
4981                 cherryview_sseu_device_status(dev, &stat);
4982         } else if (INTEL_INFO(dev)->gen >= 9) {
4983                 gen9_sseu_device_status(dev, &stat);
4984         }
4985         seq_printf(m, "  Enabled Slice Total: %u\n",
4986                    stat.slice_total);
4987         seq_printf(m, "  Enabled Subslice Total: %u\n",
4988                    stat.subslice_total);
4989         seq_printf(m, "  Enabled Subslice Per Slice: %u\n",
4990                    stat.subslice_per_slice);
4991         seq_printf(m, "  Enabled EU Total: %u\n",
4992                    stat.eu_total);
4993         seq_printf(m, "  Enabled EU Per Subslice: %u\n",
4994                    stat.eu_per_subslice);
4995
4996         return 0;
4997 }
4998
4999 static int i915_forcewake_open(struct inode *inode, struct file *file)
5000 {
5001         struct drm_device *dev = inode->i_private;
5002         struct drm_i915_private *dev_priv = dev->dev_private;
5003
5004         if (INTEL_INFO(dev)->gen < 6)
5005                 return 0;
5006
5007         intel_runtime_pm_get(dev_priv);
5008         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5009
5010         return 0;
5011 }
5012
5013 static int i915_forcewake_release(struct inode *inode, struct file *file)
5014 {
5015         struct drm_device *dev = inode->i_private;
5016         struct drm_i915_private *dev_priv = dev->dev_private;
5017
5018         if (INTEL_INFO(dev)->gen < 6)
5019                 return 0;
5020
5021         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5022         intel_runtime_pm_put(dev_priv);
5023
5024         return 0;
5025 }
5026
5027 static const struct file_operations i915_forcewake_fops = {
5028         .owner = THIS_MODULE,
5029         .open = i915_forcewake_open,
5030         .release = i915_forcewake_release,
5031 };
5032
5033 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5034 {
5035         struct drm_device *dev = minor->dev;
5036         struct dentry *ent;
5037
5038         ent = debugfs_create_file("i915_forcewake_user",
5039                                   S_IRUSR,
5040                                   root, dev,
5041                                   &i915_forcewake_fops);
5042         if (!ent)
5043                 return -ENOMEM;
5044
5045         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5046 }
5047
5048 static int i915_debugfs_create(struct dentry *root,
5049                                struct drm_minor *minor,
5050                                const char *name,
5051                                const struct file_operations *fops)
5052 {
5053         struct drm_device *dev = minor->dev;
5054         struct dentry *ent;
5055
5056         ent = debugfs_create_file(name,
5057                                   S_IRUGO | S_IWUSR,
5058                                   root, dev,
5059                                   fops);
5060         if (!ent)
5061                 return -ENOMEM;
5062
5063         return drm_add_fake_info_node(minor, ent, fops);
5064 }
5065
5066 static const struct drm_info_list i915_debugfs_list[] = {
5067         {"i915_capabilities", i915_capabilities, 0},
5068         {"i915_gem_objects", i915_gem_object_info, 0},
5069         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5070         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5071         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5072         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5073         {"i915_gem_stolen", i915_gem_stolen_list_info },
5074         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5075         {"i915_gem_request", i915_gem_request_info, 0},
5076         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5077         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5078         {"i915_gem_interrupt", i915_interrupt_info, 0},
5079         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5080         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5081         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5082         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5083         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5084         {"i915_frequency_info", i915_frequency_info, 0},
5085         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5086         {"i915_drpc_info", i915_drpc_info, 0},
5087         {"i915_emon_status", i915_emon_status, 0},
5088         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5089         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5090         {"i915_fbc_status", i915_fbc_status, 0},
5091         {"i915_ips_status", i915_ips_status, 0},
5092         {"i915_sr_status", i915_sr_status, 0},
5093         {"i915_opregion", i915_opregion, 0},
5094         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5095         {"i915_context_status", i915_context_status, 0},
5096         {"i915_dump_lrc", i915_dump_lrc, 0},
5097         {"i915_execlists", i915_execlists, 0},
5098         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5099         {"i915_swizzle_info", i915_swizzle_info, 0},
5100         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5101         {"i915_llc", i915_llc, 0},
5102         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5103         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5104         {"i915_energy_uJ", i915_energy_uJ, 0},
5105         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5106         {"i915_power_domain_info", i915_power_domain_info, 0},
5107         {"i915_display_info", i915_display_info, 0},
5108         {"i915_semaphore_status", i915_semaphore_status, 0},
5109         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5110         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5111         {"i915_wa_registers", i915_wa_registers, 0},
5112         {"i915_ddb_info", i915_ddb_info, 0},
5113         {"i915_sseu_status", i915_sseu_status, 0},
5114         {"i915_drrs_status", i915_drrs_status, 0},
5115         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5116 };
5117 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5118
5119 static const struct i915_debugfs_files {
5120         const char *name;
5121         const struct file_operations *fops;
5122 } i915_debugfs_files[] = {
5123         {"i915_wedged", &i915_wedged_fops},
5124         {"i915_max_freq", &i915_max_freq_fops},
5125         {"i915_min_freq", &i915_min_freq_fops},
5126         {"i915_cache_sharing", &i915_cache_sharing_fops},
5127         {"i915_ring_stop", &i915_ring_stop_fops},
5128         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5129         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5130         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5131         {"i915_error_state", &i915_error_state_fops},
5132         {"i915_next_seqno", &i915_next_seqno_fops},
5133         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5134         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5135         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5136         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5137         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5138         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5139         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5140         {"i915_dp_test_active", &i915_displayport_test_active_fops}
5141 };
5142
5143 void intel_display_crc_init(struct drm_device *dev)
5144 {
5145         struct drm_i915_private *dev_priv = dev->dev_private;
5146         enum pipe pipe;
5147
5148         for_each_pipe(dev_priv, pipe) {
5149                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5150
5151                 pipe_crc->opened = false;
5152                 spin_lock_init(&pipe_crc->lock);
5153                 init_waitqueue_head(&pipe_crc->wq);
5154         }
5155 }
5156
5157 int i915_debugfs_init(struct drm_minor *minor)
5158 {
5159         int ret, i;
5160
5161         ret = i915_forcewake_create(minor->debugfs_root, minor);
5162         if (ret)
5163                 return ret;
5164
5165         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5166                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5167                 if (ret)
5168                         return ret;
5169         }
5170
5171         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5172                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5173                                           i915_debugfs_files[i].name,
5174                                           i915_debugfs_files[i].fops);
5175                 if (ret)
5176                         return ret;
5177         }
5178
5179         return drm_debugfs_create_files(i915_debugfs_list,
5180                                         I915_DEBUGFS_ENTRIES,
5181                                         minor->debugfs_root, minor);
5182 }
5183
5184 void i915_debugfs_cleanup(struct drm_minor *minor)
5185 {
5186         int i;
5187
5188         drm_debugfs_remove_files(i915_debugfs_list,
5189                                  I915_DEBUGFS_ENTRIES, minor);
5190
5191         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5192                                  1, minor);
5193
5194         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5195                 struct drm_info_list *info_list =
5196                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5197
5198                 drm_debugfs_remove_files(info_list, 1, minor);
5199         }
5200
5201         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5202                 struct drm_info_list *info_list =
5203                         (struct drm_info_list *) i915_debugfs_files[i].fops;
5204
5205                 drm_debugfs_remove_files(info_list, 1, minor);
5206         }
5207 }
5208
5209 struct dpcd_block {
5210         /* DPCD dump start address. */
5211         unsigned int offset;
5212         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5213         unsigned int end;
5214         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5215         size_t size;
5216         /* Only valid for eDP. */
5217         bool edp;
5218 };
5219
5220 static const struct dpcd_block i915_dpcd_debug[] = {
5221         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5222         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5223         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5224         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5225         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5226         { .offset = DP_SET_POWER },
5227         { .offset = DP_EDP_DPCD_REV },
5228         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5229         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5230         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5231 };
5232
5233 static int i915_dpcd_show(struct seq_file *m, void *data)
5234 {
5235         struct drm_connector *connector = m->private;
5236         struct intel_dp *intel_dp =
5237                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5238         uint8_t buf[16];
5239         ssize_t err;
5240         int i;
5241
5242         if (connector->status != connector_status_connected)
5243                 return -ENODEV;
5244
5245         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5246                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5247                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5248
5249                 if (b->edp &&
5250                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5251                         continue;
5252
5253                 /* low tech for now */
5254                 if (WARN_ON(size > sizeof(buf)))
5255                         continue;
5256
5257                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5258                 if (err <= 0) {
5259                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5260                                   size, b->offset, err);
5261                         continue;
5262                 }
5263
5264                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5265         }
5266
5267         return 0;
5268 }
5269
5270 static int i915_dpcd_open(struct inode *inode, struct file *file)
5271 {
5272         return single_open(file, i915_dpcd_show, inode->i_private);
5273 }
5274
5275 static const struct file_operations i915_dpcd_fops = {
5276         .owner = THIS_MODULE,
5277         .open = i915_dpcd_open,
5278         .read = seq_read,
5279         .llseek = seq_lseek,
5280         .release = single_release,
5281 };
5282
5283 /**
5284  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5285  * @connector: pointer to a registered drm_connector
5286  *
5287  * Cleanup will be done by drm_connector_unregister() through a call to
5288  * drm_debugfs_connector_remove().
5289  *
5290  * Returns 0 on success, negative error codes on error.
5291  */
5292 int i915_debugfs_connector_add(struct drm_connector *connector)
5293 {
5294         struct dentry *root = connector->debugfs_entry;
5295
5296         /* The connector must have been registered beforehands. */
5297         if (!root)
5298                 return -ENODEV;
5299
5300         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5301             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5302                 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5303                                     &i915_dpcd_fops);
5304
5305         return 0;
5306 }