2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 static const char *yesno(int v)
51 return v ? "yes" : "no";
54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
57 drm_add_fake_info_node(struct drm_minor *minor,
61 struct drm_info_node *node;
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
71 node->info_ent = (void *) key;
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
80 static int i915_capabilities(struct seq_file *m, void *data)
82 struct drm_info_node *node = m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
86 seq_printf(m, "gen: %d\n", info->gen);
87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
88 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89 #define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
105 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
107 switch (obj->tiling_mode) {
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
115 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
120 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
123 struct i915_vma *vma;
125 list_for_each_entry(vma, &obj->vma_list, vma_link) {
126 if (i915_is_ggtt(vma->vm) &&
127 drm_mm_node_allocated(&vma->node))
128 size += vma->node.size;
135 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
137 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
138 struct intel_engine_cs *ring;
139 struct i915_vma *vma;
143 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
145 obj->active ? "*" : " ",
147 get_tiling_flag(obj),
148 get_global_flag(obj),
149 obj->base.size / 1024,
150 obj->base.read_domains,
151 obj->base.write_domain);
152 for_each_ring(ring, dev_priv, i)
154 i915_gem_request_get_seqno(obj->last_read_req[i]));
155 seq_printf(m, "] %x %x%s%s%s",
156 i915_gem_request_get_seqno(obj->last_write_req),
157 i915_gem_request_get_seqno(obj->last_fenced_req),
158 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
159 obj->dirty ? " dirty" : "",
160 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
162 seq_printf(m, " (name: %d)", obj->base.name);
163 list_for_each_entry(vma, &obj->vma_list, vma_link) {
164 if (vma->pin_count > 0)
167 seq_printf(m, " (pinned x %d)", pin_count);
168 if (obj->pin_display)
169 seq_printf(m, " (display)");
170 if (obj->fence_reg != I915_FENCE_REG_NONE)
171 seq_printf(m, " (fence: %d)", obj->fence_reg);
172 list_for_each_entry(vma, &obj->vma_list, vma_link) {
173 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
174 i915_is_ggtt(vma->vm) ? "g" : "pp",
175 vma->node.start, vma->node.size);
176 if (i915_is_ggtt(vma->vm))
177 seq_printf(m, ", type: %u)", vma->ggtt_view.type);
182 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
183 if (obj->pin_display || obj->fault_mappable) {
185 if (obj->pin_display)
187 if (obj->fault_mappable)
190 seq_printf(m, " (%s mappable)", s);
192 if (obj->last_write_req != NULL)
193 seq_printf(m, " (%s)",
194 i915_gem_request_get_ring(obj->last_write_req)->name);
195 if (obj->frontbuffer_bits)
196 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
199 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
201 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
202 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
206 static int i915_gem_object_list_info(struct seq_file *m, void *data)
208 struct drm_info_node *node = m->private;
209 uintptr_t list = (uintptr_t) node->info_ent->data;
210 struct list_head *head;
211 struct drm_device *dev = node->minor->dev;
212 struct drm_i915_private *dev_priv = dev->dev_private;
213 struct i915_address_space *vm = &dev_priv->gtt.base;
214 struct i915_vma *vma;
215 u64 total_obj_size, total_gtt_size;
218 ret = mutex_lock_interruptible(&dev->struct_mutex);
222 /* FIXME: the user of this interface might want more than just GGTT */
225 seq_puts(m, "Active:\n");
226 head = &vm->active_list;
229 seq_puts(m, "Inactive:\n");
230 head = &vm->inactive_list;
233 mutex_unlock(&dev->struct_mutex);
237 total_obj_size = total_gtt_size = count = 0;
238 list_for_each_entry(vma, head, mm_list) {
240 describe_obj(m, vma->obj);
242 total_obj_size += vma->obj->base.size;
243 total_gtt_size += vma->node.size;
246 mutex_unlock(&dev->struct_mutex);
248 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
249 count, total_obj_size, total_gtt_size);
253 static int obj_rank_by_stolen(void *priv,
254 struct list_head *A, struct list_head *B)
256 struct drm_i915_gem_object *a =
257 container_of(A, struct drm_i915_gem_object, obj_exec_link);
258 struct drm_i915_gem_object *b =
259 container_of(B, struct drm_i915_gem_object, obj_exec_link);
261 return a->stolen->start - b->stolen->start;
264 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
266 struct drm_info_node *node = m->private;
267 struct drm_device *dev = node->minor->dev;
268 struct drm_i915_private *dev_priv = dev->dev_private;
269 struct drm_i915_gem_object *obj;
270 u64 total_obj_size, total_gtt_size;
274 ret = mutex_lock_interruptible(&dev->struct_mutex);
278 total_obj_size = total_gtt_size = count = 0;
279 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
280 if (obj->stolen == NULL)
283 list_add(&obj->obj_exec_link, &stolen);
285 total_obj_size += obj->base.size;
286 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
289 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
290 if (obj->stolen == NULL)
293 list_add(&obj->obj_exec_link, &stolen);
295 total_obj_size += obj->base.size;
298 list_sort(NULL, &stolen, obj_rank_by_stolen);
299 seq_puts(m, "Stolen:\n");
300 while (!list_empty(&stolen)) {
301 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
303 describe_obj(m, obj);
305 list_del_init(&obj->obj_exec_link);
307 mutex_unlock(&dev->struct_mutex);
309 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
310 count, total_obj_size, total_gtt_size);
314 #define count_objects(list, member) do { \
315 list_for_each_entry(obj, list, member) { \
316 size += i915_gem_obj_total_ggtt_size(obj); \
318 if (obj->map_and_fenceable) { \
319 mappable_size += i915_gem_obj_ggtt_size(obj); \
326 struct drm_i915_file_private *file_priv;
330 u64 active, inactive;
333 static int per_file_stats(int id, void *ptr, void *data)
335 struct drm_i915_gem_object *obj = ptr;
336 struct file_stats *stats = data;
337 struct i915_vma *vma;
340 stats->total += obj->base.size;
342 if (obj->base.name || obj->base.dma_buf)
343 stats->shared += obj->base.size;
345 if (USES_FULL_PPGTT(obj->base.dev)) {
346 list_for_each_entry(vma, &obj->vma_list, vma_link) {
347 struct i915_hw_ppgtt *ppgtt;
349 if (!drm_mm_node_allocated(&vma->node))
352 if (i915_is_ggtt(vma->vm)) {
353 stats->global += obj->base.size;
357 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
358 if (ppgtt->file_priv != stats->file_priv)
361 if (obj->active) /* XXX per-vma statistic */
362 stats->active += obj->base.size;
364 stats->inactive += obj->base.size;
369 if (i915_gem_obj_ggtt_bound(obj)) {
370 stats->global += obj->base.size;
372 stats->active += obj->base.size;
374 stats->inactive += obj->base.size;
379 if (!list_empty(&obj->global_list))
380 stats->unbound += obj->base.size;
385 #define print_file_stats(m, name, stats) do { \
387 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
398 static void print_batch_pool_stats(struct seq_file *m,
399 struct drm_i915_private *dev_priv)
401 struct drm_i915_gem_object *obj;
402 struct file_stats stats;
403 struct intel_engine_cs *ring;
406 memset(&stats, 0, sizeof(stats));
408 for_each_ring(ring, dev_priv, i) {
409 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
410 list_for_each_entry(obj,
411 &ring->batch_pool.cache_list[j],
413 per_file_stats(0, obj, &stats);
417 print_file_stats(m, "[k]batch pool", stats);
420 #define count_vmas(list, member) do { \
421 list_for_each_entry(vma, list, member) { \
422 size += i915_gem_obj_total_ggtt_size(vma->obj); \
424 if (vma->obj->map_and_fenceable) { \
425 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
431 static int i915_gem_object_info(struct seq_file *m, void* data)
433 struct drm_info_node *node = m->private;
434 struct drm_device *dev = node->minor->dev;
435 struct drm_i915_private *dev_priv = dev->dev_private;
436 u32 count, mappable_count, purgeable_count;
437 u64 size, mappable_size, purgeable_size;
438 struct drm_i915_gem_object *obj;
439 struct i915_address_space *vm = &dev_priv->gtt.base;
440 struct drm_file *file;
441 struct i915_vma *vma;
444 ret = mutex_lock_interruptible(&dev->struct_mutex);
448 seq_printf(m, "%u objects, %zu bytes\n",
449 dev_priv->mm.object_count,
450 dev_priv->mm.object_memory);
452 size = count = mappable_size = mappable_count = 0;
453 count_objects(&dev_priv->mm.bound_list, global_list);
454 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
455 count, mappable_count, size, mappable_size);
457 size = count = mappable_size = mappable_count = 0;
458 count_vmas(&vm->active_list, mm_list);
459 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
460 count, mappable_count, size, mappable_size);
462 size = count = mappable_size = mappable_count = 0;
463 count_vmas(&vm->inactive_list, mm_list);
464 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
465 count, mappable_count, size, mappable_size);
467 size = count = purgeable_size = purgeable_count = 0;
468 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
469 size += obj->base.size, ++count;
470 if (obj->madv == I915_MADV_DONTNEED)
471 purgeable_size += obj->base.size, ++purgeable_count;
473 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
475 size = count = mappable_size = mappable_count = 0;
476 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
477 if (obj->fault_mappable) {
478 size += i915_gem_obj_ggtt_size(obj);
481 if (obj->pin_display) {
482 mappable_size += i915_gem_obj_ggtt_size(obj);
485 if (obj->madv == I915_MADV_DONTNEED) {
486 purgeable_size += obj->base.size;
490 seq_printf(m, "%u purgeable objects, %llu bytes\n",
491 purgeable_count, purgeable_size);
492 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
493 mappable_count, mappable_size);
494 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
497 seq_printf(m, "%llu [%llu] gtt total\n",
498 dev_priv->gtt.base.total,
499 (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
502 print_batch_pool_stats(m, dev_priv);
503 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
504 struct file_stats stats;
505 struct task_struct *task;
507 memset(&stats, 0, sizeof(stats));
508 stats.file_priv = file->driver_priv;
509 spin_lock(&file->table_lock);
510 idr_for_each(&file->object_idr, per_file_stats, &stats);
511 spin_unlock(&file->table_lock);
513 * Although we have a valid reference on file->pid, that does
514 * not guarantee that the task_struct who called get_pid() is
515 * still alive (e.g. get_pid(current) => fork() => exit()).
516 * Therefore, we need to protect this ->comm access using RCU.
519 task = pid_task(file->pid, PIDTYPE_PID);
520 print_file_stats(m, task ? task->comm : "<unknown>", stats);
524 mutex_unlock(&dev->struct_mutex);
529 static int i915_gem_gtt_info(struct seq_file *m, void *data)
531 struct drm_info_node *node = m->private;
532 struct drm_device *dev = node->minor->dev;
533 uintptr_t list = (uintptr_t) node->info_ent->data;
534 struct drm_i915_private *dev_priv = dev->dev_private;
535 struct drm_i915_gem_object *obj;
536 u64 total_obj_size, total_gtt_size;
539 ret = mutex_lock_interruptible(&dev->struct_mutex);
543 total_obj_size = total_gtt_size = count = 0;
544 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
545 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
549 describe_obj(m, obj);
551 total_obj_size += obj->base.size;
552 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
556 mutex_unlock(&dev->struct_mutex);
558 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
559 count, total_obj_size, total_gtt_size);
564 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
566 struct drm_info_node *node = m->private;
567 struct drm_device *dev = node->minor->dev;
568 struct drm_i915_private *dev_priv = dev->dev_private;
569 struct intel_crtc *crtc;
572 ret = mutex_lock_interruptible(&dev->struct_mutex);
576 for_each_intel_crtc(dev, crtc) {
577 const char pipe = pipe_name(crtc->pipe);
578 const char plane = plane_name(crtc->plane);
579 struct intel_unpin_work *work;
581 spin_lock_irq(&dev->event_lock);
582 work = crtc->unpin_work;
584 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
589 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
590 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
593 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
596 if (work->flip_queued_req) {
597 struct intel_engine_cs *ring =
598 i915_gem_request_get_ring(work->flip_queued_req);
600 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
602 i915_gem_request_get_seqno(work->flip_queued_req),
603 dev_priv->next_seqno,
604 ring->get_seqno(ring, true),
605 i915_gem_request_completed(work->flip_queued_req, true));
607 seq_printf(m, "Flip not associated with any ring\n");
608 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
609 work->flip_queued_vblank,
610 work->flip_ready_vblank,
611 drm_crtc_vblank_count(&crtc->base));
612 if (work->enable_stall_check)
613 seq_puts(m, "Stall check enabled, ");
615 seq_puts(m, "Stall check waiting for page flip ioctl, ");
616 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
618 if (INTEL_INFO(dev)->gen >= 4)
619 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
621 addr = I915_READ(DSPADDR(crtc->plane));
622 seq_printf(m, "Current scanout address 0x%08x\n", addr);
624 if (work->pending_flip_obj) {
625 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
626 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
629 spin_unlock_irq(&dev->event_lock);
632 mutex_unlock(&dev->struct_mutex);
637 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
639 struct drm_info_node *node = m->private;
640 struct drm_device *dev = node->minor->dev;
641 struct drm_i915_private *dev_priv = dev->dev_private;
642 struct drm_i915_gem_object *obj;
643 struct intel_engine_cs *ring;
647 ret = mutex_lock_interruptible(&dev->struct_mutex);
651 for_each_ring(ring, dev_priv, i) {
652 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
656 list_for_each_entry(obj,
657 &ring->batch_pool.cache_list[j],
660 seq_printf(m, "%s cache[%d]: %d objects\n",
661 ring->name, j, count);
663 list_for_each_entry(obj,
664 &ring->batch_pool.cache_list[j],
667 describe_obj(m, obj);
675 seq_printf(m, "total: %d\n", total);
677 mutex_unlock(&dev->struct_mutex);
682 static int i915_gem_request_info(struct seq_file *m, void *data)
684 struct drm_info_node *node = m->private;
685 struct drm_device *dev = node->minor->dev;
686 struct drm_i915_private *dev_priv = dev->dev_private;
687 struct intel_engine_cs *ring;
688 struct drm_i915_gem_request *req;
691 ret = mutex_lock_interruptible(&dev->struct_mutex);
696 for_each_ring(ring, dev_priv, i) {
700 list_for_each_entry(req, &ring->request_list, list)
705 seq_printf(m, "%s requests: %d\n", ring->name, count);
706 list_for_each_entry(req, &ring->request_list, list) {
707 struct task_struct *task;
712 task = pid_task(req->pid, PIDTYPE_PID);
713 seq_printf(m, " %x @ %d: %s [%d]\n",
715 (int) (jiffies - req->emitted_jiffies),
716 task ? task->comm : "<unknown>",
717 task ? task->pid : -1);
723 mutex_unlock(&dev->struct_mutex);
726 seq_puts(m, "No requests\n");
731 static void i915_ring_seqno_info(struct seq_file *m,
732 struct intel_engine_cs *ring)
734 if (ring->get_seqno) {
735 seq_printf(m, "Current sequence (%s): %x\n",
736 ring->name, ring->get_seqno(ring, false));
740 static int i915_gem_seqno_info(struct seq_file *m, void *data)
742 struct drm_info_node *node = m->private;
743 struct drm_device *dev = node->minor->dev;
744 struct drm_i915_private *dev_priv = dev->dev_private;
745 struct intel_engine_cs *ring;
748 ret = mutex_lock_interruptible(&dev->struct_mutex);
751 intel_runtime_pm_get(dev_priv);
753 for_each_ring(ring, dev_priv, i)
754 i915_ring_seqno_info(m, ring);
756 intel_runtime_pm_put(dev_priv);
757 mutex_unlock(&dev->struct_mutex);
763 static int i915_interrupt_info(struct seq_file *m, void *data)
765 struct drm_info_node *node = m->private;
766 struct drm_device *dev = node->minor->dev;
767 struct drm_i915_private *dev_priv = dev->dev_private;
768 struct intel_engine_cs *ring;
771 ret = mutex_lock_interruptible(&dev->struct_mutex);
774 intel_runtime_pm_get(dev_priv);
776 if (IS_CHERRYVIEW(dev)) {
777 seq_printf(m, "Master Interrupt Control:\t%08x\n",
778 I915_READ(GEN8_MASTER_IRQ));
780 seq_printf(m, "Display IER:\t%08x\n",
782 seq_printf(m, "Display IIR:\t%08x\n",
784 seq_printf(m, "Display IIR_RW:\t%08x\n",
785 I915_READ(VLV_IIR_RW));
786 seq_printf(m, "Display IMR:\t%08x\n",
788 for_each_pipe(dev_priv, pipe)
789 seq_printf(m, "Pipe %c stat:\t%08x\n",
791 I915_READ(PIPESTAT(pipe)));
793 seq_printf(m, "Port hotplug:\t%08x\n",
794 I915_READ(PORT_HOTPLUG_EN));
795 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
796 I915_READ(VLV_DPFLIPSTAT));
797 seq_printf(m, "DPINVGTT:\t%08x\n",
798 I915_READ(DPINVGTT));
800 for (i = 0; i < 4; i++) {
801 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
802 i, I915_READ(GEN8_GT_IMR(i)));
803 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
804 i, I915_READ(GEN8_GT_IIR(i)));
805 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
806 i, I915_READ(GEN8_GT_IER(i)));
809 seq_printf(m, "PCU interrupt mask:\t%08x\n",
810 I915_READ(GEN8_PCU_IMR));
811 seq_printf(m, "PCU interrupt identity:\t%08x\n",
812 I915_READ(GEN8_PCU_IIR));
813 seq_printf(m, "PCU interrupt enable:\t%08x\n",
814 I915_READ(GEN8_PCU_IER));
815 } else if (INTEL_INFO(dev)->gen >= 8) {
816 seq_printf(m, "Master Interrupt Control:\t%08x\n",
817 I915_READ(GEN8_MASTER_IRQ));
819 for (i = 0; i < 4; i++) {
820 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
821 i, I915_READ(GEN8_GT_IMR(i)));
822 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
823 i, I915_READ(GEN8_GT_IIR(i)));
824 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
825 i, I915_READ(GEN8_GT_IER(i)));
828 for_each_pipe(dev_priv, pipe) {
829 if (!intel_display_power_is_enabled(dev_priv,
830 POWER_DOMAIN_PIPE(pipe))) {
831 seq_printf(m, "Pipe %c power disabled\n",
835 seq_printf(m, "Pipe %c IMR:\t%08x\n",
837 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
838 seq_printf(m, "Pipe %c IIR:\t%08x\n",
840 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
841 seq_printf(m, "Pipe %c IER:\t%08x\n",
843 I915_READ(GEN8_DE_PIPE_IER(pipe)));
846 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
847 I915_READ(GEN8_DE_PORT_IMR));
848 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
849 I915_READ(GEN8_DE_PORT_IIR));
850 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
851 I915_READ(GEN8_DE_PORT_IER));
853 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
854 I915_READ(GEN8_DE_MISC_IMR));
855 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
856 I915_READ(GEN8_DE_MISC_IIR));
857 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
858 I915_READ(GEN8_DE_MISC_IER));
860 seq_printf(m, "PCU interrupt mask:\t%08x\n",
861 I915_READ(GEN8_PCU_IMR));
862 seq_printf(m, "PCU interrupt identity:\t%08x\n",
863 I915_READ(GEN8_PCU_IIR));
864 seq_printf(m, "PCU interrupt enable:\t%08x\n",
865 I915_READ(GEN8_PCU_IER));
866 } else if (IS_VALLEYVIEW(dev)) {
867 seq_printf(m, "Display IER:\t%08x\n",
869 seq_printf(m, "Display IIR:\t%08x\n",
871 seq_printf(m, "Display IIR_RW:\t%08x\n",
872 I915_READ(VLV_IIR_RW));
873 seq_printf(m, "Display IMR:\t%08x\n",
875 for_each_pipe(dev_priv, pipe)
876 seq_printf(m, "Pipe %c stat:\t%08x\n",
878 I915_READ(PIPESTAT(pipe)));
880 seq_printf(m, "Master IER:\t%08x\n",
881 I915_READ(VLV_MASTER_IER));
883 seq_printf(m, "Render IER:\t%08x\n",
885 seq_printf(m, "Render IIR:\t%08x\n",
887 seq_printf(m, "Render IMR:\t%08x\n",
890 seq_printf(m, "PM IER:\t\t%08x\n",
891 I915_READ(GEN6_PMIER));
892 seq_printf(m, "PM IIR:\t\t%08x\n",
893 I915_READ(GEN6_PMIIR));
894 seq_printf(m, "PM IMR:\t\t%08x\n",
895 I915_READ(GEN6_PMIMR));
897 seq_printf(m, "Port hotplug:\t%08x\n",
898 I915_READ(PORT_HOTPLUG_EN));
899 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
900 I915_READ(VLV_DPFLIPSTAT));
901 seq_printf(m, "DPINVGTT:\t%08x\n",
902 I915_READ(DPINVGTT));
904 } else if (!HAS_PCH_SPLIT(dev)) {
905 seq_printf(m, "Interrupt enable: %08x\n",
907 seq_printf(m, "Interrupt identity: %08x\n",
909 seq_printf(m, "Interrupt mask: %08x\n",
911 for_each_pipe(dev_priv, pipe)
912 seq_printf(m, "Pipe %c stat: %08x\n",
914 I915_READ(PIPESTAT(pipe)));
916 seq_printf(m, "North Display Interrupt enable: %08x\n",
918 seq_printf(m, "North Display Interrupt identity: %08x\n",
920 seq_printf(m, "North Display Interrupt mask: %08x\n",
922 seq_printf(m, "South Display Interrupt enable: %08x\n",
924 seq_printf(m, "South Display Interrupt identity: %08x\n",
926 seq_printf(m, "South Display Interrupt mask: %08x\n",
928 seq_printf(m, "Graphics Interrupt enable: %08x\n",
930 seq_printf(m, "Graphics Interrupt identity: %08x\n",
932 seq_printf(m, "Graphics Interrupt mask: %08x\n",
935 for_each_ring(ring, dev_priv, i) {
936 if (INTEL_INFO(dev)->gen >= 6) {
938 "Graphics Interrupt mask (%s): %08x\n",
939 ring->name, I915_READ_IMR(ring));
941 i915_ring_seqno_info(m, ring);
943 intel_runtime_pm_put(dev_priv);
944 mutex_unlock(&dev->struct_mutex);
949 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
951 struct drm_info_node *node = m->private;
952 struct drm_device *dev = node->minor->dev;
953 struct drm_i915_private *dev_priv = dev->dev_private;
956 ret = mutex_lock_interruptible(&dev->struct_mutex);
960 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
961 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
962 for (i = 0; i < dev_priv->num_fence_regs; i++) {
963 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
965 seq_printf(m, "Fence %d, pin count = %d, object = ",
966 i, dev_priv->fence_regs[i].pin_count);
968 seq_puts(m, "unused");
970 describe_obj(m, obj);
974 mutex_unlock(&dev->struct_mutex);
978 static int i915_hws_info(struct seq_file *m, void *data)
980 struct drm_info_node *node = m->private;
981 struct drm_device *dev = node->minor->dev;
982 struct drm_i915_private *dev_priv = dev->dev_private;
983 struct intel_engine_cs *ring;
987 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
988 hws = ring->status_page.page_addr;
992 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
993 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
995 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
1001 i915_error_state_write(struct file *filp,
1002 const char __user *ubuf,
1006 struct i915_error_state_file_priv *error_priv = filp->private_data;
1007 struct drm_device *dev = error_priv->dev;
1010 DRM_DEBUG_DRIVER("Resetting error state\n");
1012 ret = mutex_lock_interruptible(&dev->struct_mutex);
1016 i915_destroy_error_state(dev);
1017 mutex_unlock(&dev->struct_mutex);
1022 static int i915_error_state_open(struct inode *inode, struct file *file)
1024 struct drm_device *dev = inode->i_private;
1025 struct i915_error_state_file_priv *error_priv;
1027 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1031 error_priv->dev = dev;
1033 i915_error_state_get(dev, error_priv);
1035 file->private_data = error_priv;
1040 static int i915_error_state_release(struct inode *inode, struct file *file)
1042 struct i915_error_state_file_priv *error_priv = file->private_data;
1044 i915_error_state_put(error_priv);
1050 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1051 size_t count, loff_t *pos)
1053 struct i915_error_state_file_priv *error_priv = file->private_data;
1054 struct drm_i915_error_state_buf error_str;
1056 ssize_t ret_count = 0;
1059 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1063 ret = i915_error_state_to_str(&error_str, error_priv);
1067 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1074 *pos = error_str.start + ret_count;
1076 i915_error_state_buf_release(&error_str);
1077 return ret ?: ret_count;
1080 static const struct file_operations i915_error_state_fops = {
1081 .owner = THIS_MODULE,
1082 .open = i915_error_state_open,
1083 .read = i915_error_state_read,
1084 .write = i915_error_state_write,
1085 .llseek = default_llseek,
1086 .release = i915_error_state_release,
1090 i915_next_seqno_get(void *data, u64 *val)
1092 struct drm_device *dev = data;
1093 struct drm_i915_private *dev_priv = dev->dev_private;
1096 ret = mutex_lock_interruptible(&dev->struct_mutex);
1100 *val = dev_priv->next_seqno;
1101 mutex_unlock(&dev->struct_mutex);
1107 i915_next_seqno_set(void *data, u64 val)
1109 struct drm_device *dev = data;
1112 ret = mutex_lock_interruptible(&dev->struct_mutex);
1116 ret = i915_gem_set_seqno(dev, val);
1117 mutex_unlock(&dev->struct_mutex);
1122 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1123 i915_next_seqno_get, i915_next_seqno_set,
1126 static int i915_frequency_info(struct seq_file *m, void *unused)
1128 struct drm_info_node *node = m->private;
1129 struct drm_device *dev = node->minor->dev;
1130 struct drm_i915_private *dev_priv = dev->dev_private;
1133 intel_runtime_pm_get(dev_priv);
1135 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1138 u16 rgvswctl = I915_READ16(MEMSWCTL);
1139 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1141 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1142 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1143 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1145 seq_printf(m, "Current P-state: %d\n",
1146 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1147 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1148 IS_BROADWELL(dev) || IS_GEN9(dev)) {
1149 u32 rp_state_limits;
1152 u32 rpmodectl, rpinclimit, rpdeclimit;
1153 u32 rpstat, cagf, reqf;
1154 u32 rpupei, rpcurup, rpprevup;
1155 u32 rpdownei, rpcurdown, rpprevdown;
1156 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1159 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1160 if (IS_BROXTON(dev)) {
1161 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1162 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1164 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1165 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1168 /* RPSTAT1 is in the GT power well */
1169 ret = mutex_lock_interruptible(&dev->struct_mutex);
1173 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1175 reqf = I915_READ(GEN6_RPNSWREQ);
1179 reqf &= ~GEN6_TURBO_DISABLE;
1180 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1185 reqf = intel_gpu_freq(dev_priv, reqf);
1187 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1188 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1189 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1191 rpstat = I915_READ(GEN6_RPSTAT1);
1192 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1193 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1194 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1195 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1196 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1197 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1199 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1200 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1201 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1203 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1204 cagf = intel_gpu_freq(dev_priv, cagf);
1206 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1207 mutex_unlock(&dev->struct_mutex);
1209 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1210 pm_ier = I915_READ(GEN6_PMIER);
1211 pm_imr = I915_READ(GEN6_PMIMR);
1212 pm_isr = I915_READ(GEN6_PMISR);
1213 pm_iir = I915_READ(GEN6_PMIIR);
1214 pm_mask = I915_READ(GEN6_PMINTRMSK);
1216 pm_ier = I915_READ(GEN8_GT_IER(2));
1217 pm_imr = I915_READ(GEN8_GT_IMR(2));
1218 pm_isr = I915_READ(GEN8_GT_ISR(2));
1219 pm_iir = I915_READ(GEN8_GT_IIR(2));
1220 pm_mask = I915_READ(GEN6_PMINTRMSK);
1222 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1223 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1224 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1225 seq_printf(m, "Render p-state ratio: %d\n",
1226 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1227 seq_printf(m, "Render p-state VID: %d\n",
1228 gt_perf_status & 0xff);
1229 seq_printf(m, "Render p-state limit: %d\n",
1230 rp_state_limits & 0xff);
1231 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1232 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1233 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1234 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1235 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1236 seq_printf(m, "CAGF: %dMHz\n", cagf);
1237 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1238 GEN6_CURICONT_MASK);
1239 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1240 GEN6_CURBSYTAVG_MASK);
1241 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1242 GEN6_CURBSYTAVG_MASK);
1243 seq_printf(m, "Up threshold: %d%%\n",
1244 dev_priv->rps.up_threshold);
1246 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1248 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1249 GEN6_CURBSYTAVG_MASK);
1250 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1251 GEN6_CURBSYTAVG_MASK);
1252 seq_printf(m, "Down threshold: %d%%\n",
1253 dev_priv->rps.down_threshold);
1255 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1256 rp_state_cap >> 16) & 0xff;
1257 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1258 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1259 intel_gpu_freq(dev_priv, max_freq));
1261 max_freq = (rp_state_cap & 0xff00) >> 8;
1262 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1263 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1264 intel_gpu_freq(dev_priv, max_freq));
1266 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1267 rp_state_cap >> 0) & 0xff;
1268 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1269 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1270 intel_gpu_freq(dev_priv, max_freq));
1271 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1272 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1274 seq_printf(m, "Current freq: %d MHz\n",
1275 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1276 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1277 seq_printf(m, "Idle freq: %d MHz\n",
1278 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1279 seq_printf(m, "Min freq: %d MHz\n",
1280 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1281 seq_printf(m, "Max freq: %d MHz\n",
1282 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1284 "efficient (RPe) frequency: %d MHz\n",
1285 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1286 } else if (IS_VALLEYVIEW(dev)) {
1289 mutex_lock(&dev_priv->rps.hw_lock);
1290 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1291 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1292 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1294 seq_printf(m, "actual GPU freq: %d MHz\n",
1295 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1297 seq_printf(m, "current GPU freq: %d MHz\n",
1298 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1300 seq_printf(m, "max GPU freq: %d MHz\n",
1301 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1303 seq_printf(m, "min GPU freq: %d MHz\n",
1304 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1306 seq_printf(m, "idle GPU freq: %d MHz\n",
1307 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1310 "efficient (RPe) frequency: %d MHz\n",
1311 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1312 mutex_unlock(&dev_priv->rps.hw_lock);
1314 seq_puts(m, "no P-state info available\n");
1318 intel_runtime_pm_put(dev_priv);
1322 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1324 struct drm_info_node *node = m->private;
1325 struct drm_device *dev = node->minor->dev;
1326 struct drm_i915_private *dev_priv = dev->dev_private;
1327 struct intel_engine_cs *ring;
1328 u64 acthd[I915_NUM_RINGS];
1329 u32 seqno[I915_NUM_RINGS];
1332 if (!i915.enable_hangcheck) {
1333 seq_printf(m, "Hangcheck disabled\n");
1337 intel_runtime_pm_get(dev_priv);
1339 for_each_ring(ring, dev_priv, i) {
1340 seqno[i] = ring->get_seqno(ring, false);
1341 acthd[i] = intel_ring_get_active_head(ring);
1344 intel_runtime_pm_put(dev_priv);
1346 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1347 seq_printf(m, "Hangcheck active, fires in %dms\n",
1348 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1351 seq_printf(m, "Hangcheck inactive\n");
1353 for_each_ring(ring, dev_priv, i) {
1354 seq_printf(m, "%s:\n", ring->name);
1355 seq_printf(m, "\tseqno = %x [current %x]\n",
1356 ring->hangcheck.seqno, seqno[i]);
1357 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1358 (long long)ring->hangcheck.acthd,
1359 (long long)acthd[i]);
1360 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1361 (long long)ring->hangcheck.max_acthd);
1362 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1363 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1369 static int ironlake_drpc_info(struct seq_file *m)
1371 struct drm_info_node *node = m->private;
1372 struct drm_device *dev = node->minor->dev;
1373 struct drm_i915_private *dev_priv = dev->dev_private;
1374 u32 rgvmodectl, rstdbyctl;
1378 ret = mutex_lock_interruptible(&dev->struct_mutex);
1381 intel_runtime_pm_get(dev_priv);
1383 rgvmodectl = I915_READ(MEMMODECTL);
1384 rstdbyctl = I915_READ(RSTDBYCTL);
1385 crstandvid = I915_READ16(CRSTANDVID);
1387 intel_runtime_pm_put(dev_priv);
1388 mutex_unlock(&dev->struct_mutex);
1390 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1392 seq_printf(m, "Boost freq: %d\n",
1393 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1394 MEMMODE_BOOST_FREQ_SHIFT);
1395 seq_printf(m, "HW control enabled: %s\n",
1396 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1397 seq_printf(m, "SW control enabled: %s\n",
1398 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1399 seq_printf(m, "Gated voltage change: %s\n",
1400 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1401 seq_printf(m, "Starting frequency: P%d\n",
1402 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1403 seq_printf(m, "Max P-state: P%d\n",
1404 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1405 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1406 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1407 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1408 seq_printf(m, "Render standby enabled: %s\n",
1409 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1410 seq_puts(m, "Current RS state: ");
1411 switch (rstdbyctl & RSX_STATUS_MASK) {
1413 seq_puts(m, "on\n");
1415 case RSX_STATUS_RC1:
1416 seq_puts(m, "RC1\n");
1418 case RSX_STATUS_RC1E:
1419 seq_puts(m, "RC1E\n");
1421 case RSX_STATUS_RS1:
1422 seq_puts(m, "RS1\n");
1424 case RSX_STATUS_RS2:
1425 seq_puts(m, "RS2 (RC6)\n");
1427 case RSX_STATUS_RS3:
1428 seq_puts(m, "RC3 (RC6+)\n");
1431 seq_puts(m, "unknown\n");
1438 static int i915_forcewake_domains(struct seq_file *m, void *data)
1440 struct drm_info_node *node = m->private;
1441 struct drm_device *dev = node->minor->dev;
1442 struct drm_i915_private *dev_priv = dev->dev_private;
1443 struct intel_uncore_forcewake_domain *fw_domain;
1446 spin_lock_irq(&dev_priv->uncore.lock);
1447 for_each_fw_domain(fw_domain, dev_priv, i) {
1448 seq_printf(m, "%s.wake_count = %u\n",
1449 intel_uncore_forcewake_domain_to_str(i),
1450 fw_domain->wake_count);
1452 spin_unlock_irq(&dev_priv->uncore.lock);
1457 static int vlv_drpc_info(struct seq_file *m)
1459 struct drm_info_node *node = m->private;
1460 struct drm_device *dev = node->minor->dev;
1461 struct drm_i915_private *dev_priv = dev->dev_private;
1462 u32 rpmodectl1, rcctl1, pw_status;
1464 intel_runtime_pm_get(dev_priv);
1466 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1467 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1468 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1470 intel_runtime_pm_put(dev_priv);
1472 seq_printf(m, "Video Turbo Mode: %s\n",
1473 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1474 seq_printf(m, "Turbo enabled: %s\n",
1475 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1476 seq_printf(m, "HW control enabled: %s\n",
1477 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1478 seq_printf(m, "SW control enabled: %s\n",
1479 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1480 GEN6_RP_MEDIA_SW_MODE));
1481 seq_printf(m, "RC6 Enabled: %s\n",
1482 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1483 GEN6_RC_CTL_EI_MODE(1))));
1484 seq_printf(m, "Render Power Well: %s\n",
1485 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1486 seq_printf(m, "Media Power Well: %s\n",
1487 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1489 seq_printf(m, "Render RC6 residency since boot: %u\n",
1490 I915_READ(VLV_GT_RENDER_RC6));
1491 seq_printf(m, "Media RC6 residency since boot: %u\n",
1492 I915_READ(VLV_GT_MEDIA_RC6));
1494 return i915_forcewake_domains(m, NULL);
1497 static int gen6_drpc_info(struct seq_file *m)
1499 struct drm_info_node *node = m->private;
1500 struct drm_device *dev = node->minor->dev;
1501 struct drm_i915_private *dev_priv = dev->dev_private;
1502 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1503 unsigned forcewake_count;
1506 ret = mutex_lock_interruptible(&dev->struct_mutex);
1509 intel_runtime_pm_get(dev_priv);
1511 spin_lock_irq(&dev_priv->uncore.lock);
1512 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1513 spin_unlock_irq(&dev_priv->uncore.lock);
1515 if (forcewake_count) {
1516 seq_puts(m, "RC information inaccurate because somebody "
1517 "holds a forcewake reference \n");
1519 /* NB: we cannot use forcewake, else we read the wrong values */
1520 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1522 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1525 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1526 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1528 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1529 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1530 mutex_unlock(&dev->struct_mutex);
1531 mutex_lock(&dev_priv->rps.hw_lock);
1532 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1533 mutex_unlock(&dev_priv->rps.hw_lock);
1535 intel_runtime_pm_put(dev_priv);
1537 seq_printf(m, "Video Turbo Mode: %s\n",
1538 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1539 seq_printf(m, "HW control enabled: %s\n",
1540 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1541 seq_printf(m, "SW control enabled: %s\n",
1542 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1543 GEN6_RP_MEDIA_SW_MODE));
1544 seq_printf(m, "RC1e Enabled: %s\n",
1545 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1546 seq_printf(m, "RC6 Enabled: %s\n",
1547 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1548 seq_printf(m, "Deep RC6 Enabled: %s\n",
1549 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1550 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1551 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1552 seq_puts(m, "Current RC state: ");
1553 switch (gt_core_status & GEN6_RCn_MASK) {
1555 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1556 seq_puts(m, "Core Power Down\n");
1558 seq_puts(m, "on\n");
1561 seq_puts(m, "RC3\n");
1564 seq_puts(m, "RC6\n");
1567 seq_puts(m, "RC7\n");
1570 seq_puts(m, "Unknown\n");
1574 seq_printf(m, "Core Power Down: %s\n",
1575 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1577 /* Not exactly sure what this is */
1578 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1579 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1580 seq_printf(m, "RC6 residency since boot: %u\n",
1581 I915_READ(GEN6_GT_GFX_RC6));
1582 seq_printf(m, "RC6+ residency since boot: %u\n",
1583 I915_READ(GEN6_GT_GFX_RC6p));
1584 seq_printf(m, "RC6++ residency since boot: %u\n",
1585 I915_READ(GEN6_GT_GFX_RC6pp));
1587 seq_printf(m, "RC6 voltage: %dmV\n",
1588 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1589 seq_printf(m, "RC6+ voltage: %dmV\n",
1590 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1591 seq_printf(m, "RC6++ voltage: %dmV\n",
1592 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1596 static int i915_drpc_info(struct seq_file *m, void *unused)
1598 struct drm_info_node *node = m->private;
1599 struct drm_device *dev = node->minor->dev;
1601 if (IS_VALLEYVIEW(dev))
1602 return vlv_drpc_info(m);
1603 else if (INTEL_INFO(dev)->gen >= 6)
1604 return gen6_drpc_info(m);
1606 return ironlake_drpc_info(m);
1609 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1611 struct drm_info_node *node = m->private;
1612 struct drm_device *dev = node->minor->dev;
1613 struct drm_i915_private *dev_priv = dev->dev_private;
1615 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1616 dev_priv->fb_tracking.busy_bits);
1618 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1619 dev_priv->fb_tracking.flip_bits);
1624 static int i915_fbc_status(struct seq_file *m, void *unused)
1626 struct drm_info_node *node = m->private;
1627 struct drm_device *dev = node->minor->dev;
1628 struct drm_i915_private *dev_priv = dev->dev_private;
1630 if (!HAS_FBC(dev)) {
1631 seq_puts(m, "FBC unsupported on this chipset\n");
1635 intel_runtime_pm_get(dev_priv);
1636 mutex_lock(&dev_priv->fbc.lock);
1638 if (intel_fbc_enabled(dev_priv))
1639 seq_puts(m, "FBC enabled\n");
1641 seq_printf(m, "FBC disabled: %s\n",
1642 intel_no_fbc_reason_str(dev_priv->fbc.no_fbc_reason));
1644 if (INTEL_INFO(dev_priv)->gen >= 7)
1645 seq_printf(m, "Compressing: %s\n",
1646 yesno(I915_READ(FBC_STATUS2) &
1647 FBC_COMPRESSION_MASK));
1649 mutex_unlock(&dev_priv->fbc.lock);
1650 intel_runtime_pm_put(dev_priv);
1655 static int i915_fbc_fc_get(void *data, u64 *val)
1657 struct drm_device *dev = data;
1658 struct drm_i915_private *dev_priv = dev->dev_private;
1660 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1663 *val = dev_priv->fbc.false_color;
1668 static int i915_fbc_fc_set(void *data, u64 val)
1670 struct drm_device *dev = data;
1671 struct drm_i915_private *dev_priv = dev->dev_private;
1674 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1677 mutex_lock(&dev_priv->fbc.lock);
1679 reg = I915_READ(ILK_DPFC_CONTROL);
1680 dev_priv->fbc.false_color = val;
1682 I915_WRITE(ILK_DPFC_CONTROL, val ?
1683 (reg | FBC_CTL_FALSE_COLOR) :
1684 (reg & ~FBC_CTL_FALSE_COLOR));
1686 mutex_unlock(&dev_priv->fbc.lock);
1690 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1691 i915_fbc_fc_get, i915_fbc_fc_set,
1694 static int i915_ips_status(struct seq_file *m, void *unused)
1696 struct drm_info_node *node = m->private;
1697 struct drm_device *dev = node->minor->dev;
1698 struct drm_i915_private *dev_priv = dev->dev_private;
1700 if (!HAS_IPS(dev)) {
1701 seq_puts(m, "not supported\n");
1705 intel_runtime_pm_get(dev_priv);
1707 seq_printf(m, "Enabled by kernel parameter: %s\n",
1708 yesno(i915.enable_ips));
1710 if (INTEL_INFO(dev)->gen >= 8) {
1711 seq_puts(m, "Currently: unknown\n");
1713 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1714 seq_puts(m, "Currently: enabled\n");
1716 seq_puts(m, "Currently: disabled\n");
1719 intel_runtime_pm_put(dev_priv);
1724 static int i915_sr_status(struct seq_file *m, void *unused)
1726 struct drm_info_node *node = m->private;
1727 struct drm_device *dev = node->minor->dev;
1728 struct drm_i915_private *dev_priv = dev->dev_private;
1729 bool sr_enabled = false;
1731 intel_runtime_pm_get(dev_priv);
1733 if (HAS_PCH_SPLIT(dev))
1734 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1735 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1736 IS_I945G(dev) || IS_I945GM(dev))
1737 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1738 else if (IS_I915GM(dev))
1739 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1740 else if (IS_PINEVIEW(dev))
1741 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1742 else if (IS_VALLEYVIEW(dev))
1743 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1745 intel_runtime_pm_put(dev_priv);
1747 seq_printf(m, "self-refresh: %s\n",
1748 sr_enabled ? "enabled" : "disabled");
1753 static int i915_emon_status(struct seq_file *m, void *unused)
1755 struct drm_info_node *node = m->private;
1756 struct drm_device *dev = node->minor->dev;
1757 struct drm_i915_private *dev_priv = dev->dev_private;
1758 unsigned long temp, chipset, gfx;
1764 ret = mutex_lock_interruptible(&dev->struct_mutex);
1768 temp = i915_mch_val(dev_priv);
1769 chipset = i915_chipset_val(dev_priv);
1770 gfx = i915_gfx_val(dev_priv);
1771 mutex_unlock(&dev->struct_mutex);
1773 seq_printf(m, "GMCH temp: %ld\n", temp);
1774 seq_printf(m, "Chipset power: %ld\n", chipset);
1775 seq_printf(m, "GFX power: %ld\n", gfx);
1776 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1781 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1783 struct drm_info_node *node = m->private;
1784 struct drm_device *dev = node->minor->dev;
1785 struct drm_i915_private *dev_priv = dev->dev_private;
1787 int gpu_freq, ia_freq;
1788 unsigned int max_gpu_freq, min_gpu_freq;
1790 if (!HAS_CORE_RING_FREQ(dev)) {
1791 seq_puts(m, "unsupported on this chipset\n");
1795 intel_runtime_pm_get(dev_priv);
1797 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1799 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1803 if (IS_SKYLAKE(dev)) {
1804 /* Convert GT frequency to 50 HZ units */
1806 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1808 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1810 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1811 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1814 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1816 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1818 sandybridge_pcode_read(dev_priv,
1819 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1821 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1822 intel_gpu_freq(dev_priv, (gpu_freq *
1823 (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))),
1824 ((ia_freq >> 0) & 0xff) * 100,
1825 ((ia_freq >> 8) & 0xff) * 100);
1828 mutex_unlock(&dev_priv->rps.hw_lock);
1831 intel_runtime_pm_put(dev_priv);
1835 static int i915_opregion(struct seq_file *m, void *unused)
1837 struct drm_info_node *node = m->private;
1838 struct drm_device *dev = node->minor->dev;
1839 struct drm_i915_private *dev_priv = dev->dev_private;
1840 struct intel_opregion *opregion = &dev_priv->opregion;
1841 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1847 ret = mutex_lock_interruptible(&dev->struct_mutex);
1851 if (opregion->header) {
1852 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1853 seq_write(m, data, OPREGION_SIZE);
1856 mutex_unlock(&dev->struct_mutex);
1863 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1865 struct drm_info_node *node = m->private;
1866 struct drm_device *dev = node->minor->dev;
1867 struct intel_fbdev *ifbdev = NULL;
1868 struct intel_framebuffer *fb;
1870 #ifdef CONFIG_DRM_I915_FBDEV
1871 struct drm_i915_private *dev_priv = dev->dev_private;
1873 ifbdev = dev_priv->fbdev;
1874 fb = to_intel_framebuffer(ifbdev->helper.fb);
1876 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1880 fb->base.bits_per_pixel,
1881 fb->base.modifier[0],
1882 atomic_read(&fb->base.refcount.refcount));
1883 describe_obj(m, fb->obj);
1887 mutex_lock(&dev->mode_config.fb_lock);
1888 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1889 if (ifbdev && &fb->base == ifbdev->helper.fb)
1892 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1896 fb->base.bits_per_pixel,
1897 fb->base.modifier[0],
1898 atomic_read(&fb->base.refcount.refcount));
1899 describe_obj(m, fb->obj);
1902 mutex_unlock(&dev->mode_config.fb_lock);
1907 static void describe_ctx_ringbuf(struct seq_file *m,
1908 struct intel_ringbuffer *ringbuf)
1910 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1911 ringbuf->space, ringbuf->head, ringbuf->tail,
1912 ringbuf->last_retired_head);
1915 static int i915_context_status(struct seq_file *m, void *unused)
1917 struct drm_info_node *node = m->private;
1918 struct drm_device *dev = node->minor->dev;
1919 struct drm_i915_private *dev_priv = dev->dev_private;
1920 struct intel_engine_cs *ring;
1921 struct intel_context *ctx;
1924 ret = mutex_lock_interruptible(&dev->struct_mutex);
1928 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1929 if (!i915.enable_execlists &&
1930 ctx->legacy_hw_ctx.rcs_state == NULL)
1933 seq_puts(m, "HW context ");
1934 describe_ctx(m, ctx);
1935 for_each_ring(ring, dev_priv, i) {
1936 if (ring->default_context == ctx)
1937 seq_printf(m, "(default context %s) ",
1941 if (i915.enable_execlists) {
1943 for_each_ring(ring, dev_priv, i) {
1944 struct drm_i915_gem_object *ctx_obj =
1945 ctx->engine[i].state;
1946 struct intel_ringbuffer *ringbuf =
1947 ctx->engine[i].ringbuf;
1949 seq_printf(m, "%s: ", ring->name);
1951 describe_obj(m, ctx_obj);
1953 describe_ctx_ringbuf(m, ringbuf);
1957 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1963 mutex_unlock(&dev->struct_mutex);
1968 static void i915_dump_lrc_obj(struct seq_file *m,
1969 struct intel_engine_cs *ring,
1970 struct drm_i915_gem_object *ctx_obj)
1973 uint32_t *reg_state;
1975 unsigned long ggtt_offset = 0;
1977 if (ctx_obj == NULL) {
1978 seq_printf(m, "Context on %s with no gem object\n",
1983 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1984 intel_execlists_ctx_id(ctx_obj));
1986 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1987 seq_puts(m, "\tNot bound in GGTT\n");
1989 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1991 if (i915_gem_object_get_pages(ctx_obj)) {
1992 seq_puts(m, "\tFailed to get pages for context object\n");
1996 page = i915_gem_object_get_page(ctx_obj, 1);
1997 if (!WARN_ON(page == NULL)) {
1998 reg_state = kmap_atomic(page);
2000 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2001 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2002 ggtt_offset + 4096 + (j * 4),
2003 reg_state[j], reg_state[j + 1],
2004 reg_state[j + 2], reg_state[j + 3]);
2006 kunmap_atomic(reg_state);
2012 static int i915_dump_lrc(struct seq_file *m, void *unused)
2014 struct drm_info_node *node = (struct drm_info_node *) m->private;
2015 struct drm_device *dev = node->minor->dev;
2016 struct drm_i915_private *dev_priv = dev->dev_private;
2017 struct intel_engine_cs *ring;
2018 struct intel_context *ctx;
2021 if (!i915.enable_execlists) {
2022 seq_printf(m, "Logical Ring Contexts are disabled\n");
2026 ret = mutex_lock_interruptible(&dev->struct_mutex);
2030 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2031 for_each_ring(ring, dev_priv, i) {
2032 if (ring->default_context != ctx)
2033 i915_dump_lrc_obj(m, ring,
2034 ctx->engine[i].state);
2038 mutex_unlock(&dev->struct_mutex);
2043 static int i915_execlists(struct seq_file *m, void *data)
2045 struct drm_info_node *node = (struct drm_info_node *)m->private;
2046 struct drm_device *dev = node->minor->dev;
2047 struct drm_i915_private *dev_priv = dev->dev_private;
2048 struct intel_engine_cs *ring;
2054 struct list_head *cursor;
2058 if (!i915.enable_execlists) {
2059 seq_puts(m, "Logical Ring Contexts are disabled\n");
2063 ret = mutex_lock_interruptible(&dev->struct_mutex);
2067 intel_runtime_pm_get(dev_priv);
2069 for_each_ring(ring, dev_priv, ring_id) {
2070 struct drm_i915_gem_request *head_req = NULL;
2072 unsigned long flags;
2074 seq_printf(m, "%s\n", ring->name);
2076 status = I915_READ(RING_EXECLIST_STATUS(ring));
2077 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
2078 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2081 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2082 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2084 read_pointer = ring->next_context_status_buffer;
2085 write_pointer = status_pointer & 0x07;
2086 if (read_pointer > write_pointer)
2088 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2089 read_pointer, write_pointer);
2091 for (i = 0; i < 6; i++) {
2092 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2093 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2095 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2099 spin_lock_irqsave(&ring->execlist_lock, flags);
2100 list_for_each(cursor, &ring->execlist_queue)
2102 head_req = list_first_entry_or_null(&ring->execlist_queue,
2103 struct drm_i915_gem_request, execlist_link);
2104 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2106 seq_printf(m, "\t%d requests in queue\n", count);
2108 struct drm_i915_gem_object *ctx_obj;
2110 ctx_obj = head_req->ctx->engine[ring_id].state;
2111 seq_printf(m, "\tHead request id: %u\n",
2112 intel_execlists_ctx_id(ctx_obj));
2113 seq_printf(m, "\tHead request tail: %u\n",
2120 intel_runtime_pm_put(dev_priv);
2121 mutex_unlock(&dev->struct_mutex);
2126 static const char *swizzle_string(unsigned swizzle)
2129 case I915_BIT_6_SWIZZLE_NONE:
2131 case I915_BIT_6_SWIZZLE_9:
2133 case I915_BIT_6_SWIZZLE_9_10:
2134 return "bit9/bit10";
2135 case I915_BIT_6_SWIZZLE_9_11:
2136 return "bit9/bit11";
2137 case I915_BIT_6_SWIZZLE_9_10_11:
2138 return "bit9/bit10/bit11";
2139 case I915_BIT_6_SWIZZLE_9_17:
2140 return "bit9/bit17";
2141 case I915_BIT_6_SWIZZLE_9_10_17:
2142 return "bit9/bit10/bit17";
2143 case I915_BIT_6_SWIZZLE_UNKNOWN:
2150 static int i915_swizzle_info(struct seq_file *m, void *data)
2152 struct drm_info_node *node = m->private;
2153 struct drm_device *dev = node->minor->dev;
2154 struct drm_i915_private *dev_priv = dev->dev_private;
2157 ret = mutex_lock_interruptible(&dev->struct_mutex);
2160 intel_runtime_pm_get(dev_priv);
2162 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2163 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2164 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2165 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2167 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2168 seq_printf(m, "DDC = 0x%08x\n",
2170 seq_printf(m, "DDC2 = 0x%08x\n",
2172 seq_printf(m, "C0DRB3 = 0x%04x\n",
2173 I915_READ16(C0DRB3));
2174 seq_printf(m, "C1DRB3 = 0x%04x\n",
2175 I915_READ16(C1DRB3));
2176 } else if (INTEL_INFO(dev)->gen >= 6) {
2177 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2178 I915_READ(MAD_DIMM_C0));
2179 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2180 I915_READ(MAD_DIMM_C1));
2181 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2182 I915_READ(MAD_DIMM_C2));
2183 seq_printf(m, "TILECTL = 0x%08x\n",
2184 I915_READ(TILECTL));
2185 if (INTEL_INFO(dev)->gen >= 8)
2186 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2187 I915_READ(GAMTARBMODE));
2189 seq_printf(m, "ARB_MODE = 0x%08x\n",
2190 I915_READ(ARB_MODE));
2191 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2192 I915_READ(DISP_ARB_CTL));
2195 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2196 seq_puts(m, "L-shaped memory detected\n");
2198 intel_runtime_pm_put(dev_priv);
2199 mutex_unlock(&dev->struct_mutex);
2204 static int per_file_ctx(int id, void *ptr, void *data)
2206 struct intel_context *ctx = ptr;
2207 struct seq_file *m = data;
2208 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2211 seq_printf(m, " no ppgtt for context %d\n",
2216 if (i915_gem_context_is_default(ctx))
2217 seq_puts(m, " default context:\n");
2219 seq_printf(m, " context %d:\n", ctx->user_handle);
2220 ppgtt->debug_dump(ppgtt, m);
2225 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2227 struct drm_i915_private *dev_priv = dev->dev_private;
2228 struct intel_engine_cs *ring;
2229 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2235 for_each_ring(ring, dev_priv, unused) {
2236 seq_printf(m, "%s\n", ring->name);
2237 for (i = 0; i < 4; i++) {
2238 u32 offset = 0x270 + i * 8;
2239 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2241 pdp |= I915_READ(ring->mmio_base + offset);
2242 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2247 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2249 struct drm_i915_private *dev_priv = dev->dev_private;
2250 struct intel_engine_cs *ring;
2251 struct drm_file *file;
2254 if (INTEL_INFO(dev)->gen == 6)
2255 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2257 for_each_ring(ring, dev_priv, i) {
2258 seq_printf(m, "%s\n", ring->name);
2259 if (INTEL_INFO(dev)->gen == 7)
2260 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2261 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2262 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2263 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2265 if (dev_priv->mm.aliasing_ppgtt) {
2266 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2268 seq_puts(m, "aliasing PPGTT:\n");
2269 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2271 ppgtt->debug_dump(ppgtt, m);
2274 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2275 struct drm_i915_file_private *file_priv = file->driver_priv;
2277 seq_printf(m, "proc: %s\n",
2278 get_pid_task(file->pid, PIDTYPE_PID)->comm);
2279 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
2281 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2284 static int i915_ppgtt_info(struct seq_file *m, void *data)
2286 struct drm_info_node *node = m->private;
2287 struct drm_device *dev = node->minor->dev;
2288 struct drm_i915_private *dev_priv = dev->dev_private;
2290 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2293 intel_runtime_pm_get(dev_priv);
2295 if (INTEL_INFO(dev)->gen >= 8)
2296 gen8_ppgtt_info(m, dev);
2297 else if (INTEL_INFO(dev)->gen >= 6)
2298 gen6_ppgtt_info(m, dev);
2300 intel_runtime_pm_put(dev_priv);
2301 mutex_unlock(&dev->struct_mutex);
2306 static int count_irq_waiters(struct drm_i915_private *i915)
2308 struct intel_engine_cs *ring;
2312 for_each_ring(ring, i915, i)
2313 count += ring->irq_refcount;
2318 static int i915_rps_boost_info(struct seq_file *m, void *data)
2320 struct drm_info_node *node = m->private;
2321 struct drm_device *dev = node->minor->dev;
2322 struct drm_i915_private *dev_priv = dev->dev_private;
2323 struct drm_file *file;
2325 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2326 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2327 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2328 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2329 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2330 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2331 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2332 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2333 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2334 spin_lock(&dev_priv->rps.client_lock);
2335 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2336 struct drm_i915_file_private *file_priv = file->driver_priv;
2337 struct task_struct *task;
2340 task = pid_task(file->pid, PIDTYPE_PID);
2341 seq_printf(m, "%s [%d]: %d boosts%s\n",
2342 task ? task->comm : "<unknown>",
2343 task ? task->pid : -1,
2344 file_priv->rps.boosts,
2345 list_empty(&file_priv->rps.link) ? "" : ", active");
2348 seq_printf(m, "Semaphore boosts: %d%s\n",
2349 dev_priv->rps.semaphores.boosts,
2350 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2351 seq_printf(m, "MMIO flip boosts: %d%s\n",
2352 dev_priv->rps.mmioflips.boosts,
2353 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2354 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2355 spin_unlock(&dev_priv->rps.client_lock);
2360 static int i915_llc(struct seq_file *m, void *data)
2362 struct drm_info_node *node = m->private;
2363 struct drm_device *dev = node->minor->dev;
2364 struct drm_i915_private *dev_priv = dev->dev_private;
2366 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2367 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2368 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2373 static int i915_edp_psr_status(struct seq_file *m, void *data)
2375 struct drm_info_node *node = m->private;
2376 struct drm_device *dev = node->minor->dev;
2377 struct drm_i915_private *dev_priv = dev->dev_private;
2381 bool enabled = false;
2383 if (!HAS_PSR(dev)) {
2384 seq_puts(m, "PSR not supported\n");
2388 intel_runtime_pm_get(dev_priv);
2390 mutex_lock(&dev_priv->psr.lock);
2391 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2392 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2393 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2394 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2395 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2396 dev_priv->psr.busy_frontbuffer_bits);
2397 seq_printf(m, "Re-enable work scheduled: %s\n",
2398 yesno(work_busy(&dev_priv->psr.work.work)));
2401 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2403 for_each_pipe(dev_priv, pipe) {
2404 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2405 VLV_EDP_PSR_CURR_STATE_MASK;
2406 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2407 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2411 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2414 for_each_pipe(dev_priv, pipe) {
2415 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2416 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2417 seq_printf(m, " pipe %c", pipe_name(pipe));
2421 /* CHV PSR has no kind of performance counter */
2423 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2424 EDP_PSR_PERF_CNT_MASK;
2426 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2428 mutex_unlock(&dev_priv->psr.lock);
2430 intel_runtime_pm_put(dev_priv);
2434 static int i915_sink_crc(struct seq_file *m, void *data)
2436 struct drm_info_node *node = m->private;
2437 struct drm_device *dev = node->minor->dev;
2438 struct intel_encoder *encoder;
2439 struct intel_connector *connector;
2440 struct intel_dp *intel_dp = NULL;
2444 drm_modeset_lock_all(dev);
2445 for_each_intel_connector(dev, connector) {
2447 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2450 if (!connector->base.encoder)
2453 encoder = to_intel_encoder(connector->base.encoder);
2454 if (encoder->type != INTEL_OUTPUT_EDP)
2457 intel_dp = enc_to_intel_dp(&encoder->base);
2459 ret = intel_dp_sink_crc(intel_dp, crc);
2463 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2464 crc[0], crc[1], crc[2],
2465 crc[3], crc[4], crc[5]);
2470 drm_modeset_unlock_all(dev);
2474 static int i915_energy_uJ(struct seq_file *m, void *data)
2476 struct drm_info_node *node = m->private;
2477 struct drm_device *dev = node->minor->dev;
2478 struct drm_i915_private *dev_priv = dev->dev_private;
2482 if (INTEL_INFO(dev)->gen < 6)
2485 intel_runtime_pm_get(dev_priv);
2487 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2488 power = (power & 0x1f00) >> 8;
2489 units = 1000000 / (1 << power); /* convert to uJ */
2490 power = I915_READ(MCH_SECP_NRG_STTS);
2493 intel_runtime_pm_put(dev_priv);
2495 seq_printf(m, "%llu", (long long unsigned)power);
2500 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2502 struct drm_info_node *node = m->private;
2503 struct drm_device *dev = node->minor->dev;
2504 struct drm_i915_private *dev_priv = dev->dev_private;
2506 if (!HAS_RUNTIME_PM(dev)) {
2507 seq_puts(m, "not supported\n");
2511 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2512 seq_printf(m, "IRQs disabled: %s\n",
2513 yesno(!intel_irqs_enabled(dev_priv)));
2515 seq_printf(m, "Usage count: %d\n",
2516 atomic_read(&dev->dev->power.usage_count));
2518 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2524 static const char *power_domain_str(enum intel_display_power_domain domain)
2527 case POWER_DOMAIN_PIPE_A:
2529 case POWER_DOMAIN_PIPE_B:
2531 case POWER_DOMAIN_PIPE_C:
2533 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2534 return "PIPE_A_PANEL_FITTER";
2535 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2536 return "PIPE_B_PANEL_FITTER";
2537 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2538 return "PIPE_C_PANEL_FITTER";
2539 case POWER_DOMAIN_TRANSCODER_A:
2540 return "TRANSCODER_A";
2541 case POWER_DOMAIN_TRANSCODER_B:
2542 return "TRANSCODER_B";
2543 case POWER_DOMAIN_TRANSCODER_C:
2544 return "TRANSCODER_C";
2545 case POWER_DOMAIN_TRANSCODER_EDP:
2546 return "TRANSCODER_EDP";
2547 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2548 return "PORT_DDI_A_2_LANES";
2549 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2550 return "PORT_DDI_A_4_LANES";
2551 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2552 return "PORT_DDI_B_2_LANES";
2553 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2554 return "PORT_DDI_B_4_LANES";
2555 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2556 return "PORT_DDI_C_2_LANES";
2557 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2558 return "PORT_DDI_C_4_LANES";
2559 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2560 return "PORT_DDI_D_2_LANES";
2561 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2562 return "PORT_DDI_D_4_LANES";
2563 case POWER_DOMAIN_PORT_DSI:
2565 case POWER_DOMAIN_PORT_CRT:
2567 case POWER_DOMAIN_PORT_OTHER:
2568 return "PORT_OTHER";
2569 case POWER_DOMAIN_VGA:
2571 case POWER_DOMAIN_AUDIO:
2573 case POWER_DOMAIN_PLLS:
2575 case POWER_DOMAIN_AUX_A:
2577 case POWER_DOMAIN_AUX_B:
2579 case POWER_DOMAIN_AUX_C:
2581 case POWER_DOMAIN_AUX_D:
2583 case POWER_DOMAIN_INIT:
2586 MISSING_CASE(domain);
2591 static int i915_power_domain_info(struct seq_file *m, void *unused)
2593 struct drm_info_node *node = m->private;
2594 struct drm_device *dev = node->minor->dev;
2595 struct drm_i915_private *dev_priv = dev->dev_private;
2596 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2599 mutex_lock(&power_domains->lock);
2601 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2602 for (i = 0; i < power_domains->power_well_count; i++) {
2603 struct i915_power_well *power_well;
2604 enum intel_display_power_domain power_domain;
2606 power_well = &power_domains->power_wells[i];
2607 seq_printf(m, "%-25s %d\n", power_well->name,
2610 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2612 if (!(BIT(power_domain) & power_well->domains))
2615 seq_printf(m, " %-23s %d\n",
2616 power_domain_str(power_domain),
2617 power_domains->domain_use_count[power_domain]);
2621 mutex_unlock(&power_domains->lock);
2626 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2627 struct drm_display_mode *mode)
2631 for (i = 0; i < tabs; i++)
2634 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2635 mode->base.id, mode->name,
2636 mode->vrefresh, mode->clock,
2637 mode->hdisplay, mode->hsync_start,
2638 mode->hsync_end, mode->htotal,
2639 mode->vdisplay, mode->vsync_start,
2640 mode->vsync_end, mode->vtotal,
2641 mode->type, mode->flags);
2644 static void intel_encoder_info(struct seq_file *m,
2645 struct intel_crtc *intel_crtc,
2646 struct intel_encoder *intel_encoder)
2648 struct drm_info_node *node = m->private;
2649 struct drm_device *dev = node->minor->dev;
2650 struct drm_crtc *crtc = &intel_crtc->base;
2651 struct intel_connector *intel_connector;
2652 struct drm_encoder *encoder;
2654 encoder = &intel_encoder->base;
2655 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2656 encoder->base.id, encoder->name);
2657 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2658 struct drm_connector *connector = &intel_connector->base;
2659 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2662 drm_get_connector_status_name(connector->status));
2663 if (connector->status == connector_status_connected) {
2664 struct drm_display_mode *mode = &crtc->mode;
2665 seq_printf(m, ", mode:\n");
2666 intel_seq_print_mode(m, 2, mode);
2673 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2675 struct drm_info_node *node = m->private;
2676 struct drm_device *dev = node->minor->dev;
2677 struct drm_crtc *crtc = &intel_crtc->base;
2678 struct intel_encoder *intel_encoder;
2680 if (crtc->primary->fb)
2681 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2682 crtc->primary->fb->base.id, crtc->x, crtc->y,
2683 crtc->primary->fb->width, crtc->primary->fb->height);
2685 seq_puts(m, "\tprimary plane disabled\n");
2686 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2687 intel_encoder_info(m, intel_crtc, intel_encoder);
2690 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2692 struct drm_display_mode *mode = panel->fixed_mode;
2694 seq_printf(m, "\tfixed mode:\n");
2695 intel_seq_print_mode(m, 2, mode);
2698 static void intel_dp_info(struct seq_file *m,
2699 struct intel_connector *intel_connector)
2701 struct intel_encoder *intel_encoder = intel_connector->encoder;
2702 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2704 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2705 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2707 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2708 intel_panel_info(m, &intel_connector->panel);
2711 static void intel_hdmi_info(struct seq_file *m,
2712 struct intel_connector *intel_connector)
2714 struct intel_encoder *intel_encoder = intel_connector->encoder;
2715 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2717 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2721 static void intel_lvds_info(struct seq_file *m,
2722 struct intel_connector *intel_connector)
2724 intel_panel_info(m, &intel_connector->panel);
2727 static void intel_connector_info(struct seq_file *m,
2728 struct drm_connector *connector)
2730 struct intel_connector *intel_connector = to_intel_connector(connector);
2731 struct intel_encoder *intel_encoder = intel_connector->encoder;
2732 struct drm_display_mode *mode;
2734 seq_printf(m, "connector %d: type %s, status: %s\n",
2735 connector->base.id, connector->name,
2736 drm_get_connector_status_name(connector->status));
2737 if (connector->status == connector_status_connected) {
2738 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2739 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2740 connector->display_info.width_mm,
2741 connector->display_info.height_mm);
2742 seq_printf(m, "\tsubpixel order: %s\n",
2743 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2744 seq_printf(m, "\tCEA rev: %d\n",
2745 connector->display_info.cea_rev);
2747 if (intel_encoder) {
2748 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2749 intel_encoder->type == INTEL_OUTPUT_EDP)
2750 intel_dp_info(m, intel_connector);
2751 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2752 intel_hdmi_info(m, intel_connector);
2753 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2754 intel_lvds_info(m, intel_connector);
2757 seq_printf(m, "\tmodes:\n");
2758 list_for_each_entry(mode, &connector->modes, head)
2759 intel_seq_print_mode(m, 2, mode);
2762 static bool cursor_active(struct drm_device *dev, int pipe)
2764 struct drm_i915_private *dev_priv = dev->dev_private;
2767 if (IS_845G(dev) || IS_I865G(dev))
2768 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2770 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2775 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2777 struct drm_i915_private *dev_priv = dev->dev_private;
2780 pos = I915_READ(CURPOS(pipe));
2782 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2783 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2786 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2787 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2790 return cursor_active(dev, pipe);
2793 static int i915_display_info(struct seq_file *m, void *unused)
2795 struct drm_info_node *node = m->private;
2796 struct drm_device *dev = node->minor->dev;
2797 struct drm_i915_private *dev_priv = dev->dev_private;
2798 struct intel_crtc *crtc;
2799 struct drm_connector *connector;
2801 intel_runtime_pm_get(dev_priv);
2802 drm_modeset_lock_all(dev);
2803 seq_printf(m, "CRTC info\n");
2804 seq_printf(m, "---------\n");
2805 for_each_intel_crtc(dev, crtc) {
2807 struct intel_crtc_state *pipe_config;
2810 pipe_config = to_intel_crtc_state(crtc->base.state);
2812 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2813 crtc->base.base.id, pipe_name(crtc->pipe),
2814 yesno(pipe_config->base.active),
2815 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
2816 if (pipe_config->base.active) {
2817 intel_crtc_info(m, crtc);
2819 active = cursor_position(dev, crtc->pipe, &x, &y);
2820 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2821 yesno(crtc->cursor_base),
2822 x, y, crtc->base.cursor->state->crtc_w,
2823 crtc->base.cursor->state->crtc_h,
2824 crtc->cursor_addr, yesno(active));
2827 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2828 yesno(!crtc->cpu_fifo_underrun_disabled),
2829 yesno(!crtc->pch_fifo_underrun_disabled));
2832 seq_printf(m, "\n");
2833 seq_printf(m, "Connector info\n");
2834 seq_printf(m, "--------------\n");
2835 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2836 intel_connector_info(m, connector);
2838 drm_modeset_unlock_all(dev);
2839 intel_runtime_pm_put(dev_priv);
2844 static int i915_semaphore_status(struct seq_file *m, void *unused)
2846 struct drm_info_node *node = (struct drm_info_node *) m->private;
2847 struct drm_device *dev = node->minor->dev;
2848 struct drm_i915_private *dev_priv = dev->dev_private;
2849 struct intel_engine_cs *ring;
2850 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2853 if (!i915_semaphore_is_enabled(dev)) {
2854 seq_puts(m, "Semaphores are disabled\n");
2858 ret = mutex_lock_interruptible(&dev->struct_mutex);
2861 intel_runtime_pm_get(dev_priv);
2863 if (IS_BROADWELL(dev)) {
2867 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2869 seqno = (uint64_t *)kmap_atomic(page);
2870 for_each_ring(ring, dev_priv, i) {
2873 seq_printf(m, "%s\n", ring->name);
2875 seq_puts(m, " Last signal:");
2876 for (j = 0; j < num_rings; j++) {
2877 offset = i * I915_NUM_RINGS + j;
2878 seq_printf(m, "0x%08llx (0x%02llx) ",
2879 seqno[offset], offset * 8);
2883 seq_puts(m, " Last wait: ");
2884 for (j = 0; j < num_rings; j++) {
2885 offset = i + (j * I915_NUM_RINGS);
2886 seq_printf(m, "0x%08llx (0x%02llx) ",
2887 seqno[offset], offset * 8);
2892 kunmap_atomic(seqno);
2894 seq_puts(m, " Last signal:");
2895 for_each_ring(ring, dev_priv, i)
2896 for (j = 0; j < num_rings; j++)
2897 seq_printf(m, "0x%08x\n",
2898 I915_READ(ring->semaphore.mbox.signal[j]));
2902 seq_puts(m, "\nSync seqno:\n");
2903 for_each_ring(ring, dev_priv, i) {
2904 for (j = 0; j < num_rings; j++) {
2905 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2911 intel_runtime_pm_put(dev_priv);
2912 mutex_unlock(&dev->struct_mutex);
2916 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2918 struct drm_info_node *node = (struct drm_info_node *) m->private;
2919 struct drm_device *dev = node->minor->dev;
2920 struct drm_i915_private *dev_priv = dev->dev_private;
2923 drm_modeset_lock_all(dev);
2924 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2925 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2927 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2928 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2929 pll->config.crtc_mask, pll->active, yesno(pll->on));
2930 seq_printf(m, " tracked hardware state:\n");
2931 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2932 seq_printf(m, " dpll_md: 0x%08x\n",
2933 pll->config.hw_state.dpll_md);
2934 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2935 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2936 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
2938 drm_modeset_unlock_all(dev);
2943 static int i915_wa_registers(struct seq_file *m, void *unused)
2947 struct drm_info_node *node = (struct drm_info_node *) m->private;
2948 struct drm_device *dev = node->minor->dev;
2949 struct drm_i915_private *dev_priv = dev->dev_private;
2951 ret = mutex_lock_interruptible(&dev->struct_mutex);
2955 intel_runtime_pm_get(dev_priv);
2957 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2958 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2959 u32 addr, mask, value, read;
2962 addr = dev_priv->workarounds.reg[i].addr;
2963 mask = dev_priv->workarounds.reg[i].mask;
2964 value = dev_priv->workarounds.reg[i].value;
2965 read = I915_READ(addr);
2966 ok = (value & mask) == (read & mask);
2967 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2968 addr, value, mask, read, ok ? "OK" : "FAIL");
2971 intel_runtime_pm_put(dev_priv);
2972 mutex_unlock(&dev->struct_mutex);
2977 static int i915_ddb_info(struct seq_file *m, void *unused)
2979 struct drm_info_node *node = m->private;
2980 struct drm_device *dev = node->minor->dev;
2981 struct drm_i915_private *dev_priv = dev->dev_private;
2982 struct skl_ddb_allocation *ddb;
2983 struct skl_ddb_entry *entry;
2987 if (INTEL_INFO(dev)->gen < 9)
2990 drm_modeset_lock_all(dev);
2992 ddb = &dev_priv->wm.skl_hw.ddb;
2994 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2996 for_each_pipe(dev_priv, pipe) {
2997 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2999 for_each_plane(dev_priv, pipe, plane) {
3000 entry = &ddb->plane[pipe][plane];
3001 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3002 entry->start, entry->end,
3003 skl_ddb_entry_size(entry));
3006 entry = &ddb->cursor[pipe];
3007 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3008 entry->end, skl_ddb_entry_size(entry));
3011 drm_modeset_unlock_all(dev);
3016 static void drrs_status_per_crtc(struct seq_file *m,
3017 struct drm_device *dev, struct intel_crtc *intel_crtc)
3019 struct intel_encoder *intel_encoder;
3020 struct drm_i915_private *dev_priv = dev->dev_private;
3021 struct i915_drrs *drrs = &dev_priv->drrs;
3024 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3025 /* Encoder connected on this CRTC */
3026 switch (intel_encoder->type) {
3027 case INTEL_OUTPUT_EDP:
3028 seq_puts(m, "eDP:\n");
3030 case INTEL_OUTPUT_DSI:
3031 seq_puts(m, "DSI:\n");
3033 case INTEL_OUTPUT_HDMI:
3034 seq_puts(m, "HDMI:\n");
3036 case INTEL_OUTPUT_DISPLAYPORT:
3037 seq_puts(m, "DP:\n");
3040 seq_printf(m, "Other encoder (id=%d).\n",
3041 intel_encoder->type);
3046 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3047 seq_puts(m, "\tVBT: DRRS_type: Static");
3048 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3049 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3050 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3051 seq_puts(m, "\tVBT: DRRS_type: None");
3053 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3055 seq_puts(m, "\n\n");
3057 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3058 struct intel_panel *panel;
3060 mutex_lock(&drrs->mutex);
3061 /* DRRS Supported */
3062 seq_puts(m, "\tDRRS Supported: Yes\n");
3064 /* disable_drrs() will make drrs->dp NULL */
3066 seq_puts(m, "Idleness DRRS: Disabled");
3067 mutex_unlock(&drrs->mutex);
3071 panel = &drrs->dp->attached_connector->panel;
3072 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3073 drrs->busy_frontbuffer_bits);
3075 seq_puts(m, "\n\t\t");
3076 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3077 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3078 vrefresh = panel->fixed_mode->vrefresh;
3079 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3080 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3081 vrefresh = panel->downclock_mode->vrefresh;
3083 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3084 drrs->refresh_rate_type);
3085 mutex_unlock(&drrs->mutex);
3088 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3090 seq_puts(m, "\n\t\t");
3091 mutex_unlock(&drrs->mutex);
3093 /* DRRS not supported. Print the VBT parameter*/
3094 seq_puts(m, "\tDRRS Supported : No");
3099 static int i915_drrs_status(struct seq_file *m, void *unused)
3101 struct drm_info_node *node = m->private;
3102 struct drm_device *dev = node->minor->dev;
3103 struct intel_crtc *intel_crtc;
3104 int active_crtc_cnt = 0;
3106 for_each_intel_crtc(dev, intel_crtc) {
3107 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3109 if (intel_crtc->base.state->active) {
3111 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3113 drrs_status_per_crtc(m, dev, intel_crtc);
3116 drm_modeset_unlock(&intel_crtc->base.mutex);
3119 if (!active_crtc_cnt)
3120 seq_puts(m, "No active crtc found\n");
3125 struct pipe_crc_info {
3127 struct drm_device *dev;
3131 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3133 struct drm_info_node *node = (struct drm_info_node *) m->private;
3134 struct drm_device *dev = node->minor->dev;
3135 struct drm_encoder *encoder;
3136 struct intel_encoder *intel_encoder;
3137 struct intel_digital_port *intel_dig_port;
3138 drm_modeset_lock_all(dev);
3139 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3140 intel_encoder = to_intel_encoder(encoder);
3141 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3143 intel_dig_port = enc_to_dig_port(encoder);
3144 if (!intel_dig_port->dp.can_mst)
3147 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3149 drm_modeset_unlock_all(dev);
3153 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3155 struct pipe_crc_info *info = inode->i_private;
3156 struct drm_i915_private *dev_priv = info->dev->dev_private;
3157 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3159 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3162 spin_lock_irq(&pipe_crc->lock);
3164 if (pipe_crc->opened) {
3165 spin_unlock_irq(&pipe_crc->lock);
3166 return -EBUSY; /* already open */
3169 pipe_crc->opened = true;
3170 filep->private_data = inode->i_private;
3172 spin_unlock_irq(&pipe_crc->lock);
3177 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3179 struct pipe_crc_info *info = inode->i_private;
3180 struct drm_i915_private *dev_priv = info->dev->dev_private;
3181 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3183 spin_lock_irq(&pipe_crc->lock);
3184 pipe_crc->opened = false;
3185 spin_unlock_irq(&pipe_crc->lock);
3190 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3191 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3192 /* account for \'0' */
3193 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3195 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3197 assert_spin_locked(&pipe_crc->lock);
3198 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3199 INTEL_PIPE_CRC_ENTRIES_NR);
3203 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3206 struct pipe_crc_info *info = filep->private_data;
3207 struct drm_device *dev = info->dev;
3208 struct drm_i915_private *dev_priv = dev->dev_private;
3209 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3210 char buf[PIPE_CRC_BUFFER_LEN];
3215 * Don't allow user space to provide buffers not big enough to hold
3218 if (count < PIPE_CRC_LINE_LEN)
3221 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3224 /* nothing to read */
3225 spin_lock_irq(&pipe_crc->lock);
3226 while (pipe_crc_data_count(pipe_crc) == 0) {
3229 if (filep->f_flags & O_NONBLOCK) {
3230 spin_unlock_irq(&pipe_crc->lock);
3234 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3235 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3237 spin_unlock_irq(&pipe_crc->lock);
3242 /* We now have one or more entries to read */
3243 n_entries = count / PIPE_CRC_LINE_LEN;
3246 while (n_entries > 0) {
3247 struct intel_pipe_crc_entry *entry =
3248 &pipe_crc->entries[pipe_crc->tail];
3251 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3252 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3255 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3256 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3258 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3259 "%8u %8x %8x %8x %8x %8x\n",
3260 entry->frame, entry->crc[0],
3261 entry->crc[1], entry->crc[2],
3262 entry->crc[3], entry->crc[4]);
3264 spin_unlock_irq(&pipe_crc->lock);
3266 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3267 if (ret == PIPE_CRC_LINE_LEN)
3270 user_buf += PIPE_CRC_LINE_LEN;
3273 spin_lock_irq(&pipe_crc->lock);
3276 spin_unlock_irq(&pipe_crc->lock);
3281 static const struct file_operations i915_pipe_crc_fops = {
3282 .owner = THIS_MODULE,
3283 .open = i915_pipe_crc_open,
3284 .read = i915_pipe_crc_read,
3285 .release = i915_pipe_crc_release,
3288 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3290 .name = "i915_pipe_A_crc",
3294 .name = "i915_pipe_B_crc",
3298 .name = "i915_pipe_C_crc",
3303 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3306 struct drm_device *dev = minor->dev;
3308 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3311 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3312 &i915_pipe_crc_fops);
3316 return drm_add_fake_info_node(minor, ent, info);
3319 static const char * const pipe_crc_sources[] = {
3332 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3334 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3335 return pipe_crc_sources[source];
3338 static int display_crc_ctl_show(struct seq_file *m, void *data)
3340 struct drm_device *dev = m->private;
3341 struct drm_i915_private *dev_priv = dev->dev_private;
3344 for (i = 0; i < I915_MAX_PIPES; i++)
3345 seq_printf(m, "%c %s\n", pipe_name(i),
3346 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3351 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3353 struct drm_device *dev = inode->i_private;
3355 return single_open(file, display_crc_ctl_show, dev);
3358 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3361 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3362 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3365 case INTEL_PIPE_CRC_SOURCE_PIPE:
3366 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3368 case INTEL_PIPE_CRC_SOURCE_NONE:
3378 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3379 enum intel_pipe_crc_source *source)
3381 struct intel_encoder *encoder;
3382 struct intel_crtc *crtc;
3383 struct intel_digital_port *dig_port;
3386 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3388 drm_modeset_lock_all(dev);
3389 for_each_intel_encoder(dev, encoder) {
3390 if (!encoder->base.crtc)
3393 crtc = to_intel_crtc(encoder->base.crtc);
3395 if (crtc->pipe != pipe)
3398 switch (encoder->type) {
3399 case INTEL_OUTPUT_TVOUT:
3400 *source = INTEL_PIPE_CRC_SOURCE_TV;
3402 case INTEL_OUTPUT_DISPLAYPORT:
3403 case INTEL_OUTPUT_EDP:
3404 dig_port = enc_to_dig_port(&encoder->base);
3405 switch (dig_port->port) {
3407 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3410 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3413 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3416 WARN(1, "nonexisting DP port %c\n",
3417 port_name(dig_port->port));
3425 drm_modeset_unlock_all(dev);
3430 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3432 enum intel_pipe_crc_source *source,
3435 struct drm_i915_private *dev_priv = dev->dev_private;
3436 bool need_stable_symbols = false;
3438 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3439 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3445 case INTEL_PIPE_CRC_SOURCE_PIPE:
3446 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3448 case INTEL_PIPE_CRC_SOURCE_DP_B:
3449 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3450 need_stable_symbols = true;
3452 case INTEL_PIPE_CRC_SOURCE_DP_C:
3453 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3454 need_stable_symbols = true;
3456 case INTEL_PIPE_CRC_SOURCE_DP_D:
3457 if (!IS_CHERRYVIEW(dev))
3459 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3460 need_stable_symbols = true;
3462 case INTEL_PIPE_CRC_SOURCE_NONE:
3470 * When the pipe CRC tap point is after the transcoders we need
3471 * to tweak symbol-level features to produce a deterministic series of
3472 * symbols for a given frame. We need to reset those features only once
3473 * a frame (instead of every nth symbol):
3474 * - DC-balance: used to ensure a better clock recovery from the data
3476 * - DisplayPort scrambling: used for EMI reduction
3478 if (need_stable_symbols) {
3479 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3481 tmp |= DC_BALANCE_RESET_VLV;
3484 tmp |= PIPE_A_SCRAMBLE_RESET;
3487 tmp |= PIPE_B_SCRAMBLE_RESET;
3490 tmp |= PIPE_C_SCRAMBLE_RESET;
3495 I915_WRITE(PORT_DFT2_G4X, tmp);
3501 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3503 enum intel_pipe_crc_source *source,
3506 struct drm_i915_private *dev_priv = dev->dev_private;
3507 bool need_stable_symbols = false;
3509 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3510 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3516 case INTEL_PIPE_CRC_SOURCE_PIPE:
3517 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3519 case INTEL_PIPE_CRC_SOURCE_TV:
3520 if (!SUPPORTS_TV(dev))
3522 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3524 case INTEL_PIPE_CRC_SOURCE_DP_B:
3527 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3528 need_stable_symbols = true;
3530 case INTEL_PIPE_CRC_SOURCE_DP_C:
3533 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3534 need_stable_symbols = true;
3536 case INTEL_PIPE_CRC_SOURCE_DP_D:
3539 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3540 need_stable_symbols = true;
3542 case INTEL_PIPE_CRC_SOURCE_NONE:
3550 * When the pipe CRC tap point is after the transcoders we need
3551 * to tweak symbol-level features to produce a deterministic series of
3552 * symbols for a given frame. We need to reset those features only once
3553 * a frame (instead of every nth symbol):
3554 * - DC-balance: used to ensure a better clock recovery from the data
3556 * - DisplayPort scrambling: used for EMI reduction
3558 if (need_stable_symbols) {
3559 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3561 WARN_ON(!IS_G4X(dev));
3563 I915_WRITE(PORT_DFT_I9XX,
3564 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3567 tmp |= PIPE_A_SCRAMBLE_RESET;
3569 tmp |= PIPE_B_SCRAMBLE_RESET;
3571 I915_WRITE(PORT_DFT2_G4X, tmp);
3577 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3580 struct drm_i915_private *dev_priv = dev->dev_private;
3581 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3585 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3588 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3591 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3596 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3597 tmp &= ~DC_BALANCE_RESET_VLV;
3598 I915_WRITE(PORT_DFT2_G4X, tmp);
3602 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3605 struct drm_i915_private *dev_priv = dev->dev_private;
3606 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3609 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3611 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3612 I915_WRITE(PORT_DFT2_G4X, tmp);
3614 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3615 I915_WRITE(PORT_DFT_I9XX,
3616 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3620 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3623 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3624 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3627 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3628 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3630 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3631 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3633 case INTEL_PIPE_CRC_SOURCE_PIPE:
3634 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3636 case INTEL_PIPE_CRC_SOURCE_NONE:
3646 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3648 struct drm_i915_private *dev_priv = dev->dev_private;
3649 struct intel_crtc *crtc =
3650 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3651 struct intel_crtc_state *pipe_config;
3653 drm_modeset_lock_all(dev);
3654 pipe_config = to_intel_crtc_state(crtc->base.state);
3657 * If we use the eDP transcoder we need to make sure that we don't
3658 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3659 * relevant on hsw with pipe A when using the always-on power well
3662 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3663 !pipe_config->pch_pfit.enabled) {
3664 bool active = pipe_config->base.active;
3667 intel_crtc_control(&crtc->base, false);
3668 pipe_config = to_intel_crtc_state(crtc->base.state);
3671 pipe_config->pch_pfit.force_thru = true;
3673 intel_display_power_get(dev_priv,
3674 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3677 intel_crtc_control(&crtc->base, true);
3679 drm_modeset_unlock_all(dev);
3682 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3684 struct drm_i915_private *dev_priv = dev->dev_private;
3685 struct intel_crtc *crtc =
3686 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3687 struct intel_crtc_state *pipe_config;
3689 drm_modeset_lock_all(dev);
3691 * If we use the eDP transcoder we need to make sure that we don't
3692 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3693 * relevant on hsw with pipe A when using the always-on power well
3696 pipe_config = to_intel_crtc_state(crtc->base.state);
3697 if (pipe_config->pch_pfit.force_thru) {
3698 bool active = pipe_config->base.active;
3701 intel_crtc_control(&crtc->base, false);
3702 pipe_config = to_intel_crtc_state(crtc->base.state);
3705 pipe_config->pch_pfit.force_thru = false;
3707 intel_display_power_put(dev_priv,
3708 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3711 intel_crtc_control(&crtc->base, true);
3713 drm_modeset_unlock_all(dev);
3716 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3718 enum intel_pipe_crc_source *source,
3721 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3722 *source = INTEL_PIPE_CRC_SOURCE_PF;
3725 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3726 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3728 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3729 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3731 case INTEL_PIPE_CRC_SOURCE_PF:
3732 if (IS_HASWELL(dev) && pipe == PIPE_A)
3733 hsw_trans_edp_pipe_A_crc_wa(dev);
3735 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3737 case INTEL_PIPE_CRC_SOURCE_NONE:
3747 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3748 enum intel_pipe_crc_source source)
3750 struct drm_i915_private *dev_priv = dev->dev_private;
3751 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3752 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3754 u32 val = 0; /* shut up gcc */
3757 if (pipe_crc->source == source)
3760 /* forbid changing the source without going back to 'none' */
3761 if (pipe_crc->source && source)
3764 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3765 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3770 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3771 else if (INTEL_INFO(dev)->gen < 5)
3772 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3773 else if (IS_VALLEYVIEW(dev))
3774 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3775 else if (IS_GEN5(dev) || IS_GEN6(dev))
3776 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3778 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3783 /* none -> real source transition */
3785 struct intel_pipe_crc_entry *entries;
3787 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3788 pipe_name(pipe), pipe_crc_source_name(source));
3790 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3791 sizeof(pipe_crc->entries[0]),
3797 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3798 * enabled and disabled dynamically based on package C states,
3799 * user space can't make reliable use of the CRCs, so let's just
3800 * completely disable it.
3802 hsw_disable_ips(crtc);
3804 spin_lock_irq(&pipe_crc->lock);
3805 kfree(pipe_crc->entries);
3806 pipe_crc->entries = entries;
3809 spin_unlock_irq(&pipe_crc->lock);
3812 pipe_crc->source = source;
3814 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3815 POSTING_READ(PIPE_CRC_CTL(pipe));
3817 /* real source -> none transition */
3818 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3819 struct intel_pipe_crc_entry *entries;
3820 struct intel_crtc *crtc =
3821 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3823 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3826 drm_modeset_lock(&crtc->base.mutex, NULL);
3827 if (crtc->base.state->active)
3828 intel_wait_for_vblank(dev, pipe);
3829 drm_modeset_unlock(&crtc->base.mutex);
3831 spin_lock_irq(&pipe_crc->lock);
3832 entries = pipe_crc->entries;
3833 pipe_crc->entries = NULL;
3836 spin_unlock_irq(&pipe_crc->lock);
3841 g4x_undo_pipe_scramble_reset(dev, pipe);
3842 else if (IS_VALLEYVIEW(dev))
3843 vlv_undo_pipe_scramble_reset(dev, pipe);
3844 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3845 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3847 hsw_enable_ips(crtc);
3854 * Parse pipe CRC command strings:
3855 * command: wsp* object wsp+ name wsp+ source wsp*
3858 * source: (none | plane1 | plane2 | pf)
3859 * wsp: (#0x20 | #0x9 | #0xA)+
3862 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3863 * "pipe A none" -> Stop CRC
3865 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3872 /* skip leading white space */
3873 buf = skip_spaces(buf);
3875 break; /* end of buffer */
3877 /* find end of word */
3878 for (end = buf; *end && !isspace(*end); end++)
3881 if (n_words == max_words) {
3882 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3884 return -EINVAL; /* ran out of words[] before bytes */
3889 words[n_words++] = buf;
3896 enum intel_pipe_crc_object {
3897 PIPE_CRC_OBJECT_PIPE,
3900 static const char * const pipe_crc_objects[] = {
3905 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3909 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3910 if (!strcmp(buf, pipe_crc_objects[i])) {
3918 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3920 const char name = buf[0];
3922 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3931 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3935 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3936 if (!strcmp(buf, pipe_crc_sources[i])) {
3944 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3948 char *words[N_WORDS];
3950 enum intel_pipe_crc_object object;
3951 enum intel_pipe_crc_source source;
3953 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3954 if (n_words != N_WORDS) {
3955 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3960 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3961 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3965 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3966 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3970 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3971 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3975 return pipe_crc_set_source(dev, pipe, source);
3978 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3979 size_t len, loff_t *offp)
3981 struct seq_file *m = file->private_data;
3982 struct drm_device *dev = m->private;
3989 if (len > PAGE_SIZE - 1) {
3990 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3995 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3999 if (copy_from_user(tmpbuf, ubuf, len)) {
4005 ret = display_crc_ctl_parse(dev, tmpbuf, len);
4016 static const struct file_operations i915_display_crc_ctl_fops = {
4017 .owner = THIS_MODULE,
4018 .open = display_crc_ctl_open,
4020 .llseek = seq_lseek,
4021 .release = single_release,
4022 .write = display_crc_ctl_write
4025 static ssize_t i915_displayport_test_active_write(struct file *file,
4026 const char __user *ubuf,
4027 size_t len, loff_t *offp)
4032 struct drm_device *dev;
4033 struct drm_connector *connector;
4034 struct list_head *connector_list;
4035 struct intel_dp *intel_dp;
4038 m = file->private_data;
4049 connector_list = &dev->mode_config.connector_list;
4054 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4058 if (copy_from_user(input_buffer, ubuf, len)) {
4063 input_buffer[len] = '\0';
4064 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4066 list_for_each_entry(connector, connector_list, head) {
4068 if (connector->connector_type !=
4069 DRM_MODE_CONNECTOR_DisplayPort)
4072 if (connector->connector_type ==
4073 DRM_MODE_CONNECTOR_DisplayPort &&
4074 connector->status == connector_status_connected &&
4075 connector->encoder != NULL) {
4076 intel_dp = enc_to_intel_dp(connector->encoder);
4077 status = kstrtoint(input_buffer, 10, &val);
4080 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4081 /* To prevent erroneous activation of the compliance
4082 * testing code, only accept an actual value of 1 here
4085 intel_dp->compliance_test_active = 1;
4087 intel_dp->compliance_test_active = 0;
4091 kfree(input_buffer);
4099 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4101 struct drm_device *dev = m->private;
4102 struct drm_connector *connector;
4103 struct list_head *connector_list = &dev->mode_config.connector_list;
4104 struct intel_dp *intel_dp;
4109 list_for_each_entry(connector, connector_list, head) {
4111 if (connector->connector_type !=
4112 DRM_MODE_CONNECTOR_DisplayPort)
4115 if (connector->status == connector_status_connected &&
4116 connector->encoder != NULL) {
4117 intel_dp = enc_to_intel_dp(connector->encoder);
4118 if (intel_dp->compliance_test_active)
4129 static int i915_displayport_test_active_open(struct inode *inode,
4132 struct drm_device *dev = inode->i_private;
4134 return single_open(file, i915_displayport_test_active_show, dev);
4137 static const struct file_operations i915_displayport_test_active_fops = {
4138 .owner = THIS_MODULE,
4139 .open = i915_displayport_test_active_open,
4141 .llseek = seq_lseek,
4142 .release = single_release,
4143 .write = i915_displayport_test_active_write
4146 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4148 struct drm_device *dev = m->private;
4149 struct drm_connector *connector;
4150 struct list_head *connector_list = &dev->mode_config.connector_list;
4151 struct intel_dp *intel_dp;
4156 list_for_each_entry(connector, connector_list, head) {
4158 if (connector->connector_type !=
4159 DRM_MODE_CONNECTOR_DisplayPort)
4162 if (connector->status == connector_status_connected &&
4163 connector->encoder != NULL) {
4164 intel_dp = enc_to_intel_dp(connector->encoder);
4165 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4172 static int i915_displayport_test_data_open(struct inode *inode,
4175 struct drm_device *dev = inode->i_private;
4177 return single_open(file, i915_displayport_test_data_show, dev);
4180 static const struct file_operations i915_displayport_test_data_fops = {
4181 .owner = THIS_MODULE,
4182 .open = i915_displayport_test_data_open,
4184 .llseek = seq_lseek,
4185 .release = single_release
4188 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4190 struct drm_device *dev = m->private;
4191 struct drm_connector *connector;
4192 struct list_head *connector_list = &dev->mode_config.connector_list;
4193 struct intel_dp *intel_dp;
4198 list_for_each_entry(connector, connector_list, head) {
4200 if (connector->connector_type !=
4201 DRM_MODE_CONNECTOR_DisplayPort)
4204 if (connector->status == connector_status_connected &&
4205 connector->encoder != NULL) {
4206 intel_dp = enc_to_intel_dp(connector->encoder);
4207 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4215 static int i915_displayport_test_type_open(struct inode *inode,
4218 struct drm_device *dev = inode->i_private;
4220 return single_open(file, i915_displayport_test_type_show, dev);
4223 static const struct file_operations i915_displayport_test_type_fops = {
4224 .owner = THIS_MODULE,
4225 .open = i915_displayport_test_type_open,
4227 .llseek = seq_lseek,
4228 .release = single_release
4231 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4233 struct drm_device *dev = m->private;
4237 if (IS_CHERRYVIEW(dev))
4239 else if (IS_VALLEYVIEW(dev))
4242 num_levels = ilk_wm_max_level(dev) + 1;
4244 drm_modeset_lock_all(dev);
4246 for (level = 0; level < num_levels; level++) {
4247 unsigned int latency = wm[level];
4250 * - WM1+ latency values in 0.5us units
4251 * - latencies are in us on gen9/vlv/chv
4253 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
4258 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4259 level, wm[level], latency / 10, latency % 10);
4262 drm_modeset_unlock_all(dev);
4265 static int pri_wm_latency_show(struct seq_file *m, void *data)
4267 struct drm_device *dev = m->private;
4268 struct drm_i915_private *dev_priv = dev->dev_private;
4269 const uint16_t *latencies;
4271 if (INTEL_INFO(dev)->gen >= 9)
4272 latencies = dev_priv->wm.skl_latency;
4274 latencies = to_i915(dev)->wm.pri_latency;
4276 wm_latency_show(m, latencies);
4281 static int spr_wm_latency_show(struct seq_file *m, void *data)
4283 struct drm_device *dev = m->private;
4284 struct drm_i915_private *dev_priv = dev->dev_private;
4285 const uint16_t *latencies;
4287 if (INTEL_INFO(dev)->gen >= 9)
4288 latencies = dev_priv->wm.skl_latency;
4290 latencies = to_i915(dev)->wm.spr_latency;
4292 wm_latency_show(m, latencies);
4297 static int cur_wm_latency_show(struct seq_file *m, void *data)
4299 struct drm_device *dev = m->private;
4300 struct drm_i915_private *dev_priv = dev->dev_private;
4301 const uint16_t *latencies;
4303 if (INTEL_INFO(dev)->gen >= 9)
4304 latencies = dev_priv->wm.skl_latency;
4306 latencies = to_i915(dev)->wm.cur_latency;
4308 wm_latency_show(m, latencies);
4313 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4315 struct drm_device *dev = inode->i_private;
4317 if (INTEL_INFO(dev)->gen < 5)
4320 return single_open(file, pri_wm_latency_show, dev);
4323 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4325 struct drm_device *dev = inode->i_private;
4327 if (HAS_GMCH_DISPLAY(dev))
4330 return single_open(file, spr_wm_latency_show, dev);
4333 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4335 struct drm_device *dev = inode->i_private;
4337 if (HAS_GMCH_DISPLAY(dev))
4340 return single_open(file, cur_wm_latency_show, dev);
4343 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4344 size_t len, loff_t *offp, uint16_t wm[8])
4346 struct seq_file *m = file->private_data;
4347 struct drm_device *dev = m->private;
4348 uint16_t new[8] = { 0 };
4354 if (IS_CHERRYVIEW(dev))
4356 else if (IS_VALLEYVIEW(dev))
4359 num_levels = ilk_wm_max_level(dev) + 1;
4361 if (len >= sizeof(tmp))
4364 if (copy_from_user(tmp, ubuf, len))
4369 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4370 &new[0], &new[1], &new[2], &new[3],
4371 &new[4], &new[5], &new[6], &new[7]);
4372 if (ret != num_levels)
4375 drm_modeset_lock_all(dev);
4377 for (level = 0; level < num_levels; level++)
4378 wm[level] = new[level];
4380 drm_modeset_unlock_all(dev);
4386 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4387 size_t len, loff_t *offp)
4389 struct seq_file *m = file->private_data;
4390 struct drm_device *dev = m->private;
4391 struct drm_i915_private *dev_priv = dev->dev_private;
4392 uint16_t *latencies;
4394 if (INTEL_INFO(dev)->gen >= 9)
4395 latencies = dev_priv->wm.skl_latency;
4397 latencies = to_i915(dev)->wm.pri_latency;
4399 return wm_latency_write(file, ubuf, len, offp, latencies);
4402 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4403 size_t len, loff_t *offp)
4405 struct seq_file *m = file->private_data;
4406 struct drm_device *dev = m->private;
4407 struct drm_i915_private *dev_priv = dev->dev_private;
4408 uint16_t *latencies;
4410 if (INTEL_INFO(dev)->gen >= 9)
4411 latencies = dev_priv->wm.skl_latency;
4413 latencies = to_i915(dev)->wm.spr_latency;
4415 return wm_latency_write(file, ubuf, len, offp, latencies);
4418 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4419 size_t len, loff_t *offp)
4421 struct seq_file *m = file->private_data;
4422 struct drm_device *dev = m->private;
4423 struct drm_i915_private *dev_priv = dev->dev_private;
4424 uint16_t *latencies;
4426 if (INTEL_INFO(dev)->gen >= 9)
4427 latencies = dev_priv->wm.skl_latency;
4429 latencies = to_i915(dev)->wm.cur_latency;
4431 return wm_latency_write(file, ubuf, len, offp, latencies);
4434 static const struct file_operations i915_pri_wm_latency_fops = {
4435 .owner = THIS_MODULE,
4436 .open = pri_wm_latency_open,
4438 .llseek = seq_lseek,
4439 .release = single_release,
4440 .write = pri_wm_latency_write
4443 static const struct file_operations i915_spr_wm_latency_fops = {
4444 .owner = THIS_MODULE,
4445 .open = spr_wm_latency_open,
4447 .llseek = seq_lseek,
4448 .release = single_release,
4449 .write = spr_wm_latency_write
4452 static const struct file_operations i915_cur_wm_latency_fops = {
4453 .owner = THIS_MODULE,
4454 .open = cur_wm_latency_open,
4456 .llseek = seq_lseek,
4457 .release = single_release,
4458 .write = cur_wm_latency_write
4462 i915_wedged_get(void *data, u64 *val)
4464 struct drm_device *dev = data;
4465 struct drm_i915_private *dev_priv = dev->dev_private;
4467 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4473 i915_wedged_set(void *data, u64 val)
4475 struct drm_device *dev = data;
4476 struct drm_i915_private *dev_priv = dev->dev_private;
4479 * There is no safeguard against this debugfs entry colliding
4480 * with the hangcheck calling same i915_handle_error() in
4481 * parallel, causing an explosion. For now we assume that the
4482 * test harness is responsible enough not to inject gpu hangs
4483 * while it is writing to 'i915_wedged'
4486 if (i915_reset_in_progress(&dev_priv->gpu_error))
4489 intel_runtime_pm_get(dev_priv);
4491 i915_handle_error(dev, val,
4492 "Manually setting wedged to %llu", val);
4494 intel_runtime_pm_put(dev_priv);
4499 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4500 i915_wedged_get, i915_wedged_set,
4504 i915_ring_stop_get(void *data, u64 *val)
4506 struct drm_device *dev = data;
4507 struct drm_i915_private *dev_priv = dev->dev_private;
4509 *val = dev_priv->gpu_error.stop_rings;
4515 i915_ring_stop_set(void *data, u64 val)
4517 struct drm_device *dev = data;
4518 struct drm_i915_private *dev_priv = dev->dev_private;
4521 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4523 ret = mutex_lock_interruptible(&dev->struct_mutex);
4527 dev_priv->gpu_error.stop_rings = val;
4528 mutex_unlock(&dev->struct_mutex);
4533 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4534 i915_ring_stop_get, i915_ring_stop_set,
4538 i915_ring_missed_irq_get(void *data, u64 *val)
4540 struct drm_device *dev = data;
4541 struct drm_i915_private *dev_priv = dev->dev_private;
4543 *val = dev_priv->gpu_error.missed_irq_rings;
4548 i915_ring_missed_irq_set(void *data, u64 val)
4550 struct drm_device *dev = data;
4551 struct drm_i915_private *dev_priv = dev->dev_private;
4554 /* Lock against concurrent debugfs callers */
4555 ret = mutex_lock_interruptible(&dev->struct_mutex);
4558 dev_priv->gpu_error.missed_irq_rings = val;
4559 mutex_unlock(&dev->struct_mutex);
4564 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4565 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4569 i915_ring_test_irq_get(void *data, u64 *val)
4571 struct drm_device *dev = data;
4572 struct drm_i915_private *dev_priv = dev->dev_private;
4574 *val = dev_priv->gpu_error.test_irq_rings;
4580 i915_ring_test_irq_set(void *data, u64 val)
4582 struct drm_device *dev = data;
4583 struct drm_i915_private *dev_priv = dev->dev_private;
4586 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4588 /* Lock against concurrent debugfs callers */
4589 ret = mutex_lock_interruptible(&dev->struct_mutex);
4593 dev_priv->gpu_error.test_irq_rings = val;
4594 mutex_unlock(&dev->struct_mutex);
4599 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4600 i915_ring_test_irq_get, i915_ring_test_irq_set,
4603 #define DROP_UNBOUND 0x1
4604 #define DROP_BOUND 0x2
4605 #define DROP_RETIRE 0x4
4606 #define DROP_ACTIVE 0x8
4607 #define DROP_ALL (DROP_UNBOUND | \
4612 i915_drop_caches_get(void *data, u64 *val)
4620 i915_drop_caches_set(void *data, u64 val)
4622 struct drm_device *dev = data;
4623 struct drm_i915_private *dev_priv = dev->dev_private;
4626 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4628 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4629 * on ioctls on -EAGAIN. */
4630 ret = mutex_lock_interruptible(&dev->struct_mutex);
4634 if (val & DROP_ACTIVE) {
4635 ret = i915_gpu_idle(dev);
4640 if (val & (DROP_RETIRE | DROP_ACTIVE))
4641 i915_gem_retire_requests(dev);
4643 if (val & DROP_BOUND)
4644 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4646 if (val & DROP_UNBOUND)
4647 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4650 mutex_unlock(&dev->struct_mutex);
4655 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4656 i915_drop_caches_get, i915_drop_caches_set,
4660 i915_max_freq_get(void *data, u64 *val)
4662 struct drm_device *dev = data;
4663 struct drm_i915_private *dev_priv = dev->dev_private;
4666 if (INTEL_INFO(dev)->gen < 6)
4669 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4671 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4675 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4676 mutex_unlock(&dev_priv->rps.hw_lock);
4682 i915_max_freq_set(void *data, u64 val)
4684 struct drm_device *dev = data;
4685 struct drm_i915_private *dev_priv = dev->dev_private;
4689 if (INTEL_INFO(dev)->gen < 6)
4692 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4694 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4696 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4701 * Turbo will still be enabled, but won't go above the set value.
4703 val = intel_freq_opcode(dev_priv, val);
4705 hw_max = dev_priv->rps.max_freq;
4706 hw_min = dev_priv->rps.min_freq;
4708 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4709 mutex_unlock(&dev_priv->rps.hw_lock);
4713 dev_priv->rps.max_freq_softlimit = val;
4715 intel_set_rps(dev, val);
4717 mutex_unlock(&dev_priv->rps.hw_lock);
4722 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4723 i915_max_freq_get, i915_max_freq_set,
4727 i915_min_freq_get(void *data, u64 *val)
4729 struct drm_device *dev = data;
4730 struct drm_i915_private *dev_priv = dev->dev_private;
4733 if (INTEL_INFO(dev)->gen < 6)
4736 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4738 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4742 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4743 mutex_unlock(&dev_priv->rps.hw_lock);
4749 i915_min_freq_set(void *data, u64 val)
4751 struct drm_device *dev = data;
4752 struct drm_i915_private *dev_priv = dev->dev_private;
4756 if (INTEL_INFO(dev)->gen < 6)
4759 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4761 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4763 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4768 * Turbo will still be enabled, but won't go below the set value.
4770 val = intel_freq_opcode(dev_priv, val);
4772 hw_max = dev_priv->rps.max_freq;
4773 hw_min = dev_priv->rps.min_freq;
4775 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4776 mutex_unlock(&dev_priv->rps.hw_lock);
4780 dev_priv->rps.min_freq_softlimit = val;
4782 intel_set_rps(dev, val);
4784 mutex_unlock(&dev_priv->rps.hw_lock);
4789 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4790 i915_min_freq_get, i915_min_freq_set,
4794 i915_cache_sharing_get(void *data, u64 *val)
4796 struct drm_device *dev = data;
4797 struct drm_i915_private *dev_priv = dev->dev_private;
4801 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4804 ret = mutex_lock_interruptible(&dev->struct_mutex);
4807 intel_runtime_pm_get(dev_priv);
4809 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4811 intel_runtime_pm_put(dev_priv);
4812 mutex_unlock(&dev_priv->dev->struct_mutex);
4814 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4820 i915_cache_sharing_set(void *data, u64 val)
4822 struct drm_device *dev = data;
4823 struct drm_i915_private *dev_priv = dev->dev_private;
4826 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4832 intel_runtime_pm_get(dev_priv);
4833 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4835 /* Update the cache sharing policy here as well */
4836 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4837 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4838 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4839 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4841 intel_runtime_pm_put(dev_priv);
4845 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4846 i915_cache_sharing_get, i915_cache_sharing_set,
4849 struct sseu_dev_status {
4850 unsigned int slice_total;
4851 unsigned int subslice_total;
4852 unsigned int subslice_per_slice;
4853 unsigned int eu_total;
4854 unsigned int eu_per_subslice;
4857 static void cherryview_sseu_device_status(struct drm_device *dev,
4858 struct sseu_dev_status *stat)
4860 struct drm_i915_private *dev_priv = dev->dev_private;
4861 const int ss_max = 2;
4863 u32 sig1[ss_max], sig2[ss_max];
4865 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4866 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4867 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4868 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4870 for (ss = 0; ss < ss_max; ss++) {
4871 unsigned int eu_cnt;
4873 if (sig1[ss] & CHV_SS_PG_ENABLE)
4874 /* skip disabled subslice */
4877 stat->slice_total = 1;
4878 stat->subslice_per_slice++;
4879 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4880 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4881 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4882 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4883 stat->eu_total += eu_cnt;
4884 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
4886 stat->subslice_total = stat->subslice_per_slice;
4889 static void gen9_sseu_device_status(struct drm_device *dev,
4890 struct sseu_dev_status *stat)
4892 struct drm_i915_private *dev_priv = dev->dev_private;
4893 int s_max = 3, ss_max = 4;
4895 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4897 /* BXT has a single slice and at most 3 subslices. */
4898 if (IS_BROXTON(dev)) {
4903 for (s = 0; s < s_max; s++) {
4904 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4905 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4906 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4909 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4910 GEN9_PGCTL_SSA_EU19_ACK |
4911 GEN9_PGCTL_SSA_EU210_ACK |
4912 GEN9_PGCTL_SSA_EU311_ACK;
4913 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4914 GEN9_PGCTL_SSB_EU19_ACK |
4915 GEN9_PGCTL_SSB_EU210_ACK |
4916 GEN9_PGCTL_SSB_EU311_ACK;
4918 for (s = 0; s < s_max; s++) {
4919 unsigned int ss_cnt = 0;
4921 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4922 /* skip disabled slice */
4925 stat->slice_total++;
4927 if (IS_SKYLAKE(dev))
4928 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
4930 for (ss = 0; ss < ss_max; ss++) {
4931 unsigned int eu_cnt;
4933 if (IS_BROXTON(dev) &&
4934 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4935 /* skip disabled subslice */
4938 if (IS_BROXTON(dev))
4941 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4943 stat->eu_total += eu_cnt;
4944 stat->eu_per_subslice = max(stat->eu_per_subslice,
4948 stat->subslice_total += ss_cnt;
4949 stat->subslice_per_slice = max(stat->subslice_per_slice,
4954 static int i915_sseu_status(struct seq_file *m, void *unused)
4956 struct drm_info_node *node = (struct drm_info_node *) m->private;
4957 struct drm_device *dev = node->minor->dev;
4958 struct sseu_dev_status stat;
4960 if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
4963 seq_puts(m, "SSEU Device Info\n");
4964 seq_printf(m, " Available Slice Total: %u\n",
4965 INTEL_INFO(dev)->slice_total);
4966 seq_printf(m, " Available Subslice Total: %u\n",
4967 INTEL_INFO(dev)->subslice_total);
4968 seq_printf(m, " Available Subslice Per Slice: %u\n",
4969 INTEL_INFO(dev)->subslice_per_slice);
4970 seq_printf(m, " Available EU Total: %u\n",
4971 INTEL_INFO(dev)->eu_total);
4972 seq_printf(m, " Available EU Per Subslice: %u\n",
4973 INTEL_INFO(dev)->eu_per_subslice);
4974 seq_printf(m, " Has Slice Power Gating: %s\n",
4975 yesno(INTEL_INFO(dev)->has_slice_pg));
4976 seq_printf(m, " Has Subslice Power Gating: %s\n",
4977 yesno(INTEL_INFO(dev)->has_subslice_pg));
4978 seq_printf(m, " Has EU Power Gating: %s\n",
4979 yesno(INTEL_INFO(dev)->has_eu_pg));
4981 seq_puts(m, "SSEU Device Status\n");
4982 memset(&stat, 0, sizeof(stat));
4983 if (IS_CHERRYVIEW(dev)) {
4984 cherryview_sseu_device_status(dev, &stat);
4985 } else if (INTEL_INFO(dev)->gen >= 9) {
4986 gen9_sseu_device_status(dev, &stat);
4988 seq_printf(m, " Enabled Slice Total: %u\n",
4990 seq_printf(m, " Enabled Subslice Total: %u\n",
4991 stat.subslice_total);
4992 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
4993 stat.subslice_per_slice);
4994 seq_printf(m, " Enabled EU Total: %u\n",
4996 seq_printf(m, " Enabled EU Per Subslice: %u\n",
4997 stat.eu_per_subslice);
5002 static int i915_forcewake_open(struct inode *inode, struct file *file)
5004 struct drm_device *dev = inode->i_private;
5005 struct drm_i915_private *dev_priv = dev->dev_private;
5007 if (INTEL_INFO(dev)->gen < 6)
5010 intel_runtime_pm_get(dev_priv);
5011 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5016 static int i915_forcewake_release(struct inode *inode, struct file *file)
5018 struct drm_device *dev = inode->i_private;
5019 struct drm_i915_private *dev_priv = dev->dev_private;
5021 if (INTEL_INFO(dev)->gen < 6)
5024 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5025 intel_runtime_pm_put(dev_priv);
5030 static const struct file_operations i915_forcewake_fops = {
5031 .owner = THIS_MODULE,
5032 .open = i915_forcewake_open,
5033 .release = i915_forcewake_release,
5036 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5038 struct drm_device *dev = minor->dev;
5041 ent = debugfs_create_file("i915_forcewake_user",
5044 &i915_forcewake_fops);
5048 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5051 static int i915_debugfs_create(struct dentry *root,
5052 struct drm_minor *minor,
5054 const struct file_operations *fops)
5056 struct drm_device *dev = minor->dev;
5059 ent = debugfs_create_file(name,
5066 return drm_add_fake_info_node(minor, ent, fops);
5069 static const struct drm_info_list i915_debugfs_list[] = {
5070 {"i915_capabilities", i915_capabilities, 0},
5071 {"i915_gem_objects", i915_gem_object_info, 0},
5072 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5073 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5074 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5075 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5076 {"i915_gem_stolen", i915_gem_stolen_list_info },
5077 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5078 {"i915_gem_request", i915_gem_request_info, 0},
5079 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5080 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5081 {"i915_gem_interrupt", i915_interrupt_info, 0},
5082 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5083 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5084 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5085 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5086 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5087 {"i915_frequency_info", i915_frequency_info, 0},
5088 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5089 {"i915_drpc_info", i915_drpc_info, 0},
5090 {"i915_emon_status", i915_emon_status, 0},
5091 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5092 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5093 {"i915_fbc_status", i915_fbc_status, 0},
5094 {"i915_ips_status", i915_ips_status, 0},
5095 {"i915_sr_status", i915_sr_status, 0},
5096 {"i915_opregion", i915_opregion, 0},
5097 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5098 {"i915_context_status", i915_context_status, 0},
5099 {"i915_dump_lrc", i915_dump_lrc, 0},
5100 {"i915_execlists", i915_execlists, 0},
5101 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5102 {"i915_swizzle_info", i915_swizzle_info, 0},
5103 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5104 {"i915_llc", i915_llc, 0},
5105 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5106 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5107 {"i915_energy_uJ", i915_energy_uJ, 0},
5108 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5109 {"i915_power_domain_info", i915_power_domain_info, 0},
5110 {"i915_display_info", i915_display_info, 0},
5111 {"i915_semaphore_status", i915_semaphore_status, 0},
5112 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5113 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5114 {"i915_wa_registers", i915_wa_registers, 0},
5115 {"i915_ddb_info", i915_ddb_info, 0},
5116 {"i915_sseu_status", i915_sseu_status, 0},
5117 {"i915_drrs_status", i915_drrs_status, 0},
5118 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5120 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5122 static const struct i915_debugfs_files {
5124 const struct file_operations *fops;
5125 } i915_debugfs_files[] = {
5126 {"i915_wedged", &i915_wedged_fops},
5127 {"i915_max_freq", &i915_max_freq_fops},
5128 {"i915_min_freq", &i915_min_freq_fops},
5129 {"i915_cache_sharing", &i915_cache_sharing_fops},
5130 {"i915_ring_stop", &i915_ring_stop_fops},
5131 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5132 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5133 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5134 {"i915_error_state", &i915_error_state_fops},
5135 {"i915_next_seqno", &i915_next_seqno_fops},
5136 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5137 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5138 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5139 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5140 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5141 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5142 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5143 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5146 void intel_display_crc_init(struct drm_device *dev)
5148 struct drm_i915_private *dev_priv = dev->dev_private;
5151 for_each_pipe(dev_priv, pipe) {
5152 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5154 pipe_crc->opened = false;
5155 spin_lock_init(&pipe_crc->lock);
5156 init_waitqueue_head(&pipe_crc->wq);
5160 int i915_debugfs_init(struct drm_minor *minor)
5164 ret = i915_forcewake_create(minor->debugfs_root, minor);
5168 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5169 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5174 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5175 ret = i915_debugfs_create(minor->debugfs_root, minor,
5176 i915_debugfs_files[i].name,
5177 i915_debugfs_files[i].fops);
5182 return drm_debugfs_create_files(i915_debugfs_list,
5183 I915_DEBUGFS_ENTRIES,
5184 minor->debugfs_root, minor);
5187 void i915_debugfs_cleanup(struct drm_minor *minor)
5191 drm_debugfs_remove_files(i915_debugfs_list,
5192 I915_DEBUGFS_ENTRIES, minor);
5194 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5197 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5198 struct drm_info_list *info_list =
5199 (struct drm_info_list *)&i915_pipe_crc_data[i];
5201 drm_debugfs_remove_files(info_list, 1, minor);
5204 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5205 struct drm_info_list *info_list =
5206 (struct drm_info_list *) i915_debugfs_files[i].fops;
5208 drm_debugfs_remove_files(info_list, 1, minor);
5213 /* DPCD dump start address. */
5214 unsigned int offset;
5215 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5217 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5219 /* Only valid for eDP. */
5223 static const struct dpcd_block i915_dpcd_debug[] = {
5224 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5225 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5226 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5227 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5228 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5229 { .offset = DP_SET_POWER },
5230 { .offset = DP_EDP_DPCD_REV },
5231 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5232 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5233 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5236 static int i915_dpcd_show(struct seq_file *m, void *data)
5238 struct drm_connector *connector = m->private;
5239 struct intel_dp *intel_dp =
5240 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5245 if (connector->status != connector_status_connected)
5248 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5249 const struct dpcd_block *b = &i915_dpcd_debug[i];
5250 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5253 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5256 /* low tech for now */
5257 if (WARN_ON(size > sizeof(buf)))
5260 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5262 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5263 size, b->offset, err);
5267 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5273 static int i915_dpcd_open(struct inode *inode, struct file *file)
5275 return single_open(file, i915_dpcd_show, inode->i_private);
5278 static const struct file_operations i915_dpcd_fops = {
5279 .owner = THIS_MODULE,
5280 .open = i915_dpcd_open,
5282 .llseek = seq_lseek,
5283 .release = single_release,
5287 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5288 * @connector: pointer to a registered drm_connector
5290 * Cleanup will be done by drm_connector_unregister() through a call to
5291 * drm_debugfs_connector_remove().
5293 * Returns 0 on success, negative error codes on error.
5295 int i915_debugfs_connector_add(struct drm_connector *connector)
5297 struct dentry *root = connector->debugfs_entry;
5299 /* The connector must have been registered beforehands. */
5303 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5304 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5305 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,