drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/async.h>
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_fb_helper.h>
  35 #include <drm/drm_legacy.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_vgpu.h"
  40 #include "i915_trace.h"
  41 #include <linux/pci.h>
  42 #include <linux/console.h>
  43 #include <linux/vt.h>
  44 #include <linux/vgaarb.h>
  45 #include <linux/acpi.h>
  46 #include <linux/pnp.h>
  47 #include <linux/vga_switcheroo.h>
  48 #include <linux/slab.h>
  49 #include <acpi/video.h>
  50 #include <linux/pm.h>
  51 #include <linux/pm_runtime.h>
  52 #include <linux/oom.h>
  53
  54
  55 static int i915_getparam(struct drm_device *dev, void *data,
  56                          struct drm_file *file_priv)
  57 {
  58         struct drm_i915_private *dev_priv = dev->dev_private;
  59         drm_i915_getparam_t *param = data;
  60         int value;
  61
  62         switch (param->param) {
  63         case I915_PARAM_IRQ_ACTIVE:
  64         case I915_PARAM_ALLOW_BATCHBUFFER:
  65         case I915_PARAM_LAST_DISPATCH:
  66                 /* Reject all old ums/dri params. */
  67                 return -ENODEV;
  68         case I915_PARAM_CHIPSET_ID:
  69                 value = dev->pdev->device;
  70                 break;
  71         case I915_PARAM_HAS_GEM:
  72                 value = 1;
  73                 break;
  74         case I915_PARAM_NUM_FENCES_AVAIL:
  75                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
  76                 break;
  77         case I915_PARAM_HAS_OVERLAY:
  78                 value = dev_priv->overlay ? 1 : 0;
  79                 break;
  80         case I915_PARAM_HAS_PAGEFLIPPING:
  81                 value = 1;
  82                 break;
  83         case I915_PARAM_HAS_EXECBUF2:
  84                 /* depends on GEM */
  85                 value = 1;
  86                 break;
  87         case I915_PARAM_HAS_BSD:
  88                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
  89                 break;
  90         case I915_PARAM_HAS_BLT:
  91                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
  92                 break;
  93         case I915_PARAM_HAS_VEBOX:
  94                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
  95                 break;
  96         case I915_PARAM_HAS_BSD2:
  97                 value = intel_ring_initialized(&dev_priv->ring[VCS2]);
  98                 break;
  99         case I915_PARAM_HAS_RELAXED_FENCING:
 100                 value = 1;
 101                 break;
 102         case I915_PARAM_HAS_COHERENT_RINGS:
 103                 value = 1;
 104                 break;
 105         case I915_PARAM_HAS_EXEC_CONSTANTS:
 106                 value = INTEL_INFO(dev)->gen >= 4;
 107                 break;
 108         case I915_PARAM_HAS_RELAXED_DELTA:
 109                 value = 1;
 110                 break;
 111         case I915_PARAM_HAS_GEN7_SOL_RESET:
 112                 value = 1;
 113                 break;
 114         case I915_PARAM_HAS_LLC:
 115                 value = HAS_LLC(dev);
 116                 break;
 117         case I915_PARAM_HAS_WT:
 118                 value = HAS_WT(dev);
 119                 break;
 120         case I915_PARAM_HAS_ALIASING_PPGTT:
 121                 value = USES_PPGTT(dev);
 122                 break;
 123         case I915_PARAM_HAS_WAIT_TIMEOUT:
 124                 value = 1;
 125                 break;
 126         case I915_PARAM_HAS_SEMAPHORES:
 127                 value = i915_semaphore_is_enabled(dev);
 128                 break;
 129         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 130                 value = 1;
 131                 break;
 132         case I915_PARAM_HAS_SECURE_BATCHES:
 133                 value = capable(CAP_SYS_ADMIN);
 134                 break;
 135         case I915_PARAM_HAS_PINNED_BATCHES:
 136                 value = 1;
 137                 break;
 138         case I915_PARAM_HAS_EXEC_NO_RELOC:
 139                 value = 1;
 140                 break;
 141         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 142                 value = 1;
 143                 break;
 144         case I915_PARAM_CMD_PARSER_VERSION:
 145                 value = i915_cmd_parser_get_version();
 146                 break;
 147         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 148                 value = 1;
 149                 break;
 150         case I915_PARAM_MMAP_VERSION:
 151                 value = 1;
 152                 break;
 153         default:
 154                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 155                 return -EINVAL;
 156         }
 157
 158         if (copy_to_user(param->value, &value, sizeof(int))) {
 159                 DRM_ERROR("copy_to_user failed\n");
 160                 return -EFAULT;
 161         }
 162
 163         return 0;
 164 }
 165
 166 static int i915_setparam(struct drm_device *dev, void *data,
 167                          struct drm_file *file_priv)
 168 {
 169         struct drm_i915_private *dev_priv = dev->dev_private;
 170         drm_i915_setparam_t *param = data;
 171
 172         switch (param->param) {
 173         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 174         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 175         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 176                 /* Reject all old ums/dri params. */
 177                 return -ENODEV;
 178
 179         case I915_SETPARAM_NUM_USED_FENCES:
 180                 if (param->value > dev_priv->num_fence_regs ||
 181                     param->value < 0)
 182                         return -EINVAL;
 183                 /* Userspace can use first N regs */
 184                 dev_priv->fence_reg_start = param->value;
 185                 break;
 186         default:
 187                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 188                                         param->param);
 189                 return -EINVAL;
 190         }
 191
 192         return 0;
 193 }
 194
 195 static int i915_get_bridge_dev(struct drm_device *dev)
 196 {
 197         struct drm_i915_private *dev_priv = dev->dev_private;
 198
 199         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 200         if (!dev_priv->bridge_dev) {
 201                 DRM_ERROR("bridge device not found\n");
 202                 return -1;
 203         }
 204         return 0;
 205 }
 206
 207 #define MCHBAR_I915 0x44
 208 #define MCHBAR_I965 0x48
 209 #define MCHBAR_SIZE (4*4096)
 210
 211 #define DEVEN_REG 0x54
 212 #define   DEVEN_MCHBAR_EN (1 << 28)
 213
 214 /* Allocate space for the MCH regs if needed, return nonzero on error */
 215 static int
 216 intel_alloc_mchbar_resource(struct drm_device *dev)
 217 {
 218         struct drm_i915_private *dev_priv = dev->dev_private;
 219         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 220         u32 temp_lo, temp_hi = 0;
 221         u64 mchbar_addr;
 222         int ret;
 223
 224         if (INTEL_INFO(dev)->gen >= 4)
 225                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 226         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 227         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 228
 229         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 230 #ifdef CONFIG_PNP
 231         if (mchbar_addr &&
 232             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 233                 return 0;
 234 #endif
 235
 236         /* Get some space for it */
 237         dev_priv->mch_res.name = "i915 MCHBAR";
 238         dev_priv->mch_res.flags = IORESOURCE_MEM;
 239         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 240                                      &dev_priv->mch_res,
 241                                      MCHBAR_SIZE, MCHBAR_SIZE,
 242                                      PCIBIOS_MIN_MEM,
 243                                      0, pcibios_align_resource,
 244                                      dev_priv->bridge_dev);
 245         if (ret) {
 246                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 247                 dev_priv->mch_res.start = 0;
 248                 return ret;
 249         }
 250
 251         if (INTEL_INFO(dev)->gen >= 4)
 252                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 253                                        upper_32_bits(dev_priv->mch_res.start));
 254
 255         pci_write_config_dword(dev_priv->bridge_dev, reg,
 256                                lower_32_bits(dev_priv->mch_res.start));
 257         return 0;
 258 }
 259
 260 /* Setup MCHBAR if possible, return true if we should disable it again */
 261 static void
 262 intel_setup_mchbar(struct drm_device *dev)
 263 {
 264         struct drm_i915_private *dev_priv = dev->dev_private;
 265         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 266         u32 temp;
 267         bool enabled;
 268
 269         if (IS_VALLEYVIEW(dev))
 270                 return;
 271
 272         dev_priv->mchbar_need_disable = false;
 273
 274         if (IS_I915G(dev) || IS_I915GM(dev)) {
 275                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 276                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 277         } else {
 278                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 279                 enabled = temp & 1;
 280         }
 281
 282         /* If it's already enabled, don't have to do anything */
 283         if (enabled)
 284                 return;
 285
 286         if (intel_alloc_mchbar_resource(dev))
 287                 return;
 288
 289         dev_priv->mchbar_need_disable = true;
 290
 291         /* Space is allocated or reserved, so enable it. */
 292         if (IS_I915G(dev) || IS_I915GM(dev)) {
 293                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 294                                        temp | DEVEN_MCHBAR_EN);
 295         } else {
 296                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 297                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 298         }
 299 }
 300
 301 static void
 302 intel_teardown_mchbar(struct drm_device *dev)
 303 {
 304         struct drm_i915_private *dev_priv = dev->dev_private;
 305         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 306         u32 temp;
 307
 308         if (dev_priv->mchbar_need_disable) {
 309                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 310                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 311                         temp &= ~DEVEN_MCHBAR_EN;
 312                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 313                 } else {
 314                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 315                         temp &= ~1;
 316                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 317                 }
 318         }
 319
 320         if (dev_priv->mch_res.start)
 321                 release_resource(&dev_priv->mch_res);
 322 }
 323
 324 /* true = enable decode, false = disable decoder */
 325 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 326 {
 327         struct drm_device *dev = cookie;
 328
 329         intel_modeset_vga_set_state(dev, state);
 330         if (state)
 331                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 332                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 333         else
 334                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 335 }
 336
 337 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 338 {
 339         struct drm_device *dev = pci_get_drvdata(pdev);
 340         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 341
 342         if (state == VGA_SWITCHEROO_ON) {
 343                 pr_info("switched on\n");
 344                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 345                 /* i915 resume handler doesn't set to D0 */
 346                 pci_set_power_state(dev->pdev, PCI_D0);
 347                 i915_resume_legacy(dev);
 348                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 349         } else {
 350                 pr_err("switched off\n");
 351                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 352                 i915_suspend_legacy(dev, pmm);
 353                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 354         }
 355 }
 356
 357 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 358 {
 359         struct drm_device *dev = pci_get_drvdata(pdev);
 360
 361         /*
 362          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 363          * locking inversion with the driver load path. And the access here is
 364          * completely racy anyway. So don't bother with locking for now.
 365          */
 366         return dev->open_count == 0;
 367 }
 368
 369 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 370         .set_gpu_state = i915_switcheroo_set_state,
 371         .reprobe = NULL,
 372         .can_switch = i915_switcheroo_can_switch,
 373 };
 374
 375 static int i915_load_modeset_init(struct drm_device *dev)
 376 {
 377         struct drm_i915_private *dev_priv = dev->dev_private;
 378         int ret;
 379
 380         ret = intel_parse_bios(dev);
 381         if (ret)
 382                 DRM_INFO("failed to find VBIOS tables\n");
 383
 384         /* If we have > 1 VGA cards, then we need to arbitrate access
 385          * to the common VGA resources.
 386          *
 387          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 388          * then we do not take part in VGA arbitration and the
 389          * vga_client_register() fails with -ENODEV.
 390          */
 391         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
 392         if (ret && ret != -ENODEV)
 393                 goto out;
 394
 395         intel_register_dsm_handler();
 396
 397         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
 398         if (ret)
 399                 goto cleanup_vga_client;
 400
 401         /* Initialise stolen first so that we may reserve preallocated
 402          * objects for the BIOS to KMS transition.
 403          */
 404         ret = i915_gem_init_stolen(dev);
 405         if (ret)
 406                 goto cleanup_vga_switcheroo;
 407
 408         intel_power_domains_init_hw(dev_priv);
 409
 410         ret = intel_irq_install(dev_priv);
 411         if (ret)
 412                 goto cleanup_gem_stolen;
 413
 414         /* Important: The output setup functions called by modeset_init need
 415          * working irqs for e.g. gmbus and dp aux transfers. */
 416         intel_modeset_init(dev);
 417
 418         ret = i915_gem_init(dev);
 419         if (ret)
 420                 goto cleanup_irq;
 421
 422         intel_modeset_gem_init(dev);
 423
 424         /* Always safe in the mode setting case. */
 425         /* FIXME: do pre/post-mode set stuff in core KMS code */
 426         dev->vblank_disable_allowed = true;
 427         if (INTEL_INFO(dev)->num_pipes == 0)
 428                 return 0;
 429
 430         ret = intel_fbdev_init(dev);
 431         if (ret)
 432                 goto cleanup_gem;
 433
 434         /* Only enable hotplug handling once the fbdev is fully set up. */
 435         intel_hpd_init(dev_priv);
 436
 437         /*
 438          * Some ports require correctly set-up hpd registers for detection to
 439          * work properly (leading to ghost connected connector status), e.g. VGA
 440          * on gm45.  Hence we can only set up the initial fbdev config after hpd
 441          * irqs are fully enabled. Now we should scan for the initial config
 442          * only once hotplug handling is enabled, but due to screwed-up locking
 443          * around kms/fbdev init we can't protect the fdbev initial config
 444          * scanning against hotplug events. Hence do this first and ignore the
 445          * tiny window where we will loose hotplug notifactions.
 446          */
 447         async_schedule(intel_fbdev_initial_config, dev_priv);
 448
 449         drm_kms_helper_poll_init(dev);
 450
 451         return 0;
 452
 453 cleanup_gem:
 454         mutex_lock(&dev->struct_mutex);
 455         i915_gem_cleanup_ringbuffer(dev);
 456         i915_gem_context_fini(dev);
 457         mutex_unlock(&dev->struct_mutex);
 458 cleanup_irq:
 459         drm_irq_uninstall(dev);
 460 cleanup_gem_stolen:
 461         i915_gem_cleanup_stolen(dev);
 462 cleanup_vga_switcheroo:
 463         vga_switcheroo_unregister_client(dev->pdev);
 464 cleanup_vga_client:
 465         vga_client_register(dev->pdev, NULL, NULL, NULL);
 466 out:
 467         return ret;
 468 }
 469
 470 #if IS_ENABLED(CONFIG_FB)
 471 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 472 {
 473         struct apertures_struct *ap;
 474         struct pci_dev *pdev = dev_priv->dev->pdev;
 475         bool primary;
 476         int ret;
 477
 478         ap = alloc_apertures(1);
 479         if (!ap)
 480                 return -ENOMEM;
 481
 482         ap->ranges[0].base = dev_priv->gtt.mappable_base;
 483         ap->ranges[0].size = dev_priv->gtt.mappable_end;
 484
 485         primary =
 486                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 487
 488         ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 489
 490         kfree(ap);
 491
 492         return ret;
 493 }
 494 #else
 495 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 496 {
 497         return 0;
 498 }
 499 #endif
 500
 501 #if !defined(CONFIG_VGA_CONSOLE)
 502 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 503 {
 504         return 0;
 505 }
 506 #elif !defined(CONFIG_DUMMY_CONSOLE)
 507 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 508 {
 509         return -ENODEV;
 510 }
 511 #else
 512 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 513 {
 514         int ret = 0;
 515
 516         DRM_INFO("Replacing VGA console driver\n");
 517
 518         console_lock();
 519         if (con_is_bound(&vga_con))
 520                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 521         if (ret == 0) {
 522                 ret = do_unregister_con_driver(&vga_con);
 523
 524                 /* Ignore "already unregistered". */
 525                 if (ret == -ENODEV)
 526                         ret = 0;
 527         }
 528         console_unlock();
 529
 530         return ret;
 531 }
 532 #endif
 533
 534 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
 535 {
 536         const struct intel_device_info *info = &dev_priv->info;
 537
 538 #define PRINT_S(name) "%s"
 539 #define SEP_EMPTY
 540 #define PRINT_FLAG(name) info->name ? #name "," : ""
 541 #define SEP_COMMA ,
 542         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
 543                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
 544                          info->gen,
 545                          dev_priv->dev->pdev->device,
 546                          dev_priv->dev->pdev->revision,
 547                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
 548 #undef PRINT_S
 549 #undef SEP_EMPTY
 550 #undef PRINT_FLAG
 551 #undef SEP_COMMA
 552 }
 553
 554 /*
 555  * Determine various intel_device_info fields at runtime.
 556  *
 557  * Use it when either:
 558  *   - it's judged too laborious to fill n static structures with the limit
 559  *     when a simple if statement does the job,
 560  *   - run-time checks (eg read fuse/strap registers) are needed.
 561  *
 562  * This function needs to be called:
 563  *   - after the MMIO has been setup as we are reading registers,
 564  *   - after the PCH has been detected,
 565  *   - before the first usage of the fields it can tweak.
 566  */
 567 static void intel_device_info_runtime_init(struct drm_device *dev)
 568 {
 569         struct drm_i915_private *dev_priv = dev->dev_private;
 570         struct intel_device_info *info;
 571         enum pipe pipe;
 572
 573         info = (struct intel_device_info *)&dev_priv->info;
 574
 575         if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen == 9)
 576                 for_each_pipe(dev_priv, pipe)
 577                         info->num_sprites[pipe] = 2;
 578         else
 579                 for_each_pipe(dev_priv, pipe)
 580                         info->num_sprites[pipe] = 1;
 581
 582         if (i915.disable_display) {
 583                 DRM_INFO("Display disabled (module parameter)\n");
 584                 info->num_pipes = 0;
 585         } else if (info->num_pipes > 0 &&
 586                    (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
 587                    !IS_VALLEYVIEW(dev)) {
 588                 u32 fuse_strap = I915_READ(FUSE_STRAP);
 589                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
 590
 591                 /*
 592                  * SFUSE_STRAP is supposed to have a bit signalling the display
 593                  * is fused off. Unfortunately it seems that, at least in
 594                  * certain cases, fused off display means that PCH display
 595                  * reads don't land anywhere. In that case, we read 0s.
 596                  *
 597                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
 598                  * should be set when taking over after the firmware.
 599                  */
 600                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
 601                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
 602                     (dev_priv->pch_type == PCH_CPT &&
 603                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 604                         DRM_INFO("Display fused off, disabling\n");
 605                         info->num_pipes = 0;
 606                 }
 607         }
 608
 609         if (IS_CHERRYVIEW(dev)) {
 610                 u32 fuse, mask_eu;
 611
 612                 fuse = I915_READ(CHV_FUSE_GT);
 613                 mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
 614                                   CHV_FGT_EU_DIS_SS0_R1_MASK |
 615                                   CHV_FGT_EU_DIS_SS1_R0_MASK |
 616                                   CHV_FGT_EU_DIS_SS1_R1_MASK);
 617                 info->eu_total = 16 - hweight32(mask_eu);
 618         }
 619 }
 620
 621 /**
 622  * i915_driver_load - setup chip and create an initial config
 623  * @dev: DRM device
 624  * @flags: startup flags
 625  *
 626  * The driver load routine has to do several things:
 627  *   - drive output discovery via intel_modeset_init()
 628  *   - initialize the memory manager
 629  *   - allocate initial config memory
 630  *   - setup the DRM framebuffer with the allocated memory
 631  */
 632 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 633 {
 634         struct drm_i915_private *dev_priv;
 635         struct intel_device_info *info, *device_info;
 636         int ret = 0, mmio_bar, mmio_size;
 637         uint32_t aperture_size;
 638
 639         info = (struct intel_device_info *) flags;
 640
 641         /* Refuse to load on gen6+ without kms enabled. */
 642         if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) {
 643                 DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
 644                 DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
 645                 return -ENODEV;
 646         }
 647
 648         /* UMS needs agp support. */
 649         if (!drm_core_check_feature(dev, DRIVER_MODESET) && !dev->agp)
 650                 return -EINVAL;
 651
 652         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 653         if (dev_priv == NULL)
 654                 return -ENOMEM;
 655
 656         dev->dev_private = dev_priv;
 657         dev_priv->dev = dev;
 658
 659         /* Setup the write-once "constant" device info */
 660         device_info = (struct intel_device_info *)&dev_priv->info;
 661         memcpy(device_info, info, sizeof(dev_priv->info));
 662         device_info->device_id = dev->pdev->device;
 663
 664         spin_lock_init(&dev_priv->irq_lock);
 665         spin_lock_init(&dev_priv->gpu_error.lock);
 666         mutex_init(&dev_priv->backlight_lock);
 667         spin_lock_init(&dev_priv->uncore.lock);
 668         spin_lock_init(&dev_priv->mm.object_stat_lock);
 669         spin_lock_init(&dev_priv->mmio_flip_lock);
 670         mutex_init(&dev_priv->dpio_lock);
 671         mutex_init(&dev_priv->modeset_restore_lock);
 672
 673         intel_pm_setup(dev);
 674
 675         intel_display_crc_init(dev);
 676
 677         i915_dump_device_info(dev_priv);
 678
 679         /* Not all pre-production machines fall into this category, only the
 680          * very first ones. Almost everything should work, except for maybe
 681          * suspend/resume. And we don't implement workarounds that affect only
 682          * pre-production machines. */
 683         if (IS_HSW_EARLY_SDV(dev))
 684                 DRM_INFO("This is an early pre-production Haswell machine. "
 685                          "It may not be fully functional.\n");
 686
 687         if (i915_get_bridge_dev(dev)) {
 688                 ret = -EIO;
 689                 goto free_priv;
 690         }
 691
 692         mmio_bar = IS_GEN2(dev) ? 1 : 0;
 693         /* Before gen4, the registers and the GTT are behind different BARs.
 694          * However, from gen4 onwards, the registers and the GTT are shared
 695          * in the same BAR, so we want to restrict this ioremap from
 696          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 697          * the register BAR remains the same size for all the earlier
 698          * generations up to Ironlake.
 699          */
 700         if (info->gen < 5)
 701                 mmio_size = 512*1024;
 702         else
 703                 mmio_size = 2*1024*1024;
 704
 705         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
 706         if (!dev_priv->regs) {
 707                 DRM_ERROR("failed to map registers\n");
 708                 ret = -EIO;
 709                 goto put_bridge;
 710         }
 711
 712         /* This must be called before any calls to HAS_PCH_* */
 713         intel_detect_pch(dev);
 714
 715         intel_uncore_init(dev);
 716
 717         ret = i915_gem_gtt_init(dev);
 718         if (ret)
 719                 goto out_regs;
 720
 721         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 722                 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
 723                  * otherwise the vga fbdev driver falls over. */
 724                 ret = i915_kick_out_firmware_fb(dev_priv);
 725                 if (ret) {
 726                         DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
 727                         goto out_gtt;
 728                 }
 729
 730                 ret = i915_kick_out_vgacon(dev_priv);
 731                 if (ret) {
 732                         DRM_ERROR("failed to remove conflicting VGA console\n");
 733                         goto out_gtt;
 734                 }
 735         }
 736
 737         pci_set_master(dev->pdev);
 738
 739         /* overlay on gen2 is broken and can't address above 1G */
 740         if (IS_GEN2(dev))
 741                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
 742
 743         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
 744          * using 32bit addressing, overwriting memory if HWS is located
 745          * above 4GB.
 746          *
 747          * The documentation also mentions an issue with undefined
 748          * behaviour if any general state is accessed within a page above 4GB,
 749          * which also needs to be handled carefully.
 750          */
 751         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
 752                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
 753
 754         aperture_size = dev_priv->gtt.mappable_end;
 755
 756         dev_priv->gtt.mappable =
 757                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
 758                                      aperture_size);
 759         if (dev_priv->gtt.mappable == NULL) {
 760                 ret = -EIO;
 761                 goto out_gtt;
 762         }
 763
 764         dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
 765                                               aperture_size);
 766
 767         /* The i915 workqueue is primarily used for batched retirement of
 768          * requests (and thus managing bo) once the task has been completed
 769          * by the GPU. i915_gem_retire_requests() is called directly when we
 770          * need high-priority retirement, such as waiting for an explicit
 771          * bo.
 772          *
 773          * It is also used for periodic low-priority events, such as
 774          * idle-timers and recording error state.
 775          *
 776          * All tasks on the workqueue are expected to acquire the dev mutex
 777          * so there is no point in running more than one instance of the
 778          * workqueue at any time.  Use an ordered one.
 779          */
 780         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 781         if (dev_priv->wq == NULL) {
 782                 DRM_ERROR("Failed to create our workqueue.\n");
 783                 ret = -ENOMEM;
 784                 goto out_mtrrfree;
 785         }
 786
 787         dev_priv->dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 788         if (dev_priv->dp_wq == NULL) {
 789                 DRM_ERROR("Failed to create our dp workqueue.\n");
 790                 ret = -ENOMEM;
 791                 goto out_freewq;
 792         }
 793
 794         dev_priv->gpu_error.hangcheck_wq =
 795                 alloc_ordered_workqueue("i915-hangcheck", 0);
 796         if (dev_priv->gpu_error.hangcheck_wq == NULL) {
 797                 DRM_ERROR("Failed to create our hangcheck workqueue.\n");
 798                 ret = -ENOMEM;
 799                 goto out_freedpwq;
 800         }
 801
 802         intel_irq_init(dev_priv);
 803         intel_uncore_sanitize(dev);
 804
 805         /* Try to make sure MCHBAR is enabled before poking at it */
 806         intel_setup_mchbar(dev);
 807         intel_setup_gmbus(dev);
 808         intel_opregion_setup(dev);
 809
 810         intel_setup_bios(dev);
 811
 812         i915_gem_load(dev);
 813
 814         /* On the 945G/GM, the chipset reports the MSI capability on the
 815          * integrated graphics even though the support isn't actually there
 816          * according to the published specs.  It doesn't appear to function
 817          * correctly in testing on 945G.
 818          * This may be a side effect of MSI having been made available for PEG
 819          * and the registers being closely associated.
 820          *
 821          * According to chipset errata, on the 965GM, MSI interrupts may
 822          * be lost or delayed, but we use them anyways to avoid
 823          * stuck interrupts on some machines.
 824          */
 825         if (!IS_I945G(dev) && !IS_I945GM(dev))
 826                 pci_enable_msi(dev->pdev);
 827
 828         intel_device_info_runtime_init(dev);
 829
 830         if (INTEL_INFO(dev)->num_pipes) {
 831                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
 832                 if (ret)
 833                         goto out_gem_unload;
 834         }
 835
 836         intel_power_domains_init(dev_priv);
 837
 838         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 839                 ret = i915_load_modeset_init(dev);
 840                 if (ret < 0) {
 841                         DRM_ERROR("failed to init modeset\n");
 842                         goto out_power_well;
 843                 }
 844         }
 845
 846         /*
 847          * Notify a valid surface after modesetting,
 848          * when running inside a VM.
 849          */
 850         if (intel_vgpu_active(dev))
 851                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
 852
 853         i915_setup_sysfs(dev);
 854
 855         if (INTEL_INFO(dev)->num_pipes) {
 856                 /* Must be done after probing outputs */
 857                 intel_opregion_init(dev);
 858                 acpi_video_register();
 859         }
 860
 861         if (IS_GEN5(dev))
 862                 intel_gpu_ips_init(dev_priv);
 863
 864         intel_runtime_pm_enable(dev_priv);
 865
 866         i915_audio_component_init(dev_priv);
 867
 868         return 0;
 869
 870 out_power_well:
 871         intel_power_domains_fini(dev_priv);
 872         drm_vblank_cleanup(dev);
 873 out_gem_unload:
 874         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
 875         unregister_shrinker(&dev_priv->mm.shrinker);
 876
 877         if (dev->pdev->msi_enabled)
 878                 pci_disable_msi(dev->pdev);
 879
 880         intel_teardown_gmbus(dev);
 881         intel_teardown_mchbar(dev);
 882         pm_qos_remove_request(&dev_priv->pm_qos);
 883         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
 884 out_freedpwq:
 885         destroy_workqueue(dev_priv->dp_wq);
 886 out_freewq:
 887         destroy_workqueue(dev_priv->wq);
 888 out_mtrrfree:
 889         arch_phys_wc_del(dev_priv->gtt.mtrr);
 890         io_mapping_free(dev_priv->gtt.mappable);
 891 out_gtt:
 892         i915_global_gtt_cleanup(dev);
 893 out_regs:
 894         intel_uncore_fini(dev);
 895         pci_iounmap(dev->pdev, dev_priv->regs);
 896 put_bridge:
 897         pci_dev_put(dev_priv->bridge_dev);
 898 free_priv:
 899         if (dev_priv->slab)
 900                 kmem_cache_destroy(dev_priv->slab);
 901         kfree(dev_priv);
 902         return ret;
 903 }
 904
 905 int i915_driver_unload(struct drm_device *dev)
 906 {
 907         struct drm_i915_private *dev_priv = dev->dev_private;
 908         int ret;
 909
 910         i915_audio_component_cleanup(dev_priv);
 911
 912         ret = i915_gem_suspend(dev);
 913         if (ret) {
 914                 DRM_ERROR("failed to idle hardware: %d\n", ret);
 915                 return ret;
 916         }
 917
 918         intel_power_domains_fini(dev_priv);
 919
 920         intel_gpu_ips_teardown();
 921
 922         i915_teardown_sysfs(dev);
 923
 924         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
 925         unregister_shrinker(&dev_priv->mm.shrinker);
 926
 927         io_mapping_free(dev_priv->gtt.mappable);
 928         arch_phys_wc_del(dev_priv->gtt.mtrr);
 929
 930         acpi_video_unregister();
 931
 932         if (drm_core_check_feature(dev, DRIVER_MODESET))
 933                 intel_fbdev_fini(dev);
 934
 935         drm_vblank_cleanup(dev);
 936
 937         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 938                 intel_modeset_cleanup(dev);
 939
 940                 /*
 941                  * free the memory space allocated for the child device
 942                  * config parsed from VBT
 943                  */
 944                 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
 945                         kfree(dev_priv->vbt.child_dev);
 946                         dev_priv->vbt.child_dev = NULL;
 947                         dev_priv->vbt.child_dev_num = 0;
 948                 }
 949
 950                 vga_switcheroo_unregister_client(dev->pdev);
 951                 vga_client_register(dev->pdev, NULL, NULL, NULL);
 952         }
 953
 954         /* Free error state after interrupts are fully disabled. */
 955         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
 956         i915_destroy_error_state(dev);
 957
 958         if (dev->pdev->msi_enabled)
 959                 pci_disable_msi(dev->pdev);
 960
 961         intel_opregion_fini(dev);
 962
 963         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 964                 /* Flush any outstanding unpin_work. */
 965                 flush_workqueue(dev_priv->wq);
 966
 967                 mutex_lock(&dev->struct_mutex);
 968                 i915_gem_cleanup_ringbuffer(dev);
 969                 i915_gem_batch_pool_fini(&dev_priv->mm.batch_pool);
 970                 i915_gem_context_fini(dev);
 971                 mutex_unlock(&dev->struct_mutex);
 972                 i915_gem_cleanup_stolen(dev);
 973         }
 974
 975         intel_teardown_gmbus(dev);
 976         intel_teardown_mchbar(dev);
 977
 978         destroy_workqueue(dev_priv->dp_wq);
 979         destroy_workqueue(dev_priv->wq);
 980         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
 981         pm_qos_remove_request(&dev_priv->pm_qos);
 982
 983         i915_global_gtt_cleanup(dev);
 984
 985         intel_uncore_fini(dev);
 986         if (dev_priv->regs != NULL)
 987                 pci_iounmap(dev->pdev, dev_priv->regs);
 988
 989         if (dev_priv->slab)
 990                 kmem_cache_destroy(dev_priv->slab);
 991
 992         pci_dev_put(dev_priv->bridge_dev);
 993         kfree(dev_priv);
 994
 995         return 0;
 996 }
 997
 998 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
 999 {
1000         int ret;
1001
1002         ret = i915_gem_open(dev, file);
1003         if (ret)
1004                 return ret;
1005
1006         return 0;
1007 }
1008
1009 /**
1010  * i915_driver_lastclose - clean up after all DRM clients have exited
1011  * @dev: DRM device
1012  *
1013  * Take care of cleaning up after all DRM clients have exited.  In the
1014  * mode setting case, we want to restore the kernel's initial mode (just
1015  * in case the last client left us in a bad state).
1016  *
1017  * Additionally, in the non-mode setting case, we'll tear down the GTT
1018  * and DMA structures, since the kernel won't be using them, and clea
1019  * up any GEM state.
1020  */
1021 void i915_driver_lastclose(struct drm_device *dev)
1022 {
1023         intel_fbdev_restore_mode(dev);
1024         vga_switcheroo_process_delayed_switch();
1025 }
1026
1027 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1028 {
1029         mutex_lock(&dev->struct_mutex);
1030         i915_gem_context_close(dev, file);
1031         i915_gem_release(dev, file);
1032         mutex_unlock(&dev->struct_mutex);
1033
1034         if (drm_core_check_feature(dev, DRIVER_MODESET))
1035                 intel_modeset_preclose(dev, file);
1036 }
1037
1038 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1039 {
1040         struct drm_i915_file_private *file_priv = file->driver_priv;
1041
1042         if (file_priv && file_priv->bsd_ring)
1043                 file_priv->bsd_ring = NULL;
1044         kfree(file_priv);
1045 }
1046
1047 static int
1048 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1049                           struct drm_file *file)
1050 {
1051         return -ENODEV;
1052 }
1053
1054 const struct drm_ioctl_desc i915_ioctls[] = {
1055         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1056         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1057         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1058         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1059         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1060         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1061         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1062         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1063         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1064         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1065         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1066         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1067         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1068         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1069         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1070         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1071         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1072         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1073         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1074         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1075         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1076         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1077         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1078         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1079         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1080         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1081         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1082         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1083         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1084         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1085         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1086         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1087         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1088         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1089         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1090         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1091         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1092         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1093         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1094         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1095         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1096         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1097         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1098         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1099         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1100         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1101         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1102         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1103         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1104         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1105         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1106         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1107 };
1108
1109 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);
1110
1111 /*
1112  * This is really ugly: Because old userspace abused the linux agp interface to
1113  * manage the gtt, we need to claim that all intel devices are agp.  For
1114  * otherwise the drm core refuses to initialize the agp support code.
1115  */
1116 int i915_driver_device_is_agp(struct drm_device *dev)
1117 {
1118         return 1;
1119 }