drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/async.h>
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_fb_helper.h>
  35 #include <drm/drm_legacy.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <linux/pci.h>
  41 #include <linux/console.h>
  42 #include <linux/vt.h>
  43 #include <linux/vgaarb.h>
  44 #include <linux/acpi.h>
  45 #include <linux/pnp.h>
  46 #include <linux/vga_switcheroo.h>
  47 #include <linux/slab.h>
  48 #include <acpi/video.h>
  49 #include <linux/pm.h>
  50 #include <linux/pm_runtime.h>
  51 #include <linux/oom.h>
  52
  53
  54 static int i915_getparam(struct drm_device *dev, void *data,
  55                          struct drm_file *file_priv)
  56 {
  57         struct drm_i915_private *dev_priv = dev->dev_private;
  58         drm_i915_getparam_t *param = data;
  59         int value;
  60
  61         if (!dev_priv) {
  62                 DRM_ERROR("called with no initialization\n");
  63                 return -EINVAL;
  64         }
  65
  66         switch (param->param) {
  67         case I915_PARAM_IRQ_ACTIVE:
  68                 return -ENODEV;
  69         case I915_PARAM_ALLOW_BATCHBUFFER:
  70                 return -ENODEV;
  71         case I915_PARAM_LAST_DISPATCH:
  72                 return -ENODEV;
  73         case I915_PARAM_CHIPSET_ID:
  74                 value = dev->pdev->device;
  75                 break;
  76         case I915_PARAM_HAS_GEM:
  77                 value = 1;
  78                 break;
  79         case I915_PARAM_NUM_FENCES_AVAIL:
  80                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
  81                 break;
  82         case I915_PARAM_HAS_OVERLAY:
  83                 value = dev_priv->overlay ? 1 : 0;
  84                 break;
  85         case I915_PARAM_HAS_PAGEFLIPPING:
  86                 value = 1;
  87                 break;
  88         case I915_PARAM_HAS_EXECBUF2:
  89                 /* depends on GEM */
  90                 value = 1;
  91                 break;
  92         case I915_PARAM_HAS_BSD:
  93                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
  94                 break;
  95         case I915_PARAM_HAS_BLT:
  96                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
  97                 break;
  98         case I915_PARAM_HAS_VEBOX:
  99                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
 100                 break;
 101         case I915_PARAM_HAS_RELAXED_FENCING:
 102                 value = 1;
 103                 break;
 104         case I915_PARAM_HAS_COHERENT_RINGS:
 105                 value = 1;
 106                 break;
 107         case I915_PARAM_HAS_EXEC_CONSTANTS:
 108                 value = INTEL_INFO(dev)->gen >= 4;
 109                 break;
 110         case I915_PARAM_HAS_RELAXED_DELTA:
 111                 value = 1;
 112                 break;
 113         case I915_PARAM_HAS_GEN7_SOL_RESET:
 114                 value = 1;
 115                 break;
 116         case I915_PARAM_HAS_LLC:
 117                 value = HAS_LLC(dev);
 118                 break;
 119         case I915_PARAM_HAS_WT:
 120                 value = HAS_WT(dev);
 121                 break;
 122         case I915_PARAM_HAS_ALIASING_PPGTT:
 123                 value = USES_PPGTT(dev);
 124                 break;
 125         case I915_PARAM_HAS_WAIT_TIMEOUT:
 126                 value = 1;
 127                 break;
 128         case I915_PARAM_HAS_SEMAPHORES:
 129                 value = i915_semaphore_is_enabled(dev);
 130                 break;
 131         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 132                 value = 1;
 133                 break;
 134         case I915_PARAM_HAS_SECURE_BATCHES:
 135                 value = capable(CAP_SYS_ADMIN);
 136                 break;
 137         case I915_PARAM_HAS_PINNED_BATCHES:
 138                 value = 1;
 139                 break;
 140         case I915_PARAM_HAS_EXEC_NO_RELOC:
 141                 value = 1;
 142                 break;
 143         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 144                 value = 1;
 145                 break;
 146         case I915_PARAM_CMD_PARSER_VERSION:
 147                 value = i915_cmd_parser_get_version();
 148                 break;
 149         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 150                 value = 1;
 151                 break;
 152         default:
 153                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 154                 return -EINVAL;
 155         }
 156
 157         if (copy_to_user(param->value, &value, sizeof(int))) {
 158                 DRM_ERROR("copy_to_user failed\n");
 159                 return -EFAULT;
 160         }
 161
 162         return 0;
 163 }
 164
 165 static int i915_setparam(struct drm_device *dev, void *data,
 166                          struct drm_file *file_priv)
 167 {
 168         struct drm_i915_private *dev_priv = dev->dev_private;
 169         drm_i915_setparam_t *param = data;
 170
 171         if (!dev_priv) {
 172                 DRM_ERROR("called with no initialization\n");
 173                 return -EINVAL;
 174         }
 175
 176         switch (param->param) {
 177         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 178         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 179         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 180                 return -ENODEV;
 181
 182         case I915_SETPARAM_NUM_USED_FENCES:
 183                 if (param->value > dev_priv->num_fence_regs ||
 184                     param->value < 0)
 185                         return -EINVAL;
 186                 /* Userspace can use first N regs */
 187                 dev_priv->fence_reg_start = param->value;
 188                 break;
 189         default:
 190                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 191                                         param->param);
 192                 return -EINVAL;
 193         }
 194
 195         return 0;
 196 }
 197
 198 static int i915_get_bridge_dev(struct drm_device *dev)
 199 {
 200         struct drm_i915_private *dev_priv = dev->dev_private;
 201
 202         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 203         if (!dev_priv->bridge_dev) {
 204                 DRM_ERROR("bridge device not found\n");
 205                 return -1;
 206         }
 207         return 0;
 208 }
 209
 210 #define MCHBAR_I915 0x44
 211 #define MCHBAR_I965 0x48
 212 #define MCHBAR_SIZE (4*4096)
 213
 214 #define DEVEN_REG 0x54
 215 #define   DEVEN_MCHBAR_EN (1 << 28)
 216
 217 /* Allocate space for the MCH regs if needed, return nonzero on error */
 218 static int
 219 intel_alloc_mchbar_resource(struct drm_device *dev)
 220 {
 221         struct drm_i915_private *dev_priv = dev->dev_private;
 222         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 223         u32 temp_lo, temp_hi = 0;
 224         u64 mchbar_addr;
 225         int ret;
 226
 227         if (INTEL_INFO(dev)->gen >= 4)
 228                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 229         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 230         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 231
 232         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 233 #ifdef CONFIG_PNP
 234         if (mchbar_addr &&
 235             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 236                 return 0;
 237 #endif
 238
 239         /* Get some space for it */
 240         dev_priv->mch_res.name = "i915 MCHBAR";
 241         dev_priv->mch_res.flags = IORESOURCE_MEM;
 242         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 243                                      &dev_priv->mch_res,
 244                                      MCHBAR_SIZE, MCHBAR_SIZE,
 245                                      PCIBIOS_MIN_MEM,
 246                                      0, pcibios_align_resource,
 247                                      dev_priv->bridge_dev);
 248         if (ret) {
 249                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 250                 dev_priv->mch_res.start = 0;
 251                 return ret;
 252         }
 253
 254         if (INTEL_INFO(dev)->gen >= 4)
 255                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 256                                        upper_32_bits(dev_priv->mch_res.start));
 257
 258         pci_write_config_dword(dev_priv->bridge_dev, reg,
 259                                lower_32_bits(dev_priv->mch_res.start));
 260         return 0;
 261 }
 262
 263 /* Setup MCHBAR if possible, return true if we should disable it again */
 264 static void
 265 intel_setup_mchbar(struct drm_device *dev)
 266 {
 267         struct drm_i915_private *dev_priv = dev->dev_private;
 268         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 269         u32 temp;
 270         bool enabled;
 271
 272         if (IS_VALLEYVIEW(dev))
 273                 return;
 274
 275         dev_priv->mchbar_need_disable = false;
 276
 277         if (IS_I915G(dev) || IS_I915GM(dev)) {
 278                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 279                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 280         } else {
 281                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 282                 enabled = temp & 1;
 283         }
 284
 285         /* If it's already enabled, don't have to do anything */
 286         if (enabled)
 287                 return;
 288
 289         if (intel_alloc_mchbar_resource(dev))
 290                 return;
 291
 292         dev_priv->mchbar_need_disable = true;
 293
 294         /* Space is allocated or reserved, so enable it. */
 295         if (IS_I915G(dev) || IS_I915GM(dev)) {
 296                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 297                                        temp | DEVEN_MCHBAR_EN);
 298         } else {
 299                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 300                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 301         }
 302 }
 303
 304 static void
 305 intel_teardown_mchbar(struct drm_device *dev)
 306 {
 307         struct drm_i915_private *dev_priv = dev->dev_private;
 308         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 309         u32 temp;
 310
 311         if (dev_priv->mchbar_need_disable) {
 312                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 313                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 314                         temp &= ~DEVEN_MCHBAR_EN;
 315                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 316                 } else {
 317                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 318                         temp &= ~1;
 319                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 320                 }
 321         }
 322
 323         if (dev_priv->mch_res.start)
 324                 release_resource(&dev_priv->mch_res);
 325 }
 326
 327 /* true = enable decode, false = disable decoder */
 328 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 329 {
 330         struct drm_device *dev = cookie;
 331
 332         intel_modeset_vga_set_state(dev, state);
 333         if (state)
 334                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 335                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 336         else
 337                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 338 }
 339
 340 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 341 {
 342         struct drm_device *dev = pci_get_drvdata(pdev);
 343         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 344
 345         if (state == VGA_SWITCHEROO_ON) {
 346                 pr_info("switched on\n");
 347                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 348                 /* i915 resume handler doesn't set to D0 */
 349                 pci_set_power_state(dev->pdev, PCI_D0);
 350                 i915_resume_legacy(dev);
 351                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 352         } else {
 353                 pr_err("switched off\n");
 354                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 355                 i915_suspend_legacy(dev, pmm);
 356                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 357         }
 358 }
 359
 360 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 361 {
 362         struct drm_device *dev = pci_get_drvdata(pdev);
 363
 364         /*
 365          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 366          * locking inversion with the driver load path. And the access here is
 367          * completely racy anyway. So don't bother with locking for now.
 368          */
 369         return dev->open_count == 0;
 370 }
 371
 372 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 373         .set_gpu_state = i915_switcheroo_set_state,
 374         .reprobe = NULL,
 375         .can_switch = i915_switcheroo_can_switch,
 376 };
 377
 378 static int i915_load_modeset_init(struct drm_device *dev)
 379 {
 380         struct drm_i915_private *dev_priv = dev->dev_private;
 381         int ret;
 382
 383         ret = intel_parse_bios(dev);
 384         if (ret)
 385                 DRM_INFO("failed to find VBIOS tables\n");
 386
 387         /* If we have > 1 VGA cards, then we need to arbitrate access
 388          * to the common VGA resources.
 389          *
 390          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 391          * then we do not take part in VGA arbitration and the
 392          * vga_client_register() fails with -ENODEV.
 393          */
 394         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
 395         if (ret && ret != -ENODEV)
 396                 goto out;
 397
 398         intel_register_dsm_handler();
 399
 400         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
 401         if (ret)
 402                 goto cleanup_vga_client;
 403
 404         /* Initialise stolen first so that we may reserve preallocated
 405          * objects for the BIOS to KMS transition.
 406          */
 407         ret = i915_gem_init_stolen(dev);
 408         if (ret)
 409                 goto cleanup_vga_switcheroo;
 410
 411         intel_power_domains_init_hw(dev_priv);
 412
 413         ret = intel_irq_install(dev_priv);
 414         if (ret)
 415                 goto cleanup_gem_stolen;
 416
 417         /* Important: The output setup functions called by modeset_init need
 418          * working irqs for e.g. gmbus and dp aux transfers. */
 419         intel_modeset_init(dev);
 420
 421         ret = i915_gem_init(dev);
 422         if (ret)
 423                 goto cleanup_irq;
 424
 425         intel_modeset_gem_init(dev);
 426
 427         /* Always safe in the mode setting case. */
 428         /* FIXME: do pre/post-mode set stuff in core KMS code */
 429         dev->vblank_disable_allowed = true;
 430         if (INTEL_INFO(dev)->num_pipes == 0)
 431                 return 0;
 432
 433         ret = intel_fbdev_init(dev);
 434         if (ret)
 435                 goto cleanup_gem;
 436
 437         /* Only enable hotplug handling once the fbdev is fully set up. */
 438         intel_hpd_init(dev_priv);
 439
 440         /*
 441          * Some ports require correctly set-up hpd registers for detection to
 442          * work properly (leading to ghost connected connector status), e.g. VGA
 443          * on gm45.  Hence we can only set up the initial fbdev config after hpd
 444          * irqs are fully enabled. Now we should scan for the initial config
 445          * only once hotplug handling is enabled, but due to screwed-up locking
 446          * around kms/fbdev init we can't protect the fdbev initial config
 447          * scanning against hotplug events. Hence do this first and ignore the
 448          * tiny window where we will loose hotplug notifactions.
 449          */
 450         async_schedule(intel_fbdev_initial_config, dev_priv);
 451
 452         drm_kms_helper_poll_init(dev);
 453
 454         return 0;
 455
 456 cleanup_gem:
 457         mutex_lock(&dev->struct_mutex);
 458         i915_gem_cleanup_ringbuffer(dev);
 459         i915_gem_context_fini(dev);
 460         mutex_unlock(&dev->struct_mutex);
 461 cleanup_irq:
 462         drm_irq_uninstall(dev);
 463 cleanup_gem_stolen:
 464         i915_gem_cleanup_stolen(dev);
 465 cleanup_vga_switcheroo:
 466         vga_switcheroo_unregister_client(dev->pdev);
 467 cleanup_vga_client:
 468         vga_client_register(dev->pdev, NULL, NULL, NULL);
 469 out:
 470         return ret;
 471 }
 472
 473 #if IS_ENABLED(CONFIG_FB)
 474 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 475 {
 476         struct apertures_struct *ap;
 477         struct pci_dev *pdev = dev_priv->dev->pdev;
 478         bool primary;
 479         int ret;
 480
 481         ap = alloc_apertures(1);
 482         if (!ap)
 483                 return -ENOMEM;
 484
 485         ap->ranges[0].base = dev_priv->gtt.mappable_base;
 486         ap->ranges[0].size = dev_priv->gtt.mappable_end;
 487
 488         primary =
 489                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 490
 491         ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 492
 493         kfree(ap);
 494
 495         return ret;
 496 }
 497 #else
 498 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 499 {
 500         return 0;
 501 }
 502 #endif
 503
 504 #if !defined(CONFIG_VGA_CONSOLE)
 505 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 506 {
 507         return 0;
 508 }
 509 #elif !defined(CONFIG_DUMMY_CONSOLE)
 510 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 511 {
 512         return -ENODEV;
 513 }
 514 #else
 515 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 516 {
 517         int ret = 0;
 518
 519         DRM_INFO("Replacing VGA console driver\n");
 520
 521         console_lock();
 522         if (con_is_bound(&vga_con))
 523                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 524         if (ret == 0) {
 525                 ret = do_unregister_con_driver(&vga_con);
 526
 527                 /* Ignore "already unregistered". */
 528                 if (ret == -ENODEV)
 529                         ret = 0;
 530         }
 531         console_unlock();
 532
 533         return ret;
 534 }
 535 #endif
 536
 537 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
 538 {
 539         const struct intel_device_info *info = &dev_priv->info;
 540
 541 #define PRINT_S(name) "%s"
 542 #define SEP_EMPTY
 543 #define PRINT_FLAG(name) info->name ? #name "," : ""
 544 #define SEP_COMMA ,
 545         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
 546                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
 547                          info->gen,
 548                          dev_priv->dev->pdev->device,
 549                          dev_priv->dev->pdev->revision,
 550                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
 551 #undef PRINT_S
 552 #undef SEP_EMPTY
 553 #undef PRINT_FLAG
 554 #undef SEP_COMMA
 555 }
 556
 557 /*
 558  * Determine various intel_device_info fields at runtime.
 559  *
 560  * Use it when either:
 561  *   - it's judged too laborious to fill n static structures with the limit
 562  *     when a simple if statement does the job,
 563  *   - run-time checks (eg read fuse/strap registers) are needed.
 564  *
 565  * This function needs to be called:
 566  *   - after the MMIO has been setup as we are reading registers,
 567  *   - after the PCH has been detected,
 568  *   - before the first usage of the fields it can tweak.
 569  */
 570 static void intel_device_info_runtime_init(struct drm_device *dev)
 571 {
 572         struct drm_i915_private *dev_priv = dev->dev_private;
 573         struct intel_device_info *info;
 574         enum pipe pipe;
 575
 576         info = (struct intel_device_info *)&dev_priv->info;
 577
 578         if (IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen == 9)
 579                 for_each_pipe(dev_priv, pipe)
 580                         info->num_sprites[pipe] = 2;
 581         else
 582                 for_each_pipe(dev_priv, pipe)
 583                         info->num_sprites[pipe] = 1;
 584
 585         if (i915.disable_display) {
 586                 DRM_INFO("Display disabled (module parameter)\n");
 587                 info->num_pipes = 0;
 588         } else if (info->num_pipes > 0 &&
 589                    (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
 590                    !IS_VALLEYVIEW(dev)) {
 591                 u32 fuse_strap = I915_READ(FUSE_STRAP);
 592                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
 593
 594                 /*
 595                  * SFUSE_STRAP is supposed to have a bit signalling the display
 596                  * is fused off. Unfortunately it seems that, at least in
 597                  * certain cases, fused off display means that PCH display
 598                  * reads don't land anywhere. In that case, we read 0s.
 599                  *
 600                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
 601                  * should be set when taking over after the firmware.
 602                  */
 603                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
 604                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
 605                     (dev_priv->pch_type == PCH_CPT &&
 606                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 607                         DRM_INFO("Display fused off, disabling\n");
 608                         info->num_pipes = 0;
 609                 }
 610         }
 611 }
 612
 613 /**
 614  * i915_driver_load - setup chip and create an initial config
 615  * @dev: DRM device
 616  * @flags: startup flags
 617  *
 618  * The driver load routine has to do several things:
 619  *   - drive output discovery via intel_modeset_init()
 620  *   - initialize the memory manager
 621  *   - allocate initial config memory
 622  *   - setup the DRM framebuffer with the allocated memory
 623  */
 624 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 625 {
 626         struct drm_i915_private *dev_priv;
 627         struct intel_device_info *info, *device_info;
 628         int ret = 0, mmio_bar, mmio_size;
 629         uint32_t aperture_size;
 630
 631         info = (struct intel_device_info *) flags;
 632
 633         /* Refuse to load on gen6+ without kms enabled. */
 634         if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) {
 635                 DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
 636                 DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
 637                 return -ENODEV;
 638         }
 639
 640         /* UMS needs agp support. */
 641         if (!drm_core_check_feature(dev, DRIVER_MODESET) && !dev->agp)
 642                 return -EINVAL;
 643
 644         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 645         if (dev_priv == NULL)
 646                 return -ENOMEM;
 647
 648         dev->dev_private = dev_priv;
 649         dev_priv->dev = dev;
 650
 651         /* Setup the write-once "constant" device info */
 652         device_info = (struct intel_device_info *)&dev_priv->info;
 653         memcpy(device_info, info, sizeof(dev_priv->info));
 654         device_info->device_id = dev->pdev->device;
 655
 656         spin_lock_init(&dev_priv->irq_lock);
 657         spin_lock_init(&dev_priv->gpu_error.lock);
 658         mutex_init(&dev_priv->backlight_lock);
 659         spin_lock_init(&dev_priv->uncore.lock);
 660         spin_lock_init(&dev_priv->mm.object_stat_lock);
 661         spin_lock_init(&dev_priv->mmio_flip_lock);
 662         mutex_init(&dev_priv->dpio_lock);
 663         mutex_init(&dev_priv->modeset_restore_lock);
 664
 665         intel_pm_setup(dev);
 666
 667         intel_display_crc_init(dev);
 668
 669         i915_dump_device_info(dev_priv);
 670
 671         /* Not all pre-production machines fall into this category, only the
 672          * very first ones. Almost everything should work, except for maybe
 673          * suspend/resume. And we don't implement workarounds that affect only
 674          * pre-production machines. */
 675         if (IS_HSW_EARLY_SDV(dev))
 676                 DRM_INFO("This is an early pre-production Haswell machine. "
 677                          "It may not be fully functional.\n");
 678
 679         if (i915_get_bridge_dev(dev)) {
 680                 ret = -EIO;
 681                 goto free_priv;
 682         }
 683
 684         mmio_bar = IS_GEN2(dev) ? 1 : 0;
 685         /* Before gen4, the registers and the GTT are behind different BARs.
 686          * However, from gen4 onwards, the registers and the GTT are shared
 687          * in the same BAR, so we want to restrict this ioremap from
 688          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 689          * the register BAR remains the same size for all the earlier
 690          * generations up to Ironlake.
 691          */
 692         if (info->gen < 5)
 693                 mmio_size = 512*1024;
 694         else
 695                 mmio_size = 2*1024*1024;
 696
 697         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
 698         if (!dev_priv->regs) {
 699                 DRM_ERROR("failed to map registers\n");
 700                 ret = -EIO;
 701                 goto put_bridge;
 702         }
 703
 704         /* This must be called before any calls to HAS_PCH_* */
 705         intel_detect_pch(dev);
 706
 707         intel_uncore_init(dev);
 708
 709         ret = i915_gem_gtt_init(dev);
 710         if (ret)
 711                 goto out_regs;
 712
 713         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 714                 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
 715                  * otherwise the vga fbdev driver falls over. */
 716                 ret = i915_kick_out_firmware_fb(dev_priv);
 717                 if (ret) {
 718                         DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
 719                         goto out_gtt;
 720                 }
 721
 722                 ret = i915_kick_out_vgacon(dev_priv);
 723                 if (ret) {
 724                         DRM_ERROR("failed to remove conflicting VGA console\n");
 725                         goto out_gtt;
 726                 }
 727         }
 728
 729         pci_set_master(dev->pdev);
 730
 731         /* overlay on gen2 is broken and can't address above 1G */
 732         if (IS_GEN2(dev))
 733                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
 734
 735         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
 736          * using 32bit addressing, overwriting memory if HWS is located
 737          * above 4GB.
 738          *
 739          * The documentation also mentions an issue with undefined
 740          * behaviour if any general state is accessed within a page above 4GB,
 741          * which also needs to be handled carefully.
 742          */
 743         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
 744                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
 745
 746         aperture_size = dev_priv->gtt.mappable_end;
 747
 748         dev_priv->gtt.mappable =
 749                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
 750                                      aperture_size);
 751         if (dev_priv->gtt.mappable == NULL) {
 752                 ret = -EIO;
 753                 goto out_gtt;
 754         }
 755
 756         dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
 757                                               aperture_size);
 758
 759         /* The i915 workqueue is primarily used for batched retirement of
 760          * requests (and thus managing bo) once the task has been completed
 761          * by the GPU. i915_gem_retire_requests() is called directly when we
 762          * need high-priority retirement, such as waiting for an explicit
 763          * bo.
 764          *
 765          * It is also used for periodic low-priority events, such as
 766          * idle-timers and recording error state.
 767          *
 768          * All tasks on the workqueue are expected to acquire the dev mutex
 769          * so there is no point in running more than one instance of the
 770          * workqueue at any time.  Use an ordered one.
 771          */
 772         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 773         if (dev_priv->wq == NULL) {
 774                 DRM_ERROR("Failed to create our workqueue.\n");
 775                 ret = -ENOMEM;
 776                 goto out_mtrrfree;
 777         }
 778
 779         dev_priv->dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 780         if (dev_priv->dp_wq == NULL) {
 781                 DRM_ERROR("Failed to create our dp workqueue.\n");
 782                 ret = -ENOMEM;
 783                 goto out_freewq;
 784         }
 785
 786         intel_irq_init(dev_priv);
 787         intel_uncore_sanitize(dev);
 788
 789         /* Try to make sure MCHBAR is enabled before poking at it */
 790         intel_setup_mchbar(dev);
 791         intel_setup_gmbus(dev);
 792         intel_opregion_setup(dev);
 793
 794         intel_setup_bios(dev);
 795
 796         i915_gem_load(dev);
 797
 798         /* On the 945G/GM, the chipset reports the MSI capability on the
 799          * integrated graphics even though the support isn't actually there
 800          * according to the published specs.  It doesn't appear to function
 801          * correctly in testing on 945G.
 802          * This may be a side effect of MSI having been made available for PEG
 803          * and the registers being closely associated.
 804          *
 805          * According to chipset errata, on the 965GM, MSI interrupts may
 806          * be lost or delayed, but we use them anyways to avoid
 807          * stuck interrupts on some machines.
 808          */
 809         if (!IS_I945G(dev) && !IS_I945GM(dev))
 810                 pci_enable_msi(dev->pdev);
 811
 812         intel_device_info_runtime_init(dev);
 813
 814         if (INTEL_INFO(dev)->num_pipes) {
 815                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
 816                 if (ret)
 817                         goto out_gem_unload;
 818         }
 819
 820         intel_power_domains_init(dev_priv);
 821
 822         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 823                 ret = i915_load_modeset_init(dev);
 824                 if (ret < 0) {
 825                         DRM_ERROR("failed to init modeset\n");
 826                         goto out_power_well;
 827                 }
 828         } else {
 829                 /* Start out suspended in ums mode. */
 830                 dev_priv->ums.mm_suspended = 1;
 831         }
 832
 833         i915_setup_sysfs(dev);
 834
 835         if (INTEL_INFO(dev)->num_pipes) {
 836                 /* Must be done after probing outputs */
 837                 intel_opregion_init(dev);
 838                 acpi_video_register();
 839         }
 840
 841         if (IS_GEN5(dev))
 842                 intel_gpu_ips_init(dev_priv);
 843
 844         intel_runtime_pm_enable(dev_priv);
 845
 846         return 0;
 847
 848 out_power_well:
 849         intel_power_domains_fini(dev_priv);
 850         drm_vblank_cleanup(dev);
 851 out_gem_unload:
 852         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
 853         unregister_shrinker(&dev_priv->mm.shrinker);
 854
 855         if (dev->pdev->msi_enabled)
 856                 pci_disable_msi(dev->pdev);
 857
 858         intel_teardown_gmbus(dev);
 859         intel_teardown_mchbar(dev);
 860         pm_qos_remove_request(&dev_priv->pm_qos);
 861         destroy_workqueue(dev_priv->dp_wq);
 862 out_freewq:
 863         destroy_workqueue(dev_priv->wq);
 864 out_mtrrfree:
 865         arch_phys_wc_del(dev_priv->gtt.mtrr);
 866         io_mapping_free(dev_priv->gtt.mappable);
 867 out_gtt:
 868         i915_global_gtt_cleanup(dev);
 869 out_regs:
 870         intel_uncore_fini(dev);
 871         pci_iounmap(dev->pdev, dev_priv->regs);
 872 put_bridge:
 873         pci_dev_put(dev_priv->bridge_dev);
 874 free_priv:
 875         if (dev_priv->slab)
 876                 kmem_cache_destroy(dev_priv->slab);
 877         kfree(dev_priv);
 878         return ret;
 879 }
 880
 881 int i915_driver_unload(struct drm_device *dev)
 882 {
 883         struct drm_i915_private *dev_priv = dev->dev_private;
 884         int ret;
 885
 886         ret = i915_gem_suspend(dev);
 887         if (ret) {
 888                 DRM_ERROR("failed to idle hardware: %d\n", ret);
 889                 return ret;
 890         }
 891
 892         intel_power_domains_fini(dev_priv);
 893
 894         intel_gpu_ips_teardown();
 895
 896         i915_teardown_sysfs(dev);
 897
 898         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
 899         unregister_shrinker(&dev_priv->mm.shrinker);
 900
 901         io_mapping_free(dev_priv->gtt.mappable);
 902         arch_phys_wc_del(dev_priv->gtt.mtrr);
 903
 904         acpi_video_unregister();
 905
 906         if (drm_core_check_feature(dev, DRIVER_MODESET))
 907                 intel_fbdev_fini(dev);
 908
 909         drm_vblank_cleanup(dev);
 910
 911         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 912                 intel_modeset_cleanup(dev);
 913
 914                 /*
 915                  * free the memory space allocated for the child device
 916                  * config parsed from VBT
 917                  */
 918                 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
 919                         kfree(dev_priv->vbt.child_dev);
 920                         dev_priv->vbt.child_dev = NULL;
 921                         dev_priv->vbt.child_dev_num = 0;
 922                 }
 923
 924                 vga_switcheroo_unregister_client(dev->pdev);
 925                 vga_client_register(dev->pdev, NULL, NULL, NULL);
 926         }
 927
 928         /* Free error state after interrupts are fully disabled. */
 929         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
 930         cancel_work_sync(&dev_priv->gpu_error.work);
 931         i915_destroy_error_state(dev);
 932
 933         if (dev->pdev->msi_enabled)
 934                 pci_disable_msi(dev->pdev);
 935
 936         intel_opregion_fini(dev);
 937
 938         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 939                 /* Flush any outstanding unpin_work. */
 940                 flush_workqueue(dev_priv->wq);
 941
 942                 mutex_lock(&dev->struct_mutex);
 943                 i915_gem_cleanup_ringbuffer(dev);
 944                 i915_gem_context_fini(dev);
 945                 mutex_unlock(&dev->struct_mutex);
 946                 i915_gem_cleanup_stolen(dev);
 947         }
 948
 949         intel_teardown_gmbus(dev);
 950         intel_teardown_mchbar(dev);
 951
 952         destroy_workqueue(dev_priv->dp_wq);
 953         destroy_workqueue(dev_priv->wq);
 954         pm_qos_remove_request(&dev_priv->pm_qos);
 955
 956         i915_global_gtt_cleanup(dev);
 957
 958         intel_uncore_fini(dev);
 959         if (dev_priv->regs != NULL)
 960                 pci_iounmap(dev->pdev, dev_priv->regs);
 961
 962         if (dev_priv->slab)
 963                 kmem_cache_destroy(dev_priv->slab);
 964
 965         pci_dev_put(dev_priv->bridge_dev);
 966         kfree(dev_priv);
 967
 968         return 0;
 969 }
 970
 971 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
 972 {
 973         int ret;
 974
 975         ret = i915_gem_open(dev, file);
 976         if (ret)
 977                 return ret;
 978
 979         return 0;
 980 }
 981
 982 /**
 983  * i915_driver_lastclose - clean up after all DRM clients have exited
 984  * @dev: DRM device
 985  *
 986  * Take care of cleaning up after all DRM clients have exited.  In the
 987  * mode setting case, we want to restore the kernel's initial mode (just
 988  * in case the last client left us in a bad state).
 989  *
 990  * Additionally, in the non-mode setting case, we'll tear down the GTT
 991  * and DMA structures, since the kernel won't be using them, and clea
 992  * up any GEM state.
 993  */
 994 void i915_driver_lastclose(struct drm_device *dev)
 995 {
 996         struct drm_i915_private *dev_priv = dev->dev_private;
 997
 998         /* On gen6+ we refuse to init without kms enabled, but then the drm core
 999          * goes right around and calls lastclose. Check for this and don't clean
1000          * up anything. */
1001         if (!dev_priv)
1002                 return;
1003
1004         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1005                 intel_fbdev_restore_mode(dev);
1006                 vga_switcheroo_process_delayed_switch();
1007                 return;
1008         }
1009
1010         i915_gem_lastclose(dev);
1011 }
1012
1013 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1014 {
1015         mutex_lock(&dev->struct_mutex);
1016         i915_gem_context_close(dev, file);
1017         i915_gem_release(dev, file);
1018         mutex_unlock(&dev->struct_mutex);
1019
1020         if (drm_core_check_feature(dev, DRIVER_MODESET))
1021                 intel_modeset_preclose(dev, file);
1022 }
1023
1024 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1025 {
1026         struct drm_i915_file_private *file_priv = file->driver_priv;
1027
1028         if (file_priv && file_priv->bsd_ring)
1029                 file_priv->bsd_ring = NULL;
1030         kfree(file_priv);
1031 }
1032
1033 const struct drm_ioctl_desc i915_ioctls[] = {
1034         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1035         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1036         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1037         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1038         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1039         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1040         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1041         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1042         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1043         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1044         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1045         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1046         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1047         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1048         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1049         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1050         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1051         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1052         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1053         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1054         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1055         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1056         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1057         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1058         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1059         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1060         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1061         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1062         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1063         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1064         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1065         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1066         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1067         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1068         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1069         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1070         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1071         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1072         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1073         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1074         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1075         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1076         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1077         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1078         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1079         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1080         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1081         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1082         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1083         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1084 };
1085
1086 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);
1087
1088 /*
1089  * This is really ugly: Because old userspace abused the linux agp interface to
1090  * manage the gtt, we need to claim that all intel devices are agp.  For
1091  * otherwise the drm core refuses to initialize the agp support code.
1092  */
1093 int i915_driver_device_is_agp(struct drm_device *dev)
1094 {
1095         return 1;
1096 }